44546 lines
3.1 MiB
44546 lines
3.1 MiB
; --------------------------------------------------------------------------------
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; @Title: OMAP3517/OMAP3505 On-Chip Peripherals
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; @Props: Released
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; @Author: ADI, FIL
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; @Changelog: 2009-10-26
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; @Manufacturer: TI - Texas Instruments
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; @Doc: sprz306.pdf; sprugr0.pdf; am3517.pdf (rev. 2009-10-01)
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; @Core: Cortex-A8
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peram3517.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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base ad:0x00
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tree "Core Registers (Cortex-A8)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x300--0x300
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUTR,MPU type register"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
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bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
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textline " "
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bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
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bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
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bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
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textline " "
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bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
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bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
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bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
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textline " "
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bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
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bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
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bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
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bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
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textline " "
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bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
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bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
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bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
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bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
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bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
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group c15:0x201--0x201
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group c15:0x11--0x11
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group c15:0x111--0x111
|
|
line.long 0x0 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
|
|
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
group c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group c15:0x10c--0x10c
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup c15:0x1C--0x1C
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
width 8.
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
|
|
group c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
|
|
group c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
group c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
group c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
textline " "
|
|
group c15:0x002A--0x002A
|
|
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group c15:0x012A--0x012A
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group c15:0x000d++0x00
|
|
line.long 0x00 "FCSEPID,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
|
|
group c15:0x10d--0x10d
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup c15:0x1000--0x1000
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Cache Control and Configuration"
|
|
group c15:0x1009++0x00
|
|
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
|
|
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
group c15:0x1209++0x00
|
|
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
|
|
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
|
|
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
|
|
textline " "
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
|
|
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x010b++0x00
|
|
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
|
|
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
|
|
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
|
|
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x030b++0x00
|
|
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
|
|
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x002b++0x00
|
|
line.long 0x00 "PLECNR,PLE Channel Number Register"
|
|
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
|
|
wgroup c15:0x003b++0x00
|
|
line.long 0x00 "PLEER0,PLE Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
|
|
wgroup c15:0x013b++0x00
|
|
line.long 0x00 "PLEER1,PLE Enable Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
|
|
wgroup c15:0x023b++0x00
|
|
line.long 0x00 "PLEER2,PLE Enable Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
|
|
group c15:0x004b++0x00
|
|
line.long 0x00 "PLECR,PLE Control Register"
|
|
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
|
|
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
|
|
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
|
|
textline " "
|
|
group c15:0x005b++0x00
|
|
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
|
|
group c15:0x007b++0x00
|
|
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
|
|
rgroup c15:0x008b++0x00
|
|
line.long 0x00 "PLECSR,PLE Channel Status Register"
|
|
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
|
|
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
|
|
group c15:0x00fb++0x00
|
|
line.long 0x00 "PLECIDR,PLE Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "PMCCNTR,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 10.
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 10.
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
width 10.
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
width 10.
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
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|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
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width 0xC
|
|
tree "Coresight Management Registers"
|
|
width 17.
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
width 17.
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
width 17.
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
tree.end
|
|
tree.open "PRCM (Power Reset and Clock Management)"
|
|
tree "Clock Management"
|
|
base ad:0x48004000
|
|
width 22.
|
|
rgroup.long 0x800++0x3 "OCP_System_Reg Registers"
|
|
line.long 0x00 "CM_REVISION,IP revision code for the CM part of the PRCM"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MINOR ,Minor revision"
|
|
group.long 0x810++0x3
|
|
line.long 0x00 "CM_SYSCONFIG,Various parameters of the interface clock Control"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Auto gating strategy"
|
|
group.long 0x904++0x3 "MPU"
|
|
line.long 0x00 "CM_CLKEN_PLL_MPU,DPLL1 Modes Control"
|
|
bitfld.long 0x00 10. " EN_MPU_DPLL_LPMODE ,LP mode of the MPU DPLL control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MPU_DPLL_RAMPTIME ,Frequency ramp time total duration controlling" "Disabled,2-40,4-80,12-240"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MPU_DPLL_FREQSEL ,Select proper range of the DPLL1 internal frequency (MHz)" "Reserved,Reserved,Reserved,0.75-1.0,1.0-1.25,1.25-1.5,1.5-1.75,1.75-2.1,Reserved,Reserved,Reserved,7.5-10,10-12.5,12.5-15,15-17.5,17.5-21"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_MPU_DPLL_DRIFTGUARD ,Automatic recalibration feature of the MPU DPLL enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EN_MPU_DPLL ,DPLL1 control" "Reserved,Reserved,Reserved,Reserved,Reserved,Low power bypass,Reserved,Lock"
|
|
rgroup.long 0x920++0x7
|
|
line.long 0x00 "CM_IDLEST_MPU,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 0. " ST_MPU ,MPU standby status" "Active,Standby"
|
|
line.long 0x04 "CM_IDLEST_PLL_MPU,Master Clock Activity Monitoring"
|
|
bitfld.long 0x04 0. " ST_MPU_CLK ,MPU_CLK activity" "Bypassed,Locked"
|
|
group.long 0x934++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_PLL_MPU,Over The DPLL1 Activity Automatic Control"
|
|
bitfld.long 0x00 0.--2. " AUTO_MPU_DPLL ,DPLL1 automatic control" "Disabled,Auto low power stop,?..."
|
|
group.long 0x940++0xb
|
|
line.long 0x00 "CM_CLKSEL1_PLL_MPU,Over The MPU DPLL Control"
|
|
bitfld.long 0x00 19.--21. " MPU_CLK_SRC ,DPLL1 bypass source clock" "Reserved,CORE_CLK/1,CORE_CLK/2,Reserved,CORE_CLK/4,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " MPU_DPLL_MULT ,DPLL1 multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " MPU_DPLL_DIV ,DPLL1 divider factor"
|
|
line.long 0x04 "CM_CLKSEL2_PLL_MPU,Over The MPU DPLL Control"
|
|
bitfld.long 0x04 0.--4. " MPU_DPLL_CLKOUT_DIV ,DPLL1 output clock divider factor" "Reserved,Clk/1,Clk/2,Clk/3,Clk/4,Clk/5,Clk/6,Clk/7,Clk/8,Clk/9,Clk/10,Clk/11,Clk/12,Clk/13,Clk/14,Clk/15,Clk/16,?..."
|
|
line.long 0x08 "CM_CLKSTCTRL_MPU,Domain Power State Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_MPU ,Clock state transition of the MPU clock domain control" "Disabled,Reserved,Supervised wake-up,Auto"
|
|
rgroup.long 0x94C++0x3
|
|
line.long 0x00 "CM_CLKSTST_MPU,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_MPU ,Clock activity status" "Not active,Active"
|
|
group.long 0xA00++0x3 "CORE"
|
|
line.long 0x00 "CM_FCLKEN1_CORE,Functional Clock Activity Control"
|
|
bitfld.long 0x00 30. " EN_MMC3 ,MMC3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EN_MMC2 ,MMC2 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " EN_MMC1 ,MMC1 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " EN_HDQ ,HDQ-1 wire functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EN_MCSPI4 ,McSPI 4 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EN_MCSPI3 ,McSPI 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EN_MCSPI2 ,McSPI 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_MCSPI1 ,McSPI 1 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EN_I2C3 ,I2C 3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_I2C2 ,I2C 2 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_I2C1 ,I2C 1 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_UART2 ,UART 2 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_UART1 ,UART 1 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_GPT11 ,GPTIMER 11 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_GPT10 ,GPTIMER 10 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_MCBSP5 ,McBSP 5 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_MCBSP1 ,McBSP 1 functional clock control" "Disabled,Enabled"
|
|
group.long 0xA08++0x3
|
|
line.long 0x00 "CM_FCLKEN3_CORE,Controls The Module Functional Clock Activity"
|
|
bitfld.long 0x00 2. " EN_USBTLL ,USB TLL functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN_TS ,Temperature Sensors functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CPEFUSE ,CPEFUSE functional clock control" "Disabled,Enabled"
|
|
group.long 0xA10++0xB
|
|
line.long 0x00 "CM_ICLKEN1_CORE,Interface Clock Activity Control"
|
|
bitfld.long 0x00 30. " EN_MMC3 ,MMC SDIO 3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EN_AES2 ,AES 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " EN_SHA12 ,SHA 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_DES2 ,D3D2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EN_MMC2 ,MMC SDIO 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EN_MMC1 ,MMC SDIO 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EN_UART4 ,UART4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " EN_HDQ ,HDQ-wire interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EN_MCSPI4 ,McSPI 4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EN_MCSPI3 ,McSPI 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EN_MCSPI2 ,McSPI 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_MCSPI1 ,McSPI 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EN_I2C3 ,I2C 3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_I2C2 ,I2C 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_I2C1 ,I2C 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_UART2 ,UART 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_UART1 ,UART 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_GPT11 ,GPTIMER 11 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_GPT10 ,GPTIMER 10 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_MCBSP5 ,McBSP 5 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_MCBSP1 ,McBSP 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_SCMCTRL ,System Control Module interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_IPSS ,IPSS interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN_SDRC ,SDRC interface clock control" "Disabled,Enabled"
|
|
line.long 0x04 "CM_ICLKEN2_CORE,Interface Clock Activity"
|
|
bitfld.long 0x04 4. " EN_PKA ,PKA1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EN_AES1 ,AES 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EN_RNG ,RNG1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EN_SHA11 ,SHA 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN_DES1 ,D3D1 interface clock control" "Disabled,Enabled"
|
|
line.long 0x08 "CM_ICLKEN3_CORE,Interface Clock Activity"
|
|
bitfld.long 0x08 2. " EN_USBTLL ,USB TLL interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xA20++0xB
|
|
line.long 0x00 "CM_IDLEST1_CORE,CORE Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 30. " ST_MMC3 ,MMC 3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 28. " ST_AES2 ,AES 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ST_SHA12 ,SHAM 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 26. " ST_DES2 ,D3D2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ST_MMC2 ,MMC 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 24. " ST_MMC1 ,MMC SDIO 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ST_UART4 ,UART4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 22. " ST_HDQ ,HDQ-1 wire idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ST_MCSPI4 ,McSPI 4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 20. " ST_MCSPI3 ,McSPI 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ST_MCSPI2 ,McSPI 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 18. " ST_MCSPI1 ,McSPI 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ST_I2C3 ,I2C 3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 16. " ST_I2C2 ,I2C 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ST_I2C1 ,I2C 1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 14. " ST_UART2 ,UART 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ST_UART1 ,UART 1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 12. " ST_GPT11 ,GPTIMER 11 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ST_GPT10 ,GPTIMER 10 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 10. " ST_MCBSP5 ,McBSP 5 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ST_MCBSP1 ,McBSP 1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 6. " ST_SCMCTRL ,System Control Module idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ST_IPSS_IDLE ,IPSS idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ST_SDMA ,System DMA standby status" "Active,Standby"
|
|
bitfld.long 0x00 1. " ST_EMIF4 ,EMIF4 idle status" "Accessed,Not accessed"
|
|
line.long 0x04 "CM_IDLEST2_CORE,CORE Modules Access Availability Monitoring"
|
|
bitfld.long 0x04 4. " ST_PKA ,PKA idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x04 3. " ST_AES1 ,AES 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ST_RNG ,RNG idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x04 1. " ST_SHA11 ,SHAM 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ST_DES1 ,D3D1 idle status" "Accessed,Not accessed"
|
|
line.long 0x08 "CM_IDLEST3_CORE,CORE Modules Access Availability Monitoring"
|
|
bitfld.long 0x08 2. " ST_USBTLL ,USB TLL idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x08 0. " ST_CPEFUSE ,CPEFUSE idle status" "Accessed,Not accessed"
|
|
group.long 0xA30++0xB
|
|
line.long 0x00 "CM_AUTOIDLE1_CORE,Automatic Control Of The CORE Modules Interface Clock Activity"
|
|
bitfld.long 0x00 30. " AUTO_MMC3 ,MMC SDIO 3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 28. " AUTO_AES2 ,AES 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AUTO_SHA12 ,SHAM 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 26. " AUTO_DES2 ,D3D2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AUTO_MMC2 ,MMC SDIO 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 24. " AUTO_MMC1 ,MMC SDIO 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AUTO_UART4 ,UART4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 22. " AUTO_HDQ ,HDQ-1 wire auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 21. " AUTO_MCSPI4 ,McSPI 4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 20. " AUTO_MCSPI3 ,McSPI 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AUTO_MCSPI2 ,McSPI 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 18. " AUTO_MCSPI1 ,McSPI 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 17. " AUTO_I2C3 ,I2C 3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 16. " AUTO_I2C2 ,I2C 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTO_I2C1 ,I2C 1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 14. " AUTO_UART2 ,UART 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_UART1 ,UART 1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 12. " AUTO_GPT11 ,GPTIMER 11 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_GPT10 ,GPTIMER 10 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 10. " AUTO_MCBSP5 ,McBSP 5 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTO_MCBSP1 ,McBSP 1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 6. " AUTO_SCMCTRL ,System Control Module auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AUTO_IPSS ,IPSS auto clock control" "Unrelated,Related"
|
|
line.long 0x04 "CM_AUTOIDLE2_CORE,Automatic Control Of The CORE Modules Interface Clock Activity"
|
|
bitfld.long 0x04 4. " AUTO_PKA ,PKA auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x04 3. " AUTO_AES1 ,AES 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AUTO_RNG ,RNG auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x04 1. " AUTO_SHA11 ,SHAM 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AUTO_DES1 ,D3D1 auto clock control" "Unrelated,Related"
|
|
line.long 0x08 "CM_AUTOIDLE3_CORE,Automatic Control Of The CORE Modules Interface Clock Activity"
|
|
bitfld.long 0x08 2. " AUTO_USBTLL ,USB TLL auto clock control" "Unrelated,Related"
|
|
group.long 0xA40++0x3
|
|
line.long 0x00 "CM_CLKSEL_CORE,CORE Modules Clock Selection"
|
|
bitfld.long 0x00 7. " CLKSEL_GPT11 ,Selects GPTIMER 11 source clock" "CM_32K_CLK,CM_SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKSEL_GPT10 ,Selects GPTIMER 10 source clock" "CM_32K_CLK,CM_SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CLKSEL_L4 ,Selects Peripherals interconnect clock (L4_clk)" "Reserved,L3_ICLK/1,L3_ICLK/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKSEL_L3 ,Selects L3 interconnect clock (L3_clk)" "Reserved,CORE_CLK/1,CORE_CLK/2,?..."
|
|
group.long 0xA48++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_CORE,Domain Power State Transition Enable"
|
|
bitfld.long 0x00 2.--3. " CLKTRCTRL_L4 ,Clock state transition of the L4 clock domain control" "Disabled,Reserved,Reserved,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_L3 ,Clock state transition of the L3 clock domain control" "Disabled,Reserved,Reserved,Auto"
|
|
rgroup.long 0xA4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_CORE,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 1. " CLKACTIVITY_L4 ,L4 clock activity status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKACTIVITY_L3 ,L3 clock activity status" "Not active,Active"
|
|
group.long 0xB00++0x3 "SGX"
|
|
line.long 0x00 "CM_FCLKEN_SGX,Controls The Graphics Engine Functional Clock Activity"
|
|
bitfld.long 0x00 1. " EN_SGX ,SGX functional clock enable" "Disabled,Enabled"
|
|
group.long 0xB10++0x3
|
|
line.long 0x00 "CM_ICLKEN_SGX,Controls The Graphics Engine Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_SGX ,SGX interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xB20++0x3
|
|
line.long 0x00 "CM_IDLEST_SGX,SGX Standby Status"
|
|
bitfld.long 0x00 0. " ST_SGX ,SGX standby status" "Active,Standby"
|
|
group.long 0xB40++0xb
|
|
line.long 0x00 "CM_CLKSEL_SGX,SGX Clock Selection"
|
|
bitfld.long 0x00 0.--2. " CLKSEL_SGX ,Selects SGX functional clock" "CORE_CLK/3,CORE_CLK/4,CORE_CLK/6,CM_96M_FCLK,?..."
|
|
line.long 0x04 "CM_SLEEPDEP_SGX,Sleep Transition Dependency Of SGX Domain Enable"
|
|
bitfld.long 0x04 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_SGX,Domain Power State Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_SGX ,Clock state transition of the SGX clock domain control" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0xB4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_SGX,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_SGX ,Clock activity status" "Not active,Active"
|
|
group.long 0xC00++0x3 "WKUP"
|
|
line.long 0x00 "CM_FCLKEN_WKUP,Controls The Modules Functional Clock Activity"
|
|
bitfld.long 0x00 6. " EN_SR1 ,Smart Refex 1 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN_WDT2 ,WDTIMER 2 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPIO1 ,GPIO 1 clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_GPT1 ,GPTIMER 1 clock control" "Disabled,Enabled"
|
|
group.long 0xC10++0x3
|
|
line.long 0x00 "CM_ICLKEN_WKUP,Controls The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 5. " EN_WDT2 ,WDTIMER 2 interface clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN_WDT1 ,WDTIMER 1 (Secure) interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPIO1 ,GPIO 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_32KSYNC ,32 kHz Sync Timer interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_GPT12 ,GPTIMER 12 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_GPT1 ,GPTIMER 1 interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xC20++0x3
|
|
line.long 0x00 "CM_IDLEST_WKUP,WAKEUP Domain Modules Access Monitoring"
|
|
bitfld.long 0x00 7. " ST_SR2 ,Smart Reflex 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 5. " ST_WDT2 ,WDTIMER 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ST_WDT1 ,WDTIMER 1 (Secure) idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 3. " ST_GPIO1 ,GPIO 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ST_32KSYNC ,32 kHz Sync Timer idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 1. " ST_GPT12 ,GPTIMER 12 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST_GPT1 ,GPTIMER 1 idle status" "Accessed,Not accessed"
|
|
group.long 0xC30++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_WKUP,Automatic Control Of The WAKEUP Modules Interface Clock Activity"
|
|
bitfld.long 0x00 5. " AUTO_WDT2 ,WDTIMER 2 autoidle control" "Unrelated,Related"
|
|
bitfld.long 0x00 4. " AUTO_WDT1 ,WDTIMER 1 (Secure) auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AUTO_GPIO1 ,GPIO 1 autoidle control" "Unrelated,Related"
|
|
bitfld.long 0x00 2. " AUTO_32KSYNC ,32 kHz Sync Timer autoidle control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUTO_GPT12 ,GPTIMER 12 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 0. " AUTO_GPT1 ,GPTIMER 1 autoidle control" "Unrelated,Related"
|
|
group.long 0xC40++0x3
|
|
line.long 0x00 "CM_CLKSEL_WKUP,WAKEUP Domain Modules Source Clock Selection"
|
|
bitfld.long 0x00 1.--2. " CLKSEL_RM ,Selects the Reset Manager clock" "Reserved,L4_ICLK/1,L4_ICLK/2,?..."
|
|
bitfld.long 0x00 0. " CLKSEL_GPT1 ,Selects GPTIMER 1 source clock" "32K_FCLK,SYS_CLK"
|
|
group.long 0xD00++0x7 "Clock Control Registers"
|
|
line.long 0x00 "CM_CLKEN_PLL,DLL3 And DPLL4 Modes Control"
|
|
bitfld.long 0x00 31. " PWRDN_EMU_PERIPH ,DPLL4_M6X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PWRDN_DSS1 ,DPLL4_M4X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PWRDN_TV ,DPLL4_M3X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PWRDN_96M ,DPLL4_M2X2_CLK path power-down control" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 26. " EN_PERIPH_DPLL_LPMODE ,LP mode of the DPLL4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PERIPH_DPLL_RAMPTIME ,Frequency ramp time total duration control" "Disabled,2-40,4-80,12-240"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PERIPH_DPLL_FREQSEL ,Select proper range of the DPLL4 internal frequency (MHz)" "Reserved,Reserved,Reserved,0.75-1.0,1.0-1.25,1.25-1.5,1.5-1.75,1.75-2.1,Reserved,Reserved,Reserved,7.5-10,10-12.5,12.5-15,15-17.5,17.5-21"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EN_PERIPH_DPLL_DRIFTGUARD ,Automatic recalibration feature of the DPLL4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " EN_PERIPH_DPLL ,DPLL4 control" "Reserved,Low power stop,Reserved,Reserved,Reserved,Reserved,Reserved,Lock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PWRDN_EMU_CORE ,DPLL3_M3X2 HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN_CORE_DPLL_LPMODE ,LP mode of the DPLL3 enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 8.--9. " CORE_DPLL_RAMPTIME ,Frequency ramp time total duration" "Disabled,2-40,4-80,12-240"
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|
textline " "
|
|
bitfld.long 0x00 4.--7. " CORE_DPLL_FREQSEL ,Select proper range of the DPLL3 internal frequency (MHz)" "Reserved,Reserved,Reserved,0.75-1.0,1.0-1.25,1.25-1.5,1.5-1.75,1.75-2.1,Reserved,Reserved,Reserved,7.5-10,10-12.5,12.5-15,15-17.5,17.5-21"
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|
textline " "
|
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bitfld.long 0x00 3. " EN_CORE_DPLL_DRIFTGUARD ,Automatic recalibration feature of the DPLL3 enable" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x00 0.--2. " EN_CORE_DPLL ,DPLL3 control" "Reserved,Reserved,Reserved,Reserved,Reserved,Low power bypass,Fast relock bypass,Lock"
|
|
line.long 0x04 "CM_CLKEN2_PLL,DPLL5 Modes Control"
|
|
bitfld.long 0x04 10. " EN_PERIPH2_DPLL_LPMODE ,LP mode of the DPLL5 enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 8.--9. " PERIPH2_DPLL_RAMPTIME ,Frequency ramp time total duration control" "Disabled,2-40,4-80,12-240"
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|
textline " "
|
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bitfld.long 0x04 4.--7. " PERIPH2_DPLL_FREQSEL ,Proper range of the second PERIPHERAL DPLL internal frequency" "Reserved,Reserved,Reserved,0.75-1.0,1.0-1.25,1.25-1.5,1.5-1.75,1.75-2.1,Reserved,Reserved,Reserved,7.5-10,10-12.5,12.5-15,15-17.5,17.5-21"
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textline " "
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bitfld.long 0x04 3. " EN_PERIPH2_DPLL_DRIFTGUARD ,Automatic recalibration feature of the DPLL5 enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x04 0.--2. " EN_PERIPH2_DPLL ,DPLL5 control" "Reserved,Low power stop mode,Reserved,Reserved,Reserved,Reserved,Reserved,Lock"
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|
rgroup.long 0xD20++0x7
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line.long 0x00 "CM_IDLEST_CKGEN,Master Clock Activity Monitor"
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|
bitfld.long 0x00 13. " ST_EMU_PERIPH_CLK ,Emulation clock activity at the output stage of the DPLL4" "Not active,Active"
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textline " "
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bitfld.long 0x00 11. " ST_DSS1_CLK ,DSS functional clock 1 activity at the output stage of the DPLL4" "Not active,Active"
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textline " "
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bitfld.long 0x00 10. " ST_TV_CLK ,TV clock activity at the output stage of the DPLL4" "Not active,Active"
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textline " "
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bitfld.long 0x00 9. " ST_FUNC96M_CLK ,96 MHz clock activity at the output stage of the DPLL4" "Not active,Active"
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|
textline " "
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bitfld.long 0x00 8. " ST_EMU_CORE_CLK ,Emulation clock activity at the output stage of the DPLL3" "Not active,Active"
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textline " "
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bitfld.long 0x00 5. " ST_54M_CLK ,Functional clock 54 MHz activity" "Not active,Active"
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|
textline " "
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bitfld.long 0x00 4. " ST_12M_CLK ,Functional clock 12 MHz activity" "Not active,Active"
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|
textline " "
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bitfld.long 0x00 3. " ST_48M_CLK ,Functional clock 48 MHz activity" "Not active,Active"
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textline " "
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bitfld.long 0x00 2. " ST_96M_CLK ,Functional clock 96 MHz activity" "Not active,Active"
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textline " "
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bitfld.long 0x00 1. " ST_PERIPH_CLK ,DPLL4 clock activity" "Bypassed,Locked"
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|
textline " "
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bitfld.long 0x00 0. " ST_CORE_CLK ,DPLL3 clock activity" "Bypassed,Locked"
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line.long 0x04 "CM_IDLEST2_CKGEN,Master Clock Activity Monitor"
|
|
bitfld.long 0x04 3. " ST_FUNC120M_CLK ,120 MHz clock activity at the output stage of the DPLL5" "Not active,Active"
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textline " "
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bitfld.long 0x04 1. " ST_120M_CLK ,Functional clock 120 MHz activity" "Not active,Active"
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textline " "
|
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bitfld.long 0x04 0. " ST_PERIPH2_CLK ,DPLL5 clock activity" "Bypassed,Locked"
|
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group.long 0xD30++0x7
|
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line.long 0x00 "CM_AUTOIDLE_PLL,Automatic Control Over The DPLL3 And DPLL4 Activity"
|
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bitfld.long 0x00 3.--5. " AUTO_PERIPH_DPLL ,DPLL4 automatic control" "Disabled,Low power stop,?..."
|
|
textline " "
|
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bitfld.long 0x00 0.--2. " AUTO_CORE_DPLL ,DPLL3 automatic control" "Disabled,Low power stop,Reserved,Reserved,Reserved,Idle bypass low power,?..."
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line.long 0x04 "CM_AUTOIDLE2_PLL,Automatic Control Over The DPLL5 Activity"
|
|
bitfld.long 0x04 0.--2. " AUTO_PERIPH2_DPLL ,DPLL5 automatic control" "Disabled,Low power stop,?..."
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group.long 0xD40++0x13
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line.long 0x00 "CM_CLKSEL1_PLL,Master Clock Frequencies Selection Register"
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bitfld.long 0x00 27.--31. " CORE_DPLL_CLKOUT_DIV ,DPLL3 output clock divider factor M2" "Reserved,clk/1,clk/2,clk/3,clk/4,clk/5,clk/6,clk/7,clk/8,clk/9,clk/10,clk/11,clk/12,clk/13,clk/14,clk/15,clk/16,clk/17,clk/18,clk/19,clk/20,clk/21,clk/22,clk/23,clk/24,clk/25,clk/26,clk/27,clk/28,clk/29,clk/30,clk/31"
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|
textline " "
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hexmask.long.word 0x00 16.--26. 1. " CORE_DPLL_MULT ,DPLL3 multiplier factor"
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textline " "
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hexmask.long.byte 0x00 8.--14. 1. " CORE_DPLL_DIV ,DPLL3 divider factor"
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textline " "
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bitfld.long 0x00 6. " SOURCE_96M ,Selection of 96M_FCLK source" "CM_96M_FCLK,CM_SYS_CLK"
|
|
textline " "
|
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bitfld.long 0x00 5. " SOURCE_54M ,Selection of 54MHz functional clock source" "DPLL4_M3X2_CLK,Sys_altclk"
|
|
textline " "
|
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bitfld.long 0x00 3. " SOURCE_48M ,Selection of Func_12M_clk and Func_48M_clk source" "CM_96M_FCLK,Sys_altclk"
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line.long 0x04 "CM_CLKSEL2_PLL,Master Clock Frequencies Selection Register"
|
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hexmask.long.word 0x04 8.--18. 1. " PERIPH_DPLL_MULT ,DPLL4 multiplier factor"
|
|
textline " "
|
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hexmask.long.byte 0x04 0.--6. 1. " PERIPH_DPLL_DIV ,DPLL4 divider factor"
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line.long 0x08 "CM_CLKSEL3_PLL,Master Clock Frequencies Selection Register"
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bitfld.long 0x08 0.--4. " DIV_96M ,96 MHz clock divider factor M2" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
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line.long 0x0C "CM_CLKSEL4_PLL,Master Clock Frequencies Selection Register"
|
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hexmask.long.word 0x0C 8.--18. 1. " PERIPH2_DPLL_MULT ,DPLL5 multiplier factor (0 to 2047)"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " PERIPH2_DPLL_DIV ,DPLL5 divider factor (0 to 127)"
|
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line.long 0x10 "CM_CLKSEL5_PLL,Master Clock Frequencies Control Selection Register"
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|
bitfld.long 0x10 0.--4. " DIV_120M ,120 MHz clock divider factor M2" "Reserved,DPLL5 clk/1,DPLL5 clk/2,DPLL5 clk/3,DPLL5 clk/4,DPLL5 clk/5,DPLL5 clk/6,DPLL5 clk/7,DPLL5 clk/8,DPLL5 clk/9,DPLL5 clk/10,DPLL5 clk/11,DPLL5 clk/12,DPLL5 clk/13,DPLL5 clk/14,DPLL5 clk/15,DPLL5 clk/16,?..."
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group.long 0xD70++0x3
|
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line.long 0x00 "CM_CLKOUT_CTRL,SYS_CLKOUT2 Output Clock Control"
|
|
bitfld.long 0x00 7. " CLKOUT2_EN ,External output clock activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CLKOUT2_DIV ,External output clock division control" "sys_clkout2/1,sys_clkout2/2,sys_clkout2/4,sys_clkout2/8,sys_clkout2/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKOUT2SOURCE ,External output clock source" "CORE_CLK,CM_SYS_CLK,CM_96M_FCLK,54 MHz clock"
|
|
group.long 0xE00++0x3 "DSS"
|
|
line.long 0x00 "CM_FCLKEN_DSS,Controls The Modules Functional Clock Activity"
|
|
bitfld.long 0x00 2. " EN_TV ,DSS_TV_FCLK functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN_DSS2 ,Display Sub-System functional clock 2 control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_DSS1 ,Display Sub-System functional clock 1 control" "Disabled,Enabled"
|
|
group.long 0xE10++0x3
|
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line.long 0x00 "CM_ICLKEN_DSS,Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_DSS ,Display sub-system interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xE20++0x3
|
|
line.long 0x00 "CM_IDLEST_DSS,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 1. " ST_DSS_IDLE ,Display Sub-System idle status" "Active,Idle"
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|
bitfld.long 0x00 0. " ST_DSS_STDBY ,Display Sub-System standby status" "Active,Standby"
|
|
group.long 0xE30++0x3
|
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line.long 0x00 "CM_AUTOIDLE_DSS,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " AUTO_DSS ,Display Sub-System auto clock control" "Unrelated,Related"
|
|
group.long 0xE40++0xb
|
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line.long 0x00 "CM_CLKSEL_DSS,Modules Clock Selection"
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bitfld.long 0x00 8.--12. " CLKSEL_TV ,TV functional clock divider factor DPLL4 M3" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
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|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKSEL_DSS1 ,DPLL4 M4 divide factor for DSS1_ALWON_FCLK" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
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line.long 0x04 "CM_SLEEPDEP_DSS,Sleep Transition Dependency Of DSS Domain Enable"
|
|
bitfld.long 0x04 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EN_CORE ,CORE domain dependency" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_DSS,Domain Power State Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_DSS ,Clock state transition of the DSS clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0xE4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_DSS,Status On The OCP interface Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_DSS ,Clock activity status" "Not active,Active"
|
|
group.long 0x1000++0x3 "PER"
|
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line.long 0x00 "CM_FCLKEN_PER,Modules Functional Clock Activity"
|
|
bitfld.long 0x00 17. " EN_GPIO6 ,GPIO 6 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_GPIO5 ,GPIO 5 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_GPIO4 ,GPIO 4 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_GPIO3 ,GPIO 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_GPIO2 ,GPIO 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_WDT3 ,WDTIMER 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_UART3 ,UART3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_GPT9 ,GPTIMER 9 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_GPT8 ,GPTIMER 8 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EN_GPT7 ,GPTIMER 7 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_GPT6 ,GPTIMER 6 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_GPT5 ,GPTIMER 5 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_GPT4 ,GPTIMER 4 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN_GPT3 ,GPTIMER 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPT2 ,GPTIMER 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_MCBSP4 ,McBSP 4 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MCBSP3 ,McBSP 3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_MCBSP2 ,McBSP 2 functional clock control" "Disabled,Enabled"
|
|
group.long 0x1010++0x3
|
|
line.long 0x00 "CM_ICLKEN_PER,Modules Interface Clock Activity"
|
|
bitfld.long 0x00 17. " EN_GPIO6 ,GPIO 6 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_GPIO5 ,GPIO 5 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_GPIO4 ,GPIO 4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_GPIO3 ,GPIO 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_GPIO2 ,GPIO 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_WDT3 ,WDTIMER 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_UART3 ,UART3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_GPT9 ,GPTIMER 9 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_GPT8 ,GPTIMER 8 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EN_GPT7 ,GPTIMER 7 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_GPT6 ,GPTIMER 6 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_GPT5 ,GPTIMER 5 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_GPT4 ,GPTIMER 4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN_GPT3 ,GPTIMER 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPT2 ,GPTIMER 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_MCBSP4 ,McBSP 4 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MCBSP3 ,McBSP 3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_MCBSP2 ,McBSP 2 interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x00 "CM_IDLEST_PER,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 17. " ST_GPIO6 ,GPIO 6 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 16. " ST_GPIO5 ,GPIO 5 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ST_GPIO4 ,GPIO 4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 14. " ST_GPIO3 ,GPIO 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ST_GPIO2 ,GPIO 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 12. " ST_WDT3 ,WDTIMER 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ST_UART3 ,UART3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 10. " ST_GPT9 ,GPTIMER 9 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ST_GPT8 ,GPTIMER 8 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 8. " ST_GPT7 ,GPTIMER 7 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ST_GPT6 ,GPTIMER 6 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 6. " ST_GPT5 ,GPTIMER 5 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ST_GPT4 ,GPTIMER 4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 4. " ST_GPT3 ,GPTIMER 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ST_GPT2 ,GPTIMER 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 2. " ST_MCBSP4 ,McBSP 4 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ST_MCBSP3 ,McBSP 3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 0. " ST_MCBSP2 ,McBSP 2 idle status" "Accessed,Not accessed"
|
|
group.long 0x1030++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_PER,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 17. " AUTO_GPIO6 ,GPIO 6 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 16. " AUTO_GPIO5 ,GPIO 5 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTO_GPIO4 ,GPIO 4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 14. " AUTO_GPIO3 ,GPIO 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GPIO2 ,GPIO 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 12. " AUTO_WDT3 ,WDTIMER 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_UART3 ,UART3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 10. " AUTO_GPT9 ,GPTIMER 9 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTO_GPT8 ,GPTIMER 8 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 8. " AUTO_GPT7 ,GPTIMER 7 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AUTO_GPT6 ,GPTIMER 6 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 6. " AUTO_GPT5 ,GPTIMER 5 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AUTO_GPT4 ,GPTIMER 4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 4. " AUTO_GPT3 ,GPTIMER 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AUTO_GPT2 ,GPTIMER 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 2. " AUTO_MCBSP4 ,McBSP 4 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUTO_MCBSP3 ,McBSP 3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 0. " AUTO_MCBSP2 ,McBSP 2 auto clock control" "Unrelated,Related"
|
|
group.long 0x1040++0xb
|
|
line.long 0x00 "CM_CLKSEL_PER,PER domain modules source clock selection"
|
|
bitfld.long 0x00 7. " CLKSEL_GPT9 ,Selects GPTIMER 9 source clock" "32K_FCLK,SYS_CLK"
|
|
bitfld.long 0x00 6. " CLKSEL_GPT8 ,Selects GPTIMER 8 source clock" "32K_FCLK,SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLKSEL_GPT7 ,Selects GPTIMER 7 source clock" "32K_FCLK,SYS_CLK"
|
|
bitfld.long 0x00 4. " CLKSEL_GPT6 ,Selects GPTIMER 6 source clock" "32K_FCLK,SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKSEL_GPT5 ,Selects GPTIMER 5 source clock" "32K_FCLK,SYS_CLK"
|
|
bitfld.long 0x00 2. " CLKSEL_GPT4 ,Selects GPTIMER 4 source clock" "32K_FCLK,SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKSEL_GPT3 ,Selects GPTIMER 3 source clock" "32K_FCLK,SYS_CLK"
|
|
bitfld.long 0x00 0. " CLKSEL_GPT2 ,Selects GPTIMER 2 source clock" "32K_FCLK,SYS_CLK"
|
|
line.long 0x04 "CM_SLEEPDEP_PER,Sleep Transition Dependency Of PERIPHERAL Domain Enable"
|
|
bitfld.long 0x04 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_PER,HW Supervised Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_PER ,Clock state transition of the PERIPHERAL clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0x104C++0x3
|
|
line.long 0x00 "CM_CLKSTST_PER,Status On The OCP interface Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_PER ,Interface clock activity status" "Not active,Active"
|
|
group.long 0x1140++0x3 "EMU"
|
|
line.long 0x00 "CM_CLKSEL1_EMU,Modules Clock Selection"
|
|
bitfld.long 0x00 24.--28. " DIV_DPLL4 ,DPLL4 M6 clock divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " DIV_DPLL3 ,DPLL3_M3X2 clock divider factor" "Reserved,DPLL3 clk/1,DPLL3 clk/2,DPLL3 clk/3,DPLL3 clk/4,DPLL3 clk/5,DPLL3 clk/6,DPLL3 clk/7,DPLL3 clk/8,DPLL3 clk/9,DPLL3 clk/10,DPLL3 clk/11,DPLL3 clk/12,DPLL3 clk/13,DPLL3 clk/14,DPLL3 clk/15,DPLL3 clk/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " CLKSEL_TRACECLK ,Selects the TRACE clock" "Reserved,SCLK/1,SCLK/2,Reserved,SCLK/4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLKSEL_PCLK ,Selects the PCLK clock" "Reserved,Reserved,SCLK/2,SCLK/3,SCLK/4,Reserved,SCLK/6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CLKSEL_PCLKX2 ,Selects the PCLKx2 clock" "Reserved,SCLK/1,SCLK/2,SCLK/3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CLKSEL_ATCLK ,Selects the ATCLK clock" "Reserved,SCLK/1,SCLK/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TRACE_MUX_CTRL ,Selection of TRACECLK.FCLK source clock" "SYS_CLK,EMU_CORE_ALWON_CLK,EMU_PER_ALWON,EMU_MPU_ALWON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX_CTRL ,Source clock selection (ATCLK; PCLK and PCLKx2)" "SYS_CLK,EMU_CORE_ALWON_CLK,EMU_PER_ALWON,EMU_MPU_ALWON_CLK"
|
|
group.long 0x1148++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_EMU,SW and HW Supervised Transition Enable"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_EMU ,Clock state transition of the EMULATION clock domain" "Reserved,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0x114C++0x3
|
|
line.long 0x00 "CM_CLKSTST_EMU,Status on The Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_EMU ,Clock activity status" "Not active,Active"
|
|
group.long 0x1150++0x7
|
|
line.long 0x00 "CM_CLKSEL2_EMU,Override Controls Over The DPLL3"
|
|
bitfld.long 0x00 19. " OVERRIDE_ENABLE ,Emulation override control enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " CORE_DPLL_EMU_MULT ,DPLL3 override multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CORE_DPLL_EMU_DIV ,DPLL3 override divider factor"
|
|
line.long 0x04 "CM_CLKSEL3_EMU,Override Controls Over The PERIPHERAL DPLL"
|
|
bitfld.long 0x04 19. " OVERRIDE_ENABLE ,Emulation override control enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 8.--18. 1. " PERIPH_DPLL_EMU_MULT ,DPLL4 override multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " PERIPH_DPLL_EMU_DIV ,DPLL4 override divider factor"
|
|
group.long 0x129C++0x3 "Global"
|
|
line.long 0x00 "CM_POLCTRL,Polarity Of Device Outputs Control Signals"
|
|
bitfld.long 0x00 0. " CLKOUT2_POL ,External output clock 2 polarity" "sys_clkout2 low,sys_clkout2 high"
|
|
rgroup.long 0x1320++0x3 "NEON"
|
|
line.long 0x00 "CM_IDLEST_NEON,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 0. " ST_NEON ,NEON standby status" "Active,Standby"
|
|
group.long 0x1348++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_NEON,HW Supervised Domain Power State Transition"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_NEON ,Clock state transition of the NEON clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
group.long 0x1400++0x3 "USBHOST_CM"
|
|
line.long 0x00 "CM_FCLKEN_USBHOST,Controls The Modules Functional Clock Activity"
|
|
bitfld.long 0x00 1. " EN_USBHOST2 ,USB HOST 120-MHz functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_USBHOST1 ,USB HOST 48-MHz functional clock control" "Disabled,Enabled"
|
|
group.long 0x1410++0x3
|
|
line.long 0x00 "CM_ICLKEN_USBHOST,Controls The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_USBHOST ,USB HOST Interface Clock Control" "Disabled,Enabled"
|
|
rgroup.long 0x1420++0x3
|
|
line.long 0x00 "CM_IDLEST_USBHOST,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 1. " ST_USBHOST_IDLE ,USB HOST idle status" "Active,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST_USBHOST_STDBY ,USB HOST standby status" "Active,Standby"
|
|
group.long 0x1430++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_USBHOST,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " AUTO_USBHOST ,USB HOST auto clock control" "Unrelated,Related"
|
|
group.long 0x1444++0x7
|
|
line.long 0x00 "CM_SLEEPDEP_USBHOST,Sleep Transition Dependency Of USB HOST Domain Control"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
line.long 0x04 "CM_CLKSTCTRL_USBHOST,Domain Power State Transition Control"
|
|
bitfld.long 0x04 0.--1. " CLKTRCTRL_USBHOST ,Controls the clock state transition of the USB HOST clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0x144C++0x3
|
|
line.long 0x00 "CM_CLKSTST_USBHOST,Status On The Interface Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_USBHOST ,Interface clock activity status" "Not active,Active"
|
|
width 0xb
|
|
tree.end
|
|
tree "Power Reset Management"
|
|
base ad:0x48306000
|
|
width 23.
|
|
rgroup.long 0x804++0x3 "OCP System Registers"
|
|
line.long 0x00 "PRM_REVISION,IP revision code"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MINOR ,Minor revision"
|
|
group.long 0x814++0xb
|
|
line.long 0x00 "PRM_SYSCONFIG,OCP Interface Various Parameters Control"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Auto"
|
|
line.long 0x04 "PRM_IRQSTATUS_MPU,Interrupt Status Register"
|
|
eventfld.long 0x04 25. " SND_PERIPH_DPLL_ST ,DPLL5 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 7. " MPU_DPLL_ST ,DPLL1 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 6. " PERIPH_DPLL_ST ,DPLL4 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 5. " CORE_DPLL_ST ,DPLL3 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " TRANSITION_ST ,Software supervised transition completed event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 3. " EVGENOFF_ST ,Event Generator endOFFtime status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 2. " EVGENON_ST ,Event Generator endONtime status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 0. " WKUP_ST ,MPU peripherals group wake-up event status" "No interrupt,Interrupt"
|
|
line.long 0x08 "PRM_IRQENABLE_MPU,PRM Interrupt Request Enable MPU Register"
|
|
bitfld.long 0x08 25. " SND_PERIPH_DPLL_RECAL_EN ,DPLL5 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MPU_DPLL_RECAL_EN ,DPLL1 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PERIPH_DPLL_RECAL_EN ,DPLL4 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CORE_DPLL_RECAL_EN ,DPLL3 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TRANSITION_EN ,Software supervised transition completed event mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " EVGENOFF_EN ,Event Generator endOFFtime mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EVGENON_EN ,Event Generator endONtime mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WKUP_EN ,MPU peripherals group wake-up mask" "Masked,Enabled"
|
|
group.long 0x958++0x3 "MPU"
|
|
line.long 0x00 "RM_RSTST_MPU,Different Reset Sources Of The MPU Domain Log"
|
|
eventfld.long 0x00 11. " EMULATION_MPU_RST ,Emulation reset" "No reset,Reset"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x9C8++0x3
|
|
line.long 0x00 "PM_WKDEP_MPU,Wake-up Of The MPU Domain Enable"
|
|
bitfld.long 0x00 7. " EN_PER ,PERIPHERAL domain dependency" "Independent,Woken-up"
|
|
bitfld.long 0x00 5. " EN_DSS ,DSS domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Independent,Woken-up"
|
|
group.long 0x9D4++0xb
|
|
line.long 0x00 "PM_EVGENCTRL_MPU,Event Generator Control"
|
|
bitfld.long 0x00 3.--4. " OFFLOADMODE ,OFF load mode setting" "Update PM_EVGENOFFTIM_MPU,Reserved,MPU standby,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ONLOADMODE ,ON load mode setting" "Update PM_EVGENONTIM_MPU,MPU standby,Reserved,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Event generator control" "Disabled,Enabled"
|
|
line.long 0x04 "PM_EVGENONTIM_MPU,ON Count Duration Of The Event Generator"
|
|
line.long 0x08 "PM_EVGENOFFTIM_MPU,OFF Count Duration Of The Event Generator"
|
|
rgroup.long 0x9E4++0x3
|
|
line.long 0x00 "PM_PWSTST_MPU,MPU Domain Power State Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
group.long 0xA58++0x3 "CORE"
|
|
line.long 0x00 "RM_RSTST_CORE,Different Reset Sources Of The CORE Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xAA0++0x7
|
|
line.long 0x00 "PM_WKEN1_CORE,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 30. " EN_MMC3 ,MMC SDIO 3 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EN_MMC2 ,MMC SDIO 2 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " EN_MMC1 ,MMC SDIO 1 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " EN_MCSPI4 ,McSPI 4 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EN_MCSPI3 ,McSPI 3 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " EN_MCSPI2 ,McSPI 2 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EN_MCSPI1 ,McSPI 1 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EN_I2C3 ,I2C 3 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_I2C2 ,I2C 2 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_I2C1 ,I2C 1 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EN_UART2 ,UART 2 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EN_UART1 ,UART 1 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EN_GPT11 ,GPTIMER 11 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EN_GPT10 ,GPTIMER 10 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN_MCBSP5 ,McBSP 5 wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EN_MCBSP1 ,McBSP 1 wake-up control" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL1_CORE,Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x04 30. " GRPSEL_MMC3 ,MMC 3 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 25. " GRPSEL_MMC2 ,MMC 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 24. " GRPSEL_MMC1 ,MMC 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 21. " GRPSEL_MCSPI4 ,McSPI 4 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GRPSEL_MCSPI3 ,McSPI 3 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 19. " GRPSEL_MCSPI2 ,McSPI 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 18. " GRPSEL_MCSPI1 ,McSPI 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 17. " GRPSEL_I2C3 ,I2C 3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GRPSEL_I2C2 ,I2C 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 15. " GRPSEL_I2C1 ,I2C 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 14. " GRPSEL_UART2 ,UART 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 13. " GRPSEL_UART1 ,UART 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 12. " GRPSEL_GPT11 ,GPTIMER 11 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 11. " GRPSEL_GPT10 ,GPTIMER 10 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 10. " GRPSEL_MCBSP5 ,McBSP 5 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 9. " GRPSEL_MCBSP1 ,McBSP 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
group.long 0xAB0++0x3
|
|
line.long 0x00 "PM_WKST1_CORE,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 30. " ST_MMC3 ,MMC 3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ST_MMC2 ,MMC 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ST_MMC1 ,MMC 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ST_MCSPI4 ,McSPI 4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ST_MCSPI3 ,McSPI 3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ST_MCSPI2 ,McSPI 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 18. " ST_MCSPI1 ,McSPI 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ST_I2C3 ,I2C 3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ST_I2C2 ,I2C 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ST_I2C1 ,I2C 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ST_UART2 ,UART 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ST_UART1 ,UART 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ST_GPT11 ,GPTIMER 11 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ST_GPT10 ,GPTIMER 10 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ST_MCBSP5 ,McBSP 5 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ST_MCBSP1 ,McBSP 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
group.long 0xAB8++0x3
|
|
line.long 0x00 "PM_WKST3_CORE,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 2. " ST_USBTLL ,USB TLL Wake-up status" "Not occurred/masked,Occurred"
|
|
rgroup.long 0xAE4++0x3
|
|
line.long 0x00 "PM_PWSTST_CORE,Power State Transition Of The CORE Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
group.long 0xAF0++0x3
|
|
line.long 0x00 "PM_WKEN3_CORE,Enabling/Disabling Modules Wake-up Events"
|
|
bitfld.long 0x00 2. " EN_USBTLL ,USB TLL wake-up control" "Disabled,Enabled"
|
|
group.long 0xaf8++0x03
|
|
line.long 0x00 "PM_MPUGRPSEL3_CORE,Selecting The Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x00 2. " GRPSEL_USBTLL ,Select the USB TLL in the MPU wake-up events group" "Not attached,Attached"
|
|
group.long 0xB58++0x3 "SGX"
|
|
line.long 0x00 "RM_RSTST_SGX,Different Reset Sources Of The SGX Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xBC8++0x3
|
|
line.long 0x00 "PM_WKDEP_SGX,Wake-up Of The SGX Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
rgroup.long 0xBE4++0x3
|
|
line.long 0x00 "PM_PWSTST_SGX,Power State Transition Of The SGX Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
group.long 0xCA0++0x7 "WKUP"
|
|
line.long 0x00 "PM_WKEN_WKUP,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 7. " EN_SR2 ,Smart Refex 2 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EN_GPIO1 ,GPIO 1 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_GPT12 ,GPTIMER 12 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_GPT1 ,GPTIMER 1 wake-up enable" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL_WKUP,MPU Wake-up Events Group"
|
|
bitfld.long 0x04 7. " GRPSEL_SR2 ,Smart Reflex 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 3. " GRPSEL_GPIO1 ,GPIO 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GRPSEL_GPT12 ,GPTIMER 12 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 0. " GRPSEL_GPT1 ,GPTIMER 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
group.long 0xCB0++0x3
|
|
line.long 0x00 "PM_WKST_WKUP,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 7. " ST_SR2 ,Smart Reflex 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ST_GPIO1 ,GPIO 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ST_GPT12 ,GPTIMER 12 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ST_GPT1 ,GPTIMER 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
group.long 0xD40++0x3 "Clock Control Registers"
|
|
line.long 0x00 "PRM_CLKSEL,System Clock Frequency Selection"
|
|
bitfld.long 0x00 0.--2. " SYS_CLKIN_SEL ,System clock input selection (MHz)" "12,13,19.2,26,38.4,16.8,?..."
|
|
group.long 0xD70++0x3
|
|
line.long 0x00 "PRM_CLKOUT_CTRL,SYS_CLKOUT1 Output Clock Control"
|
|
bitfld.long 0x00 7. " CLKOUT_EN ,External output clock activity (sys_clkout1)" "Disabled,Enabled"
|
|
group.long 0xE58++0x3 "DSS"
|
|
line.long 0x00 "RM_RSTST_DSS,Different Reset Sources Of The DSS Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xEA0++0x3
|
|
line.long 0x00 "PM_WKEN_DSS,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 0. " EN_DSS ,DSS Wake-up enable" "Disabled,Enabled"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x00 "PM_WKDEP_DSS,Wake-up Of The DISPLAY Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
rgroup.long 0xEE4++0x3
|
|
line.long 0x00 "PM_PWSTST_DSS,Power State Transition Of The DSS Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
group.long 0x1058++0x3 "PER"
|
|
line.long 0x00 "RM_RSTST_PER,Different Reset Sources Of The PERIPHERAL Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x10A0++0x7
|
|
line.long 0x00 "PM_WKEN_PER,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 17. " EN_GPIO6 ,GPIO6 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_GPIO5 ,GPIO5 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_GPIO4 ,GPIO4 Wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EN_GPIO3 ,GPIO3 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EN_GPIO2 ,GPIO2 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EN_UART3 ,UART3 Wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN_GPT9 ,GPT9 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EN_GPT8 ,GPT8 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EN_GPT7 ,GPT7 Wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_GPT6 ,GPT6 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_GPT5 ,GPT5 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN_GPT4 ,GPT4 Wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_GPT3 ,GPT3 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EN_GPT2 ,GPT2 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_MCBSP4 ,MCBSP4 Wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MCBSP3 ,MCBSP3 Wake-up control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_MCBSP2 ,MCBSP2 Wake-up control" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL_PER,Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x04 17. " GRPSEL_GPIO6 ,GPIO6 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 16. " GRPSEL_GPIO5 ,GPIO5 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GRPSEL_GPIO4 ,GPIO4 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 14. " GRPSEL_GPIO3 ,GPIO3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 13. " GRPSEL_GPIO2 ,GPIO2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 11. " GRPSEL_UART3 ,UART3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 10. " GRPSEL_GPT9 ,GPT9 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 9. " GRPSEL_GPT8 ,GPT8 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 8. " GRPSEL_GPT7 ,GPT7 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 7. " GRPSEL_GPT6 ,GPT6 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GRPSEL_GPT5 ,GPT5 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 5. " GRPSEL_GPT4 ,GPT4 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GRPSEL_GPT3 ,GPT3 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 3. " GRPSEL_GPT2 ,GPT2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 2. " GRPSEL_MCBSP4 ,MCBSP4 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 1. " GRPSEL_MCBSP3 ,MCBSP3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 0. " GRPSEL_MCBSP2 ,MCBSP2 in the MPU wake-up events group" "Not attached,Attached"
|
|
group.long 0x10B0++0x3
|
|
line.long 0x00 "PM_WKST_PER,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 17. " ST_GPIO6 ,GPIO6 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ST_GPIO5 ,GPIO5 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ST_GPIO4 ,GPIO4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ST_GPIO3 ,GPIO3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ST_GPIO2 ,GPIO2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ST_UART3 ,UART3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ST_GPT9 ,GPT9 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ST_GPT8 ,GPT8 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ST_GPT7 ,GPT7 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ST_GPT6 ,GPT6 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ST_GPT5 ,GPT5 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ST_GPT4 ,GPT4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ST_GPT3 ,GPT3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ST_GPT2 ,GPT2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ST_MCBSP4 ,MCBSP4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ST_MCBSP3 ,MCBSP3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ST_MCBSP2 ,MCBSP2 Wake-up status" "Not occurred/masked,Occurred"
|
|
group.long 0x10C8++0x3
|
|
line.long 0x00 "PM_WKDEP_PER,Wake-up Of The PERIPHERAL Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Independent,Not woken-up"
|
|
rgroup.long 0x10E4++0x3
|
|
line.long 0x00 "PM_PWSTST_PER,Power State Transition Of The PERIPHERAL Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
group.long 0x1158++0x3 "EMU"
|
|
line.long 0x00 "RM_RSTST_EMU,Different Reset Sources Of The EMULATION Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x1250++0xb "Global Registers"
|
|
line.long 0x00 "PRM_RSTCTRL,Global Software And DPLL3 Reset Control"
|
|
bitfld.long 0x00 2. " RST_DPLL3 ,DPLL3 software reset control" "Cleared,Asserted"
|
|
bitfld.long 0x00 1. " RST_GS ,Global software reset control" "Cleared,Asserted"
|
|
line.long 0x04 "PRM_RSTTIME,Reset Duration Control"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RSTTIME1 ,(Global) Reset duration 1"
|
|
line.long 0x08 "PRM_RSTST,Global Reset Sources Log"
|
|
eventfld.long 0x08 10. " ICECRUSHER_RST ,IceCrusher reset event" "No reset,Reset"
|
|
eventfld.long 0x08 9. " ICEPICK_RST ,IcePick reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 6. " EXTERNAL_WARM_RST ,External warm reset event" "No reset,Reset"
|
|
eventfld.long 0x08 5. " SECURE_WD_RST ,Secure watchdog reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 4. " MPU_WD_RST ,MPU watchdog reset event" "No reset,Reset"
|
|
eventfld.long 0x08 3. " SECURITY_VIOL_RST ,Security violation reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 1. " GLOBAL_SW_RST ,Global software reset event" "No reset,Reset"
|
|
eventfld.long 0x08 0. " GLOBAL_COLD_RST ,Power-up (cold) reset event" "No reset,Reset"
|
|
group.long 0x1270++0x3
|
|
line.long 0x00 "PRM_CLKSRC_CTRL,Device Source Clock Control"
|
|
bitfld.long 0x00 6.--7. " SYSCLKDIV ,System clock input divider" "Reserved,EXCLK/1,EXCLK/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " AUTOEXTCLKMODE ,External clock request and oscillator control" "Asserted/Osc active,Sleep/Retention/Off,Retention/Off,Off"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SYSCLKSEL ,Mode of the oscillator" "Bypass,Oscillator,Reserved,Unknow state"
|
|
rgroup.long 0x1280++0x3
|
|
line.long 0x00 "PRM_OBS,Observable Signals Log"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " OBS_BUS ,Indicates the current value on the observable bus"
|
|
group.long 0x1358++0x3 "NEON"
|
|
line.long 0x00 "RM_RSTST_NEON,Different Reset Sources Of The NEON Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x13C8++0x3
|
|
line.long 0x00 "PM_WKDEP_NEON,Wake-up Of The NEON Domain Enable"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
rgroup.long 0x13E4++0x3
|
|
line.long 0x00 "PM_PWSTST_NEON,Power State Transition Of The NEON Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
group.long 0x1458++0x3 "USBHOST_PRM"
|
|
line.long 0x00 "RM_RSTST_USBHOST,Different Reset Sources Of The USB HOST Domain Log"
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x14A0++0x7
|
|
line.long 0x00 "PM_WKEN_USBHOST,Modules Wake-up Events Control"
|
|
bitfld.long 0x00 0. " EN_USBHOST ,USB HOST Wake-up enable" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL_USBHOST,Select The Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x04 0. " GRPSEL_USBHOST ,Select the USBHOST in the MPU wake-up events" "Not attached,Attached"
|
|
group.long 0x14B0++0x3
|
|
line.long 0x00 "PM_WKST_USBHOST,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 0. " ST_USBHOST ,USB HOST Wake-up status" "Not occurred/masked,Occurred"
|
|
group.long 0x14C8++0x3
|
|
line.long 0x00 "PM_WKDEP_USBHOST,Wake-up Of The USB HOST Domain Control"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Independent,Woken-up"
|
|
rgroup.long 0x14E4++0x3
|
|
line.long 0x00 "PM_PWSTST_USBHOST,Power State Transition Of The USB HOST Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Reserved,Reserved,Inactive,On"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "L3 Interconnect"
|
|
tree "IA (Initiator Agent Registers)"
|
|
tree "IA_MPUSS"
|
|
base ad:0x68001400
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 29. " INBAND_ERROR_SECONDARY_REP ,Reporting of in-band errors indicating debug error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 25. " RESP_TIMEOUT_REP ,Response timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " RESP_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 29. " INBAND_ERROR_SECONDARY ,Error Status for in-band errors indicating a debug error" "Not received,Received"
|
|
textline " "
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " RESP_TIMEOUT ,Response timeout status" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_WAITING ,Response Waiting" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_SGX"
|
|
base ad:0x68001C00
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_USB_HS_Host"
|
|
base ad:0x68004000
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 25. " RESP_TIMEOUT_REP ,Response timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " RESP_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " RESP_TIMEOUT ,Response timeout status" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_IPSS"
|
|
base ad:0x68004400
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_WAITING ,Response Waiting" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_sDMA_RD"
|
|
base ad:0x68004C00
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_sDMA_WR"
|
|
base ad:0x68005000
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_WAITING ,Response Waiting" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_DSS"
|
|
base ad:0x68005400
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_WAITING ,Response Waiting" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "IA_DAP"
|
|
base ad:0x68005C00
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_CONTROL,Agent Control Register Of IA Block"
|
|
bitfld.quad 0x00 28. " INBAND_ERROR_PRIMARY_REP ,Reporting of in-band errors indicating application error" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " ALL_INBAND_ERROR_REP ,Reporting of all in-band errors" "Not in-band,All in-band"
|
|
textline " "
|
|
bitfld.quad 0x00 26. " BURST_TIMEOUT_REP ,Open burst and ReadEx/Write timeout reporting" "No error,Error"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--18. " BURST_TIMEOUT ,Response Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Normal,Block"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset control for agent and reset control on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_IA_AGENT_STATUS,Agent Status Register"
|
|
eventfld.quad 0x00 28. " INBAND_ERROR_PRIMARY ,Error Status for in-band errors indicating application Error" "Not received,Received"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_TIMEOUT ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals for internal verification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of ReadEx/Write" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_WAITING ,Response Waiting" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_ACTIVE ,Requests outstanding" "0,1"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "0,1"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG,Error Log Register Of IA Block"
|
|
hexmask.quad.word 0x00 32.--47. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Indicates whether error was primary or secondary" "Primary Error,Secondary Error"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_IA_ERROR_LOG_ADDR,Error Log Address Register Of IA_$2 Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "TA (Target Agent Registers)"
|
|
tree "TA_SMS"
|
|
base ad:0x68002000
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
rgroup.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_GPMC"
|
|
base ad:0x68002400
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 24. " SERROR_REP ,SError reporting" "Suppress,Report"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 24. " SERROR ,Serror assertion detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_OCM_RAM"
|
|
base ad:0x68002800
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
rgroup.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_OCM_ROM"
|
|
base ad:0x68002C00
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
rgroup.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_IPSS"
|
|
base ad:0x68006000
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
rgroup.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_SGX"
|
|
base ad:0x68006400
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 24. " SERROR_REP ,SError reporting" "Suppress,Report"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 24. " SERROR ,Serror assertion detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_L4_CORE"
|
|
base ad:0x68006800
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 24. " SERROR_REP ,SError reporting" "Suppress,Report"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 24. " SERROR ,Serror assertion detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_L4_PER"
|
|
base ad:0x68006C00
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 24. " SERROR_REP ,SError reporting" "Suppress,Report"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 24. " SERROR ,Serror assertion detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_L4_EMU"
|
|
base ad:0x68007000
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_CONTROL,Agent Control Register Of TA Block"
|
|
bitfld.quad 0x00 25. " REQ_TIMEOUT_REP ,Request Timeout Reporting" "No reporting,Out of band"
|
|
textline " "
|
|
bitfld.quad 0x00 24. " SERROR_REP ,SError reporting" "Suppress,Report"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " REQ_TIMEOUT ,Request Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REJECT ,Request rejection control" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset output on core" "Inactive,Active"
|
|
group.long 0x28++0x7
|
|
line.quad 0x00 "L3_TA_AGENT_STATUS,Agent Status Register"
|
|
bitfld.quad 0x00 24. " SERROR ,Serror assertion detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " BURST_CLOSE ,Forced burst close status" "Normal,Burst close"
|
|
textline " "
|
|
bitfld.quad 0x00 12.--15. " TIMEBASE ,Observation of timebase signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " REQ_TIMEOUT ,Request timeout status" "Normal,Timeout"
|
|
textline " "
|
|
bitfld.quad 0x00 7. " READEX ,Status of readEx/Write" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.quad 0x00 6. " BURST ,Status of open burst" "Not open,Open"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " RESP_ACTIVE ,Responses outstanding" "No response,Response"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " REQ_WAITING ,Requests waiting" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " CORE_RESET ,Reset input from core interface" "Inactive,Active"
|
|
group.long 0x58++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG,Error Log Register Of TA Block"
|
|
hexmask.quad.word 0x00 32.--41. 1. " REQ_INFO ,MReqInfo bits of command that caused the error"
|
|
textline " "
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple Errors" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
rgroup.long 0x60++0x7
|
|
line.quad 0x00 "L3_TA_ERROR_LOG_ADDR,Error Log Address Register Of TA Block"
|
|
hexmask.quad.long 0x00 0.--31. 1. " ADDR ,Address of the command that caused the error"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "RT (Register Target Registers)"
|
|
base ad:0x68000000
|
|
width 23.
|
|
rgroup.long 0x10++0x7
|
|
line.quad 0x00 "L3_RT_NETWORK,Identifies The Interconnect And Is Present Only In The Register Target"
|
|
hexmask.quad.long 0x00 32.--63. 1. " ID ,Unique Interconnect ID"
|
|
rgroup.long 0x70++0x7
|
|
line.quad 0x00 "L3_RT_INITID_READBACK,Used By Initiators To Discover Their Own Identity"
|
|
hexmask.quad.byte 0x00 0.--7. 1. " INITID ,Returns initiator ID of core thread that initiated the read"
|
|
group.long 0x78++0x7
|
|
line.quad 0x00 "L3_RT_NETWORK_CONTROL,Timeout Base Scale And The Disabling Of Fine Grained Hardware Clock Gating"
|
|
bitfld.quad 0x00 56. " CLOCK_GATE_DISABLE ,Overrides fine grained hardware clock gating" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--10. " TIMEOUT_BASE ,Timeout base period in register target clock cycles" "Disabled,/64,/256,/1024,/4096,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PM (Protection Mechanism Common Registers)"
|
|
tree "PM_RT"
|
|
base ad:0x68010000
|
|
width 26.
|
|
group.long 0x20++0xF
|
|
line.quad 0x00 "L3_PM_ERROR_LOG,Logs Errors Detected By The Protection Mechanism"
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Secondary error present" "Not present,Present"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error Code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--20. " REQ_INFO ,MReqInfo bits of command selected for protection checking(Supervisor/Debug/Type)" "User/Functional/Data,User/Functional/Code,User/Debug/Data,User/Debug/Code,Reserved,Reserved,Reserved,Reserved,Supervisor/Functional/Data,Supervisor/Functional/Code,Supervisor/Debug/Data,Supervisor/Debug/Code,?..."
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 4.--6. " REGION ,Protection region number that command mapped to" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
line.quad 0x08 "L3_PM_CONTROL,Controls Protection Mechanism Functions Such As Error Reporting"
|
|
bitfld.quad 0x08 25. " ERROR_SECONDARY_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
textline " "
|
|
bitfld.quad 0x08 24. " ERROR_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
hgroup.long 0x30++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_SINGLE,Read To Clear Single Errors From Error Log"
|
|
in
|
|
hgroup.long 0x38++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_MULTI,Read To Clear Multiple Errors From Error Log"
|
|
in
|
|
width 0xb
|
|
width 29.
|
|
group.long 0x48++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_0,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 0"
|
|
group.long 0x68++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_1,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 1"
|
|
group.long 0x50++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_0,Configures Protection Region 0 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_0,Configures Protection Region 0 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x70++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_1,Configures Protection Region 1 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_1,Configures Protection Region 1 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
rgroup.long 0x80++0x07
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_1,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 1 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 1 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 1 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 1 address space" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree "PM_GPMC"
|
|
base ad:0x68012400
|
|
width 26.
|
|
group.long 0x20++0xF
|
|
line.quad 0x00 "L3_PM_ERROR_LOG,Logs Errors Detected By The Protection Mechanism"
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Secondary error present" "Not present,Present"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error Code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--20. " REQ_INFO ,MReqInfo bits of command selected for protection checking(Supervisor/Debug/Type)" "User/Functional/Data,User/Functional/Code,User/Debug/Data,User/Debug/Code,Reserved,Reserved,Reserved,Reserved,Supervisor/Functional/Data,Supervisor/Functional/Code,Supervisor/Debug/Data,Supervisor/Debug/Code,?..."
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 4.--6. " REGION ,Protection region number that command mapped to" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
line.quad 0x08 "L3_PM_CONTROL,Controls Protection Mechanism Functions Such As Error Reporting"
|
|
bitfld.quad 0x08 25. " ERROR_SECONDARY_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
textline " "
|
|
bitfld.quad 0x08 24. " ERROR_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
hgroup.long 0x30++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_SINGLE,Read To Clear Single Errors From Error Log"
|
|
in
|
|
hgroup.long 0x38++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_MULTI,Read To Clear Multiple Errors From Error Log"
|
|
in
|
|
width 0xb
|
|
width 29.
|
|
group.long 0x48++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_0,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 0"
|
|
group.long 0x68++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_1,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 1"
|
|
group.long 0x88++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_2,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 2"
|
|
group.long 0xA8++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_3,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 3"
|
|
group.long 0xC8++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_4,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 4"
|
|
group.long 0xE8++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_5,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 5"
|
|
group.long 0x108++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_6,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 6"
|
|
group.long 0x128++0x07
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_7,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 7"
|
|
group.long 0x50++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_0,Configures Protection Region 0 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_0,Configures Protection Region 0 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x70++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_1,Configures Protection Region 1 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_1,Configures Protection Region 1 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x90++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_2,Configures Protection Region 2 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_2,Configures Protection Region 2 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xB0++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_3,Configures Protection Region 3 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_3,Configures Protection Region 3 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xD0++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_4,Configures Protection Region 4 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_4,Configures Protection Region 4 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xF0++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_5,Configures Protection Region 5 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_5,Configures Protection Region 5 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x110++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_6,Configures Protection Region 6 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_6,Configures Protection Region 6 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x130++0x0f
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_7,Configures Protection Region 7 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_7,Configures Protection Region 7 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
rgroup.long (0x80++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_1,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 1 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 1 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 1 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 1 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xA0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_2,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 2 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 2 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 2 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 2 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xC0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_3,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 3 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 3 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 3 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 3 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xE0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_4,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 4 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 4 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 4 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 4 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x100++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_5,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 5 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 5 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 5 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 5 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x120++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_6,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 6 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 6 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 6 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 6 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x140++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_7,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 7 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 7 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 7 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 7 address space" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree "PM_OCM_RAM"
|
|
base ad:0x68012800
|
|
width 26.
|
|
group.long 0x20++0xF
|
|
line.quad 0x00 "L3_PM_ERROR_LOG,Logs Errors Detected By The Protection Mechanism"
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Secondary error present" "Not present,Present"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error Code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--20. " REQ_INFO ,MReqInfo bits of command selected for protection checking(Supervisor/Debug/Type)" "User/Functional/Data,User/Functional/Code,User/Debug/Data,User/Debug/Code,Reserved,Reserved,Reserved,Reserved,Supervisor/Functional/Data,Supervisor/Functional/Code,Supervisor/Debug/Data,Supervisor/Debug/Code,?..."
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 4.--6. " REGION ,Protection region number that command mapped to" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
line.quad 0x08 "L3_PM_CONTROL,Controls Protection Mechanism Functions Such As Error Reporting"
|
|
bitfld.quad 0x08 25. " ERROR_SECONDARY_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
textline " "
|
|
bitfld.quad 0x08 24. " ERROR_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
hgroup.long 0x30++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_SINGLE,Read To Clear Single Errors From Error Log"
|
|
in
|
|
hgroup.long 0x38++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_MULTI,Read To Clear Multiple Errors From Error Log"
|
|
in
|
|
width 0xb
|
|
width 29.
|
|
group.long 0x48++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_0,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 0"
|
|
group.long 0x68++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_1,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 1"
|
|
group.long 0x88++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_2,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 2"
|
|
group.long 0xA8++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_3,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 3"
|
|
group.long 0xC8++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_4,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 4"
|
|
group.long 0xE8++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_5,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 5"
|
|
group.long 0x108++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_6,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 6"
|
|
group.long 0x128++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_7,Configures A Protection Regions Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 7"
|
|
group.long 0x50++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_0,Configures Protection Region 0 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_0,Configures Protection Region 0 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x70++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_1,Configures Protection Region 1 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_1,Configures Protection Region 1 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x90++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_2,Configures Protection Region 2 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_2,Configures Protection Region 2 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xB0++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_3,Configures Protection Region 3 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_3,Configures Protection Region 3 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xD0++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_4,Configures Protection Region 4 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_4,Configures Protection Region 4 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xF0++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_5,Configures Protection Region 5 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_5,Configures Protection Region 5 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x110++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_6,Configures Protection Region 6 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_6,Configures Protection Region 6 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x130++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_7,Configures Protection Region 7 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " USB_HS_Host ,Read permission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 8. " DISP_SS ,Read permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 4. " IPSS ,Read permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_7,Configures Protection Region 7 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 9. " USB_HS_Host ,Writepermission for the USB_HS_Host" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 8. " DISP_SS ,Write permission for the DISP_SS" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 4. " IPSS ,Write permission for the IP-Subsystem" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
rgroup.long (0x80++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_1,Protection 1 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 1 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 1 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 1 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 1 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xA0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_2,Protection 2 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 2 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 2 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 2 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 2 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xC0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_3,Protection 3 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 3 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 3 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 3 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 3 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xE0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_4,Protection 4 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 4 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 4 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 4 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 4 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x100++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_5,Protection 5 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 5 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 5 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 5 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 5 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x120++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_6,Protection 6 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 6 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 6 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 6 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 6 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0x140++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_7,Protection 7 Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 7 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 7 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 7 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 7 address space" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree "PM_OCM_ROM"
|
|
base ad:0x68012C00
|
|
width 26.
|
|
group.long 0x20++0xF
|
|
line.quad 0x00 "L3_PM_ERROR_LOG,Logs Errors Detected By The Protection Mechanism"
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Secondary error present" "Not present,Present"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error Code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--20. " REQ_INFO ,MReqInfo bits of command selected for protection checking(Supervisor/Debug/Type)" "User/Functional/Data,User/Functional/Code,User/Debug/Data,User/Debug/Code,Reserved,Reserved,Reserved,Reserved,Supervisor/Functional/Data,Supervisor/Functional/Code,Supervisor/Debug/Data,Supervisor/Debug/Code,?..."
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 4.--6. " REGION ,Protection region number that command mapped to" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
line.quad 0x08 "L3_PM_CONTROL,Controls Protection Mechanism Functions Such As Error Reporting"
|
|
bitfld.quad 0x08 25. " ERROR_SECONDARY_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
textline " "
|
|
bitfld.quad 0x08 24. " ERROR_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
hgroup.long 0x30++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_SINGLE,Read To Clear Single Errors From Error Log"
|
|
in
|
|
hgroup.long 0x38++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_MULTI,Read To Clear Multiple Errors From Error Log"
|
|
in
|
|
width 0xb
|
|
width 29.
|
|
rgroup.long 0x48++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_0,Configures A Protection Region 0 Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 0"
|
|
rgroup.long 0x68++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_1,Configures A Protection Region 1 Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 1"
|
|
rgroup.long 0x50++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_0,Configures Protection Region 0 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_0,Configures Protection Region 0 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
rgroup.long 0x70++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_1,Configures Protection Region 1 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_1,Configures Protection Region 1 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
rgroup.long 0x80++0x7
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_1,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 1 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 1 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 1 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 1 address space" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree "PM_IPSS"
|
|
base ad:0x68014000
|
|
width 26.
|
|
group.long 0x20++0xF
|
|
line.quad 0x00 "L3_PM_ERROR_LOG,Logs Errors Detected By The Protection Mechanism"
|
|
eventfld.quad 0x00 31. " MULTI ,Multiple errors" "Not seen,Seen"
|
|
textline " "
|
|
eventfld.quad 0x00 30. " SECONDARY ,Secondary error present" "Not present,Present"
|
|
textline " "
|
|
bitfld.quad 0x00 24.--27. " CODE ,Error Code" "No error,Unsupported command,Address hole,Protection violation,In-band error,Not used,Not used,Request time-out not accepted,Request time-out not response,Not used,Not used,Not used,Not used,Not used,Not used,Not used"
|
|
textline " "
|
|
bitfld.quad 0x00 16.--20. " REQ_INFO ,MReqInfo bits of command selected for protection checking(Supervisor/Debug/Type)" "User/Functional/Data,User/Functional/Code,User/Debug/Data,User/Debug/Code,Reserved,Reserved,Reserved,Reserved,Supervisor/Functional/Data,Supervisor/Functional/Code,Supervisor/Debug/Data,Supervisor/Debug/Code,?..."
|
|
textline " "
|
|
hexmask.quad.byte 0x00 8.--15. 1. " INITID ,Initiator ID from which the command was launched"
|
|
textline " "
|
|
bitfld.quad 0x00 4.--6. " REGION ,Protection region number that command mapped to" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " CMD ,Command that caused the error" "Idle,Write,Read,ReadEx,Not used,Write nonposted,Not used,Not used"
|
|
line.quad 0x08 "L3_PM_CONTROL,Controls Protection Mechanism Functions Such As Error Reporting"
|
|
bitfld.quad 0x08 25. " ERROR_SECONDARY_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
textline " "
|
|
bitfld.quad 0x08 24. " ERROR_REP ,Out of band error reporting" "Reporting suppress,Reported"
|
|
hgroup.long 0x30++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_SINGLE,Read To Clear Single Errors From Error Log"
|
|
in
|
|
hgroup.long 0x38++0x7
|
|
hide.quad 0x00 "L3_PM_ERROR_CLEAR_MULTI,Read To Clear Multiple Errors From Error Log"
|
|
in
|
|
width 0xb
|
|
width 29.
|
|
group.long 0x48++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_0,Configures A Protection Region 0 Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 0"
|
|
group.long 0x68++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_1,Configures A Protection Region 1 Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 1"
|
|
group.long 0x88++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_2,Configures A Protection Region 2 Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 2"
|
|
group.long 0xA8++0x7
|
|
line.quad 0x00 "L3_PM_REQ_INFO_PERMISSION_3,Configures A Protection Region 3 Permissions Using The MReqInfo Bits"
|
|
hexmask.quad.word 0x00 0.--15. 1. " REQ_INFO ,Request info permission bits for region 3"
|
|
group.long 0x50++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_0,Configures Protection Region 0 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_0,Configures Protection Region 0 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x70++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_1,Configures Protection Region 1 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_1,Configures Protection Region 1 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0x90++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_2,Configures Protection Region 2 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_2,Configures Protection Region 2 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
group.long 0xB0++0xF
|
|
line.quad 0x00 "L3_PM_READ_PERMISSION_3,Configures Protection Region 3 Permissions For Read Incoming Commands"
|
|
bitfld.quad 0x00 12. " DAP ,Read permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 3. " SDMA ,Read permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " MPU ,Read permission for the MPU" "Not permitted,Permitted"
|
|
line.quad 0x08 "L3_PM_WRITE_PERMISSION_3,Configures Protection Region 3 Permissions For Write Incoming Commands"
|
|
bitfld.quad 0x08 12. " DAP ,Write permission for the DAP" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 3. " SDMA ,Write permission for the DMA" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.quad 0x08 1. " MPU ,Write permission for the MPU" "Not permitted,Permitted"
|
|
rgroup.long (0x80++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_1,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 1 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 1 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 1 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 1 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xA0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_2,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 2 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 2 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 2 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 2 address space" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (0xC0++0x07)
|
|
line.quad 0x00 "L3_PM_ADDR_MATCH_3,Protection Regions Base Address; Size; Address Space And Level"
|
|
hexmask.quad.word 0x00 10.--19. 1. " BASE_ADDR ,Protection region 3 base address"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " LEVEL ,Protection region 3 level" "0,1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 3.--7. 1. " SIZE ,Protection region 3 size"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--2. " ADDR_SPACE ,Protection region 3 address space" "0,1,2,3,4,5,6,7"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "SI (Sideband Interconnect Registers)"
|
|
base ad:0x68000400
|
|
width 21.
|
|
group.long 0x20++0x7
|
|
line.quad 0x00 "L3_SI_CONTROL,Control Of Register And Sideband Interconnect"
|
|
bitfld.quad 0x00 56. " CLOCK_GATE_DISABLE ,Overrides fine grained hardware clock gating" "Normal,Disabled"
|
|
rgroup.long 0x110++0x7
|
|
line.quad 0x00 "L3_SI_FLAG_STATUS_0,Individual Bits That Make Up A Composite Interconnect Flag"
|
|
bitfld.quad 0x00 60. " L4-Emu ,SError assertion error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 59. " L4-Per_TA ,SError assertion error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 58. " L4-Core_TA ,SError assertion error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 57. " GPMC_TA ,SError assertion error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 56. " L4-Emu_TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 54. " IPSS _TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 53. " L4-Per_TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 52. " L4-Core_TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 51. " OCM_ROM_TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 50. " OCM_RAM_TA ,Request time-out Aerror flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 49. " GPMC_TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 48. " SMS_TA ,Request time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 28. " USB_HSF_Host_IA ,Functional Inband error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 27. " USB_HSB_Host_IA ,Burst time-out error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 26. " IPSSF_IA ,Functional Inband error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 25. " IPSSR_IA ,Response time-out error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 24. " IPSSB_IA ,Burst time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 22. " sDMA_WrF_IA ,Functional Inband error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 21. " sDMA_WrB_IA ,Burst time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 19. " sDMA_RdF_IA ,Functional Inband error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 18. " sDMA_RdB_IA ,Burst time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 16. " Display_SSF_IA ,Functional Inband error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 15. " Display_SSB_IA ,Burst time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
textline " "
|
|
bitfld.quad 0x00 2. " MPUF_IA ,Functional Inband error flag" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 1. " MPUR_IA ,Response time-out error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " MPUB_IA ,Burst time-out error flag" "Not occurred,Occurred"
|
|
rgroup.long 0x130++0x7
|
|
line.quad 0x00 "L3_SI_FLAG_STATUS_1,Individual Bits That Make Up A Composite Interconnect Flag"
|
|
bitfld.quad 0x00 0. " MPU_DATA_IA ,Debug error flag" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "L4 Interconnect"
|
|
tree "L4-Core"
|
|
tree "IA (Initiator Agent Registers)"
|
|
base ad:0x48040800
|
|
width 23.
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable Error Reporting On An Initiator Interface"
|
|
bitfld.long 0x00 27. " INBAND_ERROR_REP ,In-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "Not reported,Reported"
|
|
bitfld.long 0x00 24. " MERROR_REP ,Enable MError reporting" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores Status Information For An Initiator"
|
|
eventfld.long 0x00 27. " INBAND_ERROR_REP ,In-Band error present" "No error,Error"
|
|
bitfld.long 0x00 24. " MERROR_REP ,MError error present" "No error,Error"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "L4_IA_ERROR_LOG_L,Log Information About Error Conditions"
|
|
bitfld.long 0x00 31. " MULTI ,Additional error detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request" "No error,Reserved,Address hole,Protection violation"
|
|
width 0xb
|
|
tree.end
|
|
tree "LA (Link Agent Registers)"
|
|
base ad:0x48041000
|
|
width 25.
|
|
rgroup.long 0x14++0xb
|
|
line.long 0x00 "L4_LA_NETWORK_H,Identify The Interconnect"
|
|
line.long 0x04 "L4_LA_INITIATOR_INFO_L,Initiator Subsystem Information"
|
|
bitfld.long 0x04 24.--27. " PROT_GROUPS ,The number of protection groups" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NUMBER_REGIONS ,The number of regions"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " SEGMENTS ,The number of segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "L4_LA_INITIATOR_INFO_H,Initiator Subsystem Information"
|
|
bitfld.long 0x08 16.--18. " THREADS ,Number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " CONNID_WIDTH ,Initiator subsystem connID width" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " BYTE_DATA_WIDTH_EXP ,Initiator subsystem data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--4. " ADDR_WIDTH ,Initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control Interconnect Minimum Timeout Values"
|
|
bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,Indicates the timeout period (L4 interconnect clock cycles)" "Disabled,/64,/256,/1024,/4096,?..."
|
|
line.long 0x04 "L4_LA_NETWORK_CONTROL_H,Control Interconnect Global Power Control"
|
|
bitfld.long 0x04 24. " CLOCK_GATE_DISABLE ,All clock gating disable" "No,Yes"
|
|
bitfld.long 0x04 20. " THREAD0_PRI ,Sets thread priority" "No priority,Priority"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EXT_CLOCK ,Entire L4 shut off signal" "No action,Shut off"
|
|
width 0xb
|
|
tree.end
|
|
tree "AP (Address Protection Registers)"
|
|
base ad:0x48040000
|
|
width 19.
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_0_L,Base Address Of 0 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_0_H,Size Of 0 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x108++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_1_L,Base Address Of 1 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_1_H,Size Of 1 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x110++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_2_L,Base Address Of 2 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_2_H,Size Of 2 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x118++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_3_L,Base Address Of 3 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_3_H,Size Of 3 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_4_L,Base Address Of 4 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_4_H,Size Of 4 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x128++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_5_L,Base Address Of 5 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_5_H,Size Of 5 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
width 31.
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_0_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_1_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_2_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_3_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_4_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_5_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x230++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_6_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x238++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_7_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x280++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_0_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x288++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_1_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x290++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_2_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x298++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_3_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2A0++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_4_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2A8++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_5_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2B0++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_6_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_7_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
width 19.
|
|
group.long 0x300++0x7
|
|
line.long 0x00 "L4_AP_REGION_0_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_0_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x308++0x7
|
|
line.long 0x00 "L4_AP_REGION_1_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_1_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x310++0x7
|
|
line.long 0x00 "L4_AP_REGION_2_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_2_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x318++0x7
|
|
line.long 0x00 "L4_AP_REGION_3_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_3_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "L4_AP_REGION_4_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_4_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x328++0x7
|
|
line.long 0x00 "L4_AP_REGION_5_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_5_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x330++0x7
|
|
line.long 0x00 "L4_AP_REGION_6_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_6_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x338++0x7
|
|
line.long 0x00 "L4_AP_REGION_7_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_7_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "L4_AP_REGION_8_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_8_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x348++0x7
|
|
line.long 0x00 "L4_AP_REGION_9_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_9_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "L4_AP_REGION_10_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_10_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x358++0x7
|
|
line.long 0x00 "L4_AP_REGION_11_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_11_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "L4_AP_REGION_12_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_12_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x368++0x7
|
|
line.long 0x00 "L4_AP_REGION_13_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_13_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "L4_AP_REGION_14_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_14_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x378++0x7
|
|
line.long 0x00 "L4_AP_REGION_15_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_15_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x380++0x7
|
|
line.long 0x00 "L4_AP_REGION_16_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_16_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x388++0x7
|
|
line.long 0x00 "L4_AP_REGION_17_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_17_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x390++0x7
|
|
line.long 0x00 "L4_AP_REGION_18_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_18_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x398++0x7
|
|
line.long 0x00 "L4_AP_REGION_19_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_19_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3A0++0x7
|
|
line.long 0x00 "L4_AP_REGION_20_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_20_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3A8++0x7
|
|
line.long 0x00 "L4_AP_REGION_21_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_21_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3B0++0x7
|
|
line.long 0x00 "L4_AP_REGION_22_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_22_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3B8++0x7
|
|
line.long 0x00 "L4_AP_REGION_23_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_23_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3C0++0x7
|
|
line.long 0x00 "L4_AP_REGION_24_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_24_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3C8++0x7
|
|
line.long 0x00 "L4_AP_REGION_25_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_25_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3D0++0x7
|
|
line.long 0x00 "L4_AP_REGION_26_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_26_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3D8++0x7
|
|
line.long 0x00 "L4_AP_REGION_27_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_27_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3E0++0x7
|
|
line.long 0x00 "L4_AP_REGION_28_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_28_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3E8++0x7
|
|
line.long 0x00 "L4_AP_REGION_29_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_29_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3F0++0x7
|
|
line.long 0x00 "L4_AP_REGION_30_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_30_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3F8++0x7
|
|
line.long 0x00 "L4_AP_REGION_31_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_31_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x400++0x7
|
|
line.long 0x00 "L4_AP_REGION_32_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_32_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x408++0x7
|
|
line.long 0x00 "L4_AP_REGION_33_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_33_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x410++0x7
|
|
line.long 0x00 "L4_AP_REGION_34_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_34_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x418++0x7
|
|
line.long 0x00 "L4_AP_REGION_35_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_35_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x420++0x7
|
|
line.long 0x00 "L4_AP_REGION_36_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_36_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x428++0x7
|
|
line.long 0x00 "L4_AP_REGION_37_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_37_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x430++0x7
|
|
line.long 0x00 "L4_AP_REGION_38_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_38_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x438++0x7
|
|
line.long 0x00 "L4_AP_REGION_39_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_39_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x440++0x7
|
|
line.long 0x00 "L4_AP_REGION_40_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_40_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x448++0x7
|
|
line.long 0x00 "L4_AP_REGION_41_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_41_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x450++0x7
|
|
line.long 0x00 "L4_AP_REGION_42_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_42_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x458++0x7
|
|
line.long 0x00 "L4_AP_REGION_43_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_43_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x460++0x7
|
|
line.long 0x00 "L4_AP_REGION_44_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_44_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x468++0x7
|
|
line.long 0x00 "L4_AP_REGION_45_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_45_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x470++0x7
|
|
line.long 0x00 "L4_AP_REGION_46_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_46_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x478++0x7
|
|
line.long 0x00 "L4_AP_REGION_47_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_47_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x480++0x7
|
|
line.long 0x00 "L4_AP_REGION_48_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_48_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x488++0x7
|
|
line.long 0x00 "L4_AP_REGION_49_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_49_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x490++0x7
|
|
line.long 0x00 "L4_AP_REGION_50_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_50_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x498++0x7
|
|
line.long 0x00 "L4_AP_REGION_51_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_51_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4A0++0x7
|
|
line.long 0x00 "L4_AP_REGION_52_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_52_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4A8++0x7
|
|
line.long 0x00 "L4_AP_REGION_53_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_53_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4B0++0x7
|
|
line.long 0x00 "L4_AP_REGION_54_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_54_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4B8++0x7
|
|
line.long 0x00 "L4_AP_REGION_55_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_55_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4C0++0x7
|
|
line.long 0x00 "L4_AP_REGION_56_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_56_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4C8++0x7
|
|
line.long 0x00 "L4_AP_REGION_57_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_57_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4D0++0x7
|
|
line.long 0x00 "L4_AP_REGION_58_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_58_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4D8++0x7
|
|
line.long 0x00 "L4_AP_REGION_59_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_59_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4E0++0x7
|
|
line.long 0x00 "L4_AP_REGION_60_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_60_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4E8++0x7
|
|
line.long 0x00 "L4_AP_REGION_61_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_61_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4F0++0x7
|
|
line.long 0x00 "L4_AP_REGION_62_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_62_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x4F8++0x7
|
|
line.long 0x00 "L4_AP_REGION_63_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_63_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x500++0x7
|
|
line.long 0x00 "L4_AP_REGION_64_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_64_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x508++0x7
|
|
line.long 0x00 "L4_AP_REGION_65_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_65_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x510++0x7
|
|
line.long 0x00 "L4_AP_REGION_66_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_66_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x518++0x7
|
|
line.long 0x00 "L4_AP_REGION_67_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_67_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x520++0x7
|
|
line.long 0x00 "L4_AP_REGION_68_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_68_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x528++0x7
|
|
line.long 0x00 "L4_AP_REGION_69_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_69_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x530++0x7
|
|
line.long 0x00 "L4_AP_REGION_70_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_70_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x538++0x7
|
|
line.long 0x00 "L4_AP_REGION_71_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_71_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x540++0x7
|
|
line.long 0x00 "L4_AP_REGION_72_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_72_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x548++0x7
|
|
line.long 0x00 "L4_AP_REGION_73_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_73_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x550++0x7
|
|
line.long 0x00 "L4_AP_REGION_74_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_74_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x558++0x7
|
|
line.long 0x00 "L4_AP_REGION_75_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_75_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x560++0x7
|
|
line.long 0x00 "L4_AP_REGION_76_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_76_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x568++0x7
|
|
line.long 0x00 "L4_AP_REGION_77_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_77_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x570++0x7
|
|
line.long 0x00 "L4_AP_REGION_78_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_78_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x578++0x7
|
|
line.long 0x00 "L4_AP_REGION_79_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_79_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x580++0x7
|
|
line.long 0x00 "L4_AP_REGION_80_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_80_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x588++0x7
|
|
line.long 0x00 "L4_AP_REGION_81_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_81_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x590++0x7
|
|
line.long 0x00 "L4_AP_REGION_82_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_82_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x598++0x7
|
|
line.long 0x00 "L4_AP_REGION_83_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_83_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5A0++0x7
|
|
line.long 0x00 "L4_AP_REGION_84_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_84_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5A8++0x7
|
|
line.long 0x00 "L4_AP_REGION_85_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_85_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5B0++0x7
|
|
line.long 0x00 "L4_AP_REGION_86_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_86_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5B8++0x7
|
|
line.long 0x00 "L4_AP_REGION_87_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_87_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5C0++0x7
|
|
line.long 0x00 "L4_AP_REGION_88_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_88_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5C8++0x7
|
|
line.long 0x00 "L4_AP_REGION_89_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_89_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5D0++0x7
|
|
line.long 0x00 "L4_AP_REGION_90_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_90_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5D8++0x7
|
|
line.long 0x00 "L4_AP_REGION_91_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_91_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5E0++0x7
|
|
line.long 0x00 "L4_AP_REGION_92_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_92_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5E8++0x7
|
|
line.long 0x00 "L4_AP_REGION_93_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_93_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5F0++0x7
|
|
line.long 0x00 "L4_AP_REGION_94_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_94_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x5F8++0x7
|
|
line.long 0x00 "L4_AP_REGION_95_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_95_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x600++0x7
|
|
line.long 0x00 "L4_AP_REGION_96_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_96_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x608++0x7
|
|
line.long 0x00 "L4_AP_REGION_97_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_97_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x610++0x7
|
|
line.long 0x00 "L4_AP_REGION_98_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_98_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x618++0x7
|
|
line.long 0x00 "L4_AP_REGION_99_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_99_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA (Target Agent Registers)"
|
|
tree "CORE_TA_CONTROL"
|
|
base ad:0x48003000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_CM"
|
|
base ad:0x48007000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_DISPLAY_SS"
|
|
base ad:0x48051000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_SDMA"
|
|
base ad:0x48057000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_I2C3"
|
|
base ad:0x48061000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_USB_HS_TLL"
|
|
base ad:0x48063000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_USB_HS_Host"
|
|
base ad:0x48065000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_UART1"
|
|
base ad:0x4806B000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_UART2"
|
|
base ad:0x4806D000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_I2C1"
|
|
base ad:0x48071000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_I2C2"
|
|
base ad:0x48073000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MCBSP1"
|
|
base ad:0x48075000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_GPTIMER10"
|
|
base ad:0x48087000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_GPTIMER11"
|
|
base ad:0x48089000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MCBSP5"
|
|
base ad:0x48097000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_SPI1"
|
|
base ad:0x48099000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_SPI2"
|
|
base ad:0x4809B000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MMCHS1"
|
|
base ad:0x4809D000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_UART4"
|
|
base ad:0x4809F000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MMCHS3"
|
|
base ad:0x480AE000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA_MG"
|
|
base ad:0x480B1000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_HDQ1W"
|
|
base ad:0x480B3000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MMCHS2"
|
|
base ad:0x480B5000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MCSPI3"
|
|
base ad:0x480B9000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_MCSPI4"
|
|
base ad:0x480BB000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_INTH"
|
|
base ad:0x480C8000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "CORE_TA_WKUP"
|
|
base ad:0x48340000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "L4-Per"
|
|
tree "IA (Initiator Agent Registers)"
|
|
base ad:0x49000800
|
|
width 23.
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable Error Reporting On An Initiator Interface"
|
|
bitfld.long 0x00 27. " INBAND_ERROR_REP ,In-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "Not reported,Reported"
|
|
bitfld.long 0x00 24. " MERROR_REP ,Enable MError reporting" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores Status Information For An Initiator"
|
|
eventfld.long 0x00 27. " INBAND_ERROR_REP ,In-Band error present" "No error,Error"
|
|
bitfld.long 0x00 24. " MERROR_REP ,MError error present" "No error,Error"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "L4_IA_ERROR_LOG_L,Log Information About Error Conditions"
|
|
bitfld.long 0x00 31. " MULTI ,Additional error detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request" "No error,Reserved,Address hole,Protection violation"
|
|
width 0xb
|
|
tree.end
|
|
tree "LA (Link Agent Registers)"
|
|
base ad:0x49001000
|
|
width 25.
|
|
rgroup.long 0x14++0xb
|
|
line.long 0x00 "L4_LA_NETWORK_H,Identify The Interconnect"
|
|
line.long 0x04 "L4_LA_INITIATOR_INFO_L,Initiator Subsystem Information"
|
|
bitfld.long 0x04 24.--27. " PROT_GROUPS ,The number of protection groups" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NUMBER_REGIONS ,The number of regions"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " SEGMENTS ,The number of segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "L4_LA_INITIATOR_INFO_H,Initiator Subsystem Information"
|
|
bitfld.long 0x08 16.--18. " THREADS ,Number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " CONNID_WIDTH ,Initiator subsystem connID width" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " BYTE_DATA_WIDTH_EXP ,Initiator subsystem data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--4. " ADDR_WIDTH ,Initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control Interconnect Minimum Timeout Values"
|
|
bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,Indicates the timeout period (L4 interconnect clock cycles)" "Disabled,/64,/256,/1024,/4096,?..."
|
|
line.long 0x04 "L4_LA_NETWORK_CONTROL_H,Control Interconnect Global Power Control"
|
|
bitfld.long 0x04 24. " CLOCK_GATE_DISABLE ,All clock gating disable" "No,Yes"
|
|
bitfld.long 0x04 20. " THREAD0_PRI ,Sets thread priority" "No priority,Priority"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EXT_CLOCK ,Entire L4 shut off signal" "No action,Shut off"
|
|
width 0xb
|
|
tree.end
|
|
tree "AP (Address Protection Registers)"
|
|
base ad:0x49000000
|
|
width 19.
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_0_L,Base Address Of 0 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_0_H,Size Of 0 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x108++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_1_L,Base Address Of 1 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_1_H,Size Of 1 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x110++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_2_L,Base Address Of 2 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_2_H,Size Of 2 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x118++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_3_L,Base Address Of 3 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_3_H,Size Of 3 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_4_L,Base Address Of 4 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_4_H,Size Of 4 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
width 31.
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_0_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_1_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_2_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_3_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_4_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_5_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x230++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_6_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x238++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_7_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x280++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_0_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x288++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_1_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x290++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_2_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x298++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_3_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2A0++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_4_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2A8++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_5_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2B0++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_6_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_7_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
width 19.
|
|
group.long 0x300++0x7
|
|
line.long 0x00 "L4_AP_REGION_0_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_0_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x308++0x7
|
|
line.long 0x00 "L4_AP_REGION_1_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_1_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x310++0x7
|
|
line.long 0x00 "L4_AP_REGION_2_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_2_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x318++0x7
|
|
line.long 0x00 "L4_AP_REGION_3_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_3_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "L4_AP_REGION_4_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_4_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x328++0x7
|
|
line.long 0x00 "L4_AP_REGION_5_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_5_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x330++0x7
|
|
line.long 0x00 "L4_AP_REGION_6_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_6_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x338++0x7
|
|
line.long 0x00 "L4_AP_REGION_7_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_7_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "L4_AP_REGION_8_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_8_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x348++0x7
|
|
line.long 0x00 "L4_AP_REGION_9_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_9_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "L4_AP_REGION_10_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_10_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x358++0x7
|
|
line.long 0x00 "L4_AP_REGION_11_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_11_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "L4_AP_REGION_12_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_12_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x368++0x7
|
|
line.long 0x00 "L4_AP_REGION_13_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_13_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "L4_AP_REGION_14_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_14_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x378++0x7
|
|
line.long 0x00 "L4_AP_REGION_15_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_15_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x380++0x7
|
|
line.long 0x00 "L4_AP_REGION_16_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_16_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x388++0x7
|
|
line.long 0x00 "L4_AP_REGION_17_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_17_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x390++0x7
|
|
line.long 0x00 "L4_AP_REGION_18_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_18_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x398++0x7
|
|
line.long 0x00 "L4_AP_REGION_19_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_19_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3A0++0x7
|
|
line.long 0x00 "L4_AP_REGION_20_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_20_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3A8++0x7
|
|
line.long 0x00 "L4_AP_REGION_21_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_21_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3B0++0x7
|
|
line.long 0x00 "L4_AP_REGION_22_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_22_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3B8++0x7
|
|
line.long 0x00 "L4_AP_REGION_23_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_23_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3C0++0x7
|
|
line.long 0x00 "L4_AP_REGION_24_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_24_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3C8++0x7
|
|
line.long 0x00 "L4_AP_REGION_25_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_25_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3D0++0x7
|
|
line.long 0x00 "L4_AP_REGION_26_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_26_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3D8++0x7
|
|
line.long 0x00 "L4_AP_REGION_27_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_27_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3E0++0x7
|
|
line.long 0x00 "L4_AP_REGION_28_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_28_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3E8++0x7
|
|
line.long 0x00 "L4_AP_REGION_29_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_29_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3F0++0x7
|
|
line.long 0x00 "L4_AP_REGION_30_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_30_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3F8++0x7
|
|
line.long 0x00 "L4_AP_REGION_31_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_31_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x400++0x7
|
|
line.long 0x00 "L4_AP_REGION_32_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_32_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x408++0x7
|
|
line.long 0x00 "L4_AP_REGION_33_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_33_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x410++0x7
|
|
line.long 0x00 "L4_AP_REGION_34_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_34_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x418++0x7
|
|
line.long 0x00 "L4_AP_REGION_35_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_35_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x420++0x7
|
|
line.long 0x00 "L4_AP_REGION_36_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_36_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x428++0x7
|
|
line.long 0x00 "L4_AP_REGION_37_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_37_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x430++0x7
|
|
line.long 0x00 "L4_AP_REGION_38_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_38_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x438++0x7
|
|
line.long 0x00 "L4_AP_REGION_39_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_39_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x440++0x7
|
|
line.long 0x00 "L4_AP_REGION_40_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_40_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x448++0x7
|
|
line.long 0x00 "L4_AP_REGION_41_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_41_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x450++0x7
|
|
line.long 0x00 "L4_AP_REGION_42_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_42_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA (Target Agent Registers)"
|
|
tree "PER_TA_UART3"
|
|
base ad:0x49021000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_MCBSP2"
|
|
base ad:0x49023000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_MCBSP3"
|
|
base ad:0x49025000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_MCBSP4"
|
|
base ad:0x49027000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_MCBSP2_SIDETONE2"
|
|
base ad:0x49029000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_MCBSP2_SIDETONE3"
|
|
base ad:0x4902B000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_WDTIMER3"
|
|
base ad:0x49031000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER2"
|
|
base ad:0x49033000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER3"
|
|
base ad:0x49035000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER4"
|
|
base ad:0x49037000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER5"
|
|
base ad:0x49039000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER6"
|
|
base ad:0x4903B000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER7"
|
|
base ad:0x4903D000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER8"
|
|
base ad:0x4903F000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPTIMER9"
|
|
base ad:0x49041000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPIO2"
|
|
base ad:0x49051000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPIO3"
|
|
base ad:0x49053000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPIO4"
|
|
base ad:0x49055000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPIO5"
|
|
base ad:0x49057000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "PER_TA_GPIO6"
|
|
base ad:0x49059000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "L4-Emu"
|
|
tree "IA (Initiator Agent Registers)"
|
|
tree "EMU_IA_L3"
|
|
base ad:0x54006800
|
|
width 23.
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable Error Reporting On An Initiator Interface"
|
|
bitfld.long 0x00 27. " INBAND_ERROR_REP ,In-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "Not reported,Reported"
|
|
bitfld.long 0x00 24. " MERROR_REP ,Enable MError reporting" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores Status Information For An Initiator"
|
|
eventfld.long 0x00 27. " INBAND_ERROR_REP ,In-Band error present" "No error,Error"
|
|
bitfld.long 0x00 24. " MERROR_REP ,MError error present" "No error,Error"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "L4_IA_ERROR_LOG_L,Log Information About Error Conditions"
|
|
bitfld.long 0x00 31. " MULTI ,Additional error detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request" "No error,Reserved,Address hole,Protection violation"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_IA_DAP"
|
|
base ad:0x54008000
|
|
width 23.
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable Error Reporting On An Initiator Interface"
|
|
bitfld.long 0x00 27. " INBAND_ERROR_REP ,In-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "Not reported,Reported"
|
|
bitfld.long 0x00 24. " MERROR_REP ,Enable MError reporting" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores Status Information For An Initiator"
|
|
eventfld.long 0x00 27. " INBAND_ERROR_REP ,In-Band error present" "No error,Error"
|
|
bitfld.long 0x00 24. " MERROR_REP ,MError error present" "No error,Error"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "L4_IA_ERROR_LOG_L,Log Information About Error Conditions"
|
|
bitfld.long 0x00 31. " MULTI ,Additional error detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request" "No error,Reserved,Address hole,Protection violation"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "LA (Link Agent Registers)"
|
|
base ad:0x54007000
|
|
width 25.
|
|
rgroup.long 0x14++0xb
|
|
line.long 0x00 "L4_LA_NETWORK_H,Identify The Interconnect"
|
|
line.long 0x04 "L4_LA_INITIATOR_INFO_L,Initiator Subsystem Information"
|
|
bitfld.long 0x04 24.--27. " PROT_GROUPS ,The number of protection groups" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NUMBER_REGIONS ,The number of regions"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " SEGMENTS ,The number of segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "L4_LA_INITIATOR_INFO_H,Initiator Subsystem Information"
|
|
bitfld.long 0x08 16.--18. " THREADS ,Number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " CONNID_WIDTH ,Initiator subsystem connID width" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " BYTE_DATA_WIDTH_EXP ,Initiator subsystem data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--4. " ADDR_WIDTH ,Initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control Interconnect Minimum Timeout Values"
|
|
bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,Indicates the timeout period (L4 interconnect clock cycles)" "Disabled,/64,/256,/1024,/4096,?..."
|
|
line.long 0x04 "L4_LA_NETWORK_CONTROL_H,Control Interconnect Global Power Control"
|
|
bitfld.long 0x04 24. " CLOCK_GATE_DISABLE ,All clock gating disable" "No,Yes"
|
|
bitfld.long 0x04 20. " THREAD0_PRI ,Sets thread priority" "No priority,Priority"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EXT_CLOCK ,Entire L4 shut off signal" "No action,Shut off"
|
|
width 0xb
|
|
tree.end
|
|
tree "AP (Address Protection Registers)"
|
|
base ad:0x54006000
|
|
width 19.
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_0_L,Base Address Of 0 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_0_H,Size Of 0 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x108++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_1_L,Base Address Of 1 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_1_H,Size Of 1 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x110++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_2_L,Base Address Of 2 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_2_H,Size Of 2 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
width 31.
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_0_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_1_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_2_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_3_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_4_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_5_L,ConnID Bit Vectors For A Protection Group"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNID_BIT_VECTOR ,Protection group connID allow"
|
|
rgroup.long 0x280++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_0_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x288++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_1_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x290++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_2_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x298++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_3_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2A0++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_4_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
rgroup.long 0x2A8++0x3
|
|
line.long 0x00 "L4_AP_PROT_GROUP_ROLES_5_L,Define MReqInfo Bit Vectors For A Protection Group"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Setting of type acces allowed for the group 11 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Setting of type acces allowed for the group 10 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[09] ,Setting of type acces allowed for the group 9 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[08] ,Setting of type acces allowed for the group 8 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[03] ,Setting of type acces allowed for the group 3 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[02] ,Setting of type acces allowed for the group 2 of initiators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[01] ,Setting of type acces allowed for the group 1 of initiators" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[00] ,Setting of type acces allowed for the group 0 of initiators" "Disabled,Enabled"
|
|
width 19.
|
|
group.long 0x300++0x7
|
|
line.long 0x00 "L4_AP_REGION_0_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_0_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x308++0x7
|
|
line.long 0x00 "L4_AP_REGION_1_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_1_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x310++0x7
|
|
line.long 0x00 "L4_AP_REGION_2_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_2_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x318++0x7
|
|
line.long 0x00 "L4_AP_REGION_3_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_3_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "L4_AP_REGION_4_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_4_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x328++0x7
|
|
line.long 0x00 "L4_AP_REGION_5_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_5_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x330++0x7
|
|
line.long 0x00 "L4_AP_REGION_6_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_6_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x338++0x7
|
|
line.long 0x00 "L4_AP_REGION_7_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_7_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "L4_AP_REGION_8_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_8_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x348++0x7
|
|
line.long 0x00 "L4_AP_REGION_9_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_9_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "L4_AP_REGION_10_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_10_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x358++0x7
|
|
line.long 0x00 "L4_AP_REGION_11_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_11_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "L4_AP_REGION_12_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_12_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x368++0x7
|
|
line.long 0x00 "L4_AP_REGION_13_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_13_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "L4_AP_REGION_14_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_14_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x378++0x7
|
|
line.long 0x00 "L4_AP_REGION_15_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_15_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x380++0x7
|
|
line.long 0x00 "L4_AP_REGION_16_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_16_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x388++0x7
|
|
line.long 0x00 "L4_AP_REGION_17_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_17_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x390++0x7
|
|
line.long 0x00 "L4_AP_REGION_18_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_18_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x398++0x7
|
|
line.long 0x00 "L4_AP_REGION_19_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_19_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3A0++0x7
|
|
line.long 0x00 "L4_AP_REGION_20_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_20_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3A8++0x7
|
|
line.long 0x00 "L4_AP_REGION_21_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_21_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3B0++0x7
|
|
line.long 0x00 "L4_AP_REGION_22_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_22_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3B8++0x7
|
|
line.long 0x00 "L4_AP_REGION_23_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_23_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3C0++0x7
|
|
line.long 0x00 "L4_AP_REGION_24_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_24_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x3C8++0x7
|
|
line.long 0x00 "L4_AP_REGION_25_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_25_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA (Target Agent Registers)"
|
|
tree "EMU_TA_TEST_TAP"
|
|
base ad:0x54005000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_TA_MPU"
|
|
base ad:0x54018000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_TA_TPIU"
|
|
base ad:0x5401A000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_TA_ETB"
|
|
base ad:0x5401C000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_TA_DAPCTL"
|
|
base ad:0x5401E000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_TA_SDTI"
|
|
base ad:0x5401F000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMU_TA_L4WKUP"
|
|
base ad:0x54730000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "L4-Wakeup"
|
|
tree "IA (Initiator Agent Registers)"
|
|
tree "L4-Core"
|
|
base ad:0x48328800
|
|
width 23.
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable Error Reporting On An Initiator Interface"
|
|
bitfld.long 0x00 27. " INBAND_ERROR_REP ,In-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "Not reported,Reported"
|
|
bitfld.long 0x00 24. " MERROR_REP ,Enable MError reporting" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores Status Information For An Initiator"
|
|
eventfld.long 0x00 27. " INBAND_ERROR_REP ,In-Band error present" "No error,Error"
|
|
bitfld.long 0x00 24. " MERROR_REP ,MError error present" "No error,Error"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "L4_IA_ERROR_LOG_L,Log Information About Error Conditions"
|
|
bitfld.long 0x00 31. " MULTI ,Additional error detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request" "No error,Reserved,Address hole,Protection violation"
|
|
width 0xb
|
|
tree.end
|
|
tree "L4-Emu"
|
|
base ad:0x4832A000
|
|
width 23.
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable Error Reporting On An Initiator Interface"
|
|
bitfld.long 0x00 27. " INBAND_ERROR_REP ,In-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "Not reported,Reported"
|
|
bitfld.long 0x00 24. " MERROR_REP ,Enable MError reporting" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores Status Information For An Initiator"
|
|
eventfld.long 0x00 27. " INBAND_ERROR_REP ,In-Band error present" "No error,Error"
|
|
bitfld.long 0x00 24. " MERROR_REP ,MError error present" "No error,Error"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "L4_IA_ERROR_LOG_L,Log Information About Error Conditions"
|
|
bitfld.long 0x00 31. " MULTI ,Additional error detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request" "No error,Reserved,Address hole,Protection violation"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "LA (Link Agent Registers)"
|
|
base ad:0x48329000
|
|
width 25.
|
|
rgroup.long 0x14++0xb
|
|
line.long 0x00 "L4_LA_NETWORK_H,Identify The Interconnect"
|
|
line.long 0x04 "L4_LA_INITIATOR_INFO_L,Initiator Subsystem Information"
|
|
bitfld.long 0x04 24.--27. " PROT_GROUPS ,The number of protection groups" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NUMBER_REGIONS ,The number of regions"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " SEGMENTS ,The number of segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "L4_LA_INITIATOR_INFO_H,Initiator Subsystem Information"
|
|
bitfld.long 0x08 16.--18. " THREADS ,Number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " CONNID_WIDTH ,Initiator subsystem connID width" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " BYTE_DATA_WIDTH_EXP ,Initiator subsystem data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--4. " ADDR_WIDTH ,Initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control Interconnect Minimum Timeout Values"
|
|
bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,Indicates the timeout period (L4 interconnect clock cycles)" "Disabled,/64,/256,/1024,/4096,?..."
|
|
line.long 0x04 "L4_LA_NETWORK_CONTROL_H,Control Interconnect Global Power Control"
|
|
bitfld.long 0x04 24. " CLOCK_GATE_DISABLE ,All clock gating disable" "No,Yes"
|
|
bitfld.long 0x04 20. " THREAD0_PRI ,Sets thread priority" "No priority,Priority"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EXT_CLOCK ,Entire L4 shut off signal" "No action,Shut off"
|
|
width 0xb
|
|
tree.end
|
|
tree "AP (Address Protection Registers)"
|
|
base ad:0x48328000
|
|
width 19.
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_0_L,Base Address Of 0 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_0_H,Size Of 0 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
rgroup.long 0x108++0x7
|
|
line.long 0x00 "L4_AP_SEGMENT_1_L,Base Address Of 1 Segment"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address of the segment"
|
|
line.long 0x04 "L4_AP_SEGMENT_1_H,Size Of 1 Segment"
|
|
hexmask.long.byte 0x04 0.--4. 1. " SIZE ,Segment size"
|
|
width 31.
|
|
width 19.
|
|
group.long 0x300++0x7
|
|
line.long 0x00 "L4_AP_REGION_0_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_0_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x308++0x7
|
|
line.long 0x00 "L4_AP_REGION_1_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_1_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x310++0x7
|
|
line.long 0x00 "L4_AP_REGION_2_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_2_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x318++0x7
|
|
line.long 0x00 "L4_AP_REGION_3_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_3_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "L4_AP_REGION_4_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_4_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x328++0x7
|
|
line.long 0x00 "L4_AP_REGION_5_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_5_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x330++0x7
|
|
line.long 0x00 "L4_AP_REGION_6_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_6_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x338++0x7
|
|
line.long 0x00 "L4_AP_REGION_7_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_7_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "L4_AP_REGION_8_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_8_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x348++0x7
|
|
line.long 0x00 "L4_AP_REGION_9_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_9_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "L4_AP_REGION_10_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_10_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x358++0x7
|
|
line.long 0x00 "L4_AP_REGION_11_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_11_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "L4_AP_REGION_12_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_12_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x368++0x7
|
|
line.long 0x00 "L4_AP_REGION_13_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_13_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "L4_AP_REGION_14_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_14_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x378++0x7
|
|
line.long 0x00 "L4_AP_REGION_15_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_15_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x380++0x7
|
|
line.long 0x00 "L4_AP_REGION_16_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_16_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x388++0x7
|
|
line.long 0x00 "L4_AP_REGION_17_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_17_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long 0x390++0x7
|
|
line.long 0x00 "L4_AP_REGION_18_L,Base Address Of The Region"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Base address"
|
|
line.long 0x04 "L4_AP_REGION_18_H,Size; Protection Group And Segment ID Of The Region"
|
|
bitfld.long 0x04 24.--27. " SEGMENT_ID ,Identifies the segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " BYTE_DATA_WIDTH_EXP ,Target OCP data byte width" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 1.--5. 1. " SIZE ,Size of the region in bytes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TA (Target Agent Registers)"
|
|
tree "WKUP_TA_GPTIMER12"
|
|
base ad:0x48305000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "WKUP_TA_PRM"
|
|
base ad:0x48309000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "WKUP_TA_WDTIMER1"
|
|
base ad:0x4830D000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "WKUP_TA_GPIO1"
|
|
base ad:0x48311000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "WKUP_TA_WDTIMER2"
|
|
base ad:0x48315000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "WKUP_TA_GPTIMER1"
|
|
base ad:0x48319000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "WKUP_TA_SYNCTIMER32K"
|
|
base ad:0x48321000
|
|
width 23.
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable Error Reporting"
|
|
bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Timeout Bound" "No timeout,1x,4x,16x,64x,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " OCP_RESET ,OCP reset signal control" "No reset,Reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable Clock Power Management"
|
|
bitfld.long 0x00 8. " EXT_CLOCK ,ext_clk_off_i signal on a target agent indicates" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "L4_TA_AGENT_STATUS_L,Error Reporting"
|
|
eventfld.long 0x00 8. " REQ_TIMEOUT ,Request timeout" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "SCM (System Control Module)"
|
|
tree "INTERFACE"
|
|
base ad:0x48002000
|
|
width 19.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_REVISION,Control Module Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION ,Revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CONTROL_SYSCONFIG,Set Various Parameters Relative To The Idle Mode Of The Control Module"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management" "Force-idle,Reserved,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
width 0xb
|
|
tree.end
|
|
tree "PADCONFS"
|
|
base ad:0x48002030
|
|
width 34.
|
|
group.long 0x00++0x43
|
|
line.long 0x0 "CONTROL_PADCONF_SDRC_D0,Configuration Register For Pads sdrc_d0;sdrc_d1"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for sdrc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for sdrc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_SDRC_D2,Configuration Register For Pads sdrc_d2;sdrc_d3"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for sdrc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for sdrc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_SDRC_D4,Configuration Register For Pads sdrc_d4;sdrc_d5"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for sdrc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for sdrc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_SDRC_D6,Configuration Register For Pads sdrc_d6;sdrc_d7"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for sdrc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for sdrc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_SDRC_D8,Configuration Register For Pads sdrc_d8;sdrc_d9"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for sdrc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for sdrc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_SDRC_D10,Configuration Register For Pads sdrc_d10;sdrc_d11"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for sdrc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for sdrc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_SDRC_D12,Configuration Register For Pads sdrc_d12;sdrc_d13"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for sdrc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for sdrc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_SDRC_D14,Configuration Register For Pads sdrc_d14;sdrc_d15"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for sdrc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for sdrc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_SDRC_D16,Configuration Register For Pads sdrc_d16;sdrc_d17"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for sdrc_d17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for sdrc_d16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d16" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x24 "CONTROL_PADCONF_SDRC_D18,Configuration Register For Pads sdrc_d18;sdrc_d19"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for sdrc_d19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for sdrc_d18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d18" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x28 "CONTROL_PADCONF_SDRC_D20,Configuration Register For Pads sdrc_d20;sdrc_d21"
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for sdrc_d21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for sdrc_d20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d20" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x2C "CONTROL_PADCONF_SDRC_D22,Configuration Register For Pads sdrc_d22;sdrc_d23"
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for sdrc_d23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for sdrc_d22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d22" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x30 "CONTROL_PADCONF_SDRC_D24,Configuration Register For Pads sdrc_d24;sdrc_d25"
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for sdrc_d25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d25" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for sdrc_d24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d24" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d24" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x34 "CONTROL_PADCONF_SDRC_D26,Configuration Register For Pads sdrc_d26;sdrc_d27"
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for sdrc_d27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d27" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for sdrc_d26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d26" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d26" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x38 "CONTROL_PADCONF_SDRC_D28,Configuration Register For Pads sdrc_d28;sdrc_d29"
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for sdrc_d29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d29" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for sdrc_d28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d28" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d28" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x3C "CONTROL_PADCONF_SDRC_D30,Configuration Register For Pads sdrc_d30;sdrc_d31"
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for sdrc_d31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d31" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for sdrc_d30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d30" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d30" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x40 "CONTROL_PADCONF_SDRC_CLK,Configuration Register For Pads sdrc_clk;sdrc_dqs0p"
|
|
bitfld.long 0x40 24. " INPUTENABLE1 ,Input enable for sdrc_dqs0p" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_dqs0p" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_dqs0p" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 8. " INPUTENABLE0 ,Input enable for sdrc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "CONTROL_PADCONF_SDRC_CKE,Configuration Register For Pad sdrc_cke0"
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for sdrc_cke0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_cke0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_cke0" "Disabled,Enabled"
|
|
group.long 0x44--0x8f
|
|
line.long 0x0 "CONTROL_PADCONF_SDRC_DQS1,Configuration Register For Pads sdrc_dqs1p;sdrc_dqs2p"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for sdrc_dqs2p" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_dqs2p" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_dqs2p" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for sdrc_dqs1p" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs1p" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs1p" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_SDRC_DQS3,Configuration Register For Pads sdrc_dqs3p;gpmc_a1"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for sdrc_dqs3p" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs3p" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs3p" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_GPMC_A2,Configuration Register For Pads gpmc_a2;gpmc_a3"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_GPMC_A4,Configuration Register For Pads gpmc_a4;gpmc_a5"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_GPMC_A6,Configuration Register For Pads gpmc_a6;gpmc_a7"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_GPMC_A8,Configuration Register For Pads gpmc_a8;gpmc_a9"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_GPMC_A10,Configuration Register For Pads gpmc_a10;gpmc_d0"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for gpmc_a10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a10" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_GPMC_D1,Configuration Register For Pads gpmc_d1;gpmc_d2"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for gpmc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_GPMC_D3,Configuration Register For Pads gpmc_d3;gpmc_d4"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for gpmc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x24 "CONTROL_PADCONF_GPMC_D5,Configuration Register For Pads gpmc_d5;gpmc_d6"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for gpmc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x28 "CONTROL_PADCONF_GPMC_D7,Configuration Register For Pads gpmc_d7;gpmc_d8"
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for gpmc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x2C "CONTROL_PADCONF_GPMC_D9,Configuration Register For Pads gpmc_d9;gpmc_d10"
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d10" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for gpmc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_d9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x30 "CONTROL_PADCONF_GPMC_D11,Configuration Register For Pads gpmc_d11;gpmc_d12"
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d12" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for gpmc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_d11" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x34 "CONTROL_PADCONF_GPMC_D13,Configuration Register For Pads gpmc_d13;gpmc_d14"
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d14" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for gpmc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_d13" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x38 "CONTROL_PADCONF_GPMC_D15,Configuration Register For Pads gpmc_d15;gpmc_ncs0"
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for gpmc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_d15" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x3C "CONTROL_PADCONF_GPMC_NCS1,Configuration Register For Pads gpmc_ncs1;gpmc_ncs2"
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x40 "CONTROL_PADCONF_GPMC_NCS3,Configuration Register For Pads gpmc_ncs3;gpmc_ncs4"
|
|
bitfld.long 0x40 24. " INPUTENABLE1 ,Input enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x40 8. " INPUTENABLE0 ,Input enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x44 "CONTROL_PADCONF_GPMC_NCS5,Configuration Register For Pads gpmc_ncs5;gpmc_ncs6"
|
|
bitfld.long 0x44 24. " INPUTENABLE1 ,Input enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x44 8. " INPUTENABLE0 ,Input enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x48 "CONTROL_PADCONF_GPMC_NCS7,Configuration Register For Pads gpmc_ncs7;gpmc_clk"
|
|
bitfld.long 0x48 24. " INPUTENABLE1 ,Input enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x48 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x48 8. " INPUTENABLE0 ,Input enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x48 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "CONTROL_PADCONF_NADV_ALE,Configuration Register For Pads gpmc_nadv_ale;gpmc_noe"
|
|
group.long 0x94--0xdb
|
|
line.long 0x0 "CONTROL_PADCONF_GPMC_NWE,Configuration Register For Pads gpmc_nwe;gpmc_nbe0_cle"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_nbe0_cle" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_nbe0_cle" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_GPMC_NBE1,Configuration Register For Pads gpmc_nbe1;gpmc_nwp"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_nwp" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_nwp" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_nbe1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_nbe1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_GPMC_WAIT0,Configuration Register For Pads gpmc_wait0;gpmc_wait1"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_wait1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_wait1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for gpmc_wait0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_wait0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_wait0" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_GPMC_WAIT2,Configuration Register For Pads gpmc_wait2;gpmc_wait3"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_wait3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_wait3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_wait2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_wait2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_DSS_PCLK,Configuration Register For Pads dss_pclk;dss_hsync"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_hsync" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_hsync" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_pclk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_pclk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_DSS_VSYNC,Configuration Register For Pads dss_vsync;dss_acbias"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_acbias" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_acbias" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_vsync" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_vsync" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_DSS_DATA0,Configuration Register For Pads dss_data0;dss_data1"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_DSS_DATA2,Configuration Register For Pads dss_data2;dss_data3"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_DSS_DATA4,Configuration Register For Pads dss_data4;dss_data5"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x24 "CONTROL_PADCONF_DSS_DATA6,Configuration Register For Pads dss_data6;dss_data7"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x28 "CONTROL_PADCONF_DSS_DATA8,Configuration Register For Pads dss_data8;dss_data9"
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x2C "CONTROL_PADCONF_DSS_DATA10,Configuration Register For Pads dss_data10;dss_data11"
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data11" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data10" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x30 "CONTROL_PADCONF_DSS_DATA12,Configuration Register For Pads dss_data12;dss_data13"
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data13" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data12" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x34 "CONTROL_PADCONF_DSS_DATA14,Configuration Register For Pads dss_data14;dss_data15"
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data15" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data14" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x38 "CONTROL_PADCONF_DSS_DATA16,Configuration Register For Pads dss_data16;dss_data17"
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data17" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data16" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x3C "CONTROL_PADCONF_DSS_DATA18,Configuration Register For Pads dss_data18;dss_data19"
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data19" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data18" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x40 "CONTROL_PADCONF_DSS_DATA20,Configuration Register For Pads dss_data20;dss_data21"
|
|
bitfld.long 0x40 24. " INPUTENABLE1 ,Input enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data21" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x40 8. " INPUTENABLE0 ,Input enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data20" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x44 "CONTROL_PADCONF_DSS_DATA22,Configuration Register For Pads dss_data22;dss_data23"
|
|
bitfld.long 0x44 24. " INPUTENABLE1 ,Input enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data23" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x44 8. " INPUTENABLE0 ,Input enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data22" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x10c--0x173
|
|
line.long 0x0 "CONTROL_PADCONF_MCBSP2_FSX,Configuration Register For Pads ;mcbsp2_clkx"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp2_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp2_clkx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for " "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for " "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_MCBSP2_DR,Configuration Register For Pads mcbsp2_dr;mcbsp2_dx"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp2_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp2_dx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp2_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp2_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_MMC1_CLK,Configuration Register For Pads mmc1_clk;mmc1_cmd"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_cmd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_cmd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_MMC1_DAT0,Configuration Register For Pads mmc1_dat0;mmc1_dat1"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_MMC1_DAT2,Configuration Register For Pads mmc1_dat2;mmc1_dat3"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_MMC1_DAT4,Configuration Register For Pads mmc1_dat4;mmc1_dat5"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_MMC1_DAT6,Configuration Register For Pads mmc1_dat6;mmc1_dat7"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_MMC2_CLK,Configuration Register For Pads mmc2_clk;mmc2_cmd"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_cmd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_cmd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_MMC2_DAT0,Configuration Register For Pads mmc2_dat0;mmc2_dat1"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x24 "CONTROL_PADCONF_MMC2_DAT2,Configuration Register For Pads mmc2_dat2;mmc2_dat3"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x28 "CONTROL_PADCONF_MMC2_DAT4,Configuration Register For Pads mmc2_dat4;mmc2_dat5"
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x2C "CONTROL_PADCONF_MMC2_DAT6,Configuration Register For Pads mmc2_dat6;mmc2_dat7"
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x30 "CONTROL_PADCONF_MCBSP3_DX,Configuration Register For Pads mcbsp3_dx;mcbsp3_dr"
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp3_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp3_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp3_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp3_dx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x34 "CONTROL_PADCONF_MCBSP3_CLKX,Configuration Register For Pads mcbsp3_clkx;mcbsp3_fsx"
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp3_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp3_fsx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp3_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp3_clkx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x38 "CONTROL_PADCONF_UART2_CTS,Configuration Register For Pads uart2_cts;uart2_rts"
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart2_rts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart2_rts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart2_cts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart2_cts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x3C "CONTROL_PADCONF_UART2_TX,Configuration Register For Pads uart2_tx;uart2_rx"
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart2_rx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart2_rx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart2_tx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart2_tx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x40 "CONTROL_PADCONF_UART1_TX,Configuration Register For Pads uart1_tx;uart1_rts"
|
|
bitfld.long 0x40 24. " INPUTENABLE1 ,Input enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart1_rts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart1_rts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x40 8. " INPUTENABLE0 ,Input enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart1_tx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart1_tx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x44 "CONTROL_PADCONF_UART1_CTS,Configuration Register For Pads uart1_cts;uart1_rx"
|
|
bitfld.long 0x44 24. " INPUTENABLE1 ,Input enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart1_rx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart1_rx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x44 8. " INPUTENABLE0 ,Input enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart1_cts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart1_cts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x48 "CONTROL_PADCONF_MCBSP4_CLKX,Configuration Register For Pads mcbsp4_clkx;mcbsp4_dr"
|
|
bitfld.long 0x48 24. " INPUTENABLE1 ,Input enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp4_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x48 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp4_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x48 8. " INPUTENABLE0 ,Input enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp4_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x48 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp4_clkx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4C "CONTROL_PADCONF_MCBSP4_DX,Configuration Register For Pads mcbsp4_dx;mcbsp4_fsx"
|
|
bitfld.long 0x4C 24. " INPUTENABLE1 ,Input enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp4_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4C 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp4_fsx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4C 8. " INPUTENABLE0 ,Input enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp4_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp4_dx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x50 "CONTROL_PADCONF_MCBSP1_CLKR,Configuration Register For Pads mcbsp1_clkr;mcbsp1_fsr"
|
|
bitfld.long 0x50 24. " INPUTENABLE1 ,Input enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp1_fsr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x50 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp1_fsr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x50 8. " INPUTENABLE0 ,Input enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp1_clkr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x50 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp1_clkr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x54 "CONTROL_PADCONF_MCBSP1_DX,Configuration Register For Pads mcbsp1_dx;mcbsp1_dr"
|
|
bitfld.long 0x54 24. " INPUTENABLE1 ,Input enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp1_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x54 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp1_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x54 8. " INPUTENABLE0 ,Input enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp1_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x54 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp1_dx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x58 "CONTROL_PADCONF_MCBSP_CLKS,Configuration Register For Pads mcbsp_clks;mcbsp1_fsx"
|
|
bitfld.long 0x58 24. " INPUTENABLE1 ,Input enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp1_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x58 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp1_fsx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x58 8. " INPUTENABLE0 ,Input enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp_clks" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x58 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp_clks" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x5C "CONTROL_PADCONF_MCBSP1_CLKX,Configuration Register For Pads mcbsp1_clkx;uart3_cts_rctx"
|
|
bitfld.long 0x5C 24. " INPUTENABLE1 ,Input enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart3_cts_rctx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x5C 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart3_cts_rctx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x5C 8. " INPUTENABLE0 ,Input enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp1_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x5C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp1_clkx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x60 "CONTROL_PADCONF_UART3_RTS_SD,Configuration Register For Pads uart3_rts_sd;uart3_rx_irrx"
|
|
bitfld.long 0x60 24. " INPUTENABLE1 ,Input enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart3_rx_irrx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x60 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart3_rx_irrx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x60 8. " INPUTENABLE0 ,Input enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart3_rts_sd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x60 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart3_rts_sd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x64 "CONTROL_PADCONF_UART3_TX_IRTX,Configuration Register For Pads uart3_tx_irtx;"
|
|
bitfld.long 0x64 8. " INPUTENABLE0 ,Input enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart3_tx_irtx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x64 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart3_tx_irtx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x188--0x1b3
|
|
line.long 0x0 "CONTROL_PADCONF_I2C1_SCL,Configuration Register For Pads ;i2c1_scl"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c1_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c1_scl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_I2C1_SDA,Configuration Register For Pads i2c1_sda;i2c2_scl"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c2_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c2_scl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c1_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_I2C2_SDA,Configuration Register For Pads i2c2_sda;i2c3_scl"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c3_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c3_scl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c2_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for i2c2_sda" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_I2C3_SDA,Configuration Register For Pads i2c3_sda;hdq_sio"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hdq_sio" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for hdq_sio" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c3_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for i2c3_sda" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_MCSPI1_CLK,Configuration Register For Pads mcspi1_clk;mcspi1_simo"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi1_simo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi1_simo" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_MCSPI1_SOMI,Configuration Register For Pads mcspi1_somi;mcspi1_cs0"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi1_cs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi1_cs0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_somi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_somi" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_MCSPI1_CS1,Configuration Register For Pads mcspi1_cs1;mcspi1_cs2"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi1_cs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi1_cs2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_cs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_cs1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_MCSPI1_CS3,Configuration Register For Pads mcspi1_cs3;mcspi2_clk"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi2_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi2_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_cs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_cs3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_MCSPI2_SIMO,Configuration Register For Pads mcspi2_simo;mcspi2_somi"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi2_somi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi2_somi" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi2_simo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi2_simo" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x24 "CONTROL_PADCONF_MCSPI2_CS0,Configuration Register For Pads mcspi2_cs0;mcspi2_cs1"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi2_cs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi2_cs1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi2_cs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi2_cs0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x28 "CONTROL_PADCONF_SYS_NIRQ,Configuration Register For Pads sys_nirq;"
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_nirq" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_nirq" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x5a8--0x5fb
|
|
line.long 0x0 "CONTROL_PADCONF_ETK_CLK,Configuration Register For Pads etk_clk;etk_ctl"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_ctl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_ctl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_ETK_D0,Configuration Register For Pads etk_d0;etk_d1"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_ETK_D2,Configuration Register For Pads etk_d2;etk_d3"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_ETK_D4,Configuration Register For Pads etk_d4;etk_d5"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_ETK_D6,Configuration Register For Pads etk_d6;etk_d7"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_ETK_D8,Configuration Register For Pads etk_d8;etk_d9"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_ETK_D10,Configuration Register For Pads etk_d10;etk_d11"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d11" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d10" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_ETK_D12,Configuration Register For Pads etk_d12;etk_d13"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d13" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d12" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_ETK_D14,Configuration Register For Pads etk_d14;etk_d15"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d15" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d14" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x1b4--0x1f7
|
|
line.long 0x0 "CONTROL_PADCONF_CCDC_PCLK,Configuration Register For Pads ccdc_pclk;ccdc_field"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for ccdc_field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for ccdc_field" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for ccdc_field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for ccdc_field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for ccdc_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_pclk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_pclk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_CCDC_HD,Configuration Register For Pads ccdc_hd;ccdc_vd"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for ccdc_vd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for ccdc_vd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for ccdc_vd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for ccdc_vd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for ccdc_hd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_hd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_hd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_hd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_CCDC_WEN,Configuration Register For Pads ccdc_wen;ccdc_data0"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for ccdc_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for ccdc_data0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for ccdc_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for ccdc_data0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for ccdc_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_wen" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_wen" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_CCDC_DATA1,Configuration Register For Pads ccdc_data1;ccdc_data2"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for ccdc_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for ccdc_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for ccdc_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for ccdc_data2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for ccdc_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_data1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_CCDC_DATA3,Configuration Register For Pads ccdc_data3;ccdc_data4"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for ccdc_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for ccdc_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for ccdc_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for ccdc_data4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for ccdc_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_data3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_CCDC_DATA5,Configuration Register For Pads ccdc_data5;ccdc_data6"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for ccdc_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for ccdc_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for ccdc_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for ccdc_data6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for ccdc_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_data5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x18 "CONTROL_PADCONF_CCDC_DATA7,Configuration Register For Pads ccdc_data7;rmii_mdio_data"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for rmii_mdio_data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for rmii_mdio_data" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for rmii_mdio_data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for rmii_mdio_data" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for ccdc_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for ccdc_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for ccdc_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for ccdc_data7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x1C "CONTROL_PADCONF_RMII_MDIO_CLK,Configuration Register For Pads rmii_mdio_clk;rmii_rxd0"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for rmii_rxd0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for rmii_rxd0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for rmii_rxd0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for rmii_rxd0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for rmii_mdio_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for rmii_mdio_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for rmii_mdio_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for rmii_mdio_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x20 "CONTROL_PADCONF_RMII_RXD1,Configuration Register For Pads rmii_rxd1;rmii_crs_dv"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for rmii_crs_dv" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for rmii_crs_dv" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for rmii_crs_dv" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for rmii_crs_dv" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for rmii_rxd1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for rmii_rxd1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for rmii_rxd1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for rmii_rxd1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x24 "CONTROL_PADCONF_RMII_RXER,Configuration Register For Pads rmii_rxer;rmii_txd0"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for rmii_txd0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for rmii_txd0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for rmii_txd0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for rmii_txd0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for rmii_rxer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for rmii_rxer" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for rmii_rxer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for rmii_rxer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x28 "CONTROL_PADCONF_RMII_TXD1,Configuration Register For Pads rmii_txd1;rmii_txen"
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for rmii_txen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for rmii_txen" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for rmii_txen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for rmii_txen" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for rmii_txd1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for rmii_txd1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for rmii_txd1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for rmii_txd1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x2C "CONTROL_PADCONF_RMII_50MHZ_CLK,Configuration Register For Pads rmii_50mhz_clk;usb0_drvvbus"
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for usb0_drvvbus" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for usb0_drvvbus" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for usb0_drvvbus" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16.--18. " MUXMODE1 ,Functional multiplexing selection for usb0_drvvbus" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for rmii_50mhz_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for rmii_50mhz_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for rmii_50mhz_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " MUXMODE0 ,Functional multiplexing selection for rmii_50mhz_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x30 "CONTROL_PADCONF_HECC1_TXD,Configuration Register For Pads hecc1_txd;hecc1_rxd"
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for hecc1_rxd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hecc1_rxd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for hecc1_rxd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16.--18. " MUXMODE1 ,Functional multiplexing selection for hecc1_rxd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for hecc1_txd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hecc1_txd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for hecc1_txd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " MUXMODE0 ,Functional multiplexing selection for hecc1_txd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x34 "CONTROL_PADCONF_SYS_BOOT7,Configuration Register For Pads sdrc_dqs0n;"
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for sdrc_dqs0n" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs0n" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs0n" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x38 "CONTROL_PADCONF_SDRC_DQS1N,Configuration Register For Pads sdrc_dqs1n;sdrc_dqs2n"
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for sdrc_dqs2n" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_dqs2n" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_dqs2n" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for sdrc_dqs1n" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs1n" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs1n" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x3C "CONTROL_PADCONF_SDRC_DQS3N,Configuration Register For Pads sdrc_dqs3n;sdrc_strben_dly0"
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for sdrc_strben_dly0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_strben_dly0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_strben_dly0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for sdrc_dqs3n" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs3n" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs3n" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x40 "CONTROL_PADCONF_SDRC_STRBEN_DLY1,Configuration Register For Pads sdrc_strben_dly1;"
|
|
bitfld.long 0x40 8. " INPUTENABLE0 ,Input enable for sdrc_strben_dly1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_strben_dly1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_strben_dly1" "Disabled,Enabled"
|
|
textline " "
|
|
width 0xb
|
|
tree.end
|
|
tree "GENERAL"
|
|
base ad:0x48002270
|
|
width 21.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "CONTROL_PADCONF_OFF,Off mode pad configuration register"
|
|
bitfld.long 0x00 2. " WKUPCTRLCLOCKDIV ,Wkup_ctrl module clock divider" "Clk/4,Clk/2"
|
|
line.long 0x04 "CONTROL_DEVCONF0,Static Device Configuration Register-0"
|
|
bitfld.long 0x04 6. " MCBSP2_CLKS ,Select the CLKS input for the module McBSP2" "PRCM clk,External McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MCBSP1_FSR ,Select the FSR input for the module McBSP1" "McBSP1_FSR,McBSP1_FSX"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MCBSP1_CLKR ,Select the CLKR input for the module McBSP1" "McBSP1_CLKR,McBSP1_CLKX"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCBSP1_CLKS ,Select the CLKS input for the module McBSP1" "PRCM clk,External McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SENSDMAREQ1 ,Set sensitivity on SYS_NDMAREQ1 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SENSDMAREQ0 ,Set sensitivity on SYS_NDMAREQ0 input pin" "Level,Edge"
|
|
line.long 0x08 "CONTROL_MEM_DFTRW0,DFT Read And Write Controls For Memory Blocks"
|
|
bitfld.long 0x08 15. " MEMORY4DFTGLXCTRL ,ETB memory DFT GLX ctrl" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 14. " MEMORY3DFTGLXCTRL ,WKUP memory DFT GLX ctrl" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " MEMORY2DFTWRITECTRL ,McBSP2 memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " MEMORY2DFTREADCTRL ,McBSP2 memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 7.--8. " MEMORY1DFTWRITECTRL ,EMAC; USBOTG; HECC and VPFE memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 5.--6. " MEMORY1DFTREADCTRL ,EMAC; USBOTG; HECC and VPFE memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MEMORY0DFTGLXCTRL ,SGX_ss memory DFT GLX ctrl" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " MEMORY0DFTWRITECTRL ,SGX_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MEMORY0DFTREADCTRL ,SGX_ss memory DFT read ctrl" "0,1,2,3"
|
|
line.long 0x0C "CONTROL_MEM_DFTRW1,DFT Read And Write Controls For Memory Blocks"
|
|
bitfld.long 0x0C 31. " DFTREADWRITEENABLE ,Control use of CONTROL_MEM_DFTRWx" "Test sub-system,CONTROL_MEM_DFTRWx"
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " MEMORY10DFTWRITECTRL ,DSI memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " MEMORY10DFTREADCTRL ,DSI memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " MEMORY9DFTWRITECTRL ,DISP_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " MEMORY9DFTREADCTRL ,DISP_ss memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 11.--12. " MEMORY7DFTWRITECTRL ,MPU_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 9.--10. " MEMORY7DFTREADCTRL ,MPU_ss memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " MEMORY6DFTGLXCTRL ,OCMRAM memory DFT GLX ctrl" "0,1"
|
|
width 23.
|
|
group.long 0x20++0x1b
|
|
line.long 0x00 "CONTROL_MSUSPENDMUX_0,MSuspend Control Register"
|
|
bitfld.long 0x00 21.--23. " MCBSP2MSCTRL ,Control McBSP_2 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " MCBSP1MSCTRL ,Control McBSP_1 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " I2C2MSCTRL ,Control I2C_2 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " I2C1MSCTRL ,Control I2C_1 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
line.long 0x04 "CONTROL_MSUSPENDMUX_1,MSuspend Control Register"
|
|
bitfld.long 0x04 27.--29. " GPTM7MSCTRL ,Control General Purpose Timer 7 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x04 24.--26. " GPTM6MSCTRL ,Control General Purpose Timer 6 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " GPTM5MSCTRL ,Control General Purpose Timer 5 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " GPTM4MSCTRL ,Control General Purpose Timer 4 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " GPTM3MSCTRL ,Control General Purpose Timer 3 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " GPTM2MSCTRL ,Control General Purpose Timer 2 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " GPTM1MSCTRL ,Control General Purpose Timer 1 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
line.long 0x08 "CONTROL_MSUSPENDMUX_2,MSuspend Control Register"
|
|
bitfld.long 0x08 27.--29. " SYNCTMMSCTRL ,Control Sync Timer32K sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " WD3MSCTRL ,Control Watch Dog 4 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--20. " WD2MSCTRL ,Control Watch Dog 2 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 15.--17. " WD1MSCTRL ,Control Watch Dog 1 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " GPTM12MSCTRL ,Control General Purpose Timer 12 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 9.--11. " GPTM11MSCTRL ,Control General Purpose Timer 11 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--8. " GPTM10MSCTRL ,Control General Purpose Timer 10 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " GPTM9MSCTRL ,Control General Purpose Timer 9 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " GPTM8MSCTRL ,Control General Purpose Timer 8 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
line.long 0x0C "CONTROL_MSUSPENDMUX_3,MSuspend Control Register"
|
|
bitfld.long 0x0C 27.--29. " SHA2MSCTRL ,Control SHA sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--26. " DES2MSCTRL ,Control DES3DES sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--20. " AES1MSCTRL ,Control AES sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 15.--17. " RNGMSCTRL ,Control RNG sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--14. " SHA1MSCTRL ,Control SHA sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 9.--11. " DES1MSCTRL ,Control DES3DES sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " AES2MSCTRL ,Control AES sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
line.long 0x10 "CONTROL_MSUSPENDMUX_4,MSuspend Control Register"
|
|
bitfld.long 0x10 27.--29. " DMAMSCTRL ,Control DMA sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
line.long 0x14 "CONTROL_MSUSPENDMUX_5,MSuspend Control Register"
|
|
bitfld.long 0x14 21.--23. " I2C3MSCTRL ,Control I2C-3 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6.--8. " MCBSP5MSCTRL ,Control McBSP-5 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " MCBSP4MSCTRL ,Control McBSP-4 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MCBSP3MSCTRL ,Control McBSP-3 sensitivity to MCU" "No sensitivity,MCU,?..."
|
|
line.long 0x18 "CONTROL_MSUSPENDMUX_6,MSuspend Control register"
|
|
bitfld.long 0x18 6.--8. " USB20OTGMSCTRL ,Control sensitivity USB20OTGMSCTRL to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x18 3.--5. " CPGMACMSCTRL ,Control sensitivity CPGMACMSCTRL to MCU" "No sensitivity,MCU,?..."
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " HECCMSCTRL ,Control sensitivity HECCMSCTRL to MCU" "No sensitivity,MCU,?..."
|
|
width 24.
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "CONTROL_SEC_CTRL,Security Control Register"
|
|
bitfld.long 0x00 31. " SECCTRLWRDISABLE ,Security Control Register write disable control" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 30. " SECUREMODEINITDONE ,Used by SoftWare to indicate complete secure mode initialization" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CORERAMSECURESAVE ,Used for indicating the nature of secure content save" "No content,Retention operation,Low Iddq operation,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " CPEFUSEDECODEDN ,Used for indicating the encoded state of the MSV and CEK" "Decoded,Not decoded"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CPEFUSEWRDISABLE ,Used to indicate if it is allowed to write in the SWEV" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPEFUSEAUTOLOADDONE ,Used by SoftWare to indicate complete secure mode" "In progress/Not started,Done"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BSCDISABLED ,Control the use of BSC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMLEDSYSTEMENABLE ,Control the use of DMLED module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OBSERVABILITYDISABLE ,Control the observability feature" "Configured,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PADCONFACCDISABLE ,Control the write access to the pad configuration registers" "Unrestricted,Allowed in secure mode"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECKEYACCENABLE ,Random Key and Customer Key and Test_key eFuse access control" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDREGENABLE ,Secure watchdog registers update access control" "Not allowed,Allowed in secure mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WDOPDISABLE ,Secure Watchdog operation enable control" "Running,Frozen"
|
|
group.long 0x68++0x13
|
|
line.long 0x00 "CONTROL_DEVCONF1,Static Device Configuration Register 1"
|
|
bitfld.long 0x00 18. " TVOUTBYPASS ,Active high enable Dual 10-bit video DAC TV out bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TVACEN ,TV AC coupled load enable for TV output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPUFORCEWRNP ,Force MPU writes to others to be non posted" "Posted,Not posted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SENSDMAREQ3 ,Set sensitivity on SYS_NDMAREQ3 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SENSDMAREQ2 ,Set sensitivity on SYS_NDMAREQ2 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MMCSDIO2ADPCLKISEL ,MMC/SDIO2 Module Input Clock selection" "External,Internal loop-back"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MCBSP5_CLKS ,Select the CLKS input for the module McBSP5" "PRCM functional clk,External McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MCBSP4_CLKS ,Select the CLKS input for the module McBSP4" "PRCM functional clk,External McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCBSP3_CLKS ,Select the CLKS input for the module McBSP3" "PRCM functional clk,External McBSP_CLKS"
|
|
group.long 0x70++0x0b
|
|
line.long 0x00 "CONTROL_SEC_STATUS,Security Status Register"
|
|
bitfld.long 0x00 30. " MPUL2ISNOTACCESSIBLE ,L2 I;D$ accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MPUL1ISNOTACCESSIBLE ,L1 I$ accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x00 25. " COREBANK2ISNOTACCESSIBLE ,RAM Bank2 accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COREBANK1ISNOTACCESSIBLE ,RAM Bank1 accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MPUL2ISDESTROYED ,L2 I;D$ damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MPUL1ISDESTROYED ,L1 I$ damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " COREBANK2ISDESTROYED ,RAM Bank2 damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " COREBANK1ISDESTROYED ,RAM Bank1 damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBHOSTWKUPRST ,USB Host Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NEONWKUPRST ,Neon Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SGXWKUPRST ,SGX Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DISPWKUPRST ,Display Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PERWKUPRST ,Peripheral Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMUWKUPRST ,Emulation Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COREWKUPRST ,Core Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPUWKUPRST ,MPU domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAMBISTSTARTED ,RAM BIST Started status" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECVIOLATIONRESET ,Security violation status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECWDRESET ,Secure watchdog reset status" "Not secure,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GLOBALWARMRESET ,Global Warm Reset (GWR) status" "Not GWR,GWR"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POWERONRESET ,Power On Reset status" "Not PowerOn,PowerOn"
|
|
line.long 0x04 "CONTROL_SEC_ERR_STATUS,Security Error Status Register"
|
|
bitfld.long 0x04 17. " L4EMUFWERROR ,L4 Emulation Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 16. " L4PERIPHFWERROR ,L4 Peripheral Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SMXAPERTFWERROR ,L3 Register target Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SECMODFWERROR ,Secure State Machine Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DISPDMAACCERROR ,Disp Dma Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SYSDMAACCERROR ,sDma Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " L4COREFWERROR ,L4 Security Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SMSFWERROR ,SMS Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SMSFUNCFWERROR ,SMS Functional Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 2. " GPMCFWERROR ,GPMC Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OCMRAMFWERROR ,On Chip Ram Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OCMROMFWERROR ,On Chip Rom Firewall Error" "No error,Error"
|
|
width 32.
|
|
line.long 0x08 "CONTROL_SEC_ERR_STATUS_DEBUG,Security Error Status Debug Register"
|
|
bitfld.long 0x08 17. " L4EMUDBGFWERROR ,L4 Emulation Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 16. " L4PERIPHERALDBGFWERROR ,L4 Peripheral Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 12. " SMXAPERTDBGFWERROR ,L3 Register target Debug Firewall error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 7. " L4COREDBGFWERROR ,L4 Core Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SMSDBGFWERROR ,SMS Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 2. " GPMCDBGFWERROR ,GPMC Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OCMRAMDBGFWERROR ,On Chip Ram Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 0. " OCMROMDBGFWERROR ,On Chip Rom Debug Firewall Error" "No error,Error"
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "CONTROL_STATUS,Control Module Status Register"
|
|
bitfld.long 0x00 8.--10. " DEVICETYPE ,Device Type captured at reset time" "Reserved,Emulator,Secure,GP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYSBOOT_5 ,sys_boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYSBOOT_4 ,sys_boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYSBOOT_3 ,sys_boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSBOOT_2 ,sys_boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SYSBOOT_1 ,sys_boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYSBOOT_0 ,sys_boot pin values sampled at power-on reset" "No reset,Reset"
|
|
line.long 0x04 "CONTROL_GENERAL_PURPOSE_STATUS,Status bits reflecting chip internal states"
|
|
bitfld.long 0x04 31. " RNGIDLE ,RNGIdle output from the RNG module" "Low,High"
|
|
width 24.
|
|
rgroup.long 0x90++0x13
|
|
line.long 0x00 "CONTROL_RPUB_KEY_H_0,Root Public Key Hash Bits[31:0] Fuse Keys [31:0]"
|
|
line.long 0x04 "CONTROL_RPUB_KEY_H_1,Root Public Key Hash Bits[63:32] Fuse Keys [62:32]"
|
|
line.long 0x08 "CONTROL_RPUB_KEY_H_2,Root Public Key Hash Bits[95:64] Fuse Keys [95:64]"
|
|
line.long 0x0c "CONTROL_RPUB_KEY_H_3,Root Public Key Hash Bits[127:96] Fuse Keys [127:96]"
|
|
line.long 0x10 "CONTROL_RPUB_KEY_H_4,Root Public Key Hash Bits[159:128] Fuse Keys [159:128]"
|
|
rgroup.long 0xA8++0x1F
|
|
line.long 0x00 "CONTROL_RAND_KEY_0,Random Key bits[31:0] Fuse Keys [223:192]"
|
|
line.long 0x04 "CONTROL_RAND_KEY_1,Random Key bits[63:32] Fuse Keys [255:224]"
|
|
line.long 0x08 "CONTROL_RAND_KEY_2,Random Key bits[95:64] Fuse Keys [287:256]"
|
|
line.long 0x0C "CONTROL_RAND_KEY_3,Random Key bits[127:96] Fuse Keys [319:288]"
|
|
line.long 0x10 "CONTROL_CUST_KEY_0,Customer Key bits[31:0] Fuse Keys [351:320]"
|
|
line.long 0x14 "CONTROL_CUST_KEY_1,Customer Key bits[63:32] Fuse Keys [383:352]"
|
|
line.long 0x18 "CONTROL_CUST_KEY_2,Customer Key bits[95:64] Fuse Keys [415:384]"
|
|
line.long 0x1C "CONTROL_CUST_KEY_3,Customer Key bits[127:96] Fuse Keys [447:416]"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "CONTROL_USB_CONF_0,USB Fuse conf [31:0] USB Product ID [31:16] Vendor ID [15:0]"
|
|
line.long 0x04 "CONTROL_USB_CONF_1,USB Fuse conf [63:32] SEQ_DISADAPTCLK[1] USB PHY Detection Mode [0]"
|
|
rgroup.long 0x110++0x07
|
|
line.long 0x00 "CONTROL_FUSE_EMAC_LSB,Fuse OPP [95:72]"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FUSE_OPP_95_72 ,Fuse OPP [95:72]"
|
|
line.long 0x04 "CONTROL_FUSE_EMAC_MSB,Fuse OPP [119:96]"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " FUSE_OPP_119_96 ,Fuse OPP [119:96]"
|
|
rgroup.long 0x130++0x47
|
|
line.long 0x00 "CONTROL_FUSE_SR,Fuse SR1 and SR2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FUSE_SR2 ,Fuse SR 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FUSE_SR1 ,Fuse SR 1"
|
|
line.long 0x04 "CONTROL_CEK_0,Customer Key [31:0]"
|
|
line.long 0x08 "CONTROL_CEK_1,Customer Key [63:32]"
|
|
line.long 0x0C "CONTROL_CEK_2,Customer Key [95:64]"
|
|
line.long 0x10 "CONTROL_CEK_3,Customer Key [127:96]"
|
|
line.long 0x14 "CONTROL_MSV_0,Model specific value [31:0]"
|
|
line.long 0x18 "CONTROL_CEK_BCH_0,Cpefuse CEK (BCH Decoded) [31:0]"
|
|
line.long 0x1C "CONTROL_CEK_BCH_1,Cpefuse CEK (BCH Decoded) [63:32]"
|
|
line.long 0x20 "CONTROL_CEK_BCH_2,Cpefuse CEK (BCH Decoded) [95:64]"
|
|
line.long 0x24 "CONTROL_CEK_BCH_3,Cpefuse CEK (BCH Decoded) [127:96]"
|
|
line.long 0x28 "CONTROL_CEK_BCH_4,Cpefuse CEK (BCH Decoded) [143:128]"
|
|
line.long 0x2C "CONTROL_MSV_BCH_0,Cpefuse MSV (BCH Decoded) [31:0]"
|
|
line.long 0x30 "CONTROL_MSV_BCH_1,Cpefuse MSV (BCH Decoded) [63:32]"
|
|
line.long 0x34 "CONTROL_SWRV_0,Software revision value [31:0]"
|
|
line.long 0x38 "CONTROL_SWRV_1,Software revision value [63:32]"
|
|
line.long 0x3C "CONTROL_SWRV_2,Software revision value [95:64]"
|
|
line.long 0x40 "CONTROL_SWRV_3,Software revision value [127:96]"
|
|
line.long 0x44 "CONTROL_SWRV_4,Software revision value [159:128]"
|
|
group.long 0x1B0--0x1d3
|
|
line.long 0x0 "CONTROL_DEBOBS_0,Set Of Signals To Be Observed For hw_dbg0 and hw_dbg1 "
|
|
hexmask.long.byte 0x0 16.--22. 1. " OBSMUX0 ,Select the set of signals to be exported for WKUPOBSMUX0 "
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--6. 1. " OBSMUX1 ,Select the set of signals to be exported for WKUPOBSMUX1 "
|
|
line.long 0x4 "CONTROL_DEBOBS_1,Set Of Signals To Be Observed For hw_dbg2 and hw_dbg3 "
|
|
hexmask.long.byte 0x4 16.--22. 1. " OBSMUX2 ,Select the set of signals to be exported for WKUPOBSMUX2 "
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " OBSMUX3 ,Select the set of signals to be exported for WKUPOBSMUX3 "
|
|
line.long 0x8 "CONTROL_DEBOBS_2,Set Of Signals To Be Observed For hw_dbg4 and hw_dbg5 "
|
|
hexmask.long.byte 0x8 16.--22. 1. " OBSMUX4 ,Select the set of signals to be exported for WKUPOBSMUX4 "
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--6. 1. " OBSMUX5 ,Select the set of signals to be exported for WKUPOBSMUX5 "
|
|
line.long 0xC "CONTROL_DEBOBS_3,Set Of Signals To Be Observed For hw_dbg6 and hw_dbg7 "
|
|
hexmask.long.byte 0xC 16.--22. 1. " OBSMUX6 ,Select the set of signals to be exported for WKUPOBSMUX6 "
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--6. 1. " OBSMUX7 ,Select the set of signals to be exported for WKUPOBSMUX7 "
|
|
line.long 0x10 "CONTROL_DEBOBS_4,Set Of Signals To Be Observed For hw_dbg8 and hw_dbg9 "
|
|
hexmask.long.byte 0x10 16.--22. 1. " OBSMUX8 ,Select the set of signals to be exported for WKUPOBSMUX8 "
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--6. 1. " OBSMUX9 ,Select the set of signals to be exported for WKUPOBSMUX9 "
|
|
line.long 0x14 "CONTROL_DEBOBS_5,Set Of Signals To Be Observed For hw_dbg10 and hw_dbg11"
|
|
hexmask.long.byte 0x14 16.--22. 1. " OBSMUX10 ,Select the set of signals to be exported for WKUPOBSMUX10"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--6. 1. " OBSMUX11 ,Select the set of signals to be exported for WKUPOBSMUX11"
|
|
line.long 0x18 "CONTROL_DEBOBS_6,Set Of Signals To Be Observed For hw_dbg12 and hw_dbg13"
|
|
hexmask.long.byte 0x18 16.--22. 1. " OBSMUX12 ,Select the set of signals to be exported for WKUPOBSMUX12"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--6. 1. " OBSMUX13 ,Select the set of signals to be exported for WKUPOBSMUX13"
|
|
line.long 0x1C "CONTROL_DEBOBS_7,Set Of Signals To Be Observed For hw_dbg14 and hw_dbg15"
|
|
hexmask.long.byte 0x1C 16.--22. 1. " OBSMUX14 ,Select the set of signals to be exported for WKUPOBSMUX14"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--6. 1. " OBSMUX15 ,Select the set of signals to be exported for WKUPOBSMUX15"
|
|
line.long 0x20 "CONTROL_DEBOBS_8,Set Of Signals To Be Observed For hw_dbg16 and hw_dbg17"
|
|
hexmask.long.byte 0x20 16.--22. 1. " OBSMUX16 ,Select the set of signals to be exported for WKUPOBSMUX16"
|
|
textline " "
|
|
hexmask.long.byte 0x20 0.--6. 1. " OBSMUX17 ,Select the set of signals to be exported for WKUPOBSMUX17"
|
|
width 24.
|
|
group.long 0x7ec++0x03
|
|
line.long 0x00 "CONTROL_WKUP_CTRL,USB TXEN polarity control and log modem warm reset source mux sel"
|
|
bitfld.long 0x00 2. " MM_FSUSB3_TXEN_N_OUT_POLARITY_CTRL ,Polarity control for TXEN signal of serial USB interface;port3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MM_FSUSB2_TXEN_N_OUT_POLARITY_CTRL ,Polarity control for TXEN signal of serial USB interface;port2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MM_FSUSB1_TXEN_N_OUT_POLARITY_CTRL ,Polarity control for TXEN signal of serial USB interface;port1" "Low,High"
|
|
width 32.
|
|
group.long 0x1E0++0xf
|
|
line.long 0x00 "CONTROL_DSS_DPLL_SPREADING,EMI Reduction Feature For Display_SS/DSI DPLL Control"
|
|
bitfld.long 0x00 7. " DSS_SPREADING_ENABLE_STATUS ,Indicates the status of the SSC feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DSS_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DSS_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DSS_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
line.long 0x04 "CONTROL_CORE_DPLL_SPREADING,EMI Reduction feature for CORE domain DPLL"
|
|
bitfld.long 0x04 7. " CORE_SPREADING_ENABLE_STATUS ,Indicates the status of the SSC feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CORE_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " CORE_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CORE_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
line.long 0x08 "CONTROL_PER_DPLL_SPREADING,EMI Reduction feature for PER domain DPLL"
|
|
bitfld.long 0x08 7. " PER_SPREADING_ENABLE_STATUS ,Indicates the status of the Spreading feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PER_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " PER_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " PER_SPREADING_RATE ,Controls the rate of frequency modulation" "Reserved,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
line.long 0x0c "CONTROL_USBHOST_DPLL_SPREADING,EMI Reduction feature for USBHOST DPLL"
|
|
bitfld.long 0x0c 7. " USBHOST_SPREADING_ENABLE_STATUS ,Indicates the status of the Spreading feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " USBHOST_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--3. " USBHOST_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x0c 0.--1. " USBHOST_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
width 40.
|
|
group.long 0x228++0x17
|
|
line.long 0x00 "CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH,OCM RAM Dynamic Power Framework Handing"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " REGIONOCMRAMFWADDRMATCH ,Refer to SMX FW addr_match field"
|
|
line.long 0x04 "CONTROL_DPF_OCM_RAM_FW_REQINFO,OCM RAM Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x04 0.--15. 1. " REGIONOCMRAMFWREQINFO ,Refer to SMX FW REQINFO permission field"
|
|
line.long 0x08 "CONTROL_DPF_OCM_RAM_FW_WR,OCM RAM Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x08 0.--15. 1. " REGIONOCMRAMFWWR ,Refer to SMX FW WR permission field"
|
|
line.long 0x0c "CONTROL_DPF_REGION4_GPMC_FW_ADDR_MATCH,GPMC Dynamic Power Framework Handing"
|
|
hexmask.long 0x0c 0.--29. 1. " REGION4GPMCFWADDRMATCH ,Exported value to SMX FW region 4 GPMC ADDR_MATCH4 field"
|
|
line.long 0x10 "CONTROL_DPF_REGION4_GPMC_FW_REQINFO,GPMC Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x10 0.--15. 1. " REGION4GPMCFWREQINFO ,Exported value to SMX FW region 4 GPMC REQINFO_PERMISSION_4 field"
|
|
line.long 0x14 "CONTROL_DPF_REGION4_GPMC_FW_WR,GPMC Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x14 0.--15. 1. " REGION4GPMCFWWR ,Exported value to SMX FW region 4 GPMC WRITE_PERMISSION_4 field"
|
|
group.long 0x24C++0x7
|
|
line.long 0x00 "CONTROL_APE_FW_DEFAULT_SECURE_LOCK,Firewall Security Lock Features Control Register"
|
|
bitfld.long 0x00 28. " L4TIMERDEFAULTDEBUGLOCK ,TIMER12 debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 26. " L4DISPDEFAULTDEBUGLOCK ,DISPLAY debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 25. " L4CRYPTODEFAULTDEBUGLOCK ,CRYPTO debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 24. " L4COREAPDEFAULTDEBUGLOCK ,L4 CORE AP debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L4TIMERDEFAULTSECURELOCK ,TIMER12 secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 18. " L4DISPDEFAULTSECURELOCK ,DISPLAY secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L4CRYPTODEFAULTSECURELOCK ,CRYPTO secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 16. " L4COREAPDEFAULTSECURELOCK ,L4 CORE AP secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMSDEFAULTDEBUGLOCK ,SMS debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OCMRAMDEFAULTDEBUGLOCK ,OCM-RAM debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IPSSDEFAULTDEBUGLOCK ,EMAC;USBOTG;HECC & VPFE debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPMCDEFAULTDEBUGLOCK ,GPMC debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMSDEFAULTSECURELOCK ,SMS public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCMRAMDEFAULTSECURELOCK ,OCM-RAM public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IPSSDEFAULTSECURELOCK ,EMAC;USBOTG;HECC & VPFE public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPMCDEFAULTSECURELOCK ,GPMC public" "Not public,Public"
|
|
line.long 0x04 "CONTROL_OCMROM_SECURE_DEBUG,Secure ROM Code Debug Configuration Register"
|
|
bitfld.long 0x04 0. " OCMROMSECUREDEBUG ,SECURE ROM access is granted for debug purposes" "Not granted,Granted"
|
|
group.long 0x264++0x3
|
|
line.long 0x00 "CONTROL_EXT_SEC_CONTROL,EXT SEC Control Register"
|
|
bitfld.long 0x00 2. " I2CSENABLE ,I2C module access control" "Unrestricted,Allowed in Secure Mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CCSECURITYDISABLE ,Companion Chip Security Control" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECUREEXECINDICATOR ,Secure Execution Indicator" "Reset,Set"
|
|
width 21.
|
|
group.long 0x310++0x07
|
|
line.long 0x00 "CONTROL_DEVCONF2,Static device configuration register 2"
|
|
bitfld.long 0x00 26. " VDD_HVMODEOUT ,IO Voltage detect cell (CQdetect) output" "1.8V,3.3V"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FUSE_SECIP_DISABLE_GRP2 ,Gate the clocks of Group2 Security IPs" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FUSE_SECIP_DISABLE_GRP1 ,Gate the clocks of Group1 Security Ips" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 23. " USBPHY_GPIO_MODE ,Selects the GPIO mode of USB PHY" "Normal,UART3 Tx/Rx|USBPHY"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FUNC_SYS32K_SEL ,Sys_boot7 value" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FUNC_MODE_SEL ,Sys_boot8 value" "DDR 32,DDR 16"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FUSE_AVDAC_DISABLE ,Goes high when AVDAC is disabled using efuse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " USBOTG_OTGMODE ,USB2.0 OTGMODE override" "Not overriden,USB Host,USB Device,USB Host with VBUS low"
|
|
textline " "
|
|
bitfld.long 0x00 13. " USBOTG_SESSENDEN ,Session end comparator turn on" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " USBOTG_VBUSDETECTEN ,All comparators turn on" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " USBOTG_SELINPUTCLKFREQ ,USB PHY PLL reference clock frequency" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,26 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " USBOTG_PWRCLKGOOD ,Clock is present from oscillator; all power sources are good and PLL is locked" "Not good,Good"
|
|
textline " "
|
|
bitfld.long 0x00 6. " USBOTG_VBUSSENSE ,Detects the presence of VBUS irrespective of the VDDA supplies" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " USBOTG_PHY_PLLON ,Turn on the USB PHY PLL" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 4. " USBOTG_PHY_RESET ,USB PHY Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USBOTG_PHY_PD ,USB PHY Power down" "Power up,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 2. " USBOTG_POWERDOWNOTG ,Power down the OTG module of USB PHY" "Power up,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " USBOTG_DATAPOLARITY ,Inverted polarity" "Inverted,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VPFE_PCLK_INVERT_EN ,Invert the pclk clock coming from IO buffer and going to VPFE module" "Not inverted,Inverted"
|
|
line.long 0x04 "CONTROL_DEVCONF3,Static device configuration register 3"
|
|
bitfld.long 0x04 15. " DDRPHY_CLK_EN ,DDR PHY clocks enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " EMIF4A_FCLKEN ,EMIF clocks enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " VTP_PWRSAVE ,Enable the power save mode of VTP controller" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DDR_CMOSEN ,Enable the CMOS receive buffer of DDR IO buffers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " VTP_DRVSTRENGTH ,Drive Strength Control for VTP controller (x*Ext Resistor)" "0.69,0.79,0.89,0.99,1.09,1.19,1.29,1.39"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DDR_VREF_EN ,Reference for VREF cell for DDR" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " DDR_VREF_TAP ,DDR VREF TAP" "50%,52.5%,47.5%,50%"
|
|
textline " "
|
|
bitfld.long 0x04 5. " VTP_READY ,Status from VTP controller" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " DDR_CONFIG_TERMOFF ,2-bit input signal configuration to disable termination" "No termination,Half termination,Full termination,Full termination"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " DDR_CONFIG_TERMON ,2-bit input signal configuration to enable termination" "No termination,Half termination,Full termination,Full termination"
|
|
width 24.
|
|
group.long 0x31c++0x0f
|
|
line.long 0x00 "CONTROL_CBA_PRIORITY,CBA Priority register for SCR"
|
|
bitfld.long 0x00 12.--14. " CBA_USBCDMA_PRIORITY ,VBUSP Priority of USB-CDMA master interface" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CBA_USBM_PRIORITY ,VBUSP Priority of USBM master interface" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CBA_EMAC_PRIORITY ,VBUSP Priority of CPMAC master interface" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CBA_VPFE_PRIORITY ,VBUSP Priority of VPFE master interface" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
line.long 0x04 "CONTROL_LVL_INTR_CLEAR,Interrupt clear register for VPFE, CPGMAC, and USBOTG"
|
|
bitfld.long 0x04 7. " VPFE_CCDC_VD2_INT_CLR ,VPFE_CCDC_VD2 Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VPFE_CCDC_VD1_INT_CLR ,VPFE_CCDC_VD1 Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " VPFE_CCDC_VD0_INT_CLR ,VPFE_CCDC_VD0 Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 4. " USB20OTGSS_USB_INT_CLR ,USB20OTGSS_USB Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CPGMAC_C0_TX_PULSE_CLR ,CPGMAC_C0_TX_PULSE Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CPGMAC_C0_RX_THRESH_PULSE_CLR ,CPGMAC_C0_RX_THRESH_PULSE Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CPGMAC_C0_RX_PULSE_CLR ,CPGMAC_C0_RX_PULSE Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CPGMAC_C0_MISC_PULSE_CLR ,CPGMAC_C0_MISC_PULSE Interrupt Clear" "Not cleared,Cleared"
|
|
line.long 0x08 "CONTROL_IP_SW_RESET,Software reset register for VPFE, HECC, CPGMAC, and USBOTG"
|
|
bitfld.long 0x08 4. " VPFE_PCLK_SW_RST ,SW reset for VPFE (PCLK domain)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HECC_SW_RST ,SW reset for HECC" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VPFE_VBUSP_SW_RST ,SW reset for VPFE (VBUSP domain)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CPGMACSS_SW_RST ,SW reset for CPGMAC" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 0. " USB20OTGSS_SW_RST ,SW reset for USB20OTGSS" "No reset,Reset"
|
|
line.long 0x0c "CONTROL_IPSS_CLK_CTRL,Clock control register for VPFE, USBOTG, CPGMAC, and HECC"
|
|
bitfld.long 0x0c 10. " VPFE_FUNC_CLK_EN ,Enable the Func clock of VPFE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CPGMAC_FUNC_CLK_EN ,Enable the Func clock of CPGMAC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " USB20OTG_FUNC_CLK_EN ,Enable the Func clock of USBOTG" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " HECC_VBUSP_CLK_EN_ACK ,Status of HECC VBUSP clock" "Gated,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " VPFE_VBUSP_CLK_EN_ACK ,Status of VPFE VBUSP clock" "Gated,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " CPGMAC_VBUSP_CLK_EN_ACK ,Status of CPGMAC VBUSP clock" "Gated,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " USB20OTG_VBUSP_CLK_EN_ACK ,Status of USB VBUSP clock" "Gated,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " HECC_VBUSP_CLK_EN ,Enable the VBUSP clock of HECC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " VPFE_VBUSP_CLK_EN ,Enable the VBUSP clock of VPFE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " CPGMAC_VBUSP_CLK_EN ,Enable the VBUSP clock of CPGMAC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " USB20OTG_VBUSP_CLK_EN ,Enable the VBUSP clock of USBOTG" "Disabled,Enabled"
|
|
base ad:0x4830a204
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_IDCODE,Device IDCODE"
|
|
hexmask.long.byte 0x00 28.--31. 1. " VERSION ,Revision number"
|
|
hexmask.long.word 0x00 12.--27. 1. " HAWKEYE ,Hawkeye number"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--11. 1. " TI_IDM ,Manufacturer identity (TI)"
|
|
width 0xb
|
|
tree.end
|
|
tree "MEM_WKUP"
|
|
base ad:0x48002600
|
|
width 26.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONTROL_SAVE_RESTORE_MEM,Memories mapped for save and restore location"
|
|
button "MEM" "d ad:0x48002600--(ad:0x48002600+0x3ff) /long"
|
|
width 0xb
|
|
tree.end
|
|
tree "PADCONFS_WKUP"
|
|
base ad:0x48002200
|
|
width 34.
|
|
group.long 0x800--0x817
|
|
line.long 0x0 "CONTROL_PADCONF_I2C4_SCL,Configuration Register For Pads i2c4_scl;i2c4_sda"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for i2c4_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c4_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c4_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c4_sda" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for i2c4_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c4_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c4_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for i2c4_scl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_SYS_32K,Configuration Register For Pads sys_32k;sys_clkreq"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for sys_clkreq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_clkreq" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_clkreq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_clkreq" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for sys_32k" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_SYS_NRESWARM,Configuration Register For Pads sys_nreswarm;sys_boot0"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for sys_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_nreswarm" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_nreswarm" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_SYS_BOOT1,Configuration Register For Pads sys_boot1;sys_boot2"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x10 "CONTROL_PADCONF_SYS_BOOT3,Configuration Register For Pads sys_boot3;sys_boot4"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x14 "CONTROL_PADCONF_SYS_BOOT5,Configuration Register For Pads sys_boot5;sys_boot6"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CONTROL_PADCONF_SYS_BOOT7,Configuration Register For Pad sys_boot7"
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for sys_boot7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CONTROL_PADCONF_SDRC_STRBEN_DLY1,Configuration Register For Pad sys_boot8"
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for sys_boot8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x818++0x0f
|
|
line.long 0x0 "CONTROL_PADCONF_SYS_CLKOUT1,Configuration Register For Pads ;sys_clkout1"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for sys_clkout1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_clkout1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_clkout1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_clkout1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
line.long 0x4 "CONTROL_PADCONF_JTAG_NTRST,Configuration Register For Pads jtag_ntrst;jtag_tck"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for jtag_tck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_tck" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_tck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for jtag_ntrst" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for jtag_ntrst" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for jtag_ntrst" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x8 "CONTROL_PADCONF_JTAG_TMS_TMSC,Configuration Register For Pads jtag_tms_tmsc;jtag_tdi"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for jtag_tdi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_tdi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_tdi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for jtag_tms_tmsc" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for jtag_tms_tmsc" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for jtag_tms_tmsc" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0xC "CONTROL_PADCONF_JTAG_EMU0,Configuration Register For Pads jtag_emu0;jtag_emu1"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_emu1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for jtag_emu1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for jtag_emu0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for jtag_emu0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x84c++0x03
|
|
line.long 0x00 "CONTROL_PADCONF_JTAG_RTCK,Configuration Register For Pad jtag_rtck"
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_rtck" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "CONTROL_PADCONF_JTAG_TDO,Configuration Register For Pad jtag_tdo"
|
|
width 0xb
|
|
tree.end
|
|
tree "GENERAL_WKUP"
|
|
base ad:0x48002A60
|
|
width 25.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CONTROL_SEC_TAP,Security TAP Controllers Register"
|
|
bitfld.long 0x00 31. " SECTAPWRDISABLE ,Security TAP controller register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SR2TAPENABLE ,Smart Reflex2 TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OCTTAPENABLE ,OCT TAP Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUBTAPCTRLDISABLE ,Restrict writable register list accessible through the Chip Level" "Unrestricted,Restricted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SDTITAPENABLE ,SDTI TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EFUSETAPENABLE ,E-Fuse TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHIPLEVELTAPENABLE ,Chip Level TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ETBTAPENABLE ,ETB TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CPEFUSETAPENABLE ,CP Efuse TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MPUTAPENABLE ,MPU/ICECrusher/ETM/PSA TAP control" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_SEC_EMU,Security Emulation Register"
|
|
bitfld.long 0x04 31. " SECEMUWRDISABLE ,Security EMULATION register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ICESECPRIVDBGENABLE ,ICE Secure Privilege debug control (MPU trace data)" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ETMSECPRIVDBGENABLE ,ETM Secure Privilege Control (MPU trace data)" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " GENDBGENABLE ,Generic Debug Control" "Disabled,Strict Public,Public,Secure"
|
|
line.long 0x8 "CONTROL_WKUP_DEBOBS_0,WKUP Domain Set Of Signals To Be Observed For hw_dbg[3-0]"
|
|
hexmask.long.byte 0x8 24.--28. 1. " OBSMUX3 ,Select the set of signals to be observed for hw_dbg3"
|
|
hexmask.long.byte 0x8 16.--20. 1. " OBSMUX2 ,Select the set of signals to be observed for hw_dbg2"
|
|
textline " "
|
|
hexmask.long.byte 0x8 8.--12. 1. " OBSMUX1 ,Select the set of signals to be observed for hw_dbg1"
|
|
hexmask.long.byte 0x8 0.--4. 1. " OBSMUX0 ,Select the set of signals to be observed for hw_dbg0"
|
|
line.long 0xC "CONTROL_WKUP_DEBOBS_1,WKUP Domain Set Of Signals To Be Observed For hw_dbg[7-4]"
|
|
hexmask.long.byte 0xC 24.--28. 1. " OBSMUX7 ,Select the set of signals to be observed for hw_dbg7"
|
|
hexmask.long.byte 0xC 16.--20. 1. " OBSMUX6 ,Select the set of signals to be observed for hw_dbg6"
|
|
textline " "
|
|
hexmask.long.byte 0xC 8.--12. 1. " OBSMUX5 ,Select the set of signals to be observed for hw_dbg5"
|
|
hexmask.long.byte 0xC 0.--4. 1. " OBSMUX4 ,Select the set of signals to be observed for hw_dbg4"
|
|
line.long 0x10 "CONTROL_WKUP_DEBOBS_2,WKUP Domain Set Of Signals To Be Observed For hw_dbg[11-8]"
|
|
hexmask.long.byte 0x10 24.--28. 1. " OBSMUX11 ,Select the set of signals to be observed for hw_dbg11"
|
|
hexmask.long.byte 0x10 16.--20. 1. " OBSMUX10 ,Select the set of signals to be observed for hw_dbg10"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--12. 1. " OBSMUX9 ,Select the set of signals to be observed for hw_dbg9"
|
|
hexmask.long.byte 0x10 0.--4. 1. " OBSMUX8 ,Select the set of signals to be observed for hw_dbg8"
|
|
line.long 0x14 "CONTROL_WKUP_DEBOBS_3,WKUP Domain Set Of Signals To Be Observed For hw_dbg[15-12]"
|
|
hexmask.long.byte 0x14 24.--28. 1. " OBSMUX15 ,Select the set of signals to be observed for hw_dbg15"
|
|
hexmask.long.byte 0x14 16.--20. 1. " OBSMUX14 ,Select the set of signals to be observed for hw_dbg14"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--12. 1. " OBSMUX13 ,Select the set of signals to be observed for hw_dbg13"
|
|
hexmask.long.byte 0x14 0.--4. 1. " OBSMUX12 ,Select the set of signals to be observed for hw_dbg12"
|
|
line.long 0x18 "CONTROL_WKUP_DEBOBS_4,WKUP Domain Set Of Signals To Be Observed For hw_dbg[17-16]"
|
|
bitfld.long 0x18 31. " WKUPOBSERVABILITYDISABLE ,Control the observability feature" "Enabled,Disabled"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--12. 1. " OBSMUX17 ,Select the set of signals to be observed for hw_dbg17"
|
|
hexmask.long.byte 0x18 0.--4. 1. " OBSMUX16 ,Select the set of signals to be observed for hw_dbg16"
|
|
line.long 0x1C "CONTROL_SEC_DAP,DAP Qualifiers Generated Using This Register"
|
|
bitfld.long 0x1C 31. " SECDAPWRDISABLE ,Security DAP Register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " FORCEDAPSECUSERDEBUGEN ,Force MreqSupervisor to 0 for secure DAP accesses" "Unchanged,Forced"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " FORCEDAPSECPUBLICDEBUGEN ,Force MreqSecure to 0 for secure DAP accesses" "Unchanged,Forced"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " FORCEDAPPUBUSERDEBUGEN ,Force MreqSupervisor to 0 for public DAP accesses" "Unchanged,Forced"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "SDMA (System Direct Memory Access)"
|
|
tree "Common Registers"
|
|
base ad:0x48056000
|
|
width 19.
|
|
group.long 0x08++0x27
|
|
line.long 0x0 "DMA4_IRQSTATUS_L0,Interrupt Status Over Line L0 Register"
|
|
eventfld.long 0x0 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0x4 "DMA4_IRQSTATUS_L1,Interrupt Status Over Line L1 Register"
|
|
eventfld.long 0x4 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0x8 "DMA4_IRQSTATUS_L2,Interrupt Status Over Line L2 Register"
|
|
eventfld.long 0x8 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0xC "DMA4_IRQSTATUS_L3,Interrupt Status Over Line L3 Register"
|
|
eventfld.long 0xC 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "DMA4_IRQENABLE_L0,Interrupt Over Line L0 Enable Register"
|
|
eventfld.long 0x10 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x10 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x10 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x10 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x10 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x10 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x10 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x10 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x10 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x10 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x10 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x10 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x10 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x10 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x10 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x10 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x10 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x14 "DMA4_IRQENABLE_L1,Interrupt Over Line L1 Enable Register"
|
|
eventfld.long 0x14 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x14 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x14 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x14 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x14 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x14 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x14 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x14 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x14 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x14 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x14 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x14 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x14 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x14 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x14 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x14 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x14 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x18 "DMA4_IRQENABLE_L2,Interrupt Over Line L2 Enable Register"
|
|
eventfld.long 0x18 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x18 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x18 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x18 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x18 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x18 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x18 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x18 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x18 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x18 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x18 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x18 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x18 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x18 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x18 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x18 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x18 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x1C "DMA4_IRQENABLE_L3,Interrupt Over Line L3 Enable Register"
|
|
eventfld.long 0x1C 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x1C 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x1C 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x1C 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x1C 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x1C 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x1C 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x1C 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x1C 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x1C 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x1C 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x1C 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x1C 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x1C 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x1C 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x1C 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x1C 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x20 "DMA4_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x20 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
line.long 0x24 "DMA4_OCP_SYSCONFIG,Various Parameters Of The OCP Interface Control Register"
|
|
bitfld.long 0x24 12.--13. " MIDLEMODE ,Read power management standby control" "Forced-standby,No-standby,Smart-standby,?..."
|
|
textline " "
|
|
bitfld.long 0x24 9. " CLOCKACTIVITY1 ,Clocks activities during wake-up (Functional clock)" "Switched-off,Switched-on"
|
|
textline " "
|
|
bitfld.long 0x24 8. " CLOCKACTIVITY2 ,Clocks activities during wake-up (OCP interface clock)" "Switched-off,Switched-on"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EMUFREE ,Enable sensitivity to MSuspend" "Frozen,Ignored"
|
|
textline " "
|
|
bitfld.long 0x24 3.--4. " SIDLEMODE ,Configuration port power management (idle control)" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x24 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x24 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Free running,Applied"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "DMA4_CAPS_0,DMA Capabilities Register 0 LSW"
|
|
bitfld.long 0x00 19. " CONST_FILL_CPBLTY ,Constant_Fill_Capability" "No LCH,Any LCH"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRANSPARENT_BLT_CPBLTY ,Transparent_BLT_Capability" "No LCH,Any LCH"
|
|
group.long 0x6C++0xF
|
|
line.long 0x00 "DMA4_CAPS_2,DMA Capabilities Register 2"
|
|
bitfld.long 0x00 8. " SEPARATE_SRC_AND_DST_INDEX_CPBLTY ,Separate source/destination index capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DST_DOUBLE_INDEX_ADRS_CPBLTY ,Destination double index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DST_SINGLE_INDEX_ADRS_CPBLTY ,Destination single index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DST_POST_INCRMNT_ADRS_CPBLTY ,Destination post increment address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DST_CONST_ADRS_CPBLTY ,Destination constant address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRC_DOUBLE_INDEX_ADRS_CPBLTY ,Source double index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRC_SINGLE_INDEX_ADRS_CPBLTY ,Source single index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRC_POST_INCREMENT_ADRS_CPBLTY ,Source post increment address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SRC_CONST_ADRS_CPBLTY ,Source constant address capability" "Not supported,Supported"
|
|
line.long 0x04 "DMA4_CAPS_3,DMA Capabilities Register 3"
|
|
bitfld.long 0x04 7. " BLOCK_SYNCHR_CPBLTY ,Block_synchronization_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PKT_SYNCHR_CPBLTY ,Packet_synchronization_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CHANNEL_CHAINING_CPBLTY ,Channel_chaining_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 4. " LCH_INTERLEAVE_CPBLTY ,LCh_interleave_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FRAME_SYNCHR_CPBLTY ,Frame_synchronization_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ELMNT_SYNCHR_CPBLTY ,Element_synchronization_capability" "Not supported,Supported"
|
|
line.long 0x08 "DMA4_CAPS_4,DMA Capabilities Register 4"
|
|
bitfld.long 0x08 7. " PKT_INTERRUPT_CPBLTY ,End of Packet detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SYNC_STATUS_CPBLTY ,Sync_status_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BLOCK_INTERRUPT_CPBLTY ,End of block detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 4. " LAST_FRAME_INTERRUPT_CPBLTY ,Start of last frame detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FRAME_INTERRUPT_CPBLTY ,End of frame detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HALF_FRAME_INTERRUPT_CPBLTY ,Detection capability of the half of frame end" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 1. " EVENT_DROP_INTERRUPT_CPBLTY ,Request collision detection capability" "Not supported,Supported"
|
|
line.long 0x0C "DMA4_GCR,FIFO Sharing Between High And Low Priority Channel"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ARBITRATION_RATE ,Arbitration switching rate between prioritized and regular channel queues"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " HI_LO_FIFO_BUDGET ,Separate gloabal FIFO budget for high and low priority channels" "No budget,75% low/25% high,25% low/75% high,50% low/50% high"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " HI_THREAD_RESERVED ,Thread reservation for high priority channel on r/w ports" "No reservation,Port0,Port0/Port1,Port0/Port1/Port2"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " MAX_CHANNEL_FIFO_DEPTH ,Maximum FIFO depth allocated to one logical channel"
|
|
width 0xb
|
|
tree.end
|
|
tree "Channels Registers"
|
|
width 19.
|
|
tree "Channel 0"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DMA4_CCR_0,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x80+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_0,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x80+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_0,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x80+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_0,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x80+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_0,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x80+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_0,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x80+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_0,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_0,Channel Source Start Address"
|
|
group.long (0x80+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_0,Channel Destination Start Address"
|
|
group.long (0x80+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_0,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x80+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_0,Channel Source Frame Index"
|
|
group.long (0x80+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_0,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x80+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_0,Channel Destination Frame Index"
|
|
group.long (0x80+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_0,Channel Source Address Value"
|
|
group.long (0x80+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_0,Channel Destination Address Value"
|
|
group.long (0x80+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_0,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x80+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_0,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x80+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_0,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA4_CCR_1,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xE0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_1,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xE0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_1,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xE0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_1,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xE0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_1,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xE0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_1,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xE0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_1,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xE0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_1,Channel Source Start Address"
|
|
group.long (0xE0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_1,Channel Destination Start Address"
|
|
group.long (0xE0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_1,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xE0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_1,Channel Source Frame Index"
|
|
group.long (0xE0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_1,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xE0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_1,Channel Destination Frame Index"
|
|
group.long (0xE0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_1,Channel Source Address Value"
|
|
group.long (0xE0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_1,Channel Destination Address Value"
|
|
group.long (0xE0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_1,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xE0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_1,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xE0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_1,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "DMA4_CCR_2,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x140+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_2,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x140+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_2,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x140+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_2,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x140+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_2,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x140+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_2,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x140+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_2,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x140+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_2,Channel Source Start Address"
|
|
group.long (0x140+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_2,Channel Destination Start Address"
|
|
group.long (0x140+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_2,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x140+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_2,Channel Source Frame Index"
|
|
group.long (0x140+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_2,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x140+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_2,Channel Destination Frame Index"
|
|
group.long (0x140+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_2,Channel Source Address Value"
|
|
group.long (0x140+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_2,Channel Destination Address Value"
|
|
group.long (0x140+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_2,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x140+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_2,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x140+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_2,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "DMA4_CCR_3,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1A0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_3,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1A0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_3,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x1A0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_3,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x1A0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_3,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x1A0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_3,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x1A0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_3,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x1A0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_3,Channel Source Start Address"
|
|
group.long (0x1A0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_3,Channel Destination Start Address"
|
|
group.long (0x1A0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_3,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x1A0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_3,Channel Source Frame Index"
|
|
group.long (0x1A0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_3,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x1A0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_3,Channel Destination Frame Index"
|
|
group.long (0x1A0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_3,Channel Source Address Value"
|
|
group.long (0x1A0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_3,Channel Destination Address Value"
|
|
group.long (0x1A0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_3,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x1A0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_3,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x1A0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_3,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "DMA4_CCR_4,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x200+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_4,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x200+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_4,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x200+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_4,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x200+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_4,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x200+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_4,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x200+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_4,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x200+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_4,Channel Source Start Address"
|
|
group.long (0x200+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_4,Channel Destination Start Address"
|
|
group.long (0x200+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_4,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x200+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_4,Channel Source Frame Index"
|
|
group.long (0x200+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_4,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x200+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_4,Channel Destination Frame Index"
|
|
group.long (0x200+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_4,Channel Source Address Value"
|
|
group.long (0x200+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_4,Channel Destination Address Value"
|
|
group.long (0x200+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_4,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x200+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_4,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x200+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_4,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "DMA4_CCR_5,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x260+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_5,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x260+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_5,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x260+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_5,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x260+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_5,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x260+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_5,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x260+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_5,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x260+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_5,Channel Source Start Address"
|
|
group.long (0x260+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_5,Channel Destination Start Address"
|
|
group.long (0x260+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_5,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x260+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_5,Channel Source Frame Index"
|
|
group.long (0x260+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_5,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x260+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_5,Channel Destination Frame Index"
|
|
group.long (0x260+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_5,Channel Source Address Value"
|
|
group.long (0x260+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_5,Channel Destination Address Value"
|
|
group.long (0x260+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_5,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x260+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_5,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x260+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_5,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x00 "DMA4_CCR_6,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x2C0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_6,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x2C0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_6,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x2C0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_6,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x2C0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_6,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x2C0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_6,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x2C0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_6,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x2C0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_6,Channel Source Start Address"
|
|
group.long (0x2C0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_6,Channel Destination Start Address"
|
|
group.long (0x2C0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_6,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x2C0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_6,Channel Source Frame Index"
|
|
group.long (0x2C0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_6,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x2C0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_6,Channel Destination Frame Index"
|
|
group.long (0x2C0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_6,Channel Source Address Value"
|
|
group.long (0x2C0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_6,Channel Destination Address Value"
|
|
group.long (0x2C0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_6,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x2C0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_6,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x2C0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_6,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x320++0x3
|
|
line.long 0x00 "DMA4_CCR_7,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x320+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_7,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x320+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_7,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x320+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_7,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x320+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_7,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x320+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_7,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x320+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_7,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x320+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_7,Channel Source Start Address"
|
|
group.long (0x320+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_7,Channel Destination Start Address"
|
|
group.long (0x320+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_7,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x320+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_7,Channel Source Frame Index"
|
|
group.long (0x320+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_7,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x320+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_7,Channel Destination Frame Index"
|
|
group.long (0x320+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_7,Channel Source Address Value"
|
|
group.long (0x320+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_7,Channel Destination Address Value"
|
|
group.long (0x320+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_7,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x320+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_7,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x320+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_7,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "DMA4_CCR_8,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x380+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_8,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x380+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_8,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x380+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_8,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x380+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_8,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x380+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_8,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x380+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_8,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x380+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_8,Channel Source Start Address"
|
|
group.long (0x380+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_8,Channel Destination Start Address"
|
|
group.long (0x380+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_8,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x380+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_8,Channel Source Frame Index"
|
|
group.long (0x380+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_8,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x380+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_8,Channel Destination Frame Index"
|
|
group.long (0x380+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_8,Channel Source Address Value"
|
|
group.long (0x380+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_8,Channel Destination Address Value"
|
|
group.long (0x380+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_8,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x380+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_8,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x380+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_8,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x00 "DMA4_CCR_9,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x3E0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_9,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x3E0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_9,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x3E0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_9,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x3E0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_9,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x3E0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_9,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x3E0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_9,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x3E0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_9,Channel Source Start Address"
|
|
group.long (0x3E0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_9,Channel Destination Start Address"
|
|
group.long (0x3E0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_9,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x3E0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_9,Channel Source Frame Index"
|
|
group.long (0x3E0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_9,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x3E0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_9,Channel Destination Frame Index"
|
|
group.long (0x3E0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_9,Channel Source Address Value"
|
|
group.long (0x3E0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_9,Channel Destination Address Value"
|
|
group.long (0x3E0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_9,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x3E0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_9,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x3E0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_9,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 10"
|
|
group.long 0x440++0x3
|
|
line.long 0x00 "DMA4_CCR_10,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x440+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_10,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x440+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_10,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x440+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_10,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x440+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_10,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x440+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_10,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x440+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_10,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x440+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_10,Channel Source Start Address"
|
|
group.long (0x440+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_10,Channel Destination Start Address"
|
|
group.long (0x440+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_10,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x440+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_10,Channel Source Frame Index"
|
|
group.long (0x440+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_10,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x440+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_10,Channel Destination Frame Index"
|
|
group.long (0x440+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_10,Channel Source Address Value"
|
|
group.long (0x440+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_10,Channel Destination Address Value"
|
|
group.long (0x440+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_10,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x440+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_10,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x440+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_10,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 11"
|
|
group.long 0x4A0++0x3
|
|
line.long 0x00 "DMA4_CCR_11,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x4A0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_11,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x4A0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_11,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x4A0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_11,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x4A0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_11,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x4A0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_11,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x4A0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_11,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x4A0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_11,Channel Source Start Address"
|
|
group.long (0x4A0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_11,Channel Destination Start Address"
|
|
group.long (0x4A0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_11,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x4A0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_11,Channel Source Frame Index"
|
|
group.long (0x4A0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_11,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x4A0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_11,Channel Destination Frame Index"
|
|
group.long (0x4A0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_11,Channel Source Address Value"
|
|
group.long (0x4A0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_11,Channel Destination Address Value"
|
|
group.long (0x4A0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_11,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x4A0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_11,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x4A0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_11,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 12"
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "DMA4_CCR_12,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x500+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_12,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x500+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_12,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x500+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_12,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x500+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_12,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x500+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_12,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x500+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_12,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x500+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_12,Channel Source Start Address"
|
|
group.long (0x500+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_12,Channel Destination Start Address"
|
|
group.long (0x500+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_12,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x500+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_12,Channel Source Frame Index"
|
|
group.long (0x500+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_12,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x500+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_12,Channel Destination Frame Index"
|
|
group.long (0x500+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_12,Channel Source Address Value"
|
|
group.long (0x500+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_12,Channel Destination Address Value"
|
|
group.long (0x500+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_12,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x500+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_12,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x500+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_12,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 13"
|
|
group.long 0x560++0x3
|
|
line.long 0x00 "DMA4_CCR_13,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x560+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_13,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x560+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_13,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x560+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_13,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x560+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_13,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x560+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_13,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x560+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_13,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x560+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_13,Channel Source Start Address"
|
|
group.long (0x560+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_13,Channel Destination Start Address"
|
|
group.long (0x560+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_13,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x560+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_13,Channel Source Frame Index"
|
|
group.long (0x560+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_13,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x560+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_13,Channel Destination Frame Index"
|
|
group.long (0x560+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_13,Channel Source Address Value"
|
|
group.long (0x560+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_13,Channel Destination Address Value"
|
|
group.long (0x560+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_13,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x560+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_13,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x560+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_13,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 14"
|
|
group.long 0x5C0++0x3
|
|
line.long 0x00 "DMA4_CCR_14,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x5C0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_14,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x5C0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_14,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x5C0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_14,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x5C0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_14,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x5C0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_14,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x5C0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_14,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x5C0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_14,Channel Source Start Address"
|
|
group.long (0x5C0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_14,Channel Destination Start Address"
|
|
group.long (0x5C0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_14,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x5C0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_14,Channel Source Frame Index"
|
|
group.long (0x5C0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_14,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x5C0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_14,Channel Destination Frame Index"
|
|
group.long (0x5C0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_14,Channel Source Address Value"
|
|
group.long (0x5C0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_14,Channel Destination Address Value"
|
|
group.long (0x5C0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_14,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x5C0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_14,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x5C0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_14,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 15"
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "DMA4_CCR_15,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x620+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_15,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x620+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_15,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x620+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_15,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x620+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_15,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x620+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_15,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x620+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_15,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x620+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_15,Channel Source Start Address"
|
|
group.long (0x620+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_15,Channel Destination Start Address"
|
|
group.long (0x620+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_15,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x620+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_15,Channel Source Frame Index"
|
|
group.long (0x620+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_15,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x620+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_15,Channel Destination Frame Index"
|
|
group.long (0x620+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_15,Channel Source Address Value"
|
|
group.long (0x620+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_15,Channel Destination Address Value"
|
|
group.long (0x620+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_15,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x620+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_15,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x620+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_15,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 16"
|
|
group.long 0x680++0x3
|
|
line.long 0x00 "DMA4_CCR_16,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x680+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_16,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x680+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_16,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x680+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_16,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x680+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_16,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x680+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_16,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x680+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_16,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x680+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_16,Channel Source Start Address"
|
|
group.long (0x680+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_16,Channel Destination Start Address"
|
|
group.long (0x680+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_16,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x680+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_16,Channel Source Frame Index"
|
|
group.long (0x680+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_16,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x680+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_16,Channel Destination Frame Index"
|
|
group.long (0x680+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_16,Channel Source Address Value"
|
|
group.long (0x680+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_16,Channel Destination Address Value"
|
|
group.long (0x680+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_16,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x680+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_16,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x680+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_16,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 17"
|
|
group.long 0x6E0++0x3
|
|
line.long 0x00 "DMA4_CCR_17,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x6E0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_17,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x6E0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_17,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x6E0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_17,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x6E0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_17,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x6E0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_17,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x6E0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_17,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x6E0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_17,Channel Source Start Address"
|
|
group.long (0x6E0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_17,Channel Destination Start Address"
|
|
group.long (0x6E0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_17,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x6E0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_17,Channel Source Frame Index"
|
|
group.long (0x6E0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_17,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x6E0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_17,Channel Destination Frame Index"
|
|
group.long (0x6E0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_17,Channel Source Address Value"
|
|
group.long (0x6E0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_17,Channel Destination Address Value"
|
|
group.long (0x6E0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_17,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x6E0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_17,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x6E0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_17,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 18"
|
|
group.long 0x740++0x3
|
|
line.long 0x00 "DMA4_CCR_18,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x740+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_18,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x740+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_18,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x740+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_18,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x740+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_18,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x740+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_18,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x740+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_18,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x740+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_18,Channel Source Start Address"
|
|
group.long (0x740+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_18,Channel Destination Start Address"
|
|
group.long (0x740+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_18,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x740+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_18,Channel Source Frame Index"
|
|
group.long (0x740+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_18,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x740+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_18,Channel Destination Frame Index"
|
|
group.long (0x740+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_18,Channel Source Address Value"
|
|
group.long (0x740+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_18,Channel Destination Address Value"
|
|
group.long (0x740+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_18,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x740+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_18,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x740+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_18,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 19"
|
|
group.long 0x7A0++0x3
|
|
line.long 0x00 "DMA4_CCR_19,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x7A0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_19,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x7A0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_19,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x7A0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_19,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x7A0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_19,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x7A0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_19,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x7A0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_19,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x7A0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_19,Channel Source Start Address"
|
|
group.long (0x7A0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_19,Channel Destination Start Address"
|
|
group.long (0x7A0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_19,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x7A0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_19,Channel Source Frame Index"
|
|
group.long (0x7A0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_19,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x7A0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_19,Channel Destination Frame Index"
|
|
group.long (0x7A0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_19,Channel Source Address Value"
|
|
group.long (0x7A0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_19,Channel Destination Address Value"
|
|
group.long (0x7A0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_19,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x7A0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_19,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x7A0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_19,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 20"
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "DMA4_CCR_20,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x800+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_20,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x800+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_20,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x800+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_20,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x800+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_20,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x800+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_20,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x800+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_20,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x800+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_20,Channel Source Start Address"
|
|
group.long (0x800+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_20,Channel Destination Start Address"
|
|
group.long (0x800+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_20,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x800+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_20,Channel Source Frame Index"
|
|
group.long (0x800+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_20,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x800+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_20,Channel Destination Frame Index"
|
|
group.long (0x800+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_20,Channel Source Address Value"
|
|
group.long (0x800+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_20,Channel Destination Address Value"
|
|
group.long (0x800+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_20,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x800+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_20,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x800+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_20,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 21"
|
|
group.long 0x860++0x3
|
|
line.long 0x00 "DMA4_CCR_21,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x860+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_21,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x860+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_21,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x860+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_21,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x860+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_21,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x860+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_21,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x860+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_21,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x860+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_21,Channel Source Start Address"
|
|
group.long (0x860+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_21,Channel Destination Start Address"
|
|
group.long (0x860+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_21,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x860+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_21,Channel Source Frame Index"
|
|
group.long (0x860+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_21,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x860+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_21,Channel Destination Frame Index"
|
|
group.long (0x860+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_21,Channel Source Address Value"
|
|
group.long (0x860+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_21,Channel Destination Address Value"
|
|
group.long (0x860+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_21,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x860+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_21,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x860+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_21,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 22"
|
|
group.long 0x8C0++0x3
|
|
line.long 0x00 "DMA4_CCR_22,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x8C0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_22,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x8C0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_22,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x8C0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_22,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x8C0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_22,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x8C0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_22,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x8C0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_22,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x8C0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_22,Channel Source Start Address"
|
|
group.long (0x8C0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_22,Channel Destination Start Address"
|
|
group.long (0x8C0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_22,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x8C0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_22,Channel Source Frame Index"
|
|
group.long (0x8C0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_22,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x8C0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_22,Channel Destination Frame Index"
|
|
group.long (0x8C0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_22,Channel Source Address Value"
|
|
group.long (0x8C0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_22,Channel Destination Address Value"
|
|
group.long (0x8C0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_22,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x8C0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_22,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x8C0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_22,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 23"
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "DMA4_CCR_23,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x920+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_23,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x920+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_23,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x920+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_23,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x920+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_23,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x920+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_23,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x920+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_23,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x920+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_23,Channel Source Start Address"
|
|
group.long (0x920+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_23,Channel Destination Start Address"
|
|
group.long (0x920+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_23,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x920+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_23,Channel Source Frame Index"
|
|
group.long (0x920+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_23,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x920+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_23,Channel Destination Frame Index"
|
|
group.long (0x920+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_23,Channel Source Address Value"
|
|
group.long (0x920+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_23,Channel Destination Address Value"
|
|
group.long (0x920+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_23,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x920+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_23,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x920+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_23,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 24"
|
|
group.long 0x980++0x3
|
|
line.long 0x00 "DMA4_CCR_24,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x980+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_24,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x980+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_24,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x980+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_24,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x980+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_24,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x980+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_24,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x980+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_24,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x980+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_24,Channel Source Start Address"
|
|
group.long (0x980+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_24,Channel Destination Start Address"
|
|
group.long (0x980+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_24,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x980+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_24,Channel Source Frame Index"
|
|
group.long (0x980+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_24,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x980+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_24,Channel Destination Frame Index"
|
|
group.long (0x980+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_24,Channel Source Address Value"
|
|
group.long (0x980+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_24,Channel Destination Address Value"
|
|
group.long (0x980+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_24,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x980+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_24,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x980+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_24,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 25"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x00 "DMA4_CCR_25,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x9E0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_25,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x9E0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_25,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x9E0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_25,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x9E0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_25,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x9E0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_25,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x9E0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_25,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x9E0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_25,Channel Source Start Address"
|
|
group.long (0x9E0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_25,Channel Destination Start Address"
|
|
group.long (0x9E0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_25,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x9E0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_25,Channel Source Frame Index"
|
|
group.long (0x9E0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_25,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x9E0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_25,Channel Destination Frame Index"
|
|
group.long (0x9E0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_25,Channel Source Address Value"
|
|
group.long (0x9E0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_25,Channel Destination Address Value"
|
|
group.long (0x9E0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_25,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x9E0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_25,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x9E0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_25,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 26"
|
|
group.long 0xA40++0x3
|
|
line.long 0x00 "DMA4_CCR_26,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xA40+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_26,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xA40+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_26,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xA40+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_26,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xA40+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_26,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xA40+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_26,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xA40+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_26,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xA40+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_26,Channel Source Start Address"
|
|
group.long (0xA40+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_26,Channel Destination Start Address"
|
|
group.long (0xA40+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_26,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xA40+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_26,Channel Source Frame Index"
|
|
group.long (0xA40+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_26,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xA40+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_26,Channel Destination Frame Index"
|
|
group.long (0xA40+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_26,Channel Source Address Value"
|
|
group.long (0xA40+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_26,Channel Destination Address Value"
|
|
group.long (0xA40+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_26,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xA40+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_26,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xA40+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_26,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 27"
|
|
group.long 0xAA0++0x3
|
|
line.long 0x00 "DMA4_CCR_27,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xAA0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_27,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xAA0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_27,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xAA0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_27,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xAA0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_27,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xAA0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_27,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xAA0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_27,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xAA0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_27,Channel Source Start Address"
|
|
group.long (0xAA0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_27,Channel Destination Start Address"
|
|
group.long (0xAA0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_27,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xAA0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_27,Channel Source Frame Index"
|
|
group.long (0xAA0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_27,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xAA0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_27,Channel Destination Frame Index"
|
|
group.long (0xAA0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_27,Channel Source Address Value"
|
|
group.long (0xAA0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_27,Channel Destination Address Value"
|
|
group.long (0xAA0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_27,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xAA0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_27,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xAA0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_27,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 28"
|
|
group.long 0xB00++0x3
|
|
line.long 0x00 "DMA4_CCR_28,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB00+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_28,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB00+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_28,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xB00+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_28,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xB00+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_28,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xB00+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_28,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xB00+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_28,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xB00+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_28,Channel Source Start Address"
|
|
group.long (0xB00+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_28,Channel Destination Start Address"
|
|
group.long (0xB00+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_28,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xB00+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_28,Channel Source Frame Index"
|
|
group.long (0xB00+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_28,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xB00+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_28,Channel Destination Frame Index"
|
|
group.long (0xB00+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_28,Channel Source Address Value"
|
|
group.long (0xB00+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_28,Channel Destination Address Value"
|
|
group.long (0xB00+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_28,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xB00+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_28,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xB00+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_28,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 29"
|
|
group.long 0xB60++0x3
|
|
line.long 0x00 "DMA4_CCR_29,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB60+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_29,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB60+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_29,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xB60+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_29,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xB60+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_29,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xB60+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_29,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xB60+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_29,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xB60+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_29,Channel Source Start Address"
|
|
group.long (0xB60+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_29,Channel Destination Start Address"
|
|
group.long (0xB60+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_29,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xB60+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_29,Channel Source Frame Index"
|
|
group.long (0xB60+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_29,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xB60+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_29,Channel Destination Frame Index"
|
|
group.long (0xB60+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_29,Channel Source Address Value"
|
|
group.long (0xB60+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_29,Channel Destination Address Value"
|
|
group.long (0xB60+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_29,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xB60+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_29,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xB60+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_29,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 30"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x00 "DMA4_CCR_30,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xBC0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_30,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xBC0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_30,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xBC0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_30,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xBC0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_30,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xBC0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_30,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xBC0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_30,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xBC0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_30,Channel Source Start Address"
|
|
group.long (0xBC0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_30,Channel Destination Start Address"
|
|
group.long (0xBC0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_30,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xBC0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_30,Channel Source Frame Index"
|
|
group.long (0xBC0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_30,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xBC0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_30,Channel Destination Frame Index"
|
|
group.long (0xBC0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_30,Channel Source Address Value"
|
|
group.long (0xBC0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_30,Channel Destination Address Value"
|
|
group.long (0xBC0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_30,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xBC0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_30,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xBC0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_30,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 31"
|
|
group.long 0xC20++0x3
|
|
line.long 0x00 "DMA4_CCR_31,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC20+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_31,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC20+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_31,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xC20+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_31,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xC20+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_31,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xC20+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_31,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xC20+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_31,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xC20+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_31,Channel Source Start Address"
|
|
group.long (0xC20+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_31,Channel Destination Start Address"
|
|
group.long (0xC20+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_31,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xC20+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_31,Channel Source Frame Index"
|
|
group.long (0xC20+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_31,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xC20+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_31,Channel Destination Frame Index"
|
|
group.long (0xC20+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_31,Channel Source Address Value"
|
|
group.long (0xC20+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_31,Channel Destination Address Value"
|
|
group.long (0xC20+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_31,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xC20+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_31,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xC20+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_31,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "INTC (Interrupt Controller Registers)"
|
|
tree "MPU subsystem INTC"
|
|
base ad:0x48200000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "INTCPS_SYSCONFIG,Various Parameters Of The Module Interface Control"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "INTCPS_SYSSTATUS,Module Status Information"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x00 "INTCPS_SIR_IRQ,Currently Active IRQ Interrupt Number"
|
|
hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ACTIVEIRQ ,Active IRQ number"
|
|
line.long 0x04 "INTCPS_SIR_FIQ,Currently Active FIQ Interrupt Number"
|
|
hexmask.long 0x04 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious FIQ flag"
|
|
hexmask.long.byte 0x04 0.--6. 1. " ACTIVEIRQ ,Active FIQ number"
|
|
group.long 0x48++0xb
|
|
line.long 0x00 "INTCPS_CONTROL,New Interrupt Agreement Bits"
|
|
bitfld.long 0x00 1. " NEWFIQAGR ,Reset FIQ output and enable new FIQ generation" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " NEWIRQAGR ,New IRQ generation" "No effect,Enabled"
|
|
line.long 0x04 "INTCPS_PROTECTION,Protection Of The Other Registers Control"
|
|
bitfld.long 0x04 0. " PROTECTION ,Protection mode" "Disabled,Enabled"
|
|
line.long 0x08 "INTCPS_IDLE,Functional Clock Auto-idle And The Synchronizer Clock Auto-gating Control"
|
|
bitfld.long 0x08 1. " TURBO ,Input synchronizer clock auto-gating" "Free-running,Auto-gated"
|
|
bitfld.long 0x08 0. " FUNCIDLE ,Functional clock idle mode" "Applied,Free-running"
|
|
rgroup.long 0x60++0xb
|
|
line.long 0x00 "INTCPS_IRQ_PRIORITY,Currently Active IRQ Priority Level"
|
|
hexmask.long 0x00 6.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag"
|
|
hexmask.long.byte 0x00 0.--5. 1. " IRQPRIORITY ,Current IRQ priority"
|
|
line.long 0x04 "INTCPS_FIQ_PRIORITY,Currently Active FIQ Priority Level"
|
|
hexmask.long 0x04 6.--31. 1. " SPURIOUSFIQFLAG ,Spurious FIQ flag"
|
|
hexmask.long.byte 0x04 0.--5. 1. " FIQPRIORITY ,Current FIQ priority"
|
|
line.long 0x08 "INTCPS_THRESHOLD,Priority Threshold Set"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRIORITYTHRESHOLD ,Priority threshold"
|
|
width 21.
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "INTCPS_ITR0,Raw Interrupt Input Status Before Masking"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x14 31. " M_IRQ_31_set/clr ,GPIO module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x14 30. " M_IRQ_30_set/clr ,GPIO module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x14 29. " M_IRQ_29_set/clr ,GPIO module 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x14 28. " M_IRQ_28_set/clr ,High End CAN controller line 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x14 27. " M_IRQ_27_set/clr ,McBSP module 5 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x14 25. " M_IRQ_25_set/clr ,Display subsystem module interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x10 24. 0x14 24. " M_IRQ_24_set/clr ,High End CAN controller line 0 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x14 23. " M_IRQ_23_set/clr ,McBSP module 4 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x10 22. 0x14 22. " M_IRQ_22_set/clr ,McBSP module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x14 21. " M_IRQ_21_set/clr ,SGX graphics module interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x10 20. 0x14 20. " M_IRQ_20_set/clr ,General-purpose memory controller module interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x14 18. " M_IRQ_18_set/clr ,SmartReflex 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x14 17. " M_IRQ_17_set/clr ,McBSP module 2 IRQ interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x14 16. " M_IRQ_16_set/clr ,McBSP module 1 IRQ interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x14 15. " M_IRQ_15_set/clr ,System DMA request 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x14 14. " M_IRQ_14_set/clr ,System DMA request 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x14 13. " M_IRQ_13_set/clr ,System DMA request 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x14 12. " M_IRQ_12_set/clr ,System DMA request 0 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x14 11. " M_IRQ_11_set/clr ,PRCM module IRQ interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x14 10. " M_IRQ_10_set/clr ,SMX error for application interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x14 9. " M_IRQ_9_set/clr ,SMX error for debug interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x14 7. " M_IRQ_7_set/clr ,External source interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x14 5. " M_IRQ_5_set/clr ,Sidetone MCBSP3 overflow interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x14 4. " M_IRQ_4_set/clr ,Sidetone MCBSP2 overflow interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x14 3. " M_IRQ_3_set/clr ,BENCH MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x14 2. " M_IRQ_2_set/clr ,COMMRX MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x14 1. " M_IRQ_1_set/clr ,COMMTX MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x14 0. " M_IRQ_0_set/clr ,EMUINT MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "INTCPS_ITR1,Raw Interrupt Input Status Before Masking"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x14 31. " M_IRQ_63_set/clr ,McBSP module 2 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x14 30. " M_IRQ_62_set/clr ,McBSP module 2 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x14 29. " M_IRQ_61_set/clr ,I2C module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x14 28. " M_IRQ_60_set/clr ,McBSP module 1 receive interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x14 27. " M_IRQ_59_set/clr ,McBSP module 1 transmit interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x14 26. " M_IRQ_58_set/clr ,HDQ/One-wire interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x14 25. " M_IRQ_57_set/clr ,I2C module 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x14 24. " M_IRQ_56_set/clr ,I2C module 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x14 23. " M_IRQ_55_set/clr ,McBSP module 4 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x14 22. " M_IRQ_54_set/clr ,McBSP module 4 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x14 21. " M_IRQ_53_set/clr ,EMIF4ERR interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x14 20. " M_IRQ_52_set/clr ,RNG module interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x14 19. " M_IRQ_51_set/clr ,SHA-2/MD5 crypto-accelerator 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x14 18. " M_IRQ_50_set/clr ,PKA crypto-accelerator interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x14 17. " M_IRQ_49_set/clr ,SHA-1/MD5 crypto-accelerator 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x14 16. " M_IRQ_48_set/clr ,McSPI module 4 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x14 15. " M_IRQ_47_set/clr ,General-purpose timer module 11 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x14 14. " M_IRQ_46_set/clr ,General-purpose timer module 10 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x14 13. " M_IRQ_45_set/clr ,General-purpose timer module 9 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x14 12. " M_IRQ_44_set/clr ,General-purpose timer module 8 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x14 11. " M_IRQ_43_set/clr ,General-purpose timer module 7 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x14 10. " M_IRQ_42_set/clr ,General-purpose timer module 6 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x14 9. " M_IRQ_41_set/clr ,General-purpose timer module 5 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x14 8. " M_IRQ_40_set/clr ,General-purpose timer module 4 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x14 7. " M_IRQ_39_set/clr ,General-purpose timer module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x14 6. " M_IRQ_38_set/clr ,General-purpose timer module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x14 5. " M_IRQ_37_set/clr ,General-purpose timer module 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x14 4. " M_IRQ_36_set/clr ,Watchdog timer module 3 overflow interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x10 2. 0x14 2. " M_IRQ_34set/clr ,GPIO module 6 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x14 1. " M_IRQ_33set/clr ,GPIO module 5 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x10 0. 0x14 0. " M_IRQ_32_set/clr ,GPIO module 4 interrupt status" "Interrupt,No interrupt"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "INTCPS_ITR2,Raw Interrupt Input Status Before Masking"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x14 31. " M_IRQ_95_set/clr ,General-purpose timer module 12 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x14 30. " M_IRQ_94_set/clr ,MMC/SD module 3" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x14 29. " M_IRQ_93_set/clr ,CCDC_VD2_INT VPFE interrupt 2 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x14 28. " M_IRQ_92_set/clr ,CCDC_VD1_INT VPFE interrupt 1 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x14 27. " M_IRQ_91_set/clr ,McSPI module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x14 26. " M_IRQ_90_set/clr ,McBSP module 3 receive interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x14 25. " M_IRQ_89_set/clr ,McBSP module 3 transmit interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x14 24. " M_IRQ_88_set/clr ,CCDC_VD0_INT VPFE interrupt 0 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x14 23. " M_IRQ_87_set/clr ,MPU ICR interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x14 22. " M_IRQ_86_set/clr ,MMC/SD module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x10 20. 0x14 20. " M_IRQ_84_set/clr ,UART4 module interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x14 19. " M_IRQ_83_set/clr ,MMC/SD module 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x10 18. 0x14 18. " M_IRQ_82_set/clr ,McBSP module 5 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 17. 0x10 17. 0x14 17. " M_IRQ_81_set/clr ,McBSP module 5 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x14 15. " M_IRQ_79_set/clr ,SHA2/MD5 crypto-accelerator 1" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x14 14. " M_IRQ_78_set/clr ,HSUSB MP TLL Interrupt" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x14 13. " M_IRQ_77_set/clr ,EHCI controller HSUSB MP Host Interrupt" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x14 12. " M_IRQ_76_set/clr ,OHCI controller HSUSB MP Host Interrupt" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x14 11. " M_IRQ_75_set/clr ,Merged interrupt for PBIASlite1 and 2" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x14 10. " M_IRQ_74_set/clr ,UART module 3 (also infrared) interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x14 9. " M_IRQ_73_set/clr ,UART module 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x14 8. " M_IRQ_72_set/clr ,UART module 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x14 7. " M_IRQ_71_set/clr ,USBOTG interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x14 6. " M_IRQ_70_set/clr ,C0_MISC_PULSE EMAC Interrupt 3 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x14 5. " M_IRQ_69_set/clr ,C0_TX_PULSE EMAC Interrupt 2 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x14 4. " M_IRQ_68_set/clr ,C0_RX_PULSE EMAC Interrupt 1 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x14 3. " M_IRQ_67_set/clr ,C0_RX_THRESH_PULSE EMAC Interrupt 0 status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x14 2. " M_IRQ_66_set/clr ,McSPI module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x14 1. " M_IRQ_65_set/clr ,McSPI module 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x14 0. " M_IRQ_64_set/clr ,PKA crypto-accelerator interrupt status" "Interrupt,No interrupt"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "INTCPS_MIR0,Interrupt Mask"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " M_IRQ_31_set/clr ,GPIO module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " M_IRQ_30_set/clr ,GPIO module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " M_IRQ_29_set/clr ,GPIO module 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " M_IRQ_28_set/clr ,High End CAN controller line 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " M_IRQ_27_set/clr ,McBSP module 5 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " M_IRQ_25_set/clr ,Display subsystem module interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " M_IRQ_24_set/clr ,High End CAN controller line 0 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " M_IRQ_23_set/clr ,McBSP module 4 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " M_IRQ_22_set/clr ,McBSP module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " M_IRQ_21_set/clr ,SGX graphics module interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " M_IRQ_20_set/clr ,General-purpose memory controller module interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " M_IRQ_18_set/clr ,SmartReflex 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " M_IRQ_17_set/clr ,McBSP module 2 IRQ interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " M_IRQ_16_set/clr ,McBSP module 1 IRQ interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " M_IRQ_15_set/clr ,System DMA request 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " M_IRQ_14_set/clr ,System DMA request 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " M_IRQ_13_set/clr ,System DMA request 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " M_IRQ_12_set/clr ,System DMA request 0 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " M_IRQ_11_set/clr ,PRCM module IRQ interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " M_IRQ_10_set/clr ,SMX error for application interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " M_IRQ_9_set/clr ,SMX error for debug interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " M_IRQ_7_set/clr ,External source interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " M_IRQ_5_set/clr ,Sidetone MCBSP3 overflow interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " M_IRQ_4_set/clr ,Sidetone MCBSP2 overflow interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " M_IRQ_3_set/clr ,BENCH MPU emulation interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " M_IRQ_2_set/clr ,COMMRX MPU emulation interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " M_IRQ_1_set/clr ,COMMTX MPU emulation interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " M_IRQ_0_set/clr ,EMUINT MPU emulation interrupt mask" "Not masked,Masked"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "INTCPS_MIR1,Interrupt Mask"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " M_IRQ_63_set/clr ,McBSP module 2 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " M_IRQ_62_set/clr ,McBSP module 2 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " M_IRQ_61_set/clr ,I2C module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " M_IRQ_60_set/clr ,McBSP module 1 receive interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " M_IRQ_59_set/clr ,McBSP module 1 transmit interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " M_IRQ_58_set/clr ,HDQ/One-wire interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " M_IRQ_57_set/clr ,I2C module 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " M_IRQ_56_set/clr ,I2C module 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " M_IRQ_55_set/clr ,McBSP module 4 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " M_IRQ_54_set/clr ,McBSP module 4 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " M_IRQ_53_set/clr ,EMIF4ERR interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " M_IRQ_52_set/clr ,RNG module interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " M_IRQ_51_set/clr ,SHA-2/MD5 crypto-accelerator 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " M_IRQ_50_set/clr ,PKA crypto-accelerator interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " M_IRQ_49_set/clr ,SHA-1/MD5 crypto-accelerator 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " M_IRQ_48_set/clr ,McSPI module 4 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " M_IRQ_47_set/clr ,General-purpose timer module 11 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " M_IRQ_46_set/clr ,General-purpose timer module 10 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " M_IRQ_45_set/clr ,General-purpose timer module 9 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " M_IRQ_44_set/clr ,General-purpose timer module 8 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " M_IRQ_43_set/clr ,General-purpose timer module 7 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " M_IRQ_42_set/clr ,General-purpose timer module 6 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " M_IRQ_41_set/clr ,General-purpose timer module 5 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " M_IRQ_40_set/clr ,General-purpose timer module 4 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " M_IRQ_39_set/clr ,General-purpose timer module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " M_IRQ_38_set/clr ,General-purpose timer module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " M_IRQ_37_set/clr ,General-purpose timer module 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " M_IRQ_36_set/clr ,Watchdog timer module 3 overflow interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " M_IRQ_34_set/clr ,GPIO module 6 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " M_IRQ_33set/clr ,GPIO module 5 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " M_IRQ_32_set/clr ,GPIO module 4 interrupt mask" "Not masked,Masked"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "INTCPS_MIR2,Interrupt Mask"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " M_IRQ_95_set/clr ,General-purpose timer module 12 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " M_IRQ_94_set/clr ,MMC/SD module 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " M_IRQ_93_set/clr ,CCDC_VD2_INT VPFE interrupt 2 mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " M_IRQ_92_set/clr ,CCDC_VD1_INT VPFE interrupt 1 mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " M_IRQ_91_set/clr ,McSPI module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " M_IRQ_90_set/clr ,McBSP module 3 receive interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " M_IRQ_89_set/clr ,McBSP module 3 transmit interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " M_IRQ_88_set/clr ,CCDC_VD0_INT VPFE interrupt 0 mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " M_IRQ_87_set/clr ,MPU ICR interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " M_IRQ_86_set/clr ,MMC/SD module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " M_IRQ_84_set/clr ,UART4 module interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " M_IRQ_83_set/clr ,MMC/SD module 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " M_IRQ_82_set/clr ,McBSP module 5 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " M_IRQ_81_set/clr ,McBSP module 5 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " M_IRQ_79_set/clr ,SHA2/MD5 crypto-accelerator 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " M_IRQ_78_set/clr ,HSUSB MP TLL interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " M_IRQ_77_set/clr ,EHCI controller HSUSB MP Host interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " M_IRQ_76_set/clr ,OHCI controller HSUSB MP Host interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " M_IRQ_75_set/clr ,Merged interrupt for PBIASlite1 and 2 mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " M_IRQ_74_set/clr ,UART module 3 (also infrared) interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " M_IRQ_73_set/clr ,UART module 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " M_IRQ_72_set/clr ,UART module 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " M_IRQ_71_set/clr ,USBOTG interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " M_IRQ_70_set/clr ,C0_MISC_PULSE EMAC 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " M_IRQ_69_set/clr ,C0_TX_PULSE EMAC 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " M_IRQ_68_set/clr ,C0_RX_PULSE EMAC 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " M_IRQ_67_set/clr ,C0_RX_THRESH_PULSE EMAC 0 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " M_IRQ_66_set/clr ,McSPI module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " M_IRQ_65_set/clr ,McSPI module 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " M_IRQ_64_set/clr ,PKA crypto-accelerator interrupt mask" "Not masked,Masked"
|
|
width 21.
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "INTCPS_PENDING_IRQ0,IRQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGIRQ31 ,IRQ status after masking 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGIRQ30 ,IRQ status after masking 30" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGIRQ29 ,IRQ status after masking 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGIRQ28 ,IRQ status after masking 28" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGIRQ27 ,IRQ status after masking 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGIRQ26 ,IRQ status after masking 26" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGIRQ25 ,IRQ status after masking 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGIRQ24 ,IRQ status after masking 24" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGIRQ23 ,IRQ status after masking 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGIRQ22 ,IRQ status after masking 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGIRQ21 ,IRQ status after masking 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGIRQ20 ,IRQ status after masking 20" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGIRQ19 ,IRQ status after masking 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGIRQ18 ,IRQ status after masking 18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGIRQ17 ,IRQ status after masking 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGIRQ16 ,IRQ status after masking 16" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGIRQ15 ,IRQ status after masking 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGIRQ14 ,IRQ status after masking 14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGIRQ13 ,IRQ status after masking 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGIRQ12 ,IRQ status after masking 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGIRQ11 ,IRQ status after masking 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGIRQ10 ,IRQ status after masking 10" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGIRQ9 ,IRQ status after masking 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGIRQ8 ,IRQ status after masking 8" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGIRQ7 ,IRQ status after masking 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGIRQ6 ,IRQ status after masking 6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGIRQ5 ,IRQ status after masking 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGIRQ4 ,IRQ status after masking 4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGIRQ3 ,IRQ status after masking 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGIRQ2 ,IRQ status after masking 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGIRQ1 ,IRQ status after masking 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGIRQ0 ,IRQ status after masking 0" "Not pending,Pending"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_IRQ1,IRQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGIRQ63 ,IRQ status after masking 63" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGIRQ62 ,IRQ status after masking 62" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGIRQ61 ,IRQ status after masking 61" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGIRQ60 ,IRQ status after masking 60" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGIRQ59 ,IRQ status after masking 59" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGIRQ58 ,IRQ status after masking 58" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGIRQ57 ,IRQ status after masking 57" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGIRQ56 ,IRQ status after masking 56" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGIRQ55 ,IRQ status after masking 55" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGIRQ54 ,IRQ status after masking 54" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGIRQ53 ,IRQ status after masking 53" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGIRQ52 ,IRQ status after masking 52" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGIRQ51 ,IRQ status after masking 51" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGIRQ50 ,IRQ status after masking 50" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGIRQ49 ,IRQ status after masking 49" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGIRQ48 ,IRQ status after masking 48" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGIRQ47 ,IRQ status after masking 47" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGIRQ46 ,IRQ status after masking 46" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGIRQ45 ,IRQ status after masking 45" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGIRQ44 ,IRQ status after masking 44" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGIRQ43 ,IRQ status after masking 43" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGIRQ42 ,IRQ status after masking 42" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGIRQ41 ,IRQ status after masking 41" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGIRQ40 ,IRQ status after masking 40" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGIRQ39 ,IRQ status after masking 39" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGIRQ38 ,IRQ status after masking 38" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGIRQ37 ,IRQ status after masking 37" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGIRQ36 ,IRQ status after masking 36" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGIRQ34 ,IRQ status after masking 34" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " PENDINGIRQ33 ,IRQ status after masking 33" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGIRQ32 ,IRQ status after masking 32" "Not pending,Pending"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_IRQ2,IRQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGIRQ95 ,IRQ status after masking 95" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " PENDINGIRQ93 ,IRQ status after masking 93" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PENDINGIRQ92 ,IRQ status after masking 92" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDINGIRQ91 ,IRQ status after masking 91" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDINGIRQ90 ,IRQ status after masking 90" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDINGIRQ89 ,IRQ status after masking 89" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PENDINGIRQ88 ,IRQ status after masking 88" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " PENDINGIRQ87 ,IRQ status after masking 87" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PENDINGIRQ86 ,IRQ status after masking 86" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " PENDINGIRQ85 ,IRQ status after masking 85" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PENDINGIRQ84 ,IRQ status after masking 84" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " PENDINGIRQ83 ,IRQ status after masking 83" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PENDINGIRQ82 ,IRQ status after masking 82" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " PENDINGIRQ81 ,IRQ status after masking 81" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PENDINGIRQ80 ,IRQ status after masking 80" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " PENDINGIRQ79 ,IRQ status after masking 79" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PENDINGIRQ78 ,IRQ status after masking 78" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " PENDINGIRQ77 ,IRQ status after masking 77" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PENDINGIRQ76 ,IRQ status after masking 76" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " PENDINGIRQ75 ,IRQ status after masking 75" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGIRQ74 ,IRQ status after masking 74" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " PENDINGIRQ73 ,IRQ status after masking 73" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PENDINGIRQ72 ,IRQ status after masking 72" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " PENDINGIRQ71 ,IRQ status after masking 71" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PENDINGIRQ70 ,IRQ status after masking 70" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " PENDINGIRQ69 ,IRQ status after masking 69" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENDINGIRQ68 ,IRQ status after masking 68" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " PENDINGIRQ67 ,IRQ status after masking 67" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGIRQ66 ,IRQ status after masking 66" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " PENDINGIRQ65 ,IRQ status after masking 65" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGIRQ64 ,IRQ status after masking 64" "Not pending,Pending"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "INTCPS_PENDING_FIQ0,FIQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGFIQ31 ,FIQ status after masking 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGFIQ30 ,FIQ status after masking 30" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGFIQ29 ,FIQ status after masking 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGFIQ28 ,FIQ status after masking 28" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ27 ,FIQ status after masking 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGFIQ26 ,FIQ status after masking 26" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGFIQ25 ,FIQ status after masking 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGFIQ24 ,FIQ status after masking 24" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ23 ,FIQ status after masking 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGFIQ22 ,FIQ status after masking 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGFIQ21 ,FIQ status after masking 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGFIQ20 ,FIQ status after masking 20" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ19 ,FIQ status after masking 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGFIQ18 ,FIQ status after masking 18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGFIQ17 ,FIQ status after masking 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGFIQ16 ,FIQ status after masking 16" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ15 ,FIQ status after masking 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGFIQ14 ,FIQ status after masking 14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGFIQ13 ,FIQ status after masking 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGFIQ12 ,FIQ status after masking 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ11 ,FIQ status after masking 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGFIQ10 ,FIQ status after masking 10" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ9 ,FIQ status after masking 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGFIQ8 ,FIQ status after masking 8" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGFIQ7 ,FIQ status after masking 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGFIQ6 ,FIQ status after masking 6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ5 ,FIQ status after masking 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGFIQ4 ,FIQ status after masking 4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGFIQ3 ,FIQ status after masking 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGFIQ2 ,FIQ status after masking 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGFIQ1 ,FIQ status after masking 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGFIQ0 ,FIQ status after masking 0" "Not pending,Pending"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_FIQ1,FIQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGFIQ63 ,FIQ status after masking 63" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGFIQ62 ,FIQ status after masking 62" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGFIQ61 ,FIQ status after masking 61" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGFIQ60 ,FIQ status after masking 60" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ59 ,FIQ status after masking 59" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGFIQ58 ,FIQ status after masking 58" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGFIQ57 ,FIQ status after masking 57" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGFIQ56 ,FIQ status after masking 56" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ55 ,FIQ status after masking 55" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGFIQ54 ,FIQ status after masking 54" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGFIQ53 ,FIQ status after masking 53" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGFIQ52 ,FIQ status after masking 52" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ51 ,FIQ status after masking 51" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGFIQ50 ,FIQ status after masking 50" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGFIQ49 ,FIQ status after masking 49" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGFIQ48 ,FIQ status after masking 48" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ47 ,FIQ status after masking 47" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGFIQ46 ,FIQ status after masking 46" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGFIQ45 ,FIQ status after masking 45" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGFIQ44 ,FIQ status after masking 44" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ43 ,FIQ status after masking 43" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGFIQ42 ,FIQ status after masking 42" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ41 ,FIQ status after masking 41" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGFIQ40 ,FIQ status after masking 40" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGFIQ39 ,FIQ status after masking 39" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGFIQ38 ,FIQ status after masking 38" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ37 ,FIQ status after masking 37" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGFIQ36 ,FIQ status after masking 36" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGFIQ35 ,FIQ status after masking 35" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGFIQ34 ,FIQ status after masking 34" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGFIQ33 ,FIQ status after masking 33" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGFIQ32 ,FIQ status after masking 32" "Not pending,Pending"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_FIQ2,FIQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGFIQ95 ,FIQ status after masking 95" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGFIQ94 ,FIQ status after masking 94" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGFIQ93 ,FIQ status after masking 93" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGFIQ92 ,FIQ status after masking 92" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ91 ,FIQ status after masking 91" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGFIQ90 ,FIQ status after masking 90" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGFIQ89 ,FIQ status after masking 89" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGFIQ88 ,FIQ status after masking 88" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ87 ,FIQ status after masking 87" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGFIQ86 ,FIQ status after masking 86" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGFIQ85 ,FIQ status after masking 85" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGFIQ84 ,FIQ status after masking 84" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ83 ,FIQ status after masking 83" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGFIQ82 ,FIQ status after masking 82" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGFIQ81 ,FIQ status after masking 81" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGFIQ80 ,FIQ status after masking 80" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ79 ,FIQ status after masking 79" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGFIQ78 ,FIQ status after masking 78" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGFIQ77 ,FIQ status after masking 77" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGFIQ76 ,FIQ status after masking 76" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ75 ,FIQ status after masking 75" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGFIQ74 ,FIQ status after masking 74" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ73 ,FIQ status after masking 73" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGFIQ72 ,FIQ status after masking 72" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGFIQ71 ,FIQ status after masking 71" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGFIQ70 ,FIQ status after masking 70" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ69 ,FIQ status after masking 69" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGFIQ68 ,FIQ status after masking 68" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGFIQ67 ,FIQ status after masking 67" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGFIQ66 ,FIQ status after masking 66" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGFIQ65 ,FIQ status after masking 65" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGFIQ64 ,FIQ status after masking 64" "Not pending,Pending"
|
|
width 21.
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "INTCPS_ILR0,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR1,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR2,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR3,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR4,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR5,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x11c++0x03
|
|
line.long 0x00 "INTCPS_ILR7,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x00 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x124++0x2b
|
|
line.long 0x0 "INTCPS_ILR9,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR10,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR11,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR12,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR13,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR14,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x18 "INTCPS_ILR15,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x18 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x18 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x1C "INTCPS_ILR16,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x1C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x20 "INTCPS_ILR17,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x20 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x20 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x24 "INTCPS_ILR18,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x24 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x24 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x150++0x17
|
|
line.long 0x0 "INTCPS_ILR20,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR21,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR22,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR23,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR24,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR25,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x16c++0x1f
|
|
line.long 0x0 "INTCPS_ILR27,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR28,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR29,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR30,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR31,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR32,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x18 "INTCPS_ILR33,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x18 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x18 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x1C "INTCPS_ILR34,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x1C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x190++0xaf
|
|
line.long 0x0 "INTCPS_ILR36,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR37,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR38,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR39,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR40,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR41,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x18 "INTCPS_ILR42,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x18 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x18 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x1C "INTCPS_ILR43,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x1C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x20 "INTCPS_ILR44,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x20 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x20 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x24 "INTCPS_ILR45,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x24 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x24 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x28 "INTCPS_ILR46,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x28 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x28 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x2C "INTCPS_ILR47,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x2C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x2C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x30 "INTCPS_ILR48,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x30 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x30 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x34 "INTCPS_ILR49,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x34 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x34 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x38 "INTCPS_ILR50,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x38 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x38 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x3C "INTCPS_ILR51,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x3C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x3C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x40 "INTCPS_ILR52,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x40 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x40 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x44 "INTCPS_ILR53,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x44 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x44 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x48 "INTCPS_ILR54,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x48 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x48 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4C "INTCPS_ILR55,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x50 "INTCPS_ILR56,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x50 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x50 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x54 "INTCPS_ILR57,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x54 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x54 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x58 "INTCPS_ILR58,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x58 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x58 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x5C "INTCPS_ILR59,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x5C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x5C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x60 "INTCPS_ILR60,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x60 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x60 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x64 "INTCPS_ILR61,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x64 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x64 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x68 "INTCPS_ILR62,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x68 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x68 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x6C "INTCPS_ILR63,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x6C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x6C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x70 "INTCPS_ILR64,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x70 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x70 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x74 "INTCPS_ILR65,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x74 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x74 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x78 "INTCPS_ILR66,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x78 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x78 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x7C "INTCPS_ILR67,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x7C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x7C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x80 "INTCPS_ILR68,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x80 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x80 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x84 "INTCPS_ILR69,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x84 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x84 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x88 "INTCPS_ILR70,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x88 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x88 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8C "INTCPS_ILR71,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x90 "INTCPS_ILR72,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x90 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x90 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x94 "INTCPS_ILR73,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x94 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x94 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x98 "INTCPS_ILR74,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x98 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x98 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x9C "INTCPS_ILR75,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x9C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x9C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xA0 "INTCPS_ILR76,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xA0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xA0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xA4 "INTCPS_ILR77,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xA4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xA4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xA8 "INTCPS_ILR78,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xA8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xA8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xAC "INTCPS_ILR79,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xAC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xAC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x244++0x0f
|
|
line.long 0x0 "INTCPS_ILR81,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR82,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR83,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR84,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
group.long 0x258++0x27
|
|
line.long 0x0 "INTCPS_ILR86,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR87,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR88,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR89,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR90,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR91,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x18 "INTCPS_ILR92,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x18 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x18 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x1C "INTCPS_ILR93,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x1C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x20 "INTCPS_ILR94,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x20 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x20 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x24 "INTCPS_ILR95,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x24 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x24 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
width 0xb
|
|
tree.end
|
|
tree "Device INTC"
|
|
base ad:0x480C7000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "INTC_INIT_REGISTER1,Power Optimization Enable Register"
|
|
bitfld.long 0x00 0. " INIT1 ,Lowest power configuration" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "INTC_INIT_REGISTER2,Power Optimization Enable Register"
|
|
bitfld.long 0x00 1. " INIT2 ,Optimal power consumption" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "Memory Subsystem"
|
|
tree "General Purpose Memory Controller (GPMC)"
|
|
base ad:0x6E000000
|
|
width 22.
|
|
tree "Miscellaneous Registers"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The Interconnect Control"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPMC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "GPMC_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 11. " WAIT3EDGEDETECTIONSTATUS ,Status of the Wait3 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT2EDGEDETECTIONSTATUS ,Status of the Wait2 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt (COUNTVALUE)" ">0,=0"
|
|
textline " "
|
|
eventfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "<FIFOTHRESHOLD,=FIFOTHRESHOLD"
|
|
line.long 0x04 "GPMC_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 11. " WAIT3EDGEDETECTIONENABLE ,Enables the Wait3 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WAIT2EDGEDETECTIONENABLE ,Enables the Wait2 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "Masked,Enabled"
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "GPMC_TIMEOUT_CONTROL,Start Value Of The Timeout Counter Set Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "Disabled,Enabled"
|
|
line.long 0x04 "GPMC_ERR_ADDRESS,Stores The Address Of The Illegal Access"
|
|
hexmask.long 0x04 0.--30. 1. " ILLEGALADD ,Address of illegal access"
|
|
line.long 0x08 "GPMC_ERR_TYPE,Stores The Type Of Error"
|
|
bitfld.long 0x08 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ERRORNOTSUPPADD ,Not supported Address error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERRORNOTSUPPMCMD ,Not supported Command error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ERRORTIMEOUT ,Time-out error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "GPMC_CONFIG,Global Configuration Of The GPMC Module"
|
|
bitfld.long 0x00 11. " WAIT3PINPOLARITY ,Selects the polarity of input pin WAIT3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAIT2PINPOLARITY ,Selects the polarity of input pin WAIT2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WRITEPROTECT ,Controls the WP output pin level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "No effect,A26-A11 not modified"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "Disabled,Enabled"
|
|
line.long 0x04 "GPMC_STATUS,Global Status Bits Of The GPMC Module"
|
|
bitfld.long 0x04 11. " WAIT3STATUS ,Copy of input pin WAIT3" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WAIT2STATUS ,Copy of input pin WAIT2" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT1STATUS ,Copy of input pin WAIT1" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT0STATUS ,Copy of input pin WAIT0" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "Not empty,Empty"
|
|
group.long 0x1E0++0x7
|
|
line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch Engine Configuration 1"
|
|
bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Defines the number of GPMC_FCLK cycles to be subtracted" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,CS where Prefetch Postwrite engine is active" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFPWENROUNDROBIN ,PFPW RoundRobin arbitration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,Arbitration between a direct memory access and a PFPW engine access (next access is granted to the PFPW engine)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Maximum number of bytes read/write from the FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLEENGINE ,Prefetch Postwite engine enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,Wait2EdgeDetection,Wait3EdgeDetection"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHROMODE ,Selects when the engine starts the access to CS" "StartEngine set,StartEngine set/wait to nonwait edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization" "Interrupt,DMA request"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses" "Prefetch read,Write-posting"
|
|
line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch Engine Configuration 2"
|
|
hexmask.long.word 0x04 0.--13. 1. " TRANSFERCOUNT ,Number of bytes to be read/write by the engine to the selected CS"
|
|
group.long 0x1EC++0x13
|
|
line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch Engine Control"
|
|
bitfld.long 0x00 0. " STARTENGINE ,Reset FIFO pointer and start the engine" "Stopped,Running"
|
|
line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch Engine Status"
|
|
hexmask.long.byte 0x04 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read/write"
|
|
textline " "
|
|
bitfld.long 0x04 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPOINTER exceeds FIFOTHRESHOLD value" "<=FIFOTHRESHOLD,>FIFOTHRESHOLD"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read/write"
|
|
line.long 0x08 "GPMC_ECC_CONFIG,ECC Configuration"
|
|
bitfld.long 0x08 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH"
|
|
textline " "
|
|
bitfld.long 0x08 12. " ECCBCHT8 ,Error correction capability used for BCH" "t=4,t=8"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8 columns,16 columns"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x08 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,Chip-select 6,Chip-select 7"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled"
|
|
line.long 0x0C "GPMC_ECC_CONTROL,ECC Control"
|
|
eventfld.long 0x0C 8. " ECCCLEAR ,Clear all ECC result registers" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " ECCPOINTER ,ECC result register" "ECC engine disabled,ECC result register 1,ECC result register 2,ECC result register 3,ECC result register 4,ECC result register 5,ECC result register 6,ECC result register 7,ECC result register 8,ECC result register 9,?..."
|
|
line.long 0x10 "GPMC_ECC_SIZE_CONFIG,ECC Size"
|
|
hexmask.long.byte 0x10 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1"
|
|
hexmask.long.byte 0x10 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0"
|
|
textline " "
|
|
bitfld.long 0x10 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "ECCSize0,ECCSize1"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x00 "GPMC_BCH_SWDATA,Pass Data To The BCH ECC Calculator"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation"
|
|
tree.end
|
|
tree "Chip Select #0"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_0,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x60+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_0,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,0CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,0CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,0CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,0CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_0,0ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,0ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,0ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,0ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,0ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_0,0WE and 0OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,0WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,0WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,0WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,0OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,0OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,0OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_0,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x60+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_0,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x60+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_0,Address Location"
|
|
hgroup.long (0x60+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_0,Address Location"
|
|
hgroup.long (0x60+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_0,Address Location"
|
|
group.long (0x60+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_0,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #1"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_1,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x90+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_1,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,1CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,1CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,1CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,1CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_1,1ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,1ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,1ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,1ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,1ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_1,1WE and 1OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,1WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,1WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,1WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,1OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,1OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,1OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_1,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x90+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_1,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x90+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_1,Address Location"
|
|
hgroup.long (0x90+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_1,Address Location"
|
|
hgroup.long (0x90+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_1,Address Location"
|
|
group.long (0x90+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_1,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #2"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_2,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0xC0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_2,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,2CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,2CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,2CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,2CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_2,2ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,2ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,2ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,2ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,2ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_2,2WE and 2OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,2WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,2WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,2WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,2OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,2OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,2OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_2,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_2,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0xC0+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_2,Address Location"
|
|
hgroup.long (0xC0+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_2,Address Location"
|
|
hgroup.long (0xC0+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_2,Address Location"
|
|
group.long (0xC0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_2,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #3"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_3,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0xF0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_3,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,3CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,3CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,3CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,3CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_3,3ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,3ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,3ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,3ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,3ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_3,3WE and 3OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,3WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,3WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,3WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,3OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,3OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,3OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_3,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xF0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_3,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0xF0+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_3,Address Location"
|
|
hgroup.long (0xF0+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_3,Address Location"
|
|
hgroup.long (0xF0+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_3,Address Location"
|
|
group.long (0xF0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_3,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #4"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_4,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x120+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_4,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,4CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,4CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,4CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,4CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_4,4ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,4ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,4ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,4ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,4ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_4,4WE and 4OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,4WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,4WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,4WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,4OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,4OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,4OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_4,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x120+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_4,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x120+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_4,Address Location"
|
|
hgroup.long (0x120+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_4,Address Location"
|
|
hgroup.long (0x120+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_4,Address Location"
|
|
group.long (0x120+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_4,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #5"
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_5,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x150+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_5,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,5CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,5CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,5CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,5CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_5,5ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,5ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,5ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,5ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,5ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_5,5WE and 5OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,5WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,5WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,5WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,5OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,5OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,5OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_5,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x150+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_5,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hgroup.long (0x150+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_5,Address Location"
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|
hgroup.long (0x150+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_5,Address Location"
|
|
hgroup.long (0x150+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_5,Address Location"
|
|
group.long (0x150+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_5,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #6"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_6,Signal Control Parameters Per Chip-select"
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|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
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|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
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|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
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|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
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|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
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|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
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|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
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|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x180+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_6,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,6CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,6CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,6CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,6CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_6,6ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,6ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,6ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,6ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,6ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_6,6WE and 6OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,6WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,6WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,6WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,6OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,6OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,6OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_6,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x180+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_6,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x180+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_6,Address Location"
|
|
hgroup.long (0x180+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_6,Address Location"
|
|
hgroup.long (0x180+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_6,Address Location"
|
|
group.long (0x180+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_6,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #7"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_7,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x1B0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_7,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,7CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,7CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,7CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,7CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_7,7ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,7ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,7ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,7ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,7ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_7,7WE and 7OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,7WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,7WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,7WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,7OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,7OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,7OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_7,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1B0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_7,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x1B0+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_7,Address Location"
|
|
hgroup.long (0x1B0+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_7,Address Location"
|
|
hgroup.long (0x1B0+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_7,Address Location"
|
|
group.long (0x1B0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_7,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Result Registers"
|
|
width 19.
|
|
group.long 0x200++0x23
|
|
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
|
|
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
|
|
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
|
|
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
|
|
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
|
|
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
|
|
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
|
|
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
|
|
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
|
|
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
group.long 0x240++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_0,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_0,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_0,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x250++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_1,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_1,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_1,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x260++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_2,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_2,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_2,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x270++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_3,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_3,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_3,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x280++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_4,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_4,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_4,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x290++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_5,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_5,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_5,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x2A0++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_6,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_6,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_6,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x2B0++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_7,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_7,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_7,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_7,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "SDRC (SDRAM Controller)"
|
|
tree "EMIF4"
|
|
base ad:0x6d000000
|
|
width 24.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EMIF_MOD_ID_REV,EMIF Module ID and Revision Register"
|
|
bitfld.long 0x00 30.--31. " REG_SCHEME ,Distinguish between old and current revision schemes" "Old,New,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " REG_MODULE_ID ,EMIF module ID"
|
|
textline " "
|
|
hexmask.long.byte 0x00 11.--15. 1. " REG_RTL_VERSION ,RTL Version"
|
|
hexmask.long.byte 0x00 8.--10. 1. " REG_MAJOR_REVISION ,Major Revision"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " REG_MINOR_REVISION ,Minor Revision"
|
|
line.long 0x04 "STATUS,SDRAM Status Register"
|
|
bitfld.long 0x04 31. " REG_BE ,Big Endian" "Big,Little"
|
|
bitfld.long 0x04 30. " REG_DUAL_CLK_MODE ,Dual Clock mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " REG_FAST_INIT ,Fast Initialization" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REG_PHY_DLL_READY ,DDR PHY Ready" "Not ready,Ready"
|
|
if (((data.long(ad:0x6d000000+0x08))&0xe0000000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register"
|
|
bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,Reserved,DDR2,?..."
|
|
bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "4/5/6,7,8,9"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " REG_DDR_TERM ,DDR2 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
|
|
bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes"
|
|
bitfld.long 0x00 18.--19. " REG_SDRAM_DRIVE ,SDRAM drive strength" "Normal,Weak,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..."
|
|
bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,2,3,Reserved,1.5,2.5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]"
|
|
bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..."
|
|
elif (((data.long(ad:0x6d000000+0x08))&0xe0000000)==0x40000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register"
|
|
bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,Reserved,DDR2,?..."
|
|
bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "4/5/6,7,8,9"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " REG_DDR_TERM ,DDR2 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
|
|
bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes"
|
|
bitfld.long 0x00 18.--19. " REG_SDRAM_DRIVE ,SDRAM drive strength" "Full,Reduced,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..."
|
|
bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]"
|
|
bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register"
|
|
bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,Reserved,DDR2,?..."
|
|
bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "4/5/6,7,8,9"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " REG_DDR_TERM ,DDR2 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
|
|
bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes"
|
|
bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]"
|
|
bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..."
|
|
endif
|
|
group.long 0x10++0x1f
|
|
line.long 0x00 "SDRAM_REF_CTRL,SDRAM Refresh Control Register"
|
|
bitfld.long 0x00 31. " REG_INITREF_DIS ,Initialization and Refresh disable" "No,Yes"
|
|
hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE ,Refresh Rate"
|
|
line.long 0x04 "SDRAM_REF_CTRL_SHDW,SDRAM Refresh Control Shadow Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " REG_REFRESH_RATE_SHDW ,Shadow field for reg_refresh_rate"
|
|
line.long 0x08 "SDRAM_TIM_1,SDRAM Timing 1 Register"
|
|
bitfld.long 0x08 25.--28. " REG_T_RP ,Minimum number of m_clk cycles from Precharge to Activate or Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 21.--24. " REG_T_RCD ,Minimum number of m_clk cycles from Activate to Read or Write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--16. " REG_T_RAS ,Minimum number of m_clk cycles from Activate to Pre-charge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 17.--20. " REG_T_WR ,Minimum number of m_clk cycles from last Write transfer to Pre-charge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 6.--11. " REG_T_RC ,Minimum number of m_clk cycles from Activate to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 3.--5. " REG_T_RRD ,Minimum number of m_clk cycles from Activate to Activate for a different bank" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " REG_T_WTR ,Minimum number of m_clk cycles from last Write to Read" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "SDRAM_TIM_1_SHDW,SDRAM Timing 1 Shadow Register"
|
|
bitfld.long 0x0C 25.--28. " REG_T_RP_SHDW ,Shadow field for reg_t_rp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 21.--24. " REG_T_RCD_SHDW ,Shadow field for reg_t_rcd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 17.--20. " REG_T_WR_SHDW ,Shadow field for reg_t_wr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--16. " REG_T_RAS_SHDW ,Shadow field for reg_t_ras" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--11. " REG_T_RC_SHDW ,Shadow field for reg_t_rc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 3.--5. " REG_T_RRD_SHDW ,Shadow field for reg_t_rrd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " REG_T_WTR_SHDW ,Shadow field for reg_t_wtr" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SDRAM_TIM_2,SDRAM Timing 2 Register"
|
|
bitfld.long 0x10 28.--30. " REG_T_XP ,Minimum number of m_clk cycles from Power-Down exit to any command other than a Read command" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 25.--27. " REG_T_ODT ,Minimum number of m_clk cycles from ODT enable to write data driven for DDR2" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x10 16.--24. 1. " REG_T_XSNR ,Minimum number of m_clk cycles from Self-Refresh exit to any command other than a Read command"
|
|
textline " "
|
|
hexmask.long.word 0x10 6.--15. 1. " REG_T_XSRD ,Minimum number of m_clk cycles from Self-Refresh exit to a Read command"
|
|
bitfld.long 0x10 3.--5. " REG_T_RTP ,Minimum number of m_clk cycles from the last Read command to a Pre-charge command for DDR2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " REG_T_CKE ,Minimum number of m_clk cycles between pad_cke_o changes" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDRAM_TIM_2_SHDW,SDRAM Timing 2 Shadow Register"
|
|
bitfld.long 0x14 28.--30. " REG_T_XP_SHDW ,Shadow field for reg_t_xp" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 25.--27. " REG_T_ODT_SHDW ,Shadow field for reg_t_odt" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x14 16.--24. 1. " REG_T_XSNR_SHDW ,Shadow field for reg_t_xsnr"
|
|
hexmask.long.word 0x14 6.--15. 1. " REG_T_XSRD_SHDW ,Shadow field for reg_t_xsrd"
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " REG_T_RTP_SHDW ,Shadow field for reg_t_rtp" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. " REG_T_CKE_SHDW ,Shadow field for reg_t_cke" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SDRAM_TIM_3,SDRAM Timing 3 Register"
|
|
hexmask.long.word 0x18 4.--12. 1. " REG_T_RFC ,Minimum number of m_clk cycles from Refresh or Load Mode to Refresh or Activate"
|
|
bitfld.long 0x18 0.--3. " REG_T_RAS_MAX ,Maximum number of reg_refresh_rate intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1c "SDRAM_TIM_3_SHDW,SDRAM Timing 3 Shadow Register"
|
|
hexmask.long.word 0x1c 4.--12. 1. " REG_T_RFC_SHDW ,Shadow field for reg_t_rfc"
|
|
bitfld.long 0x1c 0.--3. " REG_T_RAS_MAX_SHDW ,Shadow field for reg_t_ras_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "PWR_MGMT_CTRL,Power Management Control Register"
|
|
bitfld.long 0x00 30.--31. " REG_IDLEMODE ,Power-Idle IP Generic mode" "Force-idle,No-idle,Smart-idle,Not supported"
|
|
bitfld.long 0x00 10. " REG_DPD_EN ,Deep Power-Down enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " REG_LP_MODE ,Automatic Power Management enable" "Disabled,Clock Stop,Self Refresh,Power-Down"
|
|
bitfld.long 0x00 0.--3. " REG_PM_TIM ,Power Management timer (clocks)" "Immediately,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144"
|
|
line.long 0x04 "PWR_MGMT_CTRL_SHDW,Power Management Control Shadow Register"
|
|
bitfld.long 0x04 0.--3. " REG_PM_TIM_SHDW ,Shadow field for reg_pm_tim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OCP_CONFIG,OCP Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REG_PR_OLD_COUNT ,Priority Raise Old Counter"
|
|
rgroup.long 0x58++0x07
|
|
line.long 0x00 "OCP_CFG_VAL_1,OCP Configuration Value 1 Register"
|
|
bitfld.long 0x00 30.--31. " REG_SYS_BUS_WIDTH ,L3 OCP data bus width for a particular configuration (bit)" "32,64,128,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " REG_WR_FIFO_DEPTH ,Write Data FIFO depth for a particular configuration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " REG_CMD_FIFO_DEPTH ,Command FIFO depth for a particular configuration"
|
|
line.long 0x04 "OCP_CFG_VAL_2,OCP Configuration Value 2 Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " REG_RREG_FIFO_DEPTH ,Register Read Data FIFO depth for a particular configuration"
|
|
hexmask.long.byte 0x04 8.--15. 1. " REG_RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth for a particular configuration"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " REG_RCMD_FIFO_DEPTH ,Read Command FIFO depth for a particular configuration"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IODFT_TLGC,ODFT Test Logic Global Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " REG_TLEC ,IODFT Test Logic Execution Counter"
|
|
textline " "
|
|
bitfld.long 0x00 14. " REG_MT ,MISR on/off trigger command" "Inactive/no affect,MISR capture/Pattern generator"
|
|
textline " "
|
|
bitfld.long 0x00 13. " REG_ACT_CAP_EN ,Active cycles capture enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " REG_OPG_LD ,Load pattern generators' initial value" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REG_RESET_PHY ,Reset DDR PHY" "No reset,Reset"
|
|
bitfld.long 0x00 8. " REG_MMS ,Chooses the source of the MISR input" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " REG_MC ,MISR state" "Download results,Current value,Load from pc,Enabled"
|
|
bitfld.long 0x00 1.--3. " REG_PC ,Pattern code" "Functional,Reserved,Reserved,Reserved,Current register value,Random XOR,Random XNOR,8 bit shifter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REG_TM ,Functional mode enable" "IODFT,Functional"
|
|
rgroup.long 0x64++0x13
|
|
line.long 0x00 "IODFT_CTRL_MISR_RSLT,IODFT Test Logic Control MISR Result Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " REG_DQM_TLMR ,MISR result signature for the control signals"
|
|
hexmask.long.word 0x00 0.--10. 1. " REG_CTL_TLMR ,MISR result signature for the control signals"
|
|
line.long 0x04 "IODFT_ADDR_MISR_RSLT,ODFT Test Logic Address MISR Result Register"
|
|
hexmask.long.tbyte 0x04 0.--20. 1. " REG_ADDR_TLMR ,MISR result signature for the address signals"
|
|
line.long 0x08 "IODFT_DATA_MISR_RSLT_1,IODFT Test Logic Data MISR Result 1 Register"
|
|
line.long 0x0c "IODFT_DATA_MISR_RSLT_2,IODFT Test Logic Data MISR Result 2 Register"
|
|
line.long 0x10 "IODFT_DATA_MISR_RSLT_3,IODFT Test Logic Data MISR Result 3 Register"
|
|
bitfld.long 0x10 0.--2. " REG_DATA_TLMR_66_64 ,Most significant bits of the MISR result signature for data bus" "0,1,2,3,4,5,6,7"
|
|
width 14.
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register"
|
|
line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "PERF_CNT_CFG,Performance Counter Configuration Register"
|
|
bitfld.long 0x00 31. " REG_CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " REG_CNTR2_REGION_EN ,Chip Select filter enable for Performance Counter 2 register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " REG_CNTR2_CFG ,Filter configuration for Performance Counter 2" "Total SDRAM accesses,Total SDRAM activates,Total reads,Total writes,Num. of Command FIFO is full,Num. of Write Data FIFO is full,Num. of Read Data FIFO is full,Num. of Return Command FIFO is full,Num. of priority elevations,Num. of m_clk cycles that command pending,Num. of m_clk cycles for which memory data bus Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " REG_CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " REG_CNTR1_REGION_EN ,Chip Select filter enable for Performance Counter 1 register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " REG_CNTR1_CFG ,Filter configuration for Performance Counter 1" "Total SDRAM accesses,Total SDRAM activates,Total reads,Total writes,Num. of Command FIFO is full,Num. of Write Data FIFO is full,Num. of Read Data FIFO is full,Num. of Return Command FIFO is full,Num. of priority elevations,Num. of m_clk cycles that command pending,Num. of m_clk cycles for which memory data bus Tx,?..."
|
|
line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " REG_MCONNID2 ,MConnID for Performance Counter 2 register"
|
|
bitfld.long 0x04 16.--17. " REG_REGION_SEL2 ,MAddrSpace for Performance Counter 2 register" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " REG_MCONNID1 ,MConnID for Performance Counter 1 register"
|
|
bitfld.long 0x04 0.--1. " REG_REGION_SEL1 ,MAddrSpace for Performance Counter 1 register" "0,1,2,3"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PERF_CNT_TIM,Performance Counter Time Register"
|
|
group.long 0xa0++0x03
|
|
line.long 0x00 "IRQ_EOI,End of Interrupt Register"
|
|
bitfld.long 0x00 0. " REG_EOI ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
|
|
width 21.
|
|
wgroup.long 0xa4++0x03
|
|
line.long 0x00 "IRQSTATUS_RAW_SYS,System OCP Interrupt Raw Status Register"
|
|
bitfld.long 0x00 0. " REG_RAW_SYS ,Raw status of system OCP interrupt" "No effect,Set"
|
|
group.long 0xac++0x03
|
|
line.long 0x00 "IRQSTATUS_SYS,System OCP Interrupt Status Register"
|
|
eventfld.long 0x00 0. " REG_ENABLED_SYS ,Enabled status of system OCP interrupt" "No effect,Clear"
|
|
wgroup.long 0xb4++0x03
|
|
line.long 0x00 "IRQENABLE_SET_SYS,System OCP Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " REG_EN_SYS ,Enable set for system OCP interrupt" "No effect,Set"
|
|
group.long 0xbc++0x03
|
|
line.long 0x00 "IRQENABLE_CLR_SYS,System OCP Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 0. " REG_EN_SYS ,Enable clear for system OCP interrupt" "No effect,Clear"
|
|
rgroup.long 0xd0++0x03
|
|
line.long 0x00 "OCP_ERR_LOG,OCP Error Log Register"
|
|
bitfld.long 0x00 14.--15. " REG_MADDRSPACE ,Address space of the first errored transaction" "0,1,2,3"
|
|
bitfld.long 0x00 11.--13. " REG_MBURSTSEQ ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " REG_MCMD ,Command type of the first errored transaction" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REG_MCONNID ,Connection ID of the first errored transaction"
|
|
group.long 0xe4++0x0b
|
|
line.long 0x00 "DDR_PHY_CTRL_1,DDR PHY Control 1 Register"
|
|
bitfld.long 0x00 23. " TESTIN_LB_CK_SELECT ,Controls the value assigned to the TESTIN_LB_CK_SELECT input on the command macro" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CONFIG_VTP_DYNAMIC_UPDATE ,Controls the value assigned to the CONFIG_VTP_DYNAMIC_UPDATE input on the command macro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " CONFIG_DLL_MODE ,Controls the value assigned to the CONFIG_DLL_MODE input on the data macros" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. " DDR_16B_MODE_PWRSAVE ,Set to gate the clock of second data macro when DDR is used in 16b mode" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CONFIG_EXT_STRBEN ,Controls the value assigned to the CONFIG_EXT_STRBEN input on the DDR PHY data macro" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CONFIG_PWRDN_DISABLE ,Controls the value assigned to the CONFIG_PWRDNEN input on the DDR PHY data macro" "Powered down,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " READ_LATENCY ,Latency for read data from DDR SDRAM in number of X1_CLK_OUT cycles" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "DDR_PHY_CTRL_1_SHDW,DDR PHY Control 1 Shadow Register"
|
|
hexmask.long 0x04 3.--31. 1. " REG_DDR_PHY_CTRL_1_SHDW ,Shadow field for REG_DDR_PHY_CTRL_1"
|
|
bitfld.long 0x04 0.--2. " REG_READ_LATENCY_SHDW ,Shadow field for REG_READ_LATENCY" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "DDR_PHY_CTRL_2,DDR PHY Control 2 Register"
|
|
bitfld.long 0x08 1. " CONFIG_RX_DLL_BYPASS ,Controls the value assigned to the CONFIG_RX_DLL_BYPASS input on the DDR PHY data macro" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CONFIG_TX_STRB_DATA_ALIGN ,Controls the value assigned to the CONFIG_TX_STRB_DATA_ALIGN input on the DDR PHY data macro" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SMS (SDRAM Memory Scheduler)"
|
|
base ad:0x6c000000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SMS_SYSCONFIG,Various Parameters Of The Interconnect"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management req/ack control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SMS_SYSSTATUS,Module Status Information"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "SMS_RG_ATT0,Request Information Permission"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "SMS_RG_ATT1,Request Information Permission"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "SMS_RG_ATT2,Request Information Permission"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "SMS_RG_ATT3,Request Information Permission"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "SMS_RG_ATT4,Request Information Permission"
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "SMS_RG_ATT5,Request Information Permission"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "SMS_RG_ATT6,Request Information Permission"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "SMS_RG_ATT7,Request Information Permission"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM0,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM1,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM2,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM3,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM4,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM5,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM6,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x130++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM7,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM0,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM1,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM2,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM3,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM4,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM5,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM6,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x138++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM7,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "SMS_RG_START1,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "SMS_RG_START2,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "SMS_RG_START3,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "SMS_RG_START4,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "SMS_RG_START5,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "SMS_RG_START6,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "SMS_RG_START7,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "SMS_RG_END1,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "SMS_RG_END2,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "SMS_RG_END3,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "SMS_RG_END4,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SMS_RG_END5,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "SMS_RG_END6,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "SMS_RG_END7,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
width 22.
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "SMS_SECURITY_CONTROL,Security Level Required To Access All SMS Registers"
|
|
bitfld.long 0x00 27. " ROTCTXT11LOCK ,Security level to program rotation context 11 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ROTCTXT10LOCK ,Security level to program rotation context 10 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ROTCTXT9LOCK ,Security level to program rotation context 9 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ROTCTXT8LOCK ,Security level to program rotation context 8 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ROTCTXT7LOCK ,Security level to program rotation context 7 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ROTCTXT6LOCK ,Security level to program rotation context 6 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ROTCTXT5LOCK ,Security level to program rotation context 5 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ROTCTXT4LOCK ,Security level to program rotation context 4 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ROTCTXT3LOCK ,Security level to program rotation context 3 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ROTCTXT2LOCK ,Security level to program rotation context 2 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ROTCTXT1LOCK ,Security level to program rotation context 1 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ROTCTXT0LOCK ,Security level to program rotation context 0 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ARBITRATIONREGSLOCK ,Security level to program arbitration control registers (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REGION1REGSLOCK ,Region1 security firewall registers lock bit" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOFTRESETLOCK ,Soft reset lock bit (triggered with access)" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERRORREGSLOCK ,Error registers lock bit" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FIREWALLLOCK ,All security firewall registers lock bit" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECURITYCONTROLREGLOCK ,SMS_SECURITY_CONTROL register configuration lock bit" "Unlocked,Locked"
|
|
group.long 0x150++0xb
|
|
line.long 0x00 "SMS_CLASS_ARBITER0,Arbitration Parameters Between The Class 0 Request Groups"
|
|
bitfld.long 0x00 31. " BURSTCOMPLETE7 ,Delayed service until burst request complete BurstComplete for group 7" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 30. " BURSTCOMPLETE6 ,Delayed service until burst request complete BurstComplete for group 6" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " EXTENDEDGRANT7 ,Extended grant service inside a class (service for group 7 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTENDEDGRANT6 ,Extended grant service inside a class (service for group 6 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIGHPRIOVECTOR7 ,High priority attribute inside a class for group 7" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HIGHPRIOVECTOR6 ,High priority attribute inside a class for group 6" "Standard,Highest"
|
|
line.long 0x04 "SMS_CLASS_ARBITER1,Arbitration Parameters Between The Class 1 Request Groups"
|
|
bitfld.long 0x04 25. " BURSTCOMPLETE1 ,Delayed service until burst request complete BurstComplete for group 1" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x04 24. " BURSTCOMPLETE0 ,Delayed service until burst request complete BurstComplete for group 0" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EXTENDEDGRANT1 ,Extended grant service inside a class (service for group 1 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " EXTENDEDGRANT0 ,Extended grant service inside a class (service for group 0 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HIGHPRIOVECTOR1 ,High priority attribute inside a class for group 1" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HIGHPRIOVECTOR0 ,High priority attribute inside a class for group 0" "Standard,Highest"
|
|
line.long 0x08 "SMS_CLASS_ARBITER2,Arbitration Parameters Between The Class 2 Request Groups"
|
|
bitfld.long 0x08 29. " BURSTCOMPLETE5 ,Delayed service until burst request complete BurstComplete for group 5" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 28. " BURSTCOMPLETE4 ,Delayed service until burst request complete BurstComplete for group 4" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " BURSTCOMPLETE3 ,Delayed service until burst request complete BurstComplete for group 3" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 26. " BURSTCOMPLETE2 ,Delayed service until burst request complete BurstComplete for group 2" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " EXTENDEDGRANT5 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 16.--17. " EXTENDEDGRANT4 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " EXTENDEDGRANT3 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " EXTENDEDGRANT2 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHPRIOVECTOR5 ,High priority attribute inside a class for group 5" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x08 4. " HIGHPRIOVECTOR4 ,High priority attribute inside a class for group 4" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHPRIOVECTOR3 ,High priority attribute inside a class for group 3" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HIGHPRIOVECTOR2 ,High priority attribute inside a class for group 2" "Standard,Highest"
|
|
group.long 0x160++0xF
|
|
line.long 0x00 "SMS_INTERCLASS_ARBITER,Priority Alternance Between Class 1/Class 2 Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS2PRIO ,Class 2 high priority window width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLASS1PRIO ,Class 1 high priority window width"
|
|
line.long 0x4 "SMS_CLASS_ROTATION0,Number Of Consecutive Services Control Register"
|
|
hexmask.long.byte 0x4 0.--4. 1. " NOFSERVICES ,Number of RE split transactions serviced consecutively"
|
|
line.long 0x8 "SMS_CLASS_ROTATION1,Number Of Consecutive Services Control Register"
|
|
hexmask.long.byte 0x8 0.--4. 1. " NOFSERVICES ,Number of RE split transactions serviced consecutively"
|
|
line.long 0xC "SMS_CLASS_ROTATION2,Number Of Consecutive Services Control Register"
|
|
hexmask.long.byte 0xC 0.--4. 1. " NOFSERVICES ,Number of RE split transactions serviced consecutively"
|
|
rgroup.long 0x170++0x3
|
|
line.long 0x00 "SMS_ERR_ADDR,Address Of An Access That Has Generated An Error"
|
|
group.long 0x174++0x7
|
|
line.long 0x00 "SMS_ERR_TYPE,Additional Information About The Access That Has Generated The Error"
|
|
bitfld.long 0x00 24.--26. " ERRORREGIONID ,Region ID of the region that has been illegally accessed" "Region0,Region1,Region2,Region3,Region4,Region5,Region6,Region7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " ERRORMCMD ,Interconnect command that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " ERRORCONNID ,Identifies the illegal access initiator interconnect ConnID of the illegal access initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
eventfld.long 0x00 10. " UNEXPECTEDADD ,Unexpected request targeting nondefined rotation contexts" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 9. " UNEXPECTEDREQ ,Unexpected request received during SMS idle state" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ILLEGALCMD ,Illegal command on the L3 interface" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERRORSECOVERLAP ,Protection region overlapping error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ERRORSECREG ,SMS security register accessed by nonsecure write transaction" "No violation,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERRORSECURITY ,Security violation error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
line.long 0x04 "SMS_POW_CTRL,SMS Power Management"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDLEDELAY ,Delay before autoidle"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL0,Virtual Rotated Frame Buffer Module For Context 0 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL1,Virtual Rotated Frame Buffer Module For Context 1 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL2,Virtual Rotated Frame Buffer Module For Context 2 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL3,Virtual Rotated Frame Buffer Module For Context 3 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL4,Virtual Rotated Frame Buffer Module For Context 4 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL5,Virtual Rotated Frame Buffer Module For Context 5 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL6,Virtual Rotated Frame Buffer Module For Context 6 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL7,Virtual Rotated Frame Buffer Module For Context 7 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL8,Virtual Rotated Frame Buffer Module For Context 8 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL9,Virtual Rotated Frame Buffer Module For Context 9 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL10,Virtual Rotated Frame Buffer Module For Context 10 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL11,Virtual Rotated Frame Buffer Module For Context 11 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE0,Bank Organization For Context 0 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 0"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 0"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE1,Bank Organization For Context 1 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 1"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE2,Bank Organization For Context 2 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 2"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 2"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE3,Bank Organization For Context 3 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 3"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 3"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE4,Bank Organization For Context 4 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 4"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 4"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE5,Bank Organization For Context 5 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 5"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 5"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE6,Bank Organization For Context 6 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 6"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 6"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE7,Bank Organization For Context 7 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 7"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 7"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE8,Bank Organization For Context 8 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 8"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 8"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE9,Bank Organization For Context 9 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 9"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 9"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE10,Bank Organization For Context 10 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 10"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 10"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE11,Bank Organization For Context 11 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 11"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 11"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA0,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 0"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA1,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA2,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 2"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA3,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 3"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA4,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 4"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA5,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 5"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA6,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 6"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA7,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 7"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA8,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 8"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA9,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 9"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA10,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 10"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA11,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 11"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "VPFE (Video Processing Front End)"
|
|
base ad:0x5c060000
|
|
width 21.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "PID,Peripherial ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " PID ,Peripheral Revision and Class Information"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "VPFE_PCR,VPFE Peripherial Control Register"
|
|
bitfld.long 0x00 1. " BUSY ,CCDC module busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " ENABLE ,CCDC module enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYN_MODE,SYNC And Mode Set Register"
|
|
bitfld.long 0x04 17. " WEN ,Data write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " VDHDEN ,VD/HD timing generator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FLDSTAT ,Field signal status" "Odd,Even"
|
|
bitfld.long 0x04 14. " LPF ,Three-tap low pass filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " INPMOD ,cam_d format in SYNC mode" "Raw,YCbCr 16bit,YCbCr 8bit,?..."
|
|
bitfld.long 0x04 11. " PACK8 ,Data packing" "Normal,Pack"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " DATSIZ ,cam_d signal width in SYNC mode" "16 bits,15 bits,14 bits,13 bits,12 bits,11 bits,10 bits,8 bits"
|
|
bitfld.long 0x04 7. " FLDMODE ,Sensor field signal mode" "Progressive,Interlaced"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATAPOL ,Input data signal polarity" "Normal,Ones complement"
|
|
bitfld.long 0x04 5. " EXWEN ,External write enable selection" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FLDPOL ,Field signal polarity" "Positive,Negative"
|
|
bitfld.long 0x04 3. " HDPOL ,HD sync signal polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VDPOL ,VD sync signal polarity" "Positive,Negative"
|
|
group.long 0x14++0x2b
|
|
line.long 0x00 "HORZ_INFO,Horizontal Pixel Info Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " SPH ,Start pixel horizontal"
|
|
hexmask.long.word 0x00 0.--14. 1. " NPH ,Number of pixels horizontal"
|
|
line.long 0x04 "VERT_START,Vertical Line Start Register"
|
|
hexmask.long.word 0x04 16.--30. 1. " SLV0 ,Start line vertical - field0"
|
|
hexmask.long.word 0x04 0.--14. 1. " SLV1 ,Start line vertical - field1"
|
|
line.long 0x08 "VERT_LINES,Vertical Line Number Register"
|
|
hexmask.long.word 0x08 0.--14. 1. " NLV ,Number of lines - vertical direction"
|
|
line.long 0x0C "CULLING,Cull Control Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " CULHEVN ,Horizontal culling patterns for even lines"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " CULHODD ,Horizontal culling patterns for odd lines"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CULV ,Vertical culling pattern"
|
|
line.long 0x10 "HSIZE_OFF,Horizontal Size Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " LNOFST , Line offset"
|
|
line.long 0x14 "SDOFST,Memory Offset Register"
|
|
bitfld.long 0x14 14. " FIINV ,Field identification signal inverse" "Non Inverse,Inverse"
|
|
bitfld.long 0x14 12.--13. " FOFST ,Line offset value" "+1 line,+2 line,+3 line,+4 line"
|
|
textline " "
|
|
bitfld.long 0x14 9.--11. " LOFST0 ,Line offset values of even lines and even fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
bitfld.long 0x14 6.--8. " LOFST1 ,Line offset values of odd lines and even fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " LOFST2 ,Line offset values of even lines and odd fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
bitfld.long 0x14 0.--2. " LOFST3 ,Line offset values of odd lines and odd fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
line.long 0x18 "SDR_ADDR,Memory Address Register"
|
|
line.long 0x1C "CLAMP,Optical Black Clamping Settings Register"
|
|
bitfld.long 0x1C 31. " CLAMPEN ,Clamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28.--30. " OBSLEN ,Optical black sample length" "1 pixel,2 pixels,4 pixels,8 pixels,16 pixels,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 25.--27. " OBSLN ,Optical black sample lines" "1 line,2 lines,4 lines,8 lines,16 lines,?..."
|
|
hexmask.long.word 0x1C 10.--24. 1. " OBST ,Start pixel of optical black samples"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--4. 1. " OBGAIN ,Gain to apply to the optical black average"
|
|
line.long 0x20 "DCSUB,DC Clamp Register"
|
|
hexmask.long.word 0x20 0.--13. 1. " DCSUB ,DC value to subtract from the data"
|
|
line.long 0x24 "COLPTN,Color Pattern Register"
|
|
bitfld.long 0x24 30.--31. " CP3LPC3 ,Collor pattern 3rd line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 28.--29. " CP3LPC2 ,Collor pattern 3rd line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 26.--27. " CP3LPC1 ,Collor pattern 3rd line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 24.--25. " CP3LPC0 ,Collor pattern 3rd line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 22.--23. " CP2PLC3 ,Collor pattern 2nd line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 20.--21. " CP2PLC2 ,Collor pattern 2nd line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 18.--19. " CP2PLC1 ,Collor pattern 2nd line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 16.--17. " CP2PLC0 ,Collor pattern 2nd line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 14.--15. " CP1PLC3 ,Collor pattern 1st line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 12.--13. " CP1PLC2 ,Collor pattern 1st line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 10.--11. " CP1PLC1 ,Collor pattern 1st line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 8.--9. " CP1PLC0 ,Collor pattern 1st line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 6.--7. " CP0PLC3 ,Collor pattern 0th line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 4.--5. " CP0PLC2 ,Collor pattern 0th line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x24 2.--3. " CP0PLC1 ,Collor pattern 0th line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x24 0.--1. " CP0PLC0 ,Collor pattern 0th line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
line.long 0x28 "BLKCMP,Black Compensation Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " R_YE ,Black level compensation R/Ye pixels"
|
|
hexmask.long.byte 0x28 16.--23. 1. " GR_CY ,Black level compensation Gr/Cy pixels"
|
|
textline " "
|
|
hexmask.long.byte 0x28 8.--15. 1. " GB_G ,Black level compensation Gb/G pixels"
|
|
hexmask.long.byte 0x28 0.--7. 1. " B_MG ,Black level compensation B/Mg pixels"
|
|
group.long 0x48++0x0f
|
|
line.long 0x00 "VDINT,VD Interrupt Control Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " VDINT0 ,VD0 interrupt timing"
|
|
hexmask.long.word 0x00 0.--14. 1. " VDINT1 ,VD1 interrupt timing"
|
|
line.long 0x04 "ALAW,Alaw Configuration Register"
|
|
bitfld.long 0x04 3. " CCDTBL ,Apply A-Law compression to data saved to memory" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " GWDI ,A-Law input width" "Bits 15 to 6,Bits 14 to 5,Bits 13 to 4,Bits 12 to 3,Bits 11 to 2,Bits 10 to 1,Bits 9 to 0,?..."
|
|
line.long 0x08 "REC656IF,ITU-R BT.656 Configuration Register"
|
|
bitfld.long 0x08 1. " ECCFVH ,FVH error correction enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " R656ON ,ITU-R BT656 interface enable" "Disabled,Enabled"
|
|
line.long 0x0c "CCDCFG,Configuration Register"
|
|
bitfld.long 0x0c 15. " VDLC ,Enable latching function registers on the internal VS sync pulse" "Latched,Not latched"
|
|
bitfld.long 0x0c 13. " MSBINVI ,MSB of chroma input signal stored to memory inverted" "Normal,MSB inverted"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " BSWD ,Byte swap data stored to memory" "Normal,Swap bytes"
|
|
bitfld.long 0x0c 11. " Y8POS ,Location of Y color component when YCbCr 8-bit data is input" "Even pixel,Odd pixel"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " WENLOG ,Valid area settings" "ANDed,ORed"
|
|
bitfld.long 0x0c 6.--7. " FIDMD ,Settings of field identification detection function (FLD signal at the VS timing)" "Latched,Not latched,Latched at edge,Latched on phase VD/HD"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " BW656 ,The data width in CCIR656 input mode" "8 bits,10 bits"
|
|
bitfld.long 0x0c 4. " YCINSWP ,Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped" "C signal,Y signal"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "DMA_CNTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " OVERFLOW ,DMA Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 0.--2. " CPRIORITY ,Command Priority" "Highest priority,1,2,3,4,5,6,Lowest priority"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "Display Subsystem"
|
|
tree "DISS"
|
|
base ad:0x48050000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DSS_SYSCONFIG,Configuration Register"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Power management capability" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x00 "DSS_SYSSTATUS,Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
line.long 0x04 "DSS_IRQSTATUS,Source Of The Interrupt And The Status Of The Interrupt Line"
|
|
bitfld.long 0x04 1. " DSI_IRQ ,DSI interrupt status" "Not active,Active"
|
|
bitfld.long 0x04 0. " DISPC_IRQ ,DISPC interrupt status" "Not active,Active"
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "DSS_CONTROL,Display Subsystem Control Register"
|
|
bitfld.long 0x00 6. " VENC_OUT_SEL ,Venc output select" "Composite,Luminance"
|
|
bitfld.long 0x00 5. " DAC_POWERDN_BGZ ,DAC power-down band gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DAC_DEMEN ,DAC dynamic element matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VENC_CLOCK_4X_ENABLE ,VENC clock 4x enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VENC_CLOCK_MODE ,VENC clock mode" "Normal,Square pixel"
|
|
bitfld.long 0x00 1. " DSI_CLK_SWITCH ,DSS1_ALWON_FCLK/DSI2_PLL_FCLK clock source for DSI clk" "DSS1_ALWON_FCLK,DSI2_PLL_FCLK"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DISPC_CLK_SWITCH ,DSS1_PLL_FCLK/DSI1_ALWON_FCLK clock siwtch" "DSI1_ALWON_FCLK,DSI1_PLL_FCLK"
|
|
line.long 0x04 "DSS_SDI_CONTROL,Display Subsystem Control Register"
|
|
bitfld.long 0x04 15.--19. " SDI_PDIV ,Ratio of PLL output to pixel clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. " SDI_PHYLPMODE ,FlatLink3G output buffer low power option" "Standard,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " SDI_RBITS ,FlatLink3G reserved bits F1 and F0" "0,1,2,3"
|
|
bitfld.long 0x04 11. " SDI_AUTOSTDBY ,High-speed serial buffers enable" "PLL locked,SDI active"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SDI_PRSEL ,Selection of the number of data pairs" "DATA0,DATA0 and DATA1,DATA0 DATA1 and DATA2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDI_BWSEL ,Color depth" "Reserved,Reserved,24 bits,?..."
|
|
line.long 0x08 "DSS_PLL_CONTROL,Display Subsystem Control Register"
|
|
bitfld.long 0x08 28. " SDI_PLL_GOBIT ,PLL locking sequence request" "Not requested,Requested"
|
|
bitfld.long 0x08 26.--27. " SDI_PLL_LOCKSEL ,Lock criteria for PLL" "Phase,Fine phase,Frequency,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--25. " SDI_PLL_FREQSEL ,PLL internal refererence frequency range selection" "Reserved,Reserved,Reserved,0.75MHz to 1.0MHz,1.0MHz to 1.25MHz,1.25MHz to 1.5MHz,1.5MHz to 1.75MHz,1.75MHz to 2.1MHz,Reserved,Reserved,Reserved,7.5MHz to 10MHz,10MHz to 12.5MHz,12.5MHz to 15MHz,15MHz to 17.5MHz,17.5MHz to 21MHz"
|
|
bitfld.long 0x08 21. " SDI_PLL_PLLPMODE ,Select the power / performance of the PLL" "Performance,Power"
|
|
textline " "
|
|
bitfld.long 0x08 20. " SDI_PLL_LOWCURRSTBY ,PLL low current standby" "Not selected,Selected"
|
|
bitfld.long 0x08 19. " SDI_PLL_HIGHFREQ ,Division of pixel clock by 2 before input of PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " SDI_PLL_SYSRESET ,SDI PLL reset" "Reset,Operational"
|
|
bitfld.long 0x08 17. " SDI_PLL_STOPMODE ,SDI PLL STOPMODE" "Not selected,Selected"
|
|
textline " "
|
|
hexmask.long.byte 0x08 11.--16. 1. " SDI_PLL_REGN ,SDI PLL REGN register"
|
|
hexmask.long.word 0x08 1.--10. 1. " SDI_PLL_REGM ,SDI PLL REGM register"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SDI_PLL_IDLE ,IDLE select" "Not selected,Selected"
|
|
rgroup.long 0x5c++0x3
|
|
line.long 0x00 "DSS_SDI_STATUS,Display Subsystem Status Register"
|
|
bitfld.long 0x00 8. " DSI_PLL_CLK2_STATUS ,DSI2_PLL_FCLK clock selection status" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " DSS_DSI_CLK1_STATUS ,DSI1_ALWON_FCLK clock selection status" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SDI_PLL_BUSYFLAG ,PLL locking sequence status" "Completed,Not completed"
|
|
bitfld.long 0x00 5. " SDI_PLL_LOCK ,SDI PLL lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDI_PLL_RECAL ,SDI DPLL re-calibration status" "Not required,Required"
|
|
bitfld.long 0x00 3. " SDI_ERROR ,SDI error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SDI_RESET_DONE ,SDI reset done status" "Not done,Done"
|
|
bitfld.long 0x00 1. " DSI_PLL_CLK1_STATUS ,DSI1_PLL_FCLK clock selection status" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DSS_CLK1_STATUS ,DSI1_ALWON_FCLK clock selection status" "Not selected,Selected"
|
|
width 11.
|
|
tree.end
|
|
tree "DISPC"
|
|
base ad:0x48050400
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DISPC_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management" "Force standby,No standby,Smart Standby,?..."
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake up mode period (interface clk/functional clk)" "Switched-off,Maintained/Switched-off,Switched-off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force idle,No idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENWAKEUP ,Wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal auto-clock gating strategy" "Free running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DISPC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DISPC_IRQSTATUS,Status Of Module Internal Events That Generate An Interrupt"
|
|
eventfld.long 0x00 16. " WAKEUP ,Wakeup" "Not occurred,Occurred"
|
|
eventfld.long 0x00 15. " SYNCLOSTDIGITAL ,SyncLostDigital" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " SYNCLOST ,SyncLost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 13. " VID2ENDWINDOW ,Vid2EndWindow" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 12. " VID2FIFOUNDERFLOW ,Vid2FIFOUnderflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " VID1ENDWINDOW ,Vid1EndWindow" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " VID1FIFOUNDERFLOW ,Vid1FIFOUnderflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " OCPERROR ,OCPError" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PALETTEGAMMALOADING ,PaletteGammaLoading" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " GFXENDWINDOW ,GfxEndWindow" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " GFXFIFOUNDERFLOW ,GfxFIFOUnderflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " PROGRAMMEDLINENUMBER ,ProgrammedLineNumber" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ACBIASCOUNTSTATUS ,ACBiasCountStatus" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EVSYNC_ODD ,EVSYNC_ODD" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EVSYNC_EVEN ,EVSYNC_EVEN" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " VSYNC ,VSYNC" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " FRAMEDONE ,FrameDone" "Not occurred,Occurred"
|
|
line.long 0x04 "DISPC_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 16. " WAKEUP ,Wakeup" "Masked,Not masked"
|
|
bitfld.long 0x04 15. " SYNCLOSTDIGITAL ,SyncLostDigital" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " SYNCLOST ,SyncLost" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VID2ENDWINDOW ,Vid2EndWindow" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " VID2FIFOUNDERFLOW ,Vid2FIFOUnderflow" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " VID1ENDWINDOW ,Vid1EndWindow" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " VID1FIFOUNDERFLOW ,Vid1FIFOUnderflow" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " OCPERROR ,OCPError" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PALETTEGAMMALOADING ,PaletteGammaLoading" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " GFXENDWINDOW ,GfxEndWindow" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GFXFIFOUNDERFLOW ,GfxFIFOUnderflow" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PROGRAMMEDLINENUMBER ,ProgrammedLineNumber" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACBIASCOUNTSTATUS ,ACBiasCountStatus" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " EVSYNC_ODD ,EVSYNC_ODD" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EVSYNC_EVEN ,EVSYNC_EVEN" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " VSYNC ,VSYNC" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FRAMEMASK ,FrameMask" "Masked,Not masked"
|
|
if (((d.l((ad:0x48050400+0x40)))&0x100000)==0x100000)
|
|
;DISPC_CONTROL(20) = TDM Enable
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DISPC_CONTROL,Display Controller Module Configure Register"
|
|
bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames" "Spatial only,Spatial/temporal over 2,Spatial/temporal over 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " LCDENABLEPOL ,LCD Enable Signal Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LCDENABLESIGNAL ,LCD Enable Signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PCKFREEENABLE ,Pixel clock free-running enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TDMUNUSEDBITS ,State of unused bits" "Low,High,Unchanged,?..."
|
|
bitfld.long 0x00 23.--24. " TDMCYCLEFORMAT ,Cycle format (cycle/pixel)" "1c/1p,2c/1p,3c/1p,3c/2p"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " TDMPARALLELMODE ,Output Interface width" "8-bit,9-bit,12-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " HT ,Hold Time for digital output" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal" "Reset,Set"
|
|
bitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal" "Reset,Set"
|
|
bitfld.long 0x00 12. " OVERLAYOPTIMIZATION ,Overlay Optimization" "Fetched,Not fetched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STALLMODE ,STALL Mode for the LCD output" "Normal,Stall"
|
|
bitfld.long 0x00 10. " SECURE ,Secure bit set/reset by secure request only" "Non-secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the LCD interface" "12-bit,16-bit,18-bit,24-bit"
|
|
bitfld.long 0x00 7. " STDITHERENABLE ,Spatial temporal dithering enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " GODIGITAL ,Digital GO Command" "Hardaware finished,User finished"
|
|
bitfld.long 0x00 5. " GOLCD ,LCD GO Command" "Hardaware finished,User finished"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M8B ,Mono 8-bit mode" "Pixel data[3:0],Pixel data[7:0]"
|
|
bitfld.long 0x00 3. " STNTFT ,LCD display type" "Passive/Passive matrix,Active matrix"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color" "Color,Monochrome"
|
|
bitfld.long 0x00 1. " DIGITALENABLE ,Digital enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCDENABLE ,LCD enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DISPC_CONTROL,Display Controller Module Configure Register"
|
|
bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames" "Spatial only,Spatial/temporal over 2,Spatial/temporal over 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " LCDENABLEPOL ,LCD Enable Signal Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LCDENABLESIGNAL ,LCD Enable Signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PCKFREEENABLE ,Pixel clock free-running enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " HT ,Hold Time for digital output" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal" "Reset,Set"
|
|
bitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal" "Reset,Set"
|
|
bitfld.long 0x00 12. " OVERLAYOPTIMIZATION ,Overlay Optimization" "Fetched,Not fetched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STALLMODE ,STALL Mode for the LCD output" "Normal,Stall"
|
|
bitfld.long 0x00 10. " SECURE ,Secure bit set/reset by secure request only" "Non-secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the LCD interface" "12-bit,16-bit,18-bit,24-bit"
|
|
bitfld.long 0x00 7. " STDITHERENABLE ,Spatial temporal dithering enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " GODIGITAL ,Digital GO Command" "Hardaware finished,User finished"
|
|
bitfld.long 0x00 5. " GOLCD ,LCD GO Command" "Hardaware finished,User finished"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M8B ,Mono 8-bit mode" "Pixel data[3:0],Pixel data[7:0]"
|
|
bitfld.long 0x00 3. " STNTFT ,LCD display type" "Passive/Passive matrix,Active matrix"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color" "Color,Monochrome"
|
|
bitfld.long 0x00 1. " DIGITALENABLE ,Digital enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCDENABLE ,LCD enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l((ad:0x48050400+0x40)))&0x8)==0x8)
|
|
;DISPC_CONTROL(3) = Active matrix
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "DISPC_CONFIG,Display Controller Module Configuration Register"
|
|
bitfld.long 0x00 19. " TVALPHABLENDERENABLE ,Selects the alpha blender overlay manager (TV)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LCDALPHABLENDERENABLE ,Selects the alpha blender overlay manager (LCD)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FIFOFILLING ,FIFO control (when reach Low treshold)" "Each FIFO re-filled,All FIFO re-filled"
|
|
bitfld.long 0x00 16. " FIFOHANDCHECK ,Handscheck control" "Only STALL,STALL/FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CPR ,Color phase rotation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOMERGE ,FIFO merge control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCKDIGSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 12. " TCKDIGENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCKLCDSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FUNCGATED ,Functional clocks gated enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIXELCLOCKGATED ,Pixel Clock Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PIXELDATAGATED ,Pixel Data Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PALETTEGAMMATABLE ,Palette/Gamma Table selection" "Palette,Gamma"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " LOADMODE ,Loading Mode for the Palette/Gamma Table (PGT) and Frame data (FD)" "PGT every frame,PGT loaded,FD every frame,PGT/FD first frame than 10"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIXELGATED ,Pixel Gated Enable" "Always toggles,Toggles when valid data"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "DISPC_CONFIG,Display Controller Module Configuration Register"
|
|
bitfld.long 0x00 19. " TVALPHABLENDERENABLE ,Selects the alpha blender overlay manager (TV)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LCDALPHABLENDERENABLE ,Selects the alpha blender overlay manager (LCD)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FIFOFILLING ,FIFO control (when reach Low treshold)" "Each FIFO re-filled,All FIFO re-filled"
|
|
bitfld.long 0x00 16. " FIFOHANDCHECK ,Handscheck control" "Only STALL,STALL/FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CPR ,Color phase rotation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOMERGE ,FIFO merge control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCKDIGSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 12. " TCKDIGENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCKLCDSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FUNCGATED ,Functional clocks gated enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIXELCLOCKGATED ,Pixel Clock Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PIXELDATAGATED ,Pixel Data Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PALETTEGAMMATABLE ,Palette/Gamma Table selection" "Palette,Gamma"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " LOADMODE ,Loading Mode for the Palette/Gamma Table (PGT) and Frame data (FD)" "PGT every frame,PGT loaded,FD every frame,PGT/FD first frame than 10"
|
|
endif
|
|
width 24.
|
|
group.long 0x4c++0x0f
|
|
line.long 0x0 "DISPC_DEFAULT_COLOR0,Default Solid Background Color For The LCD"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display"
|
|
line.long 0x4 "DISPC_DEFAULT_COLOR1,Default Solid Background Color For The LCD"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display"
|
|
line.long 0x8 "DISPC_TRANS_COLOR0,Transparency Color Value For The Video/Graphics Overlays"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format"
|
|
line.long 0xC "DISPC_TRANS_COLOR1,Transparency Color Value For The Video/Graphics Overlays"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format"
|
|
rgroup.long 0x5C++0x3
|
|
line.long 0x00 "DISPC_LINE_STATUS,Current LCD Panel Display Line Number"
|
|
hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Current LCD panel line number"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "DISPC_LINE_NUMBER,LCD panel line number For Interrupt And DMA Request"
|
|
hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,LCD panel line number programming"
|
|
line.long 0x04 "DISPC_TIMING_H,Timing Logic For The HSYNC Signal"
|
|
hexmask.long.word 0x04 20.--31. 1. " HBP ,Horizontal Back Porch"
|
|
hexmask.long.word 0x04 8.--19. 1. " HFP ,Horizontal front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " HSW ,Horizontal synchronization pulse width"
|
|
line.long 0x08 "DISPC_TIMING_V,Timing Logic For The VSYNC Signal"
|
|
hexmask.long.byte 0x08 20.--27. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.byte 0x08 8.--15. 1. " VFP ,Vertical front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " VSW ,Vertical synchronization pulse width"
|
|
if (((d.l((ad:0x48050400+0x6C)))&0x20000)==0x20000)
|
|
;DISPC_POL_FREQ(17) = Off
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "DISPC_POL_FREQ,Signal Configuration"
|
|
bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off" "On,Off"
|
|
bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall" "Falling-edge,Rising-edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IEO ,Invert output enable" "High,Low"
|
|
bitfld.long 0x00 14. " IPC ,Invert pixel clock" "Rising-edge,Falling-edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IHS ,Invert HSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
bitfld.long 0x00 12. " IVS ,Invert VSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ACBI ,AC-bias pin transitions per interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC-bias pin frequency"
|
|
else
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "DISPC_POL_FREQ,Signal Configuration"
|
|
bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off" "On,Off"
|
|
bitfld.long 0x00 15. " IEO ,Invert output enable" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 14. " IPC ,Invert pixel clock" "Rising-edge,Falling-edge"
|
|
bitfld.long 0x00 13. " IHS ,Invert HSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IVS ,Invert VSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
bitfld.long 0x00 8.--11. " ACBI ,AC-bias pin transitions per interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC-bias pin frequency"
|
|
endif
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "DISPC_DIVISOR,Divisors Configure Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor"
|
|
line.long 0x04 "DISPC_GLOBAL_ALPHA,Global Alpha Value For The Graphics And Video 2 Pipelines"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VID2GLOBALALPHA ,Global alpha value from 0 to 255"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " GFXGLOBALALPHA ,Global alpha value from 0 to 255"
|
|
group.long 0x78++0x7
|
|
line.long 0x00 "DISPC_SIZE_DIG,Size Of The Digital Output Field"
|
|
hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel"
|
|
hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line"
|
|
line.long 0x04 "DISPC_SIZE_LCD,Panel Size"
|
|
hexmask.long.word 0x04 16.--26. 1. " LPP ,Lines per panel"
|
|
hexmask.long.word 0x04 0.--10. 1. " PPL ,Pixels per line"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "DISPC_GFX_BA0,Base Address Of The Graphics Buffer Displayed In The Graphics Window"
|
|
line.long 0x4 "DISPC_GFX_BA1,Base Address Of The Graphics Buffer Displayed In The Graphics Window"
|
|
line.long 0x08 "DISPC_GFX_POSITION,Position Of The Graphics Window"
|
|
hexmask.long.word 0x08 16.--26. 1. " GFXPOSY ,Y position of the graphics window"
|
|
hexmask.long.word 0x08 0.--10. 1. " GFXPOSX ,X position of the graphics window"
|
|
line.long 0x0c "DISPC_GFX_SIZE,Size Of The Graphics Window"
|
|
hexmask.long.word 0x0c 16.--26. 1. " GFXSIZEY ,Number of lines of the graphics window"
|
|
hexmask.long.word 0x0c 0.--10. 1. " GFXSIZEX ,Number of pixels of the graphics window"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "DISPC_GFX_ATTRIBUTES,Graphics Attributes"
|
|
bitfld.long 0x00 15. " GFXSELFREFRESH ,Enables the self refresh of the graphics window (data from the system memory)" "Fetch,Not fetch"
|
|
bitfld.long 0x00 14. " GFXARBITRATION ,Priority of the graphics pipeline" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " GFXROTATION ,Graphics rotation flag" "No rotation,90 degrees,180 degrees,270 degrees"
|
|
bitfld.long 0x00 11. " GFXFIFOPRELOAD ,Graphics preload value (H/W prefetches pixels up to)" "Preload value,High threshold value"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GFXENDIANNESS ,Graphics endianness" "Little,Big"
|
|
bitfld.long 0x00 9. " GFXNIBBLEMODE ,Graphics Nibble Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GFXCHANNELOUT ,Graphics Channel Out configuration" "LCD,24-bit"
|
|
bitfld.long 0x00 6.--7. " GFXBURSTSIZE ,Graphics DMA Burst Size" "4x32bit,8x32bit,16x32bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " GFXREPLICATIONENABLE ,GfxReplicationEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--4. " GFXFORMAT ,Graphics format" "BITMAP 1,BITMAP 2,BITMAP 4,BITMAP 8,RGB 12,ARGB 16,RGB 16,Reserved,RGB 24/32-bit,RGB 24/24-bit,Reserved,Reserved,ARGB 32,RGBA 32,RGBx 32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " GFXENABLE ,GfxEnable" "Disabled,Enabled"
|
|
width 29.
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "DISPC_GFX_FIFO_THRESHOLD,Graphics FIFO Configuration Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " GFXFIFOHIGHTHRESHOLD ,Graphics FIFO High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " GFXFIFOLOWTHRESHOLD ,Graphics FIFO Low Threshold"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x00 "DISPC_GFX_FIFO_SIZE_STATUS,Graphics FIFO Size Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " GFXFIFOSIZE ,Graphics FIFO Size"
|
|
group.long 0xAC++0xF
|
|
line.long 0x00 "DISPC_GFX_ROW_INC,Number Of Bytes To Increment At The End Of The Row"
|
|
line.long 0x04 "DISPC_GFX_PIXEL_INC,Number Of Bytes To Increment Between Two Pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " GFXPIXELINC ,Number of bytes to increment between two pixels"
|
|
line.long 0x08 "DISPC_GFX_WINDOW_SKIP,Number Of Bytes To Skip During Video Window Display"
|
|
line.long 0x0C "DISPC_GFX_TABLE_BA,Base Address Of The Palette Buffer Or The Gamma Table Buffer"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x00 "DISPC_DATA_CYCLE1,Output Data Format For 1st Cycle"
|
|
hexmask.long.byte 0x00 24.--27. 1. " BITALIGNMENTPIXEL2 ,Bit alignment"
|
|
hexmask.long.byte 0x00 16.--20. 1. " NBBITSPIXEL2 ,Number of bits"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--11. 1. " BITALIGNMENTPIXEL1 ,Bit alignment"
|
|
hexmask.long.byte 0x00 0.--4. 1. " NBBITSPIXEL1 ,Number of bits"
|
|
group.long 0x1D8++0x3
|
|
line.long 0x00 "DISPC_DATA_CYCLE2,Output Data Format For 2nd Cycle"
|
|
hexmask.long.byte 0x00 24.--27. 1. " BITALIGNMENTPIXEL2 ,Bit alignment"
|
|
hexmask.long.byte 0x00 16.--20. 1. " NBBITSPIXEL2 ,Number of bits"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--11. 1. " BITALIGNMENTPIXEL1 ,Bit alignment"
|
|
hexmask.long.byte 0x00 0.--4. 1. " NBBITSPIXEL1 ,Number of bits"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x00 "DISPC_DATA_CYCLE3,Output Data Format For 3rd Cycle"
|
|
hexmask.long.byte 0x00 24.--27. 1. " BITALIGNMENTPIXEL2 ,Bit alignment"
|
|
hexmask.long.byte 0x00 16.--20. 1. " NBBITSPIXEL2 ,Number of bits"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--11. 1. " BITALIGNMENTPIXEL1 ,Bit alignment"
|
|
hexmask.long.byte 0x00 0.--4. 1. " NBBITSPIXEL1 ,Number of bits"
|
|
group.long 0x220++0xF
|
|
line.long 0x00 "DISPC_CPR_COEF_R,Color Phase Rotation Matrix Coefficients Configuration"
|
|
hexmask.long.word 0x00 22.--31. 1. " RR ,RR coefficient"
|
|
hexmask.long.word 0x00 11.--20. 1. " RG ,RG coefficient"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " RB ,RB coefficient"
|
|
line.long 0x04 "DISPC_CPR_COEF_G,Color Phase Rotation Matrix Coefficients Configuration"
|
|
hexmask.long.word 0x04 22.--31. 1. " GR ,GR coefficient"
|
|
hexmask.long.word 0x04 11.--20. 1. " GG ,GG coefficient"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " GB ,GB coefficient"
|
|
line.long 0x08 "DISPC_CPR_COEF_B,Color Phase Rotation Matrix Coefficients Configuration"
|
|
hexmask.long.word 0x08 22.--31. 1. " BR ,BR coefficient"
|
|
hexmask.long.word 0x08 11.--20. 1. " BG ,BG coefficient"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " BB ,BB coefficient"
|
|
line.long 0x0C "DISPC_GFX_PRELOAD,Graphics FIFO Configuration"
|
|
hexmask.long.word 0x0C 0.--11. 1. " PRELOAD ,Graphics preload value"
|
|
group.long 0xBC++0x7 "VID 0"
|
|
line.long 0x00 "DISPC_VID0_BA0,Base Address Of The Video Buffer For Video Window"
|
|
line.long 0x04 "DISPC_VID0_BA1,Base Address Of The Video Buffer For Video Window"
|
|
group.long (0xBC+0x08)++0x3
|
|
line.long 0x00 "DISPC_VID0_POSITION,Position Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDPOSY ,Y position of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDPOSX ,X position of the Video window"
|
|
group.long (0xBC+0x0C)++0x3
|
|
line.long 0x00 "DISPC_VID0_SIZE,Size Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDSIZEY ,Number of lines of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDSIZEX ,Number of pixels of the Video window"
|
|
group.long (0xBC+0x10)++0x7
|
|
line.long 0x00 "DISPC_VID0_ATTRIBUTES,Video Attributes"
|
|
bitfld.long 0x00 24. " VIDSELFREFRESH ,Enables the self refresh of the video window (data from the system memory)" "Not fetch,Fetch"
|
|
textline " "
|
|
bitfld.long 0x00 23. " VIDARBITRATION ,Priority of the video pipeline" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VIDLINEBUFFERSPLIT ,Video vertical line buffer split" "Not split,Split"
|
|
textline " "
|
|
bitfld.long 0x00 21. " VIDVERTICALTAPS ,Video vertical resize tap number" "3,5"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIDDMAOPTIMIZATION ,Video optimization in case of (pixel for each 32-bit OCP)" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VIDFIFOPRELOAD ,Video preload value (H/W prefetches pixels up to)" "Preload,High threshold"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VIDROWREPEATENABLE ,Video Row Repeat" "Disabled,Fetched twice"
|
|
textline " "
|
|
bitfld.long 0x00 17. " VIDENDIANNESS ,Video Endianness" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIDCHANNELOUT ,Video Channel Out configuration" "LCD,24 bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " VIDBURSTSIZE ,Video DMA Burst Size" "4x32bit,8x32bit,16x32bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " VIDROTATION ,Video rotation flag" "No rotation,90 degrees,180 degrees,270 degrees"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VIDFULLRANGE ,VidFullRange" "Limited,Full"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIDREPLICATIONENABLE ,VidReplicationEnable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VIDCOLORCONVENABLE ,VidColorConvEnable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VIDVRESIZECONF ,Video Vertical Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VIDHRESIZECONF ,Video Horizontal Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VIDRESIZEENABLE ,Video Resize Enable" "Disabled,Horizontal,Vertical,Horizontal/Vertical"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " VIDFORMAT ,Video format" "Reserved,Reserved,Reserved,Reserved,RGB 12,Reserved,RGB 16,Reserved,RGB 24/32-bit,RGB 24/24-bit,YUV2 4:2:2 co-sited,UYVY 4:2:2 co-sited,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " VIDENABLE ,VIDEnable" "Disabled,Enabled"
|
|
line.long 0x04 "DISPC_VID0_FIFO_THRESHOLD,Video FIFO Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " VIDFIFOHIGHTHRESHOLD ,Video FIFO High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " VIDFIFOLOWTHRESHOLD ,Video FIFO Low Threshold"
|
|
rgroup.long (0xBC+0x18)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIFO_SIZE_STATUS,Video FIFO Size Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDFIFOSIZE ,Video FIFO Size"
|
|
group.long (0xBC+0x1C)++0x7
|
|
line.long 0x00 "DISPC_VID0_ROW_INC,Number Of Bytes To Increment At The End Of The Row"
|
|
line.long 0x04 "DISPC_VID0_PIXEL_INC,Number Of Bytes To Increment Between Two Pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " VIDPIXELINC ,Number of bytes to increment between two pixels"
|
|
group.long (0xBC+0x24)++0xF
|
|
line.long 0x00 "DISPC_VID0_FIR,Resize Factors For Horizontal And Vertical Up-/Down-sampling Of Video Window"
|
|
hexmask.long.word 0x00 16.--28. 1. " VIDFIRVINC ,Vertical increment of the up-/down-sampling filter"
|
|
hexmask.long.word 0x00 0.--12. 1. " VIDFIRHINC ,Horizontal increment of the up-/down-sampling filter"
|
|
line.long 0x04 "DISPC_VID0_FIFO_PICTURE_SIZE,Size Of The Video Picture Associated With Video Layer"
|
|
hexmask.long.word 0x04 16.--26. 1. " VIDORGSIZEY ,Number of lines of the video picture"
|
|
hexmask.long.word 0x04 0.--10. 1. " VIDORGSIZEX ,Number of pixels of the video picture"
|
|
line.long 0x08 "DISPC_VID0_ACCU0,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x08 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x08 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
line.long 0x0C "DISPC_VID0_ACCU1,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x0C 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x0C 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
group.long (0xBC+0x34)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x3C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x44)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x4C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x54)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x5C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x64)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x6C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x38)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x40)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x48)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x50)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x58)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x60)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x68)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x70)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x74)++0x13
|
|
line.long 0x00 "DISPC_VID0_CONV_COEF0,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient"
|
|
hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient"
|
|
line.long 0x04 "DISPC_VID0_CONV_COEF1,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x04 16.--26. 1. " GY ,GY Coefficient"
|
|
hexmask.long.word 0x04 0.--10. 1. " RCB ,RCB Coefficient"
|
|
line.long 0x08 "DISPC_VID0_CONV_COEF2,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x08 16.--26. 1. " GCB ,GCB Coefficient"
|
|
hexmask.long.word 0x08 0.--10. 1. " GCR ,GCR Coefficient"
|
|
line.long 0x0C "DISPC_VID0_CONV_COEF3,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x0C 16.--26. 1. " BCR ,BCR Coefficient"
|
|
hexmask.long.word 0x0C 0.--10. 1. " BY ,BY Coefficient"
|
|
line.long 0x10 "DISPC_VID0_CONV_COEF4,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x10 0.--10. 1. " BCB ,BCB Coefficient"
|
|
group.long (0x0+0x1E0)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V0,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1E4)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V1,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1E8)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V2,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1EC)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V3,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1F0)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V4,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1F4)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V5,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1F8)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V6,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1FC)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_V7,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x230)++0x3
|
|
line.long 0x00 "DISPC_VID0_PRELOAD,Video FIFO Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Video preload value"
|
|
group.long 0x14C++0x7 "VID 1"
|
|
line.long 0x00 "DISPC_VID1_BA0,Base Address Of The Video Buffer For Video Window"
|
|
line.long 0x04 "DISPC_VID1_BA1,Base Address Of The Video Buffer For Video Window"
|
|
group.long (0x14C+0x08)++0x3
|
|
line.long 0x00 "DISPC_VID1_POSITION,Position Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDPOSY ,Y position of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDPOSX ,X position of the Video window"
|
|
group.long (0x14C+0x0C)++0x3
|
|
line.long 0x00 "DISPC_VID1_SIZE,Size Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDSIZEY ,Number of lines of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDSIZEX ,Number of pixels of the Video window"
|
|
group.long (0x14C+0x10)++0x7
|
|
line.long 0x00 "DISPC_VID1_ATTRIBUTES,Video Attributes"
|
|
bitfld.long 0x00 24. " VIDSELFREFRESH ,Enables the self refresh of the video window (data from the system memory)" "Not fetch,Fetch"
|
|
textline " "
|
|
bitfld.long 0x00 23. " VIDARBITRATION ,Priority of the video pipeline" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VIDLINEBUFFERSPLIT ,Video vertical line buffer split" "Not split,Split"
|
|
textline " "
|
|
bitfld.long 0x00 21. " VIDVERTICALTAPS ,Video vertical resize tap number" "3,5"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIDDMAOPTIMIZATION ,Video optimization in case of (pixel for each 32-bit OCP)" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VIDFIFOPRELOAD ,Video preload value (H/W prefetches pixels up to)" "Preload,High threshold"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VIDROWREPEATENABLE ,Video Row Repeat" "Disabled,Fetched twice"
|
|
textline " "
|
|
bitfld.long 0x00 17. " VIDENDIANNESS ,Video Endianness" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIDCHANNELOUT ,Video Channel Out configuration" "LCD,24 bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " VIDBURSTSIZE ,Video DMA Burst Size" "4x32bit,8x32bit,16x32bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " VIDROTATION ,Video rotation flag" "No rotation,90 degrees,180 degrees,270 degrees"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VIDFULLRANGE ,VidFullRange" "Limited,Full"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIDREPLICATIONENABLE ,VidReplicationEnable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VIDCOLORCONVENABLE ,VidColorConvEnable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VIDVRESIZECONF ,Video Vertical Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VIDHRESIZECONF ,Video Horizontal Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VIDRESIZEENABLE ,Video Resize Enable" "Disabled,Horizontal,Vertical,Horizontal/Vertical"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " VIDFORMAT ,Video format" "Reserved,Reserved,Reserved,Reserved,RGB 12,ARGB 16,RGB 16,Reserved,RGB 24/32-bit,RGB 24/24-bit,YUV2 4:2:2 co-sited,UYVY 4:2:2 co-sited,ARGB 32,RGBA 32,RGBx 32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " VIDENABLE ,VIDEnable" "Disabled,Enabled"
|
|
line.long 0x04 "DISPC_VID1_FIFO_THRESHOLD,Video FIFO Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " VIDFIFOHIGHTHRESHOLD ,Video FIFO High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " VIDFIFOLOWTHRESHOLD ,Video FIFO Low Threshold"
|
|
rgroup.long (0x14C+0x18)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIFO_SIZE_STATUS,Video FIFO Size Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDFIFOSIZE ,Video FIFO Size"
|
|
group.long (0x14C+0x1C)++0x7
|
|
line.long 0x00 "DISPC_VID1_ROW_INC,Number Of Bytes To Increment At The End Of The Row"
|
|
line.long 0x04 "DISPC_VID1_PIXEL_INC,Number Of Bytes To Increment Between Two Pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " VIDPIXELINC ,Number of bytes to increment between two pixels"
|
|
group.long (0x14C+0x24)++0xF
|
|
line.long 0x00 "DISPC_VID1_FIR,Resize Factors For Horizontal And Vertical Up-/Down-sampling Of Video Window"
|
|
hexmask.long.word 0x00 16.--28. 1. " VIDFIRVINC ,Vertical increment of the up-/down-sampling filter"
|
|
hexmask.long.word 0x00 0.--12. 1. " VIDFIRHINC ,Horizontal increment of the up-/down-sampling filter"
|
|
line.long 0x04 "DISPC_VID1_FIFO_PICTURE_SIZE,Size Of The Video Picture Associated With Video Layer"
|
|
hexmask.long.word 0x04 16.--26. 1. " VIDORGSIZEY ,Number of lines of the video picture"
|
|
hexmask.long.word 0x04 0.--10. 1. " VIDORGSIZEX ,Number of pixels of the video picture"
|
|
line.long 0x08 "DISPC_VID1_ACCU0,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x08 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x08 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
line.long 0x0C "DISPC_VID1_ACCU1,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x0C 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x0C 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
group.long (0x14C+0x34)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x3C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x44)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x4C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x54)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x5C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x64)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x6C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x38)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x40)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x48)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x50)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x58)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x60)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x68)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x70)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x74)++0x13
|
|
line.long 0x00 "DISPC_VID1_CONV_COEF0,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient"
|
|
hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient"
|
|
line.long 0x04 "DISPC_VID1_CONV_COEF1,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x04 16.--26. 1. " GY ,GY Coefficient"
|
|
hexmask.long.word 0x04 0.--10. 1. " RCB ,RCB Coefficient"
|
|
line.long 0x08 "DISPC_VID1_CONV_COEF2,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x08 16.--26. 1. " GCB ,GCB Coefficient"
|
|
hexmask.long.word 0x08 0.--10. 1. " GCR ,GCR Coefficient"
|
|
line.long 0x0C "DISPC_VID1_CONV_COEF3,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x0C 16.--26. 1. " BCR ,BCR Coefficient"
|
|
hexmask.long.word 0x0C 0.--10. 1. " BY ,BY Coefficient"
|
|
line.long 0x10 "DISPC_VID1_CONV_COEF4,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x10 0.--10. 1. " BCB ,BCB Coefficient"
|
|
group.long (0x20+0x1E0)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V0,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1E4)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V1,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1E8)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V2,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1EC)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V3,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1F0)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V4,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1F4)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V5,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1F8)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V6,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1FC)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V7,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x4+0x230)++0x3
|
|
line.long 0x00 "DISPC_VID1_PRELOAD,Video FIFO Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Video preload value"
|
|
width 0xb
|
|
tree.end
|
|
tree "RFBI"
|
|
base ad:0x48050800
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "RFBI_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force idle,No idle,Smart-idle,?..."
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal auto-clock gating strategy" "Free running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DISPC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 9. " BUSYRFBIDATA ,Data are pending to be processed from internal FIFO" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " BUSY ,L4 Interface busy status bit" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "RFBI_CONTROL,Configuration Of The RFBI Module"
|
|
bitfld.long 0x00 8. " SMART_DMA_REQ ,Smart DMA request" "Asserted,Not asserted"
|
|
bitfld.long 0x00 7. " DISABLE_DMA_REQ ,Disable DMA request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " HIGHTHRESHOLD ,Defines the FIFO high threshold" "4 words,8 words,16 words,?..."
|
|
bitfld.long 0x00 4. " ITE ,Internal Trigger" "H/W wait,User set"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CONFIGSELECT ,Select the CS and configuration" "No CS,CS0,CS1,CS0/CS1"
|
|
bitfld.long 0x00 1. " BYPASSMODE ,Bypass Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Enable/Disable flag" "Disabled,Enabled"
|
|
line.long 0x04 "RFBI_PIXEL_CNT,RFBI Pixel Count Value Configuration Register"
|
|
line.long 0x08 "RFBI_LINE_NUMBER,Number Of Lines To Synchronize The Beginning Of The Transfer"
|
|
hexmask.long.word 0x08 0.--10. 1. " LINENUMBER ,Programmable line number"
|
|
wgroup.long 0x4C++0xB
|
|
line.long 0x00 "RFBI_CMD,RFBI Command Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMD ,Command value"
|
|
line.long 0x04 "RFBI_PARAM,RFBI Parameter Configuration Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PARAM ,Param value"
|
|
line.long 0x08 "RFBI_DATA,RFBI Data Configuration Register"
|
|
group.long 0x58++0x7
|
|
line.long 0x00 "RFBI_READ,RFBI Read Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " READ ,Read value"
|
|
line.long 0x04 "RFBI_STATUS,RFBI Status Configuration Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " STATUS ,Status value"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RFBI_CONFIG0,RFBI Module Configuration Register"
|
|
bitfld.long 0x00 21. " HSYNCPOLARITY ,HSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSPOLARITY ,CS Polarity" "Low,High"
|
|
bitfld.long 0x00 18. " WEPOLARITY ,WE Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " REPOLARITY ,RE Polarity" "Low,High"
|
|
bitfld.long 0x00 16. " A0POLARITY ,A0 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " UNUSEDBITS ,State of unused bits" "Low,High,Unchanged,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " CYCLEFORMAT ,Cycle format" "1 cycle/1 pixel,2 cycles/1 pixel,3 cycles/1 pixel,3 cycles/2 pixels"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L4FORMAT ,L4 Write Access format" "1 pixel,Reserved,2 pixels 1st at[15:0],2 pixels 1st at[31:16]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " DATA_TYPE ,Data type from the display controller and L4" "12-bit,16-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEGRANULARITY ,Multiplies signal timing latencies by two" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TRIGGERMODE ,Trigger Mode" "ITE bit mode,Tearing effect signal,RFB_TE_VSYNC/RFB_HSYNC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PARALLEL_MODE ,Parallel Mode" "8-bit,9-bit,12-bit,16-bit"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RFBI_CONFIG1,RFBI Module Configuration Register"
|
|
bitfld.long 0x00 21. " HSYNCPOLARITY ,HSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSPOLARITY ,CS Polarity" "Low,High"
|
|
bitfld.long 0x00 18. " WEPOLARITY ,WE Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " REPOLARITY ,RE Polarity" "Low,High"
|
|
bitfld.long 0x00 16. " A0POLARITY ,A0 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " UNUSEDBITS ,State of unused bits" "Low,High,Unchanged,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " CYCLEFORMAT ,Cycle format" "1 cycle/1 pixel,2 cycles/1 pixel,3 cycles/1 pixel,3 cycles/2 pixels"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L4FORMAT ,L4 Write Access format" "1 pixel,Reserved,2 pixels 1st at[15:0],2 pixels 1st at[31:16]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " DATA_TYPE ,Data type from the display controller and L4" "12-bit,16-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEGRANULARITY ,Multiplies signal timing latencies by two" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TRIGGERMODE ,Trigger Mode" "ITE bit mode,Tearing effect signal,RFB_TE_VSYNC/RFB_HSYNC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PARALLEL_MODE ,Parallel Mode" "8-bit,9-bit,12-bit,16-bit"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RFBI_ONOFF_TIME0,RFBI Timing Control Register"
|
|
hexmask.long.byte 0x00 24.--29. 1. " REOFFTIME ,Read Enable deassertion time from start access time"
|
|
bitfld.long 0x00 20.--23. " REONTIME ,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 14.--19. 1. " WEOFFTIME ,Write Enable deassertion time from start access time"
|
|
bitfld.long 0x00 10.--13. " WEONTIME ,Write Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--9. 1. " CSOFFTIME ,CS deassertion time from start access time"
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "RFBI_ONOFF_TIME1,RFBI Timing Control Register"
|
|
hexmask.long.byte 0x00 24.--29. 1. " REOFFTIME ,Read Enable deassertion time from start access time"
|
|
bitfld.long 0x00 20.--23. " REONTIME ,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 14.--19. 1. " WEOFFTIME ,Write Enable deassertion time from start access time"
|
|
bitfld.long 0x00 10.--13. " WEONTIME ,Write Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--9. 1. " CSOFFTIME ,CS deassertion time from start access time"
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RFBI_CYCLE_TIME0,RFBI Timing Configuration Register"
|
|
hexmask.long.byte 0x00 22.--27. 1. " ACCESSTIME ,Access Time"
|
|
bitfld.long 0x00 21. " WRENABLE ,Write to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WWENABLE ,Write to Write Pulse Width Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " RRENABLE ,Read to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWENABLE ,Read to Write Pulse Width Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " CSPULSEWIDTH ,CS Pulse Width"
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--11. 1. " RECYCLETIME ,RE Cycle Time"
|
|
hexmask.long.byte 0x00 0.--5. 1. " WECYCLETIME ,WE Cycle Time"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RFBI_CYCLE_TIME1,RFBI Timing Configuration Register"
|
|
hexmask.long.byte 0x00 22.--27. 1. " ACCESSTIME ,Access Time"
|
|
bitfld.long 0x00 21. " WRENABLE ,Write to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WWENABLE ,Write to Write Pulse Width Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " RRENABLE ,Read to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWENABLE ,Read to Write Pulse Width Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " CSPULSEWIDTH ,CS Pulse Width"
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--11. 1. " RECYCLETIME ,RE Cycle Time"
|
|
hexmask.long.byte 0x00 0.--5. 1. " WECYCLETIME ,WE Cycle Time"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE1_0,RFBI Data Format For 1st Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE1_1,RFBI Data Format For 1st Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE2_0,RFBI Data Format For 2nd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE2_1,RFBI Data Format For 2nd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE3_0,RFBI Data Format For 3rd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE3_1,RFBI Data Format For 3rd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "RFBI_VSYNC_WIDTH,RFBI VSYNC Minimum Pulse Width Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MINVSYNCPULSEWIDTH ,Programmable min VSYNC pulse width"
|
|
line.long 0x04 "RFBI_HSYNC_WIDTH,RFBI HSYNC Minimum Pulse Width Configuration Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MINHSYNCPULSEWIDTH ,Programmable min HSYNC pulse width"
|
|
width 0xb
|
|
tree.end
|
|
tree "VENC"
|
|
base ad:0x48050C00
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width 18.
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rgroup.long 0x04++0x3
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line.long 0x00 "VENC_STATUS,VENC Status Register"
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bitfld.long 0x00 4. " CCE ,Closed Caption Status for Even Field" "Not encoded,Encoded"
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bitfld.long 0x00 3. " CCO ,Closed Caption Status for Odd Field" "Not encoded,Encoded"
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textline " "
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bitfld.long 0x00 0.--2. " FSQ ,Field Sequence ID" "ODD,EVEN,?..."
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group.long 0x08++0x3
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line.long 0x00 "VENC_F_CONTROL,Input Video Source And Format Configuration Register"
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bitfld.long 0x00 8. " RESET ,RESET the encoder" "No effect,Reset"
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bitfld.long 0x00 6.--7. " SVDS ,Select Video Data Source" "External video source,Internal color BAR,Background color,?..."
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textline " "
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bitfld.long 0x00 5. " RGBF ,RGB/YCrCb input coding range" "0-255,16-235"
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bitfld.long 0x00 2.--4. " BCOLOR ,Background color select" "Black,Blue,Red,Magenta,Green,Cyan,Yellow,White"
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textline " "
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bitfld.long 0x00 0.--1. " FMT ,Video input data stream format and timing" "24-bit 4:4:4 RGB,24-bit 4:4:4,16-bit 4:2:2,8-bit ITU-R 656 4:2:2"
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group.long 0x10++0x7
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line.long 0x00 "VENC_VIDOUT_CTRL,Encoder Output Clock"
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bitfld.long 0x00 0. " 27_54 ,Encoder output clock" "54MHz 4xoversampling,27MHz 2xoversampling"
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line.long 0x04 "VENC_SYNC_CTRL,Sync Control Register"
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bitfld.long 0x04 15. " FREE ,Free running" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 14. " ESAV ,Enable to detect F and V bits" "EAV/SAV,Only EAV"
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textline " "
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bitfld.long 0x04 13. " IGNP ,Ignore protection bits in ITU-R 656 input mode" "Not ignored,Ignored"
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textline " "
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bitfld.long 0x04 12. " NBLNKS ,Blank shaping" "Enabled,Disabled"
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textline " "
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bitfld.long 0x04 10.--11. " VBLKM ,Vertical blanking mode" "Internal default,Internal default/programmable,?..."
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textline " "
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bitfld.long 0x04 8.--9. " HBLKM ,Horizontal blanking mode" "Internal default,Internal programmable,External,?..."
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textline " "
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bitfld.long 0x04 6. " FID_POL ,FID output polarity" "ODD=0/EVEN=1,ODD=1/EVEN=0"
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width 24.
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group.long 0x1C++0x2B
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line.long 0x00 "VENC_LLEN,VENC_LLEN Control Register"
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hexmask.long.word 0x00 0.--10. 1. " LLEN ,Line length or total number of pixels in a scan line"
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line.long 0x04 "VENC_FLENS,VENC_FLENS Control Register"
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hexmask.long.word 0x04 0.--10. 1. " FLENS ,The frame length or total number of lines in a frame"
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line.long 0x08 "VENC_HFLTR_CTRL,VENC_HFLTR_CTRL Control Register"
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bitfld.long 0x08 1.--2. " CINTP ,Chrominance interpolation filter control" "Enabled,1st sec bypassed,2nd sec bypassed,1st/2nd sec bypassed"
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bitfld.long 0x08 0. " YINTP ,Luminance interpolation filter control" "Enabled,Bypassed"
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line.long 0x0C "VENC_CC_CARR_WSS_CARR,Frequency Code Control"
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hexmask.long.word 0x0C 16.--31. 1. " FWSS ,Wide screen signaling run-in code frequency control"
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hexmask.long.word 0x0C 0.--15. 1. " FCC ,Close caption run-in code frequency control"
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line.long 0x10 "VENC_C_PHASE,VENC_C_PHASE Control Register"
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hexmask.long.byte 0x10 0.--7. 1. " CPHS ,Phase of the encoded video color subcarrier"
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line.long 0x14 "VENC_GAIN_U,Gain Control For Cb Signal"
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hexmask.long.word 0x14 0.--8. 1. " GU ,Gain control for Cb signal"
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line.long 0x18 "VENC_GAIN_V,Gain Control Of Cr Signal"
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hexmask.long.word 0x18 0.--8. 1. " GV ,Gain control of Cr signal"
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line.long 0x1C "VENC_GAIN_Y,Gain Control Of Y Signal"
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hexmask.long.word 0x1C 0.--8. 1. " GY ,Gain control of Y signal"
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line.long 0x20 "VENC_BLACK_LEVEL,Video Encoder BLACK LEVEL"
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hexmask.long.byte 0x20 0.--6. 1. " BLACK ,Black level setting"
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line.long 0x24 "VENC_BLANK_LEVEL,Video Encoder BLANK LEVEL"
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hexmask.long.byte 0x24 0.--6. 1. " BLANK ,Blank level setting"
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line.long 0x28 "VENC_X_COLOR,Cross-Colour Control Register"
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bitfld.long 0x28 6. " XCE ,Cross color reduction enable for composite video output" "Disabled,Enabled"
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bitfld.long 0x28 3.--4. " XCBW ,Cross color reduction filter selection" "Notch 32.8%,Notch 26.5%,Notch 30.0%,Notch 29.2%"
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textline " "
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bitfld.long 0x28 0.--2. " LCD ,chroma channel delay compensation" "0,0.5 pixel,1.0 pixel,1.5 pixel,-2.0 pixel,-1.5 pixel,-1.0 pixel,-0.5 pixel"
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if (((d.l((ad:0x48050C00+0x4C)))&0x80)==0x80)
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;VENC_BSTAMP_WSS_DATA[7] SQP = Square-pixel sampling rate
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group.long 0x48++0x3
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line.long 0x00 "VENC_M_CONTROL,VENC_M Control Register"
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bitfld.long 0x00 7. " PALI ,PAL I enable" "Normal,Enabled"
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bitfld.long 0x00 6. " PALN ,PAL N enable" "Normal,Enabled"
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textline " "
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bitfld.long 0x00 5. " PALPHS ,PAL switch phase setting" "Nominal,Inverted"
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bitfld.long 0x00 2.--4. " CBW ,Chrominance lowpass filter bandwidth control" "-6db 21.8%,-6db 19.8%,-6db 18.0%,Reserved,Reserved,-6db 23.7%,-6db 26.8%,Filter bypass"
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textline " "
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bitfld.long 0x00 1. " PAL ,Phase alternation line encoding selection" "Disabled,Enabled"
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bitfld.long 0x00 0. " FFRQ ,number of horizontal pixels displayed per scan line" "944,780"
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else
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group.long 0x48++0x3
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line.long 0x00 " VENC_M_CONTROL,VENC_M Control Register"
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bitfld.long 0x00 7. " PALI ,PAL I enable" "Normal,Enabled"
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bitfld.long 0x00 6. " PALN ,PAL N enable" "Normal,Enabled"
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textline " "
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bitfld.long 0x00 5. " PALPHS ,PAL switch phase setting" "Nominal,Inverted"
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bitfld.long 0x00 2.--4. " CBW ,Chrominance lowpass filter bandwidth control" "-6db 21.8%,-6db 19.8%,-6db 18.0%,Reserved,Reserved,-6db 23.7%,-6db 26.8%,Filter bypass"
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textline " "
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bitfld.long 0x00 1. " PAL ,Phase alternation line encoding selection" "Disabled,Enabled"
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bitfld.long 0x00 0. " FFRQ ,number of horizontal pixels displayed per scan line" "864,858"
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endif
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group.long 0x4C++0x3F
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line.long 0x00 "VENC_BSTAMP_WSS_DATA,VENC BSTAMP and WSS_DATA"
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hexmask.long.tbyte 0x00 8.--27. 1. " WSS_DAT ,Wide Screen Signaling data"
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bitfld.long 0x00 7. " SQP ,Square-pixel sampling rate" "ITU-R 601,Square-pixel"
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textline " "
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hexmask.long.byte 0x00 0.--6. 1. " BSTAP ,Setting of amplitude of color burst"
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line.long 0x04 "VENC_S_CARR,Color Subcarrier Frequency Registers"
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line.long 0x08 "VENC_LINE21,VENC LINE 21 Register"
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hexmask.long.word 0x08 16.--31. 1. " L21E ,The two bytes of the closed caption data in the even field"
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hexmask.long.word 0x08 0.--15. 1. " L21O ,The two bytes of the closed caption data in the odd field"
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line.long 0x0C "VENC_LN_SEL,VENC_LN_SEL Register"
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hexmask.long.word 0x0C 16.--25. 1. " LN21_RUNIN ,The two bytes of the closed caption runin code position from the HSYNC"
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hexmask.long.byte 0x0C 0.--4. 1. " SLINE ,Selects the line where closed caption or extended service data are encoded"
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line.long 0x10 "VENC_L21_WC_CTL,VENC L21 & WC_CTL Registers"
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bitfld.long 0x10 15. " INV ,WSS inverter" "No effect,Inverted"
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bitfld.long 0x10 13.--14. " EVEN_ODD_EN ,WSS encoding control" "Off,ODD,EVEN,ODD/EVEN"
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textline " "
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hexmask.long.byte 0x10 8.--12. 1. " LINE ,Selects the line where WSS data are encoded"
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bitfld.long 0x10 0.--1. " L21EN ,Line21 closed caption encoding according to the mode" "Off,ODD,EVEN,ODD/EVEN"
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line.long 0x14 "VENC_HTRIGGER_VTRIGGER,VENC HTRIGGER and VTRIGGER"
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hexmask.long.word 0x14 16.--25. 1. " VTRIG ,Vertical trigger reference for VSYNC"
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hexmask.long.word 0x14 0.--10. 1. " HTRIG ,Horizontal trigger phase"
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line.long 0x18 "VENC_SAVID_EAVID,VENC SAVID and EAVID"
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hexmask.long.word 0x18 16.--26. 1. " EAVID ,End of active video"
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hexmask.long.word 0x18 0.--10. 1. " SAVID ,Start of active video"
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line.long 0x1C "VENC_FLEN_FAL,VENC FLEN and FAL"
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hexmask.long.word 0x1C 16.--24. 1. " FAL ,First Active Line of Field"
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hexmask.long.word 0x1C 0.--9. 1. " FLEN ,Field length"
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line.long 0x20 "VENC_LAL_PHASE_RESET,VENC LAL and PHASE_RESET"
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bitfld.long 0x20 17.--18. " PRES ,Phase reset mode" "No reset,Reset every two lines,Reset every eight fields,Reset every four fields"
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bitfld.long 0x20 16. " SBLANK ,Data output enable" "Disabled,Enabled"
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textline " "
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hexmask.long.word 0x20 0.--8. 1. " LAL ,Last Active Line of Field"
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width 35.
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line.long 0x24 "VENC_HS_INT_START_STOP_X,HSYNC Internal Start/Stop Pixel Value"
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hexmask.long.word 0x24 16.--25. 1. " HS_INT_STOP_X ,HSYNC internal stop"
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textline " "
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hexmask.long.word 0x24 0.--9. 1. " HS_INT_START_X ,HSYNC internal start"
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line.long 0x28 "VENC_HS_EXT_START_STOP_X,HSYNC External Start/Stop Pixel Value"
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hexmask.long.word 0x28 16.--25. 1. " HS_EXT_STOP_X ,HSYNC external stop"
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textline " "
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hexmask.long.word 0x28 0.--9. 1. " HS_EXT_START_X ,HSYNC external start"
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line.long 0x2C "VENC_HS_EXT_START_STOP_X,VSYNC Internal Start Pixel Value"
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hexmask.long.word 0x2C 16.--25. 1. " VS_INT_START_X ,VSYNC internal start"
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line.long 0x30 "VENC_VS_INT_STOP_X_VS_INT_START_Y,VSYNC Internal Start/Stop Pixel Value"
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hexmask.long.word 0x30 16.--25. 1. " VS_INT_START_Y ,VSYNC internal start"
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textline " "
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hexmask.long.word 0x30 0.--9. 1. " VS_INT_STOP_X ,VSYNC internal stop"
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line.long 0x34 "VENC_VS_INT_STOP_Y_VS_EXT_START_X,VSYNC External Start/Stop Pixel Value"
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hexmask.long.word 0x34 16.--25. 1. " VS_EXT_START_X ,VSYNC external start"
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textline " "
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hexmask.long.word 0x34 0.--9. 1. " VS_INT_STOP_Y ,VSYNC external stop"
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line.long 0x38 "VENC_VS_EXT_STOP_X_VS_EXT_START_Y,VSYNC External Start/Stop Line Value"
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hexmask.long.word 0x38 16.--25. 1. " VS_EXT_START_Y ,VSYNC external start"
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textline " "
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hexmask.long.word 0x38 0.--9. 1. " VS_EXT_STOP_X ,VSYNC external stop"
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line.long 0x3C "VENC_VS_EXT_STOP_Y,VSYNC External Start/Stop Line Value"
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hexmask.long.word 0x3C 0.--9. 1. " VS_EXT_STOP_Y ,VSYNC external stop"
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group.long 0x90++0x7
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line.long 0x00 "VENC_AVID_START_STOP_X,VSYNC External Start/Stop Line Value"
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hexmask.long.word 0x00 16.--25. 1. " AVID_STOP_X ,AVID stop pixel value"
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textline " "
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hexmask.long.word 0x00 0.--9. 1. " AVID_START_X ,AVID start pixel value"
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line.long 0x04 "VENC_AVID_START_STOP_Y,VSYNC External Start/Stop Line Value"
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hexmask.long.word 0x04 16.--25. 1. " AVID_STOP_Y ,AVID stop"
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textline " "
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hexmask.long.word 0x04 0.--9. 1. " AVID_START_Y ,AVID start"
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width 38.
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group.long 0xA0++0xB
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line.long 0x00 "VENC_FID_INT_START_X_FID_INT_START_Y,FID Internal Start Line/Pixel Value"
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hexmask.long.word 0x00 16.--25. 1. " FID_INT_START_Y ,FID internal stop"
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textline " "
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hexmask.long.word 0x00 0.--9. 1. " FID_INT_START_X ,FID internal start"
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line.long 0x04 "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,FID External Start Pixel/Internal Offset Line Value"
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hexmask.long.word 0x04 16.--25. 1. " FID_EXT_START_X ,FID external start"
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textline " "
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hexmask.long.word 0x04 0.--9. 1. " FID_INT_OFFSET_Y ,FID internal offset"
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line.long 0x08 "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,FID External Start/External Offset Line Value"
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hexmask.long.word 0x08 16.--25. 1. " FID_EXT_OFFSET_Y ,FID external offset"
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textline " "
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hexmask.long.word 0x08 0.--9. 1. " FID_EXT_START_Y ,FID external start"
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group.long 0xB0++0xB
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line.long 0x00 "VENC_TVDETGP_INT_START_STOP_X,TV Detection Start And Stop Pixel Values"
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hexmask.long.word 0x00 16.--25. 1. " TVDETGP_INT_STOP_X ,TVDETGP internal stop"
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textline " "
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hexmask.long.word 0x00 0.--9. 1. " TVDETGP_INT_START_X ,TVDETGP internal start"
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line.long 0x04 "VENC_TVDETGP_INT_START_STOP_Y,TV Detection Start And Stop Line Values"
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hexmask.long.word 0x04 16.--25. 1. " TVDETGP_INT_STOP_Y ,TVDETGP internal stop"
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textline " "
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hexmask.long.word 0x04 0.--9. 1. " TVDETGP_INT_START_Y ,TVDETGP internal start"
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width 21.
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line.long 0x08 "VENC_GEN_CTRL,TVDETGP Enable And SYNC_POLARITY And UVPHASE_POL"
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bitfld.long 0x08 26. " MS ,UVPHASE_POL MS mode UV phase" "CbCr,CrCb"
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bitfld.long 0x08 25. " 656 ,UVPHASE_POL 656 input mode UV phase" "CbCr,CrCb"
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textline " "
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bitfld.long 0x08 24. " CBAR ,UVPHASE_POL CBAR mode UV phase" "CbCr,CrCb"
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bitfld.long 0x08 23. " HIP ,HSYNC internal polarity" "Low,High"
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textline " "
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bitfld.long 0x08 22. " VIP ,VSYNC internal polarity" "Low,High"
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bitfld.long 0x08 21. " HEP ,HSYNC external polarity" "Low,High"
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textline " "
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bitfld.long 0x08 20. " VEP ,VSYNC external polarity" "Low,High"
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bitfld.long 0x08 19. " AVIDP ,AVID polarity" "Low,High"
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textline " "
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bitfld.long 0x08 18. " FIP ,FID internal polarity" "Low,High"
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bitfld.long 0x08 17. " FEP ,FID external polarity" "Low,High"
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textline " "
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bitfld.long 0x08 16. " TVDP ,TVDETGP polarity" "Low,High"
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bitfld.long 0x08 0. " EN ,TVDETGP generation enable" "Disabled,Enabled"
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group.long 0xC4++0x7
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line.long 0x00 "VENC_OUTPUT_CONTROL,Output channel control register"
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hexmask.long.word 0x00 16.--25. 1. " LUMA_TEST ,DAC 1 input value"
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textline " "
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bitfld.long 0x00 7. " CHROMA_SOURCE ,Source of chroma video data in test mode" "Internal register OUTPUT_TEST[25:16],Disp. ctrl. port G[1:0] B[7:0]"
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textline " "
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bitfld.long 0x00 6. " COMPOSITE_SOURCE ,Source of composite video data in test mode" "Internal register OUTPUT_TEST[9:0],Disp. ctrl. video port G[1:0] B[7:0]"
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textline " "
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bitfld.long 0x00 5. " LUMA_SOURCE ,Source of luminance video data in test mode" "Internal register OUTPUT_TEST[25:16],Disp. ctrl. video port G[1:0] B[7:0]"
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textline " "
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bitfld.long 0x00 4. " TEST_MODE ,DACs Test Enable" "Normal,Test"
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textline " "
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bitfld.long 0x00 3. " VIDEO_INVERT ,Video output polarity" "Inverted,Normal polarity"
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textline " "
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bitfld.long 0x00 2. " CHROMA_ENABLE ,CHROMA_ENABLE Enable the Chrominance output channel" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " COMPOSITE_ENABLE ,Enable the Composite output channel" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " LUMA_ENABLE ,Enable the Luminance output channel" "Disabled,Enabled"
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line.long 0x04 "VENC_OUTPUT_TEST,Test values for the Luma/Composite Video DAC1 and the Chroma Video DAC2"
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hexmask.long.word 0x04 16.--25. 1. " CHROMA_TEST ,DAC 2 input value"
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hexmask.long.word 0x04 0.--9. 1. " COMPOSITE_TEST ,DAC 1 input value"
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width 0xb
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|
tree.end
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tree "DSI"
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tree "Protocol Engine Registers"
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base ad:0x4804FC00
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width 15.
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group.long 0x10++0x3
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line.long 0x00 "DSI_SYSCONFIG,System Configuration Register"
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bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (Interface/Functional clocks)" "Off,Maintained/Off,Off/Maintained,Maintained"
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bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
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textline " "
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bitfld.long 0x00 2. " ENWAKEUP ,Wakeup enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " SOFT_RESET ,Software reset" "Normal,Reset"
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|
textline " "
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bitfld.long 0x00 0. " AUTO_IDLE ,Internal intrface clock gating strategy" "Free running,Applied"
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rgroup.long 0x14++0x3
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line.long 0x00 "DSI_SYSSTATUS,System Status Register"
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bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring" "On going,Reset"
|
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group.long 0x18++0x7
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line.long 0x00 "DSI_IRQSTATUS,Interrupt Status Register"
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eventfld.long 0x00 20. " TA_TO_IRQ ,Turn-around Time out" "Not pending,Pending"
|
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eventfld.long 0x00 19. " LDO_POWER_GOOD_IRQ ,Transition of the status signal LDOPWRGOOD" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 18. " SYNC_LOST_IRQ ,Synchronization with Video port is lost" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " ACK_TRIGGER_IRQ ,Acknowledge Trigger" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " TE_TRIGGER_IRQ ,Tearing Effect Trigger" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " LP_RX_TO_IRQ ,Interrupt for Low Power Rx Time out" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 14. " HS_TX_TO_IRQ ,Interrupt for High Speed Tx Time out" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " COMPLEXIO_ERR_IRQ ,Error signaling from complex I/O" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " PLL_RECAL_IRQ ,PLL recalibration event" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " PLL_UNLOCK_IRQ ,PLL un-lock event" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PLL_LOCK_IRQ ,PLL lock event" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAKEUP_IRQ ,Wakeup" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " VIRTUAL_CHANNEL3_IRQ ,Virtual channel #3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 2. " VIRTUAL_CHANNEL2_IRQ ,Virtual channel #2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " VIRTUAL_CHANNEL1_IRQ ,Virtual channel #1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " VIRTUAL_CHANNEL0_IRQ ,Virtual channel #0" "Not pending,Pending"
|
|
line.long 0x04 "DSI_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 20. " TA_TO_IRQ_EN ,Turn-around Time out" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " LDO_POWER_GOOD_IRQ_EN ,Transition of the status signal LDOPWRGOOD" "Masked,Enabled"
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textline " "
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bitfld.long 0x04 18. " SYNC_LOST_IRQ_EN ,Synchronization with Video port is lost" "Masked,Enabled"
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bitfld.long 0x04 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge Trigger" "Masked,Enabled"
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textline " "
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bitfld.long 0x04 16. " TE_TRIGGER_IRQ_EN ,Tearing Effect Trigger" "Masked,Enabled"
|
|
bitfld.long 0x04 15. " LP_RX_TO_IRQ_EN ,Interrupt for Low Power Rx Time out" "Masked,Enabled"
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|
textline " "
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bitfld.long 0x04 14. " HS_TX_TO_IRQ_EN ,Interrupt for High Speed Tx Time out" "Masked,Enabled"
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bitfld.long 0x04 9. " PLL_RECAL_IRQ_EN ,PLL recalibration event" "Masked,Enabled"
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textline " "
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bitfld.long 0x04 8. " PLL_UNLOCK_IRQ_EN ,PLL un-lock event" "Masked,Enabled"
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|
bitfld.long 0x04 7. " PLL_LOCK_IRQ_EN ,PLL lock event" "Masked,Enabled"
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textline " "
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bitfld.long 0x04 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization" "Masked,Enabled"
|
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bitfld.long 0x04 4. " WAKEUP_IRQ_EN ,Wakeup" "Masked,Enabled"
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group.long 0x40++0x3
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line.long 0x00 "DSI_CTRL,Global Control Register"
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bitfld.long 0x00 23. " HSA_BLANKING_MODE ,Blanking mode" "Blanking period/LPS,Long blanking packets only"
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textline " "
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bitfld.long 0x00 22. " HBP_BLANKING_MODE ,Blanking mode" "Blanking period/LPS,Long blanking packets only"
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textline " "
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bitfld.long 0x00 21. " HFP_BLANKING_MODE ,Blanking mode" "Blanking period/LPS,Long blanking packets only"
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textline " "
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bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode" "ULPS,Long blanking packets"
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textline " "
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bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse" "Disabled,Enabled"
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bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse" "Disabled,Enabled"
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bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode" "Synchronized,Immediate"
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bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port" "No line,1 line,2 line,?..."
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textline " "
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bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity" "Active low,Active high"
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bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity" "Active low,Active high"
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textline " "
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bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity" "Active low,Active high"
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bitfld.long 0x00 8. " VP_CLK_POL ,VP clock polarity" "Falling edge,Raising edge"
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textline " "
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bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus" "16-bits,18-bits,24-bits,?..."
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bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral" "Completed,Requested"
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textline " "
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bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio" "VP_CLK/2,VP_CLK/3"
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bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,Arbitration scheme for granting the virtual channel request" "Round-robin,Sequential"
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textline " "
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bitfld.long 0x00 2. " ECC_RX_EN ,Enables the Error Correction Code check for the received header" "Disabled,Enabled"
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bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " IF_EN ,Enables the module" "Disabled,Enabled"
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width 25.
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group.long 0x48++0x33
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line.long 0x00 "DSI_COMPLEXIO_CFG1,Complexio Configuration Register"
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bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow registers" "Reset,Set"
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textline " "
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bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring" "On going,Reset"
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textline " "
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bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O" "Off,On,Ultra low power,?..."
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textline " "
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bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O" "Off,On,Ultra low power,?..."
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textline " "
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bitfld.long 0x00 21. " LDO_POWER_GOOD_STATE ,Indicates the state of the signal LDOPWRGOOD" "Down,Up"
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textline " "
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bitfld.long 0x00 20. " USE_LDO_EXTERNAL ,Select the external LDO for the DSIPHY" "Internal LDO,External LDO"
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textline " "
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bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2" "+/-,-/+"
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textline " "
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bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2" "Not used/connected,Lane 2 at position 1,Lane 2 at position 2,Lane 2 at position 3,?..."
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textline " "
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bitfld.long 0x00 7. " DATA1_POL ,+/- pin order of DATA lane 1" "+/-,-/+"
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textline " "
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bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1" "Reserved,Lane 1 at position 1,Lane 1 at position 2,Lane 1 at position 3,?..."
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textline " "
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bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of CLOCK lane" "+/-,-/+"
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textline " "
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bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane" "Reserved,Lane is at the position 1,Lane is at the position 2,Lane is at the position 3,?..."
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line.long 0x04 "DSI_COMPLEXIO_IRQSTATUS,Interrupt Status Register"
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eventfld.long 0x04 31. " ULPSACTIVENOT_ALL1_IRQ ,ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane #3" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane #3" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane #2" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane #2" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane #1" "Not pending,Pending"
|
|
textline " "
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eventfld.long 0x04 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane #1" "Not pending,Pending"
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|
textline " "
|
|
eventfld.long 0x04 17. " STATEULPS3_IRQ ,Lane #3 in Ultra Low Power State" "Not pending,Pending"
|
|
textline " "
|
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eventfld.long 0x04 16. " STATEULPS2_IRQ ,Lane #2 in Ultra Low Power State" "Not pending,Pending"
|
|
textline " "
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eventfld.long 0x04 15. " STATEULPS1_IRQ ,Lane #1 in Ultra Low Power State" "Not pending,Pending"
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textline " "
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eventfld.long 0x04 12. " ERRCONTROL3_IRQ ,Control error for lane #3" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 11. " ERRCONTROL2_IRQ ,Control error for lane #2" "Not pending,Pending"
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textline " "
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eventfld.long 0x04 10. " ERRCONTROL1_IRQ ,Control error for lane #1" "Not pending,Pending"
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|
textline " "
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eventfld.long 0x04 7. " ERRESC3_IRQ ,Escape entry error for lane #3" "Not pending,Pending"
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|
textline " "
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|
eventfld.long 0x04 6. " ERRESC2_IRQ ,Escape entry error for lane #2" "Not pending,Pending"
|
|
textline " "
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|
eventfld.long 0x04 5. " ERRESC1_IRQ ,Escape entry error for lane #1" "Not pending,Pending"
|
|
textline " "
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eventfld.long 0x04 2. " ERRSYNCESC3_IRQ ,Low power Data transmission synchronization error for lane #3" "Not pending,Pending"
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textline " "
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eventfld.long 0x04 1. " ERRSYNCESC2_IRQ ,Low power Data transmission synchronization error for lane #2" "Not pending,Pending"
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textline " "
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eventfld.long 0x04 0. " ERRSYNCESC1_IRQ ,Low power Data transmission synchronization error for lane #1" "Not pending,Pending"
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line.long 0x08 "DSI_COMPLEXIO_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x08 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high" "Masked,Enabled"
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|
textline " "
|
|
bitfld.long 0x08 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0" "Masked,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane #3" "Masked,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane #3" "Masked,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane #2" "Masked,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane #2" "Masked,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane #1" "Masked,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " STATEULPS3_IRQ_EN ,Lane #3 in Ultra Low Power State" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " STATEULPS2_IRQ_EN ,Lane #2 in Ultra Low Power State" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " STATEULPS1_IRQ_EN ,Lane #1 in Ultra Low Power State" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " ERRCONTROL3_IRQ_EN ,Control error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ERRCONTROL2_IRQ_EN ,Control error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " ERRCONTROL1_IRQ_EN ,Control error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ERRESC3_IRQ_EN ,Escape entry error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " ERRESC2_IRQ_EN ,Escape entry error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ERRESC1_IRQ_EN ,Escape entry error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ERRSYNCESC3_IRQ_EN ,Low power Data transmission synchronization error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ERRSYNCESC2_IRQ_EN ,Low power Data transmission synchronization error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ERRSYNCESC1_IRQ_EN ,Low power Data transmission synchronization error for lane #1" "Masked,Enabled"
|
|
width 16.
|
|
line.long 0x0C "DSI_CLK_CTRL,Clock Control Register"
|
|
bitfld.long 0x0C 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control module" "Off,On for PLL,On for PLL/HSDIVISER,On for PLL/HSDIVISER no clk"
|
|
textline " "
|
|
bitfld.long 0x0C 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module" "Off,On for PLL,On for PLL/HSDIVISER,On for PLL/HSDIVISER no clk"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " LP_RX_SYNCHRO_ENABLE ,DSI functional clock is higher or lower than 30 MHz" "<=30MHz,>30MHz"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " HS_MANUEL_STOP_CTRL ,In case HS_AUTO_STOP_ENABLE bit is set to 0" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " HS_AUTO_STOP_ENABLE ,Enables the automatic assertion/de-assertion of DSIStopClk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Indicates the size of LS NULL Packets" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " CIO_CLK_ICG ,Controls the signal for gating the L3_ICLK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--12. 1. " LP_CLK_DIVISOR ,Ratio to be used for the generation of the Low Power mode clock from DSI functional clock"
|
|
line.long 0x10 "DSI_TIMING1,DSI Protocol Engine Module Timers Control"
|
|
bitfld.long 0x10 31. " TA_TO ,Enables the turn-around timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 30. " TA_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x10 29. " TA_TO_X8 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x8"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " TA_TO_COUNTER ,Turn around counter"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x10 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x10 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x4"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--12. 1. " STOP_STATE_COUNTER_IO ,Stop state counter"
|
|
line.long 0x14 "DSI_TIMING2,DSI Protocol Engine Module Timers Control"
|
|
bitfld.long 0x14 31. " HS_TX_TO ,Enables the HS TX timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 30. " HS_TX_TO_X16 ,Multiplication factor for the number of TxByteClkHS clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x14 29. " HS_TX_TO_X8 ,Multiplication factor for the number of TxByteClkHS clock cycles" "x1,x8"
|
|
textline " "
|
|
hexmask.long.word 0x14 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter"
|
|
textline " "
|
|
bitfld.long 0x14 15. " LP_RX_TO ,Enables the LP RX timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " LP_RX_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " LP_RX_TO_X4 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x4"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter"
|
|
line.long 0x18 "DSI_VM_TIMING1,Video Mode Timing Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " HSA ,Horizontal Sync active period used in video mode"
|
|
textline " "
|
|
hexmask.long.word 0x18 12.--23. 1. " HFP ,Horizontal front porch used in video mode"
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--11. 1. " HBP ,Horizontal back porch used in video mode"
|
|
line.long 0x1C "DSI_VM_TIMING2,Video Mode Timing Register"
|
|
bitfld.long 0x1C 24.--27. " WINDOW_SYNC ,Number of TxByteClkHS clock cycles for the synchronization window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 16.--23. 1. " VSA ,vertical Sync active period used in video mode"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " VFP ,vertical front porch used in video mode"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " VBP ,vertical back porch used in video mode"
|
|
line.long 0x20 "DSI_VM_TIMING3,Video Mode Timing Register"
|
|
hexmask.long.word 0x20 16.--31. 1. " TL ,Defines the number of length of the line in video mode"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--15. 1. " VACT ,Defines the number of active lines used in video mode"
|
|
line.long 0x24 "DSI_CLK_TIMING,Clock Timing Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. " DDR_CLK_PRE ,Number of PPI Byte clock cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x24 0.--7. 1. " DDR_CLK_POST ,Number of PPI Byte clock cycles"
|
|
width 21.
|
|
line.long 0x28 "DSI_TX_FIFO_VC_SIZE,Corresponding Memory Entries Allocated For Each Virtual Channel"
|
|
bitfld.long 0x28 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x28 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3" "0,32,64,96,128,?..."
|
|
textline " "
|
|
bitfld.long 0x28 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x28 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2" "0,32,64,96,128,?..."
|
|
textline " "
|
|
bitfld.long 0x28 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x28 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1" "0,32,64,96,128,?..."
|
|
textline " "
|
|
bitfld.long 0x28 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x28 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0" "0,32,64,96,128,?..."
|
|
line.long 0x2C "DSI_RX_FIFO_VC_SIZE,Corresponding Memory Entries Allocated For Each Virtual Channel And The Addresses"
|
|
bitfld.long 0x2C 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x2C 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3" "0,32,64,96,128,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x2C 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2" "0,32,64,96,128,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x2C 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1" "0,32,64,96,128,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0" "0 x 33 bits,32 x 33 bits,64 x 33 bits,96 x 33 bits,128 x 33 bits,?..."
|
|
bitfld.long 0x2C 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0" "0,32,64,96,128,?..."
|
|
line.long 0x30 "DSI_COMPLEXIO_CFG2,Complexio Configuration Register"
|
|
bitfld.long 0x30 17. " LP_BUSY ,Still pending operations for VCs configured for LP mode" "Idle,Active"
|
|
bitfld.long 0x30 16. " HS_BUSY ,Still pending operations for VCs configured for HS mode" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x30 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane #3" "Not active,Active"
|
|
bitfld.long 0x30 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane #2" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x30 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane #1" "Not active,Active"
|
|
bitfld.long 0x30 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane #3" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x30 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane #2" "Not active,Active"
|
|
bitfld.long 0x30 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane #1" "Not active,Active"
|
|
width 25.
|
|
rgroup.long 0x7C++0x3
|
|
line.long 0x00 "DSI_RX_FIFO_VC_FULLNESS,Defines The Fullness Of Each Space Allocated For Each Virtual Channel"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DSI_VM_TIMING4,Video Mode Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HSA_HS_INTERLEAVING ,number of HS byte clock cycles during HSA"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HFP_HS_INTERLEAVING ,number of HS byte clock cycles during HFP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " HBP_HS_INTERLEAVING ,number of HS byte clock cycles during HBP"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "DSI_TX_FIFO_VC_EMPTINESS,Defines The Emptiness Of Each Space Allocated For Each Virtual Channel"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0"
|
|
width 20.
|
|
group.long 0x88++0xF
|
|
line.long 0x00 "DSI_VM_TIMING5,Video Mode Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HSA_LP_INTERLEAVING ,Number of bytes for Low Power command mode during HSA"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HFP_LP_INTERLEAVING ,Number of bytes for Low Power command mode during HFP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " HBP_LP_INTERLEAVING ,Number of bytes for Low Power command mode during HBP"
|
|
line.long 0x04 "DSI_VM_TIMING6,Video Mode Timing Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BL_HS_INTERLEAVING ,Number of TxByteClkHS clock cycles"
|
|
hexmask.long.word 0x04 0.--15. 1. " BL_LP_INTERLEAVING ,Maximum number of bytes for Low Power command"
|
|
line.long 0x08 "DSI_VM_TIMING7,Video Mode Timing Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Number of TxByteClkHS clock cycles necessary for entering to HS mode"
|
|
hexmask.long.word 0x08 0.--15. 1. " EXIT_HS_MODE_LATENCY ,Number of TxByteClkHS clock cycles necessary for exiting from HS mode"
|
|
line.long 0x0C "DSI_STOPCLK_TIMING,Number Of Functional Clock Cycles To Wait For TxByteClock To Stop/Start"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DSI_STOPCLK_LATENCY ,Clock gating latency from DSI Protocol engine to TxByteClkHS"
|
|
width 14.
|
|
group.long 0x100++0xB "Virtual Channel 0"
|
|
line.long 0x00 "DSI_VC0_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PP_BUSY ,Line buffer busy status" "Permitted,Not permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC0_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_SIZE ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC0_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x100+0xC)++0x3
|
|
line.long 0x00 "DSI_VC0_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x100+0x10)++0x3
|
|
line.long 0x00 "DSI_VC0_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x100+0x18)++0x7
|
|
line.long 0x00 "DSI_VC0_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC0_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 14.
|
|
group.long 0x120++0xB "Virtual Channel 1"
|
|
line.long 0x00 "DSI_VC1_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PP_BUSY ,Line buffer busy status" "Permitted,Not permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC1_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_SIZE ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC1_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x120+0xC)++0x3
|
|
line.long 0x00 "DSI_VC1_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "DSI_VC1_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x120+0x18)++0x7
|
|
line.long 0x00 "DSI_VC1_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC1_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 14.
|
|
group.long 0x140++0xB "Virtual Channel 2"
|
|
line.long 0x00 "DSI_VC2_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PP_BUSY ,Line buffer busy status" "Permitted,Not permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC2_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_SIZE ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC2_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x140+0xC)++0x3
|
|
line.long 0x00 "DSI_VC2_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x140+0x10)++0x3
|
|
line.long 0x00 "DSI_VC2_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x140+0x18)++0x7
|
|
line.long 0x00 "DSI_VC2_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC2_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 14.
|
|
group.long 0x160++0xB "Virtual Channel 3"
|
|
line.long 0x00 "DSI_VC3_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PP_BUSY ,Line buffer busy status" "Permitted,Not permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC3_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_SIZE ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC3_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x160+0xC)++0x3
|
|
line.long 0x00 "DSI_VC3_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x160+0x10)++0x3
|
|
line.long 0x00 "DSI_VC3_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x160+0x18)++0x7
|
|
line.long 0x00 "DSI_VC3_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC3_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Complex I/O Registers"
|
|
base ad:0x4804FE00
|
|
width 13.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "DSIPHY_CFG0,Configuration Register For HS Mode Timings"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THS_PREPARE ,THS-PREPARE timing parameter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " THS_PREPARE_THS_ZERO ,THS-PREPARE + THS-ZERO timing parameter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " THS_TRAIL ,THS-TRAIL timing parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " THS_EXIT ,Ths-exit timing parameter"
|
|
line.long 0x04 "DSIPHY_CFG1,Configuration Register For LP Mode And HS Mode Timings"
|
|
hexmask.long.byte 0x04 16.--22. 1. " TLPX_HALF ,(TLPX)/2 timing parameter in multiples of DDR clock frequency"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TCLK_TRAIL ,TCLK-TRAIL timing parameter in multiples of DDR clock frequency"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCLK_ZERO ,TCLK-ZERO timing parameter in multiples of DDR clock period"
|
|
line.long 0x08 "DSIPHY_CFG2,Sync Pattern And Reserved Bits"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TCLK_PREPARE ,TCLK-PREPARE timing parameter in multiples of DDR clock period"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DSIPHY_CFG5,Reset Done Bits"
|
|
bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK" "Normal,Reset"
|
|
bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK" "Normal,Reset"
|
|
bitfld.long 0x00 28. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1" "Normal,Reset"
|
|
bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2" "Normal,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "PLL Control Module Registers"
|
|
base ad:0x4804FF00
|
|
width 24.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "DSI_PLL_CONTROL,This Register Controls The PLL Reset/Power And Modes"
|
|
bitfld.long 0x00 4. " DSI_HSDIV_SYSRESET ,Force HSDIVIDER SYSRESET" "Controlled by FSM,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSI_PLL_SYSRESET ,Force ADPLLV2 SYSRESET" "Controlled by FSM,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DSI_PLL_HALTMODE ,Allow PLL to be halted if no activity" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSI_PLL_GATEMODE ,Allow PLL clock gating for poser saving" "On,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DSI_PLL_AUTOMODE ,Automatic update mode" "Manual,Automatic"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "DSI_PLL_STATUS,This Register Contains The Status Information"
|
|
bitfld.long 0x00 9. " DSI_BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER" "Switched,In use"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DSIPROTO_CLOCK_ACK ,Acknowledge for enable of DSI Protcol Engine clock" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DSS_CLOCK_ACK ,Acknowledge for enable of DSS clock" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSI_PLL_BYPASS ,DSI PLL Bypass status" "Not bypassing,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DSI_PLL_HIGHJITTER ,DSI PLL High Jitter status" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DSI_PLL_LIMP ,DSI PLL Limp status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSI_PLL_LOSSREF ,DSI PLL Reference Loss status" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DSI_PLL_RECAL ,DSI PLL re-calibration status" "Not required,Required"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSI_PLL_LOCK ,DSI PLL Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DSI_PLLCTRL_RESET_DONE ,DSI PLL Controller reset done status" "In progress,Completed"
|
|
group.long 0x08++0xB
|
|
line.long 0x00 "DSI_PLL_GO,This register contains the GO bit"
|
|
bitfld.long 0x00 0. " DSI_PLL_GO ,Request (re-)locking sequence of the PLL" "Not pending,Pending"
|
|
line.long 0x04 "DSI_PLL_CONFIGURATION1,Latched PLL And HSDIVDER Configuration Bits"
|
|
bitfld.long 0x04 23.--26. " DSIPROTO_CLOCK_DIV ,Divider value for DSI Protocol Engine clock source M4REG" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 19.--22. " DSS_CLOCK_DIV ,Divider value for DSS clock source M3REG" "0,1,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 8.--18. 1. " DSI_PLL_REGM ,M Divider for PLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 1.--7. 1. " DSI_PLL_REGN ,N Divider for PLL"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DSI_PLL_STOPMODE ,DSI PLL STOPMODE" "Not selected,Selected"
|
|
line.long 0x08 "DSI_PLL_CONFIGURATION2,Unlatched PLL And HSDIVDER Configuration Bits"
|
|
bitfld.long 0x08 20. " DSI_HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "Normal,Forced to bypass"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DSI_PROTO_CLOCK_PWDN ,Power down for DSI Protocol Engine clock source" "Active,Powered-down"
|
|
textline " "
|
|
bitfld.long 0x08 18. " DSI_PROTO_CLOCK_EN ,Enable for DSI Protocol Engine clock source" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " DSS_CLOCK_PWDN ,Power down for DSS clock source" "Active,Powered-down"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSS_CLOCK_EN ,Enable for DSS clock source" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DSI_BYPASSEN ,Selects DSS functional clock as CLKIN4DDR clock source" "PLL DCO,Force DSS functional clk"
|
|
textline " "
|
|
bitfld.long 0x08 14. " DSI_PHY_CLKINEN ,CLKIN4DDR clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DSI_PLL_REFEN ,PLL reference clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the PLL" "Not divided,/2"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DSI_PLL_CLKSEL ,Reference clock selection" "DSS2_ALWON_FCLK,Pixel Clock"
|
|
textline " "
|
|
bitfld.long 0x08 9.--10. " DSI_PLL_LOCKSEL ,Selects the lock criteria for the PLL" "Phase Lock,Frequency Lock,Spare,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8. " DSI_PLL_DRIFTGUARDEN ,DSI PLL DRIFTGUARDEN" "Only RECAL flag,Automatic recalibration"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSI_PLL_TIGHTPHASELOCK ,DSI PLL Phase Lock criteria" "Normal,Tightened"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSI_PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSI_PLL_PLLLPMODE ,Select the power / performance of the PLL" "Full/minimized,Reduced/increased"
|
|
textline " "
|
|
bitfld.long 0x08 1.--4. " DSI_PLL_FREQSEL ,PLL internal reference frequency range selection" "Reserved,Reserved,Reserved,0.75MHz-1.0MHz,1.0MHz-1.25MHz,1.25MHz-1.5MHz,1.5MHz-1.75MHz,1.75MHz-2.1MHz,Reserved,Reserved,Reserved,7.5MHz-10MHz,10MHz-12.5MHz,12.5MHz-15MHz,15MHz-17.5MHz,17.5MHz-21MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DSI_PLL_IDLE ,DSI PLL IDLE" "Not selected,Selected"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "Timers"
|
|
tree "GPT (General Purpose Timer)"
|
|
tree "GPTIMER1"
|
|
base ad:0x48318000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "TPIR,Timer Positive Increment Register"
|
|
line.long 0x04 "TNIR,GP Timer Negative Increment Register"
|
|
line.long 0x08 "TCVR,GP Timer Counter Value Register"
|
|
line.long 0x0c "TOCR,GP Timer Overflow Counter Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events"
|
|
line.long 0x10 "TOWR,GP Timer Overflow Wrapping Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER2"
|
|
base ad:0x49032000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "TPIR,Timer Positive Increment Register"
|
|
line.long 0x04 "TNIR,GP Timer Negative Increment Register"
|
|
line.long 0x08 "TCVR,GP Timer Counter Value Register"
|
|
line.long 0x0c "TOCR,GP Timer Overflow Counter Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events"
|
|
line.long 0x10 "TOWR,GP Timer Overflow Wrapping Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER3"
|
|
base ad:0x49034000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER4"
|
|
base ad:0x49036000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER5"
|
|
base ad:0x49038000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER6"
|
|
base ad:0x4903A000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER7"
|
|
base ad:0x4903C000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER8"
|
|
base ad:0x4903E000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER9"
|
|
base ad:0x49040000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER10"
|
|
base ad:0x48086000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "TPIR,Timer Positive Increment Register"
|
|
line.long 0x04 "TNIR,GP Timer Negative Increment Register"
|
|
line.long 0x08 "TCVR,GP Timer Counter Value Register"
|
|
line.long 0x0c "TOCR,GP Timer Overflow Counter Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events"
|
|
line.long 0x10 "TOWR,GP Timer Overflow Wrapping Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER11"
|
|
base ad:0x48088000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER12"
|
|
base ad:0x48304000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
tree "WDT1"
|
|
base ad:0x4830c000
|
|
width 14.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity selection " "Cut off,At least L4,At least timer,Both"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode selection" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable wakeup control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,L4 interconnect clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WISR,Watchdog Interrupt Event Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WIER,Watchdog Overflow Interrupt Control Register"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "WCLR,Watchdog Control Register"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "2,4,8,16,32,64,128,256"
|
|
line.long 0x04 "WCRR,Watchdog Counter Register"
|
|
line.long 0x08 "WLDR,Watchdog Load Register"
|
|
line.long 0x0c "WTGR,Watchdog Trigger Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "WWPS,Watchdog Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog Start/Stop Register"
|
|
width 11.
|
|
tree.end
|
|
tree "WDT2"
|
|
base ad:0x48314000
|
|
width 14.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity selection " "Cut off,At least L4,At least timer,Both"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode selection" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable wakeup control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,L4 interconnect clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WISR,Watchdog Interrupt Event Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WIER,Watchdog Overflow Interrupt Control Register"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "WCLR,Watchdog Control Register"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "2,4,8,16,32,64,128,256"
|
|
line.long 0x04 "WCRR,Watchdog Counter Register"
|
|
line.long 0x08 "WLDR,Watchdog Load Register"
|
|
line.long 0x0c "WTGR,Watchdog Trigger Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "WWPS,Watchdog Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog Start/Stop Register"
|
|
width 11.
|
|
tree.end
|
|
tree "WDT3"
|
|
base ad:0x49030000
|
|
width 14.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity selection " "Cut off,At least L4,At least timer,Both"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode selection" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable wakeup control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,L4 interconnect clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WISR,Watchdog Interrupt Event Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WIER,Watchdog Overflow Interrupt Control Register"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "WCLR,Watchdog Control Register"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "2,4,8,16,32,64,128,256"
|
|
line.long 0x04 "WCRR,Watchdog Counter Register"
|
|
line.long 0x08 "WLDR,Watchdog Load Register"
|
|
line.long 0x0c "WTGR,Watchdog Trigger Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "WWPS,Watchdog Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog Start/Stop Register"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "32-kHz Sync"
|
|
base ad:0x48320000
|
|
width 25.
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "REG_32KSYNCNT_SYSCONFIG,This Register Is Used For IDLE Modes Only"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management REQ/ACK control" "Force idle,No-idle,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "REG_32KSYNCNT_CR,Read Counter Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART/IrDA/CIR"
|
|
tree "UART1"
|
|
base ad:0x4806a000
|
|
width 13.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806a000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806a000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
width 13.
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806a000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806a000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806a000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
; OPERATIONAL
|
|
width 13.
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 13.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,Reserved,UART 16x autobaud,UART 13x,Reserved,Reserved,Reserved,Disabled"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "MDR2,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 03. " UART_PULSE ,Pulse shaping mode" "Disabled,Enabled"
|
|
hgroup.word 0x28++0x1
|
|
hide.word 0x00 "SFLSR/TXFLL,Status FIFO line Status Register (read) / Transmit Frame Length Low Register (write)"
|
|
hgroup.word 0x2c++0x1
|
|
hide.word 0x00 "RESUME/TXFLH,Resume register (read) / Transmit Frame Length High Register (write)"
|
|
hgroup.word 0x30++0x1
|
|
hide.word 0x00 "SFREGL/RXFLL,Status FIFO Register Low (read) / Received Frame Length Low Register (write)"
|
|
hgroup.word 0x34++0x1
|
|
hide.word 0x00 "SFREGH/RXFLH,Status FIFO Register High (read) / Received Frame Length High Register (write)"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WU_EN ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_WUP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x1
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RHR_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RX_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RI_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_CTS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
hgroup.word 0x60++0x1
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x4806c000
|
|
width 13.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806c000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806c000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
width 13.
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806c000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806c000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806c000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
; OPERATIONAL
|
|
width 13.
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 13.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,Reserved,UART 16x autobaud,UART 13x,Reserved,Reserved,Reserved,Disabled"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "MDR2,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 03. " UART_PULSE ,Pulse shaping mode" "Disabled,Enabled"
|
|
hgroup.word 0x28++0x1
|
|
hide.word 0x00 "SFLSR/TXFLL,Status FIFO line Status Register (read) / Transmit Frame Length Low Register (write)"
|
|
hgroup.word 0x2c++0x1
|
|
hide.word 0x00 "RESUME/TXFLH,Resume register (read) / Transmit Frame Length High Register (write)"
|
|
hgroup.word 0x30++0x1
|
|
hide.word 0x00 "SFREGL/RXFLL,Status FIFO Register Low (read) / Received Frame Length Low Register (write)"
|
|
hgroup.word 0x34++0x1
|
|
hide.word 0x00 "SFREGH/RXFLH,Status FIFO Register High (read) / Received Frame Length High Register (write)"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WU_EN ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_WUP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x1
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RHR_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RX_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RI_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_CTS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
hgroup.word 0x60++0x1
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree "UART3/IrDA/CIR"
|
|
base ad:0x49020000
|
|
width 13.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x49020000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x49020000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
width 13.
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x49020000+0x10)))&0x40)==0x40)&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;cir
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR,UART Autobauding Status"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x49020000+0x10)))&0x40)==0x40)&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x49020000+0x10)))&0x40)==0x40)&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;IrDA
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR,UART Autobauding Status"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;cir
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR,UART Autobauding Status"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;IrDA
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR,UART Autobauding Status"
|
|
; OPERATIONAL
|
|
width 13.
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
;cir
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
;IrDA
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT_I ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
elif (((d.w((ad:0x49020000+0x0c)))&0x80)==0x00&&((d.w((ad:0x49020000+0x10)))&0x40)==0x40&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
;cir
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
elif (((d.w((ad:0x49020000+0x0c)))&0x80)==0x00&&((d.w((ad:0x49020000+0x10)))&0x40)==0x40&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x49020000+0x0c)))&0x80)==0x00&&((d.w((ad:0x49020000+0x10)))&0x40)==0x40&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
;IrDA
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT_I ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "BLR,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 13.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,IRTX pin output forced high" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA/CIR sleep mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x0024++0x1
|
|
line.word 0x00 "MDR2,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No inversion performed" "Inversion,No inversion"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
textline " "
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "SFLSR/TXFLL,Status FIFO line Status Register (read) / Transmit Frame Length Low Register (write) (IrDA mode only)"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FTL_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
group.word 0x2c++0x1
|
|
line.word 0x00 "RESUME/TXFLH,Resume register (read) / Transmit Frame Length High Register (write) (IrDA mode only)"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "SFREGL/RXFLL,Status FIFO Register Low (read) / Received Frame Length Low Register (write) (IrDA mode only)"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL/RXFLL ,LSB part of the frame length"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "SFREGH/RXFLH,Status FIFO Register High (read) / Received Frame Length High Register (write) (IrDA mode only)"
|
|
bitfld.word 0x00 0.--3. " SFREGH/RXFLH ,MSB part of frame length (read) / Frame length high (write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WU_EN ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_WUP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x1
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RHR_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RX_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RI_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_CTS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
group.word 0x60++0x1
|
|
line.word 0x00 "CFPS,Carrier Frequency Prescaler (CIR mode only)"
|
|
hexmask.word 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree "UART4"
|
|
base ad:0x4809E000
|
|
width 13.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4809E000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4809E000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPEC_CHAR ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
width 13.
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4809E000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4809E000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4809E000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4809E000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x00&&((d.w((ad:0x4809E000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x00&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4809E000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x00&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
; OPERATIONAL
|
|
width 13.
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x00&&((d.w((ad:0x4809E000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x00&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif ((((d.w((ad:0x4809E000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x00&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4809E000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x40&&((d.w((ad:0x4809E000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4809E000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x40&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
elif (((d.w((ad:0x4809E000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4809E000+0x10)))&0x40)==0x40&&((d.w((ad:0x4809E000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR,BOF Length Register"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 13.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,Reserved,UART 16x autobaud,UART 13x,Reserved,Reserved,Reserved,Disabled"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "MDR2,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 03. " UART_PULSE ,Pulse shaping mode" "Disabled,Enabled"
|
|
hgroup.word 0x28++0x1
|
|
hide.word 0x00 "SFLSR/TXFLL,Status FIFO line Status Register (read) / Transmit Frame Length Low Register (write)"
|
|
hgroup.word 0x2c++0x1
|
|
hide.word 0x00 "RESUME/TXFLH,Resume register (read) / Transmit Frame Length High Register (write)"
|
|
hgroup.word 0x30++0x1
|
|
hide.word 0x00 "SFREGL/RXFLL,Status FIFO Register Low (read) / Received Frame Length Low Register (write)"
|
|
hgroup.word 0x34++0x1
|
|
hide.word 0x00 "SFREGH/RXFLH,Status FIFO Register High (read) / Received Frame Length High Register (write)"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WU_EN ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_WUP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
rgroup.word 0x58++0x1
|
|
line.word 0x00 "SYSS,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RHR_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RX_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RI_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_CTS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
hgroup.word 0x60++0x1
|
|
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C1"
|
|
base ad:0x48070000
|
|
width 13.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_IE,I2C Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " XDR_IE ,Transmit draining interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_IE ,Receive draining interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_IE ,Addressed as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_IE ,Bus free interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " AERR_IE ,Access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STC_IE ,Start condition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_STAT,I2C Status Information About Module"
|
|
eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status" "Inactive,Active"
|
|
eventfld.word 0x00 13. " RDR ,Receive draining IRQ status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BB ,Bus busy status" "Free,Occupied"
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun status" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status" "No effect,Recognized"
|
|
textline " "
|
|
eventfld.word 0x00 8. " BF ,Bus free IRQ status" "No effect,Free"
|
|
eventfld.word 0x00 7. " AERR ,Access error IRQ status" "No effect,Error"
|
|
textline " "
|
|
eventfld.word 0x00 6. " STC ,Start condition IRQ status" "No effect,Detected"
|
|
eventfld.word 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not requested,Requested"
|
|
eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status" "Not availabled,Availabled"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status" "Busy,Ready"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgment IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status" "Not detected,Detected"
|
|
group.word 0x0c++0x01
|
|
line.word 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.word 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_WE ,Address as slave wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_WE ,Bus free wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STC_WE ,Start condition wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " GC_WE ,General call wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRDY_WE ,Transmit/receive data ready wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_WE ,Register access ready wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_WE ,No acknowledgment wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_WE ,Arbitration lost wakeup enable" "Disabled,Enabled"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2C_SYSS,I2C Status Information About Module"
|
|
bitfld.word 0x00 0. " RDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2C_BUF,I2C Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--13. 1. " RTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " XTRSH ,Threshold value for FIFO buffer in TX mode"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "I2C_CNT,I2C Data Count Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count"
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "I2C_DATA,I2C Transmit/Receive FIFO data"
|
|
in
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C Parameters of the L4-Core Interconnect Interface"
|
|
bitfld.word 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity (interface/functional)" "Cut off,Active/Cut off,Cut off/Active,Active"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Enable wakeup" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SRST ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x48070000+0x24)))&0x400)==0x400)
|
|
;master mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
textline " "
|
|
bitfld.word 0x00 9. " TRX ,Transmitter/receiver mode" "Receiver,Transmitter"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STP ,Stop condition" "No action/Detected,Queried"
|
|
bitfld.word 0x00 0. " STT ,Start condition" "No action/Detected,Queried"
|
|
else
|
|
;slave mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x80)==0x80)
|
|
;I2C_CON[7]= 10-bit
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address 0 value"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address 0 value"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x100)==0x100)
|
|
;I2C_CON[8]= 10-bit
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Slave address value"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Slave address value"
|
|
endif
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Prescale Sampling Clock Divider"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard and SCCB modes prescale sampling clock divider value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "I2C_SCLL,I2C SCL"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,I2C High Speed mode SCL low time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLL ,I2C Fast/Standard or SCCB modes SCL low time value"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2C_SCLH,I2C SCLH"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,I2C high-speed mode SCL high time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLH ,I2C Fast/Standard or SCCB modes SCL high time value"
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.word 0x00 15. " ST_EN ,System test enable" "No effect,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free-running mode" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,SCL counters,Loop back/SDA/SCL IO"
|
|
bitfld.word 0x00 11. " SSB ,Set status" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SCCBE_O ,SCCBE line sense output value" "0,1"
|
|
bitfld.word 0x00 3. " SCL_I ,SCL line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SCL_O ,SCL line drive output value" "0,1"
|
|
bitfld.word 0x00 1. " SDA_I ,SDA line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDA_O ,SDA line drive output value" "0,1"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "I2C_BUFSTAT,I2C FIFO Status Information"
|
|
bitfld.word 0x00 14.--15. " FIFODEPTH ,FIFO depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
hexmask.word.byte 0x00 8.--13. 1. " RXSTAT ,RX buffer status"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " TXSTAT ,TX buffer status"
|
|
if (((d.w((ad:0x48070000+0x24)))&0x40)==0x40)
|
|
;I2C_CON[6]= 10-bit
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1 value"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA1 ,Own address 1 value"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x20)==0x20)
|
|
;I2C_CON[5]= 10-bit
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2 value"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA2 ,Own address 2 value"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x10)==0x10)
|
|
;I2C_CON[4]= 10-bit
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3 value"
|
|
else
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA3 ,Own address 3 value"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2C_ACTOA,I2C Accessed Slave Own Address Indicators"
|
|
bitfld.word 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active"
|
|
bitfld.word 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2C_SBLOCK,I2C Slave Mode Bus Lock Features"
|
|
bitfld.word 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked"
|
|
bitfld.word 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked"
|
|
bitfld.word 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked"
|
|
width 11.
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x48072000
|
|
width 13.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_IE,I2C Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " XDR_IE ,Transmit draining interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_IE ,Receive draining interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_IE ,Addressed as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_IE ,Bus free interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " AERR_IE ,Access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STC_IE ,Start condition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_STAT,I2C Status Information About Module"
|
|
eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status" "Inactive,Active"
|
|
eventfld.word 0x00 13. " RDR ,Receive draining IRQ status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BB ,Bus busy status" "Free,Occupied"
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun status" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status" "No effect,Recognized"
|
|
textline " "
|
|
eventfld.word 0x00 8. " BF ,Bus free IRQ status" "No effect,Free"
|
|
eventfld.word 0x00 7. " AERR ,Access error IRQ status" "No effect,Error"
|
|
textline " "
|
|
eventfld.word 0x00 6. " STC ,Start condition IRQ status" "No effect,Detected"
|
|
eventfld.word 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not requested,Requested"
|
|
eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status" "Not availabled,Availabled"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status" "Busy,Ready"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgment IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status" "Not detected,Detected"
|
|
group.word 0x0c++0x01
|
|
line.word 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.word 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_WE ,Address as slave wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_WE ,Bus free wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STC_WE ,Start condition wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " GC_WE ,General call wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRDY_WE ,Transmit/receive data ready wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_WE ,Register access ready wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_WE ,No acknowledgment wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_WE ,Arbitration lost wakeup enable" "Disabled,Enabled"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2C_SYSS,I2C Status Information About Module"
|
|
bitfld.word 0x00 0. " RDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2C_BUF,I2C Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--13. 1. " RTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " XTRSH ,Threshold value for FIFO buffer in TX mode"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "I2C_CNT,I2C Data Count Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count"
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "I2C_DATA,I2C Transmit/Receive FIFO data"
|
|
in
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C Parameters of the L4-Core Interconnect Interface"
|
|
bitfld.word 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity (interface/functional)" "Cut off,Active/Cut off,Cut off/Active,Active"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Enable wakeup" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SRST ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x48072000+0x24)))&0x400)==0x400)
|
|
;master mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
textline " "
|
|
bitfld.word 0x00 9. " TRX ,Transmitter/receiver mode" "Receiver,Transmitter"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STP ,Stop condition" "No action/Detected,Queried"
|
|
bitfld.word 0x00 0. " STT ,Start condition" "No action/Detected,Queried"
|
|
else
|
|
;slave mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x80)==0x80)
|
|
;I2C_CON[7]= 10-bit
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address 0 value"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address 0 value"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x100)==0x100)
|
|
;I2C_CON[8]= 10-bit
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Slave address value"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Slave address value"
|
|
endif
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Prescale Sampling Clock Divider"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard and SCCB modes prescale sampling clock divider value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "I2C_SCLL,I2C SCL"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,I2C High Speed mode SCL low time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLL ,I2C Fast/Standard or SCCB modes SCL low time value"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2C_SCLH,I2C SCLH"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,I2C high-speed mode SCL high time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLH ,I2C Fast/Standard or SCCB modes SCL high time value"
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.word 0x00 15. " ST_EN ,System test enable" "No effect,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free-running mode" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,SCL counters,Loop back/SDA/SCL IO"
|
|
bitfld.word 0x00 11. " SSB ,Set status" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SCCBE_O ,SCCBE line sense output value" "0,1"
|
|
bitfld.word 0x00 3. " SCL_I ,SCL line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SCL_O ,SCL line drive output value" "0,1"
|
|
bitfld.word 0x00 1. " SDA_I ,SDA line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDA_O ,SDA line drive output value" "0,1"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "I2C_BUFSTAT,I2C FIFO Status Information"
|
|
bitfld.word 0x00 14.--15. " FIFODEPTH ,FIFO depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
hexmask.word.byte 0x00 8.--13. 1. " RXSTAT ,RX buffer status"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " TXSTAT ,TX buffer status"
|
|
if (((d.w((ad:0x48072000+0x24)))&0x40)==0x40)
|
|
;I2C_CON[6]= 10-bit
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1 value"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA1 ,Own address 1 value"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x20)==0x20)
|
|
;I2C_CON[5]= 10-bit
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2 value"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA2 ,Own address 2 value"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x10)==0x10)
|
|
;I2C_CON[4]= 10-bit
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3 value"
|
|
else
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA3 ,Own address 3 value"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2C_ACTOA,I2C Accessed Slave Own Address Indicators"
|
|
bitfld.word 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active"
|
|
bitfld.word 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2C_SBLOCK,I2C Slave Mode Bus Lock Features"
|
|
bitfld.word 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked"
|
|
bitfld.word 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked"
|
|
bitfld.word 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked"
|
|
width 11.
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x48060000
|
|
width 13.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_IE,I2C Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " XDR_IE ,Transmit draining interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_IE ,Receive draining interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_IE ,Addressed as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_IE ,Bus free interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " AERR_IE ,Access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STC_IE ,Start condition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_STAT,I2C Status Information About Module"
|
|
eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status" "Inactive,Active"
|
|
eventfld.word 0x00 13. " RDR ,Receive draining IRQ status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BB ,Bus busy status" "Free,Occupied"
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun status" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status" "No effect,Recognized"
|
|
textline " "
|
|
eventfld.word 0x00 8. " BF ,Bus free IRQ status" "No effect,Free"
|
|
eventfld.word 0x00 7. " AERR ,Access error IRQ status" "No effect,Error"
|
|
textline " "
|
|
eventfld.word 0x00 6. " STC ,Start condition IRQ status" "No effect,Detected"
|
|
eventfld.word 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not requested,Requested"
|
|
eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status" "Not availabled,Availabled"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status" "Busy,Ready"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgment IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status" "Not detected,Detected"
|
|
group.word 0x0c++0x01
|
|
line.word 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.word 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_WE ,Address as slave wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_WE ,Bus free wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STC_WE ,Start condition wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " GC_WE ,General call wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRDY_WE ,Transmit/receive data ready wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_WE ,Register access ready wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_WE ,No acknowledgment wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_WE ,Arbitration lost wakeup enable" "Disabled,Enabled"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2C_SYSS,I2C Status Information About Module"
|
|
bitfld.word 0x00 0. " RDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2C_BUF,I2C Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--13. 1. " RTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " XTRSH ,Threshold value for FIFO buffer in TX mode"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "I2C_CNT,I2C Data Count Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count"
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "I2C_DATA,I2C Transmit/Receive FIFO data"
|
|
in
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C Parameters of the L4-Core Interconnect Interface"
|
|
bitfld.word 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity (interface/functional)" "Cut off,Active/Cut off,Cut off/Active,Active"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Enable wakeup" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SRST ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x48060000+0x24)))&0x400)==0x400)
|
|
;master mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
textline " "
|
|
bitfld.word 0x00 9. " TRX ,Transmitter/receiver mode" "Receiver,Transmitter"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STP ,Stop condition" "No action/Detected,Queried"
|
|
bitfld.word 0x00 0. " STT ,Start condition" "No action/Detected,Queried"
|
|
else
|
|
;slave mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x80)==0x80)
|
|
;I2C_CON[7]= 10-bit
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address 0 value"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address 0 value"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x100)==0x100)
|
|
;I2C_CON[8]= 10-bit
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Slave address value"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Slave address value"
|
|
endif
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Prescale Sampling Clock Divider"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard and SCCB modes prescale sampling clock divider value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "I2C_SCLL,I2C SCL"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,I2C High Speed mode SCL low time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLL ,I2C Fast/Standard or SCCB modes SCL low time value"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2C_SCLH,I2C SCLH"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,I2C high-speed mode SCL high time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLH ,I2C Fast/Standard or SCCB modes SCL high time value"
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.word 0x00 15. " ST_EN ,System test enable" "No effect,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free-running mode" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,SCL counters,Loop back/SDA/SCL IO"
|
|
bitfld.word 0x00 11. " SSB ,Set status" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SCCBE_O ,SCCBE line sense output value" "0,1"
|
|
bitfld.word 0x00 3. " SCL_I ,SCL line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SCL_O ,SCL line drive output value" "0,1"
|
|
bitfld.word 0x00 1. " SDA_I ,SDA line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDA_O ,SDA line drive output value" "0,1"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "I2C_BUFSTAT,I2C FIFO Status Information"
|
|
bitfld.word 0x00 14.--15. " FIFODEPTH ,FIFO depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
hexmask.word.byte 0x00 8.--13. 1. " RXSTAT ,RX buffer status"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " TXSTAT ,TX buffer status"
|
|
if (((d.w((ad:0x48060000+0x24)))&0x40)==0x40)
|
|
;I2C_CON[6]= 10-bit
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1 value"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA1 ,Own address 1 value"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x20)==0x20)
|
|
;I2C_CON[5]= 10-bit
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2 value"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA2 ,Own address 2 value"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x10)==0x10)
|
|
;I2C_CON[4]= 10-bit
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3 value"
|
|
else
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA3 ,Own address 3 value"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2C_ACTOA,I2C Accessed Slave Own Address Indicators"
|
|
bitfld.word 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active"
|
|
bitfld.word 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2C_SBLOCK,I2C Slave Mode Bus Lock Features"
|
|
bitfld.word 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked"
|
|
bitfld.word 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked"
|
|
bitfld.word 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "McSPI (Multichannel Serial Port Interface)"
|
|
tree "MCSPI1"
|
|
base ad:0x48098000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
|
|
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x48098000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x40++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x40+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x40+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Transmit Register"
|
|
hgroup.long (0x40+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Receive Register"
|
|
in
|
|
group.long 0x54++0x3 "Channel 2"
|
|
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 2" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x54+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
|
|
group.long (0x54+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX2,MCSPI Transmit Register"
|
|
hgroup.long (0x54+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX2,MCSPI Receive Register"
|
|
in
|
|
group.long 0x68++0x3 "Channel 3"
|
|
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x68+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
|
|
group.long (0x68+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX3,MCSPI Transmit Register"
|
|
hgroup.long (0x68+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX3,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree "MCSPI2"
|
|
base ad:0x4809a000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x4809a000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x40++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x40+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x40+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Transmit Register"
|
|
hgroup.long (0x40+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree "MCSPI3"
|
|
base ad:0x480b8000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x480b8000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x40++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x40+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x40+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Transmit Register"
|
|
hgroup.long (0x40+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree "MCSPI4"
|
|
base ad:0x480ba000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x480ba000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "McBSP (Multi-Channel Buffered Serial Port)"
|
|
tree "McBSP1"
|
|
base ad:0x48074000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48074000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x48074000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x48074000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP2"
|
|
base ad:0x49022000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49022000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x49022000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x49022000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.word 0x04 0.--10. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.word 0x08 0.--10. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.word 0x00 0.--10. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.word 0x04 0.--10. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "SIDETONE_McBSP2"
|
|
base ad:0x49028000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "ST_REV_REG,SIDETONE Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ST_SYSCONFIG_REG,SIDETONE System Configuration Register"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Automatic McBSPi_ICLK clock gating" "Disabled,Enabled"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "ST_IRQSTATUS_REG,SIDETONE Interrupt Status Register"
|
|
eventfld.long 0x00 0. " OVRRERROR ,Over-run error occured" "Not occurred,Occurred"
|
|
line.long 0x04 "ST_IRQENABLE_REG,SIDETONE Interrupt Enable Register"
|
|
bitfld.long 0x04 0. " OVRRERROREN ,Over-run error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x24++0xb
|
|
line.long 0x00 "ST_SGAINCR_REG,Sidetone Gain Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CH1GAIN ,Second sidetone channel gain"
|
|
hexmask.long.word 0x00 0.--15. 1. " CH0GAIN ,First sidetone channel gain"
|
|
line.long 0x04 "ST_SFIRCR_REG,Sidetone FIR Coefficients Control Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FIRCOEFF ,FIR coefficients control register"
|
|
line.long 0x08 "ST_SSELCR_REG,Sidetone Select Register"
|
|
bitfld.long 0x08 2. " COEFFWRDONE ,Write FIR coefficients completed" "Not completed,Completed"
|
|
bitfld.long 0x08 1. " COEFFWREN ,Write enable FIR coefficients" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP3"
|
|
base ad:0x49024000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49024000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x49024000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x49024000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "SIDETONE_McBSP3"
|
|
base ad:0x4902a000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "ST_REV_REG,SIDETONE Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ST_SYSCONFIG_REG,SIDETONE System Configuration Register"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Automatic McBSPi_ICLK clock gating" "Disabled,Enabled"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "ST_IRQSTATUS_REG,SIDETONE Interrupt Status Register"
|
|
eventfld.long 0x00 0. " OVRRERROR ,Over-run error occured" "Not occurred,Occurred"
|
|
line.long 0x04 "ST_IRQENABLE_REG,SIDETONE Interrupt Enable Register"
|
|
bitfld.long 0x04 0. " OVRRERROREN ,Over-run error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x24++0xb
|
|
line.long 0x00 "ST_SGAINCR_REG,Sidetone Gain Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CH1GAIN ,Second sidetone channel gain"
|
|
hexmask.long.word 0x00 0.--15. 1. " CH0GAIN ,First sidetone channel gain"
|
|
line.long 0x04 "ST_SFIRCR_REG,Sidetone FIR Coefficients Control Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FIRCOEFF ,FIR coefficients control register"
|
|
line.long 0x08 "ST_SSELCR_REG,Sidetone Select Register"
|
|
bitfld.long 0x08 2. " COEFFWRDONE ,Write FIR coefficients completed" "Not completed,Completed"
|
|
bitfld.long 0x08 1. " COEFFWREN ,Write enable FIR coefficients" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP4"
|
|
base ad:0x49026000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49026000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x49026000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x49026000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP5"
|
|
base ad:0x48096000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x880)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x0)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x80)))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48096000+0x48)))&0x880)==0x800)))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x48096000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x48096000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x34)))&0x201)==0x201))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x34)))&0x201)==0x201))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x34)))&0x201)==0x201))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "HDQ/1-Wire"
|
|
base ad:0x480b2000
|
|
width 17.
|
|
textline ""
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "HDQ_TX_DATA,HDQ Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data"
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "HDQ_RX_DATA,HDQ Receive Data Register"
|
|
in
|
|
if (((d.l((ad:0x480b2000+0x0c)))&0x1)==0x1)
|
|
;1-wire
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HDQ_CTRL_STATUS,HDQ Status Information About Module"
|
|
bitfld.long 0x00 0. " MODE ,Mode selection" "HDQ,1-Wire"
|
|
bitfld.long 0x00 7. " 1_WIRE_SINGLE_BIT ,Single-bit mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INTERRUPTMASK ,Interrupt masking" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " CLOCKENABLE ,Power down mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GO ,Send the appropriate commands" "No effect,Sent"
|
|
bitfld.long 0x00 3. " PRESENCEDETECT ,Presence detect received" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INITIALIZATION ,Initialization pulse" "No effect,Sent"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Read,Write"
|
|
else
|
|
;HDQ
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HDQ_CTRL_STATUS,HDQ Status Information About Module"
|
|
bitfld.long 0x00 0. " MODE ,Mode selection" "HDQ,1-Wire"
|
|
bitfld.long 0x00 6. " INTERRUPTMASK ,Interrupt masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCKENABLE ,Power down mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " GO ,Send the appropriate commands" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INITIALIZATION ,Initialization pulse" "No effect,Sent"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Read,Write"
|
|
endif
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "HDQ_INT_STATUS,HDQ Interrupt Status Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "HDQ_SYSCONFIG,HDQ System Configuration Register"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Start soft reset sequence" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interconnect idle" "Free-running,Power-saving"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "HDQ_SYSSTATUS,HDQ System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset monitoring" "Performing,Finished"
|
|
width 11.
|
|
tree.end
|
|
tree.open "MMC/SD/SDIO Card Interface"
|
|
tree "MMCHS1"
|
|
base ad:0x4809c000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMCHS_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "MMCHS_CSRE,Card Status Response Error"
|
|
bitfld.long 0x00 31. " CSRE[31] ,Card status response error bit 31" "No error,Error"
|
|
bitfld.long 0x00 30. " CSRE[30] ,Card status response error bit 30" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSRE[29] ,Card status response error bit 29" "No error,Error"
|
|
bitfld.long 0x00 28. " CSRE[28] ,Card status response error bit 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSRE[27] ,Card status response error bit 27" "No error,Error"
|
|
bitfld.long 0x00 26. " CSRE[26] ,Card status response error bit 26" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CSRE[25] ,Card status response error bit 25" "No error,Error"
|
|
bitfld.long 0x00 24. " CSRE[24] ,Card status response error bit 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CSRE[23] ,Card status response error bit 23" "No error,Error"
|
|
bitfld.long 0x00 22. " CSRE[22] ,Card status response error bit 22" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSRE[21] ,Card status response error bit 21" "No error,Error"
|
|
bitfld.long 0x00 20. " CSRE[20] ,Card status response error bit 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSRE[19] ,Card status response error bit 19" "No error,Error"
|
|
bitfld.long 0x00 18. " CSRE[18] ,Card status response error bit 18" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSRE[17] ,Card status response error bit 17" "No error,Error"
|
|
bitfld.long 0x00 16. " CSRE[16] ,Card status response error bit 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSRE[15] ,Card status response error bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " CSRE[14] ,Card status response error bit 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSRE[13] ,Card status response error bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " CSRE[12] ,Card status response error bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CSRE[11] ,Card status response error bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " CSRE[10] ,Card status response error bit 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSRE[9] ,Card status response error bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " CSRE[8] ,Card status response error bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSRE[7] ,Card status response error bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " CSRE[6] ,Card status response error bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSRE[5] ,Card status response error bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " CSRE[4] ,Card status response error bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSRE[3] ,Card status response error bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " CSRE[2] ,Card status response error bit 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSRE[1] ,Card status response error bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " CSRE[0] ,Card status response error bit 0" "No error,Error"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MMCHS_SYSTEST,System Test register"
|
|
bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt" "Low,High"
|
|
bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High"
|
|
bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB ,Set status bit" "0,1"
|
|
bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High"
|
|
group.long 0x2c++0x7
|
|
line.long 0x00 "MMCHS_CON,Configuration Register"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for mmci_dat[1] line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " MIT ,MMC interrupt command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select" "1-bit/4-bit,8-bit"
|
|
bitfld.long 0x00 4. " MODE ,Mode select" "Functional,SYSTEST"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STR ,Stream command" "Block,Stream"
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response" "No response,Response"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode" "No open drain,Open drain"
|
|
line.long 0x04 "MMCHS_PWCNT,Power Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter register"
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "MMCHS_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--10. 1. " BLEN ,Transfer block size"
|
|
line.long 0x04 "MMCHS_ARG,Command Argument Register"
|
|
line.long 0x08 "MMCHS_CMD,Command and Transfer Mode Register"
|
|
bitfld.long 0x08 24.--29. " INDX ,Command index" "CMD0/ACMD0,CMD1/ACMD1,CMD2/ACMD2,CMD3/ACMD3,CMD4/ACMD4,CMD5/ACMD5,CMD6/ACMD6,CMD7/ACMD7,CMD8/ACMD8,CMD9/ACMD9,CMD10/ACMD10,CMD11/ACMD11,CMD12/ACMD12,CMD13/ACMD13,CMD14/ACMD14,CMD15/ACMD15,CMD16/ACMD16,CMD17/ACMD17,CMD18/ACMD18,CMD19/ACMD19,CMD20/ACMD20,CMD21/ACMD21,CMD22/ACMD22,CMD23/ACMD23,CMD24/ACMD24,CMD25/ACMD25,CMD26/ACMD26,CMD27/ACMD27,CMD28/ACMD28,CMD29/ACMD29,CMD30/ACMD30,CMD31/ACMD31,CMD32/ACMD32,CMD33/ACMD33,CMD34/ACMD34,CMD35/ACMD35,CMD36/ACMD36,CMD37/ACMD37,CMD38/ACMD38,CMD39/ACMD39,CMD40/ACMD40,CMD41/ACMD41,CMD42/ACMD42,CMD43/ACMD43,CMD44/ACMD44,CMD45/ACMD45,CMD46/ACMD46,CMD47/ACMD47,CMD48/ACMD48,CMD49/ACMD49,CMD50/ACMD50,CMD51/ACMD51,CMD52/ACMD52,CMD53/ACMD53,CMD54/ACMD54,CMD55/ACMD55,CMD56/ACMD56,CMD57/ACMD57,CMD58/ACMD58,CMD59/ACMD59,CMD60/ACMD60,CMD61/ACMD61,CMD62/ACMD62,CMD63/ACMD63"
|
|
bitfld.long 0x08 22.--23. " CMD_TYPE ,Command type" "Other,Bus Suspend,Function Select,I/O Abort"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DP ,Data present" "No transfer,Transfer"
|
|
bitfld.long 0x08 20. " CICE ,Command Index check enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x08 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACEN ,Auto CMD12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " BCE ,Block count enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DE ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x110++0xf
|
|
line.long 0x00 "MMCHS_RSP10,Command Response[31:0] Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command response"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command response"
|
|
line.long 0x04 "MMCHS_RSP32,Command Response[63:32] Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command response"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command response"
|
|
line.long 0x08 "MMCHS_RSP54,Command Response[95:64] Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command response"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command response"
|
|
line.long 0x0c "MMCHS_RSP76,Command Response[127:96] Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " RSP7 ,Command response"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RSP6 ,Command response"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MMCHS_DATA,Data Register"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "MMCHS_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,The mmci_cmd line level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,The mmci_dat[3] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLEV[2] ,The mmci_dat[2] line level" "0,1"
|
|
bitfld.long 0x00 21. " DLEV[1] ,The mmci_dat[1] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLEV[0] ,The mmci_dat[0] line level" "0,1"
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DLA ,mmci_dat Line active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATI ,Issuing of command using the mmci_dat lines" "Allowed,Not allowed"
|
|
bitfld.long 0x00 0. " CMDI ,Issuing of command using mmci_cmd line" "Allowed,Not allowed"
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "MMCHS_HCTL,Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wakeup event enable for Out-of-Band interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Continue request" "No effect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "MMCHS_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for mmci_dat line" "Completed,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for mmci_cmd line" "Completed,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "Completed,Reset"
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,TCF x 2^15,TCF x 2^16,TCF x 2^17,TCF x 2^18,TCF x 2^19,TCF x 2^20,TCF x 2^21,TCF x 2^22,TCF x 2^23,TCF x 2^24,TCF x 2^25,TCF x 2^26,TCF x 2^27,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable" "Not stable,Stable"
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Stopped,Enabled"
|
|
line.long 0x08 "MMCHS_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No error,Error"
|
|
eventfld.long 0x08 22. " DEB ,Data End Bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out-Of-Band interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No event,Interrupt"
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " CC ,Command completed" "Not completed,Completed"
|
|
line.long 0x0c "MMCHS_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0C 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x0C 9. " OBI_ENABLE ,Out-of-Band interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "MMCHS_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x10 9. " OBI_SIGEN ,Out-Of-Band interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Black gap event signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Masked,Enabled"
|
|
rgroup.long 0x13c++0x3
|
|
line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "MMCHS_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported"
|
|
bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
hexmask.long.byte 0x00 8.--13. 1. " BCF ,Base clock frequency"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TCF ,Timeout clock frequency"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V"
|
|
rgroup.long 0x1fc++0x3
|
|
line.long 0x00 "MMCHS_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification version number"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIS ,Slot interrupt status" "0,1"
|
|
width 11.
|
|
tree.end
|
|
tree "MMCHS2"
|
|
base ad:0x480b4000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMCHS_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "MMCHS_CSRE,Card Status Response Error"
|
|
bitfld.long 0x00 31. " CSRE[31] ,Card status response error bit 31" "No error,Error"
|
|
bitfld.long 0x00 30. " CSRE[30] ,Card status response error bit 30" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSRE[29] ,Card status response error bit 29" "No error,Error"
|
|
bitfld.long 0x00 28. " CSRE[28] ,Card status response error bit 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSRE[27] ,Card status response error bit 27" "No error,Error"
|
|
bitfld.long 0x00 26. " CSRE[26] ,Card status response error bit 26" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CSRE[25] ,Card status response error bit 25" "No error,Error"
|
|
bitfld.long 0x00 24. " CSRE[24] ,Card status response error bit 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CSRE[23] ,Card status response error bit 23" "No error,Error"
|
|
bitfld.long 0x00 22. " CSRE[22] ,Card status response error bit 22" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSRE[21] ,Card status response error bit 21" "No error,Error"
|
|
bitfld.long 0x00 20. " CSRE[20] ,Card status response error bit 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSRE[19] ,Card status response error bit 19" "No error,Error"
|
|
bitfld.long 0x00 18. " CSRE[18] ,Card status response error bit 18" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSRE[17] ,Card status response error bit 17" "No error,Error"
|
|
bitfld.long 0x00 16. " CSRE[16] ,Card status response error bit 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSRE[15] ,Card status response error bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " CSRE[14] ,Card status response error bit 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSRE[13] ,Card status response error bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " CSRE[12] ,Card status response error bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CSRE[11] ,Card status response error bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " CSRE[10] ,Card status response error bit 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSRE[9] ,Card status response error bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " CSRE[8] ,Card status response error bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSRE[7] ,Card status response error bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " CSRE[6] ,Card status response error bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSRE[5] ,Card status response error bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " CSRE[4] ,Card status response error bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSRE[3] ,Card status response error bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " CSRE[2] ,Card status response error bit 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSRE[1] ,Card status response error bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " CSRE[0] ,Card status response error bit 0" "No error,Error"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MMCHS_SYSTEST,System Test register"
|
|
bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt" "Low,High"
|
|
bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High"
|
|
bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB ,Set status bit" "0,1"
|
|
bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High"
|
|
group.long 0x2c++0x7
|
|
line.long 0x00 "MMCHS_CON,Configuration Register"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for mmci_dat[1] line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " MIT ,MMC interrupt command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select" "1-bit/4-bit,8-bit"
|
|
bitfld.long 0x00 4. " MODE ,Mode select" "Functional,SYSTEST"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STR ,Stream command" "Block,Stream"
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response" "No response,Response"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode" "No open drain,Open drain"
|
|
line.long 0x04 "MMCHS_PWCNT,Power Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter register"
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "MMCHS_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--10. 1. " BLEN ,Transfer block size"
|
|
line.long 0x04 "MMCHS_ARG,Command Argument Register"
|
|
line.long 0x08 "MMCHS_CMD,Command and Transfer Mode Register"
|
|
bitfld.long 0x08 24.--29. " INDX ,Command index" "CMD0/ACMD0,CMD1/ACMD1,CMD2/ACMD2,CMD3/ACMD3,CMD4/ACMD4,CMD5/ACMD5,CMD6/ACMD6,CMD7/ACMD7,CMD8/ACMD8,CMD9/ACMD9,CMD10/ACMD10,CMD11/ACMD11,CMD12/ACMD12,CMD13/ACMD13,CMD14/ACMD14,CMD15/ACMD15,CMD16/ACMD16,CMD17/ACMD17,CMD18/ACMD18,CMD19/ACMD19,CMD20/ACMD20,CMD21/ACMD21,CMD22/ACMD22,CMD23/ACMD23,CMD24/ACMD24,CMD25/ACMD25,CMD26/ACMD26,CMD27/ACMD27,CMD28/ACMD28,CMD29/ACMD29,CMD30/ACMD30,CMD31/ACMD31,CMD32/ACMD32,CMD33/ACMD33,CMD34/ACMD34,CMD35/ACMD35,CMD36/ACMD36,CMD37/ACMD37,CMD38/ACMD38,CMD39/ACMD39,CMD40/ACMD40,CMD41/ACMD41,CMD42/ACMD42,CMD43/ACMD43,CMD44/ACMD44,CMD45/ACMD45,CMD46/ACMD46,CMD47/ACMD47,CMD48/ACMD48,CMD49/ACMD49,CMD50/ACMD50,CMD51/ACMD51,CMD52/ACMD52,CMD53/ACMD53,CMD54/ACMD54,CMD55/ACMD55,CMD56/ACMD56,CMD57/ACMD57,CMD58/ACMD58,CMD59/ACMD59,CMD60/ACMD60,CMD61/ACMD61,CMD62/ACMD62,CMD63/ACMD63"
|
|
bitfld.long 0x08 22.--23. " CMD_TYPE ,Command type" "Other,Bus Suspend,Function Select,I/O Abort"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DP ,Data present" "No transfer,Transfer"
|
|
bitfld.long 0x08 20. " CICE ,Command Index check enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x08 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACEN ,Auto CMD12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " BCE ,Block count enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DE ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x110++0xf
|
|
line.long 0x00 "MMCHS_RSP10,Command Response[31:0] Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command response"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command response"
|
|
line.long 0x04 "MMCHS_RSP32,Command Response[63:32] Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command response"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command response"
|
|
line.long 0x08 "MMCHS_RSP54,Command Response[95:64] Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command response"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command response"
|
|
line.long 0x0c "MMCHS_RSP76,Command Response[127:96] Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " RSP7 ,Command response"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RSP6 ,Command response"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MMCHS_DATA,Data Register"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "MMCHS_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,The mmci_cmd line level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,The mmci_dat[3] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLEV[2] ,The mmci_dat[2] line level" "0,1"
|
|
bitfld.long 0x00 21. " DLEV[1] ,The mmci_dat[1] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLEV[0] ,The mmci_dat[0] line level" "0,1"
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DLA ,mmci_dat Line active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATI ,Issuing of command using the mmci_dat lines" "Allowed,Not allowed"
|
|
bitfld.long 0x00 0. " CMDI ,Issuing of command using mmci_cmd line" "Allowed,Not allowed"
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "MMCHS_HCTL,Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wakeup event enable for Out-of-Band interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Continue request" "No effect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "MMCHS_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for mmci_dat line" "Completed,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for mmci_cmd line" "Completed,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "Completed,Reset"
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,TCF x 2^15,TCF x 2^16,TCF x 2^17,TCF x 2^18,TCF x 2^19,TCF x 2^20,TCF x 2^21,TCF x 2^22,TCF x 2^23,TCF x 2^24,TCF x 2^25,TCF x 2^26,TCF x 2^27,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable" "Not stable,Stable"
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Stopped,Enabled"
|
|
line.long 0x08 "MMCHS_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No error,Error"
|
|
eventfld.long 0x08 22. " DEB ,Data End Bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out-Of-Band interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No event,Interrupt"
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " CC ,Command completed" "Not completed,Completed"
|
|
line.long 0x0c "MMCHS_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0C 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x0C 9. " OBI_ENABLE ,Out-of-Band interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "MMCHS_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x10 9. " OBI_SIGEN ,Out-Of-Band interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Black gap event signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Masked,Enabled"
|
|
rgroup.long 0x13c++0x3
|
|
line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "MMCHS_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported"
|
|
bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
hexmask.long.byte 0x00 8.--13. 1. " BCF ,Base clock frequency"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TCF ,Timeout clock frequency"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V"
|
|
rgroup.long 0x1fc++0x3
|
|
line.long 0x00 "MMCHS_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification version number"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIS ,Slot interrupt status" "0,1"
|
|
width 11.
|
|
tree.end
|
|
tree "MMCHS3"
|
|
base ad:0x480AD000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMCHS_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "MMCHS_CSRE,Card Status Response Error"
|
|
bitfld.long 0x00 31. " CSRE[31] ,Card status response error bit 31" "No error,Error"
|
|
bitfld.long 0x00 30. " CSRE[30] ,Card status response error bit 30" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSRE[29] ,Card status response error bit 29" "No error,Error"
|
|
bitfld.long 0x00 28. " CSRE[28] ,Card status response error bit 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSRE[27] ,Card status response error bit 27" "No error,Error"
|
|
bitfld.long 0x00 26. " CSRE[26] ,Card status response error bit 26" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CSRE[25] ,Card status response error bit 25" "No error,Error"
|
|
bitfld.long 0x00 24. " CSRE[24] ,Card status response error bit 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CSRE[23] ,Card status response error bit 23" "No error,Error"
|
|
bitfld.long 0x00 22. " CSRE[22] ,Card status response error bit 22" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSRE[21] ,Card status response error bit 21" "No error,Error"
|
|
bitfld.long 0x00 20. " CSRE[20] ,Card status response error bit 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSRE[19] ,Card status response error bit 19" "No error,Error"
|
|
bitfld.long 0x00 18. " CSRE[18] ,Card status response error bit 18" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSRE[17] ,Card status response error bit 17" "No error,Error"
|
|
bitfld.long 0x00 16. " CSRE[16] ,Card status response error bit 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSRE[15] ,Card status response error bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " CSRE[14] ,Card status response error bit 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSRE[13] ,Card status response error bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " CSRE[12] ,Card status response error bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CSRE[11] ,Card status response error bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " CSRE[10] ,Card status response error bit 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSRE[9] ,Card status response error bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " CSRE[8] ,Card status response error bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSRE[7] ,Card status response error bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " CSRE[6] ,Card status response error bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSRE[5] ,Card status response error bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " CSRE[4] ,Card status response error bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSRE[3] ,Card status response error bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " CSRE[2] ,Card status response error bit 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSRE[1] ,Card status response error bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " CSRE[0] ,Card status response error bit 0" "No error,Error"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MMCHS_SYSTEST,System Test register"
|
|
bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt" "Low,High"
|
|
bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High"
|
|
bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB ,Set status bit" "0,1"
|
|
bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High"
|
|
bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High"
|
|
group.long 0x2c++0x7
|
|
line.long 0x00 "MMCHS_CON,Configuration Register"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for mmci_dat[1] line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " MIT ,MMC interrupt command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select" "1-bit/4-bit,8-bit"
|
|
bitfld.long 0x00 4. " MODE ,Mode select" "Functional,SYSTEST"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STR ,Stream command" "Block,Stream"
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response" "No response,Response"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode" "No open drain,Open drain"
|
|
line.long 0x04 "MMCHS_PWCNT,Power Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter register"
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "MMCHS_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--10. 1. " BLEN ,Transfer block size"
|
|
line.long 0x04 "MMCHS_ARG,Command Argument Register"
|
|
line.long 0x08 "MMCHS_CMD,Command and Transfer Mode Register"
|
|
bitfld.long 0x08 24.--29. " INDX ,Command index" "CMD0/ACMD0,CMD1/ACMD1,CMD2/ACMD2,CMD3/ACMD3,CMD4/ACMD4,CMD5/ACMD5,CMD6/ACMD6,CMD7/ACMD7,CMD8/ACMD8,CMD9/ACMD9,CMD10/ACMD10,CMD11/ACMD11,CMD12/ACMD12,CMD13/ACMD13,CMD14/ACMD14,CMD15/ACMD15,CMD16/ACMD16,CMD17/ACMD17,CMD18/ACMD18,CMD19/ACMD19,CMD20/ACMD20,CMD21/ACMD21,CMD22/ACMD22,CMD23/ACMD23,CMD24/ACMD24,CMD25/ACMD25,CMD26/ACMD26,CMD27/ACMD27,CMD28/ACMD28,CMD29/ACMD29,CMD30/ACMD30,CMD31/ACMD31,CMD32/ACMD32,CMD33/ACMD33,CMD34/ACMD34,CMD35/ACMD35,CMD36/ACMD36,CMD37/ACMD37,CMD38/ACMD38,CMD39/ACMD39,CMD40/ACMD40,CMD41/ACMD41,CMD42/ACMD42,CMD43/ACMD43,CMD44/ACMD44,CMD45/ACMD45,CMD46/ACMD46,CMD47/ACMD47,CMD48/ACMD48,CMD49/ACMD49,CMD50/ACMD50,CMD51/ACMD51,CMD52/ACMD52,CMD53/ACMD53,CMD54/ACMD54,CMD55/ACMD55,CMD56/ACMD56,CMD57/ACMD57,CMD58/ACMD58,CMD59/ACMD59,CMD60/ACMD60,CMD61/ACMD61,CMD62/ACMD62,CMD63/ACMD63"
|
|
bitfld.long 0x08 22.--23. " CMD_TYPE ,Command type" "Other,Bus Suspend,Function Select,I/O Abort"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DP ,Data present" "No transfer,Transfer"
|
|
bitfld.long 0x08 20. " CICE ,Command Index check enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x08 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACEN ,Auto CMD12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " BCE ,Block count enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DE ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x110++0xf
|
|
line.long 0x00 "MMCHS_RSP10,Command Response[31:0] Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command response"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command response"
|
|
line.long 0x04 "MMCHS_RSP32,Command Response[63:32] Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command response"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command response"
|
|
line.long 0x08 "MMCHS_RSP54,Command Response[95:64] Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command response"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command response"
|
|
line.long 0x0c "MMCHS_RSP76,Command Response[127:96] Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " RSP7 ,Command response"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RSP6 ,Command response"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MMCHS_DATA,Data Register"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "MMCHS_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,The mmci_cmd line level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,The mmci_dat[3] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLEV[2] ,The mmci_dat[2] line level" "0,1"
|
|
bitfld.long 0x00 21. " DLEV[1] ,The mmci_dat[1] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLEV[0] ,The mmci_dat[0] line level" "0,1"
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DLA ,mmci_dat Line active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATI ,Issuing of command using the mmci_dat lines" "Allowed,Not allowed"
|
|
bitfld.long 0x00 0. " CMDI ,Issuing of command using mmci_cmd line" "Allowed,Not allowed"
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "MMCHS_HCTL,Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wakeup event enable for Out-of-Band interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Continue request" "No effect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "MMCHS_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for mmci_dat line" "Completed,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for mmci_cmd line" "Completed,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "Completed,Reset"
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,TCF x 2^15,TCF x 2^16,TCF x 2^17,TCF x 2^18,TCF x 2^19,TCF x 2^20,TCF x 2^21,TCF x 2^22,TCF x 2^23,TCF x 2^24,TCF x 2^25,TCF x 2^26,TCF x 2^27,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable" "Not stable,Stable"
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Stopped,Enabled"
|
|
line.long 0x08 "MMCHS_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No error,Error"
|
|
eventfld.long 0x08 22. " DEB ,Data End Bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " OBI ,Out-Of-Band interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No event,Interrupt"
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " CC ,Command completed" "Not completed,Completed"
|
|
line.long 0x0c "MMCHS_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0C 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x0C 9. " OBI_ENABLE ,Out-of-Band interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "MMCHS_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x10 9. " OBI_SIGEN ,Out-Of-Band interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Black gap event signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Masked,Enabled"
|
|
rgroup.long 0x13c++0x3
|
|
line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "MMCHS_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported"
|
|
bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
hexmask.long.byte 0x00 8.--13. 1. " BCF ,Base clock frequency"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TCF ,Timeout clock frequency"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V"
|
|
rgroup.long 0x1fc++0x3
|
|
line.long 0x00 "MMCHS_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification version number"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIS ,Slot interrupt status" "0,1"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "USB (Universal Serial Bus v2.0)"
|
|
tree "USB 2.0 Controller"
|
|
base asd:0x5c040000
|
|
width 15.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONTROL,USB Control Register"
|
|
bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes"
|
|
bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes"
|
|
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UINT ,USB non-PDR interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,Soft reset" "No reset,Reset"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,USB Status Register"
|
|
bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High"
|
|
width 15.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "AUTO_REQ,USB Auto Req Register"
|
|
bitfld.long 0x00 28.--29. " Rx15_autoreq ,RX endpoint 15 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 26.--27. " Rx14_autoreq ,RX endpoint 14 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " Rx13_autoreq ,RX endpoint 13 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 22.--23. " Rx12_autoreq ,RX endpoint 12 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " Rx11_autoreq ,RX endpoint 11 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 18.--19. " Rx10_autoreq ,RX endpoint 10 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " Rx9_autoreq ,RX endpoint 9 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 14.--15. " Rx8_autoreq ,RX endpoint 8 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " Rx7_autoreq ,RX endpoint 7 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 10.--11. " Rx6_autoreq ,RX endpoint 6 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " Rx5_autoreq ,RX endpoint 5 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 6.--7. " Rx4_autoreq ,RX endpoint 4 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " Rx3_autoreq ,RX endpoint 3 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
bitfld.long 0x00 2.--3. " Rx2_autoreq ,RX endpoint 2 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " Rx1_autoreq ,RX endpoint 1 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req always"
|
|
width 15.
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "TEARDOWN,USB Teardown Register"
|
|
bitfld.long 0x00 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled"
|
|
width 15.
|
|
line.long 0x04 "INTSRCR,USB Endpoint Interrupt Source Register"
|
|
setclrfld.long 0x04 31. 0x08 31. 0x0c 31. " RX[15]_set/clr ,Receive endpoint 15 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 30. 0x08 30. 0x0c 30. " RX[14]_set/clr ,Receive endpoint 14 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x08 29. 0x0c 29. " RX[13]_set/clr ,Receive endpoint 13 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 28. 0x08 28. 0x0c 28. " RX[12]_set/clr ,Receive endpoint 12 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x08 27. 0x0c 27. " RX[11]_set/clr ,Receive endpoint 11 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 26. 0x08 26. 0x0c 26. " RX[10]_set/clr ,Receive endpoint 10 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x08 25. 0x0c 25. " RX[9]_set/clr ,Receive endpoint 9 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 24. 0x08 24. 0x0c 24. " RX[8]_set/clr ,Receive endpoint 8 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x08 23. 0x0c 23. " RX[7]_set/clr ,Receive endpoint 7 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 22. 0x08 22. 0x0c 22. " RX[6]_set/clr ,Receive endpoint 6 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x08 21. 0x0c 21. " RX[5]_set/clr ,Receive endpoint 5 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 20. 0x08 20. 0x0c 20. " RX[4]_set/clr ,Receive endpoint 4 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x08 19. 0x0c 19. " RX[3]_set/clr ,Receive endpoint 3 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 18. 0x08 18. 0x0c 18. " RX[2]_set/clr ,Receive endpoint 2 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x08 17. 0x0c 17. " RX[1]_set/clr ,Receive endpoint 1 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 15. 0x08 15. 0x0c 15. " TX[15]_set/clr ,Transmit endpoint 15 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 14. 0x08 14. 0x0c 14. " TX[14]_set/clr ,Transmit endpoint 14 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 13. 0x08 13. 0x0c 13. " TX[13]_set/clr ,Transmit endpoint 13 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 12. 0x08 12. 0x0c 12. " TX[12]_set/clr ,Transmit endpoint 12 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 11. 0x08 11. 0x0c 11. " TX[11]_set/clr ,Transmit endpoint 11 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 10. 0x08 10. 0x0c 10. " TX[10]_set/clr ,Transmit endpoint 10 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 9. 0x08 9. 0x0c 9. " TX[9]_set/clr ,Transmit endpoint 9 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 8. 0x08 8. 0x0c 8. " TX[8]_set/clr ,Transmit endpoint 8 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0c 7. " TX[3]_set/clr ,Transmit endpoint 7 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0c 6. " TX[6]_set/clr ,Transmit endpoint 6 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0c 5. " TX[5]_set/clr ,Transmit endpoint 5 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0c 4. " TX[4]_set/clr ,Transmit endpoint 4 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0c 3. " TX[3]_set/clr ,Transmit endpoint 3 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0c 2. " TX[2]_set/clr ,Transmit endpoint 2 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0c 1. " TX[1]_set/clr ,Transmit endpoint 1 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0c 0. " EP0_set/clr ,Endpoint 0 interrupt source" "Not caused,Caused"
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "INTMSKR,USB Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " RX[15]_set/clr ,Receive endpoint 15 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " RX[14]_set/clr ,Receive endpoint 14 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " RX[13]_set/clr ,Receive endpoint 13 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " RX[12]_set/clr ,Receive endpoint 12 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " RX[11]_set/clr ,Receive endpoint 11 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " RX[10]_set/clr ,Receive endpoint 10 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " RX[9]_set/clr ,Receive endpoint 9 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " RX[8]_set/clr ,Receive endpoint 8 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " RX[7]_set/clr ,Receive endpoint 7 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " RX[6]_set/clr ,Receive endpoint 6 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " RX[5]_set/clr ,Receive endpoint 5 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " RX[4]_set/clr ,Receive endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " RX[3]_set/clr ,Receive endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " RX[2]_set/clr ,Receive endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RX[1]_set/clr ,Receive endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TX[15]_set/clr ,Transmit endpoint 15 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TX[14]_set/clr ,Transmit endpoint 14 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TX[13]_set/clr ,Transmit endpoint 13 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TX[12]_set/clr ,Transmit endpoint 12 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " TX[11]_set/clr ,Transmit endpoint 11 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " TX[10]_set/clr ,Transmit endpoint 10 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " TX[9]_set/clr ,Transmit endpoint 9 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " TX[8]_set/clr ,Transmit endpoint 8 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TX[3]_set/clr ,Transmit endpoint 7 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TX[6]_set/clr ,Transmit endpoint 6 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TX[5]_set/clr ,Transmit endpoint 5 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TX[4]_set/clr ,Transmit endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TX[3]_set/clr ,Transmit endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX[2]_set/clr ,Transmit endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TX[1]_set/clr ,Transmit endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EP0_set/clr ,Endpoint 0 interrupt source mask" "Not masked,Masked"
|
|
group.long 0x38++0x03
|
|
line.long 0x0 "INTMASKEDR,USB Endpoint Interrupt Source Masked Register"
|
|
bitfld.long 0x00 31. " RX[15] ,Receive endpoint 15 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " RX[14] ,Receive endpoint 14 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RX[13] ,Receive endpoint 13 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " RX[12] ,Receive endpoint 12 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RX[11] ,Receive endpoint 11 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " RX[10] ,Receive endpoint 10 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX[9] ,Receive endpoint 9 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " RX[8] ,Receive endpoint 8 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RX[7] ,Receive endpoint 7 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " RX[6] ,Receive endpoint 6 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX[5] ,Receive endpoint 5 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " RX[4] ,Receive endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX[3] ,Receive endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RX[2] ,Receive endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX[1] ,Receive endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " TX[15] ,Transmit endpoint 15 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX[14] ,Transmit endpoint 14 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " TX[13] ,Transmit endpoint 13 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX[12] ,Transmit endpoint 12 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " TX[11] ,Transmit endpoint 11 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TX[10] ,Transmit endpoint 10 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " TX[9] ,Transmit endpoint 9 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TX[8] ,Transmit endpoint 8 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TX[3] ,Transmit endpoint 7 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TX[6] ,Transmit endpoint 6 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " TX[5] ,Transmit endpoint 5 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX[4] ,Transmit endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " TX[3] ,Transmit endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX[2] ,Transmit endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " TX[1] ,Transmit endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EP0 ,Endpoint 0 interrupt source mask" "Not masked,Masked"
|
|
width 15.
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "COREINTSRC,USB Core Interrupt Source Register"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " USB[8]_set/clr ,USB interrupt 8 source" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " USB[7]_set/clr ,USB interrupt 7 source" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " USB[6]_set/clr ,USB interrupt 6 source" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " USB[5]_set/clr ,USB interrupt 5 source" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " USB[4]_set/clr ,USB interrupt 4 source" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " USB[3]_set/clr ,USB interrupt 3 source" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " USB[2]_set/clr ,USB interrupt 2 source" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " USB[1]_set/clr ,USB interrupt 1 source" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " USB[0]_set/clr ,USB interrupt 0 source" "No interrupt,Interrupt"
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "COREINTMSK,USB Core Interrupt Mask Register"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " USB[8]_set/clr ,USB interrupt 8 source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " USB[7]_set/clr ,USB interrupt 7 source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " USB[6]_set/clr ,USB interrupt 6 source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " USB[5]_set/clr ,USB interrupt 5 source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " USB[4]_set/clr ,USB interrupt 4 source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " USB[3]_set/clr ,USB interrupt 3 source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " USB[2]_set/clr ,USB interrupt 2 source mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " USB[1]_set/clr ,USB interrupt 1 source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " USB[0]_set/clr ,USB interrupt 0 source mask" "Not masked,Masked"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "COREINTMASKED,USB Core Interrupt Source Masked Register"
|
|
bitfld.long 0x00 24. " USB[8] ,USB interrupt 8 source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " USB[7] ,USB interrupt 7 source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " USB[6] ,USB interrupt 6 source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " USB[5] ,USB interrupt 5 source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " USB[4] ,USB interrupt 4 source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " USB[3] ,USB interrupt 3 source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " USB[2] ,USB interrupt 2 source mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " USB[1] ,USB interrupt 1 source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " USB[0] ,USB interrupt 0 source mask" "Not masked,Masked"
|
|
width 15.
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "EOIR,End Of Interrupt vector"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EOI_VECTOR ,End Of Interrupt vector"
|
|
line.long 0x04 "MOP/SOPINTEN,USB MOP/SOP Interrupt Enable Register"
|
|
bitfld.long 0x04 1. " SOP_EN ,DMA sop starvation interrupt is enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MOP_EN ,DMA mop starvation interrupt is enable" "Disabled,Enabled"
|
|
group.long 0x70++0x0b
|
|
line.long 0x00 "TXMODE,USB Tx Mode Register"
|
|
bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
line.long 0x04 "RXMODE,USB Rx Mode Register"
|
|
bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
line.long 0x08 "EPCNTMODE,USB EP Count Mode Register"
|
|
bitfld.long 0x08 28. " EP15_COUNT_MODE ,EP 15 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " EP14_COUNT_MODE ,EP 14 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " EP13_COUNT_MODE ,EP 13 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " EP12_COUNT_MODE ,EP 12 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " EP11_COUNT_MODE ,EP 11 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " EP10_COUNT_MODE ,EP 10 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " EP9_COUNT_MODE ,EP 9 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " EP8_COUNT_MODE ,EP 8 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " EP7_COUNT_MODE ,EP 7 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " EP6_COUNT_MODE ,EP 6 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " EP5_COUNT_MODE ,EP 5 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " EP4_COUNT_MODE ,EP 4 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EP3_COUNT_MODE ,EP 3 Count Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " EP2_COUNT_MODE ,EP 2 Count Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EP1_COUNT_MODE ,EP 1 Count Mode Enable" "Disabled,Enabled"
|
|
width 15.
|
|
group.long 0x80++0x03
|
|
line.long 0x0 "GENRNDISSZ1,Generic RNDIS EP1 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x84++0x03
|
|
line.long 0x0 "GENRNDISSZ2,Generic RNDIS EP2 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP2_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x88++0x03
|
|
line.long 0x0 "GENRNDISSZ3,Generic RNDIS EP3 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP3_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x8C++0x03
|
|
line.long 0x0 "GENRNDISSZ4,Generic RNDIS EP4 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP4_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x90++0x03
|
|
line.long 0x0 "GENRNDISSZ5,Generic RNDIS EP5 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP5_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x94++0x03
|
|
line.long 0x0 "GENRNDISSZ6,Generic RNDIS EP6 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP6_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x98++0x03
|
|
line.long 0x0 "GENRNDISSZ7,Generic RNDIS EP7 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP7_SIZE ,Generic RNDIS packet size"
|
|
group.long 0x9C++0x03
|
|
line.long 0x0 "GENRNDISSZ8,Generic RNDIS EP8 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP8_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xA0++0x03
|
|
line.long 0x0 "GENRNDISSZ9,Generic RNDIS EP9 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP9_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xA4++0x03
|
|
line.long 0x0 "GENRNDISSZ10,Generic RNDIS EP10 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP10_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xA8++0x03
|
|
line.long 0x0 "GENRNDISSZ11,Generic RNDIS EP11 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP11_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xAC++0x03
|
|
line.long 0x0 "GENRNDISSZ12,Generic RNDIS EP12 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP12_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xB0++0x03
|
|
line.long 0x0 "GENRNDISSZ13,Generic RNDIS EP13 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP13_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xB4++0x03
|
|
line.long 0x0 "GENRNDISSZ14,Generic RNDIS EP14 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP14_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xB8++0x03
|
|
line.long 0x0 "GENRNDISSZ15,Generic RNDIS EP15 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP15_SIZE ,Generic RNDIS packet size"
|
|
group.long 0xc0++0x07
|
|
line.long 0x00 "QUEINTTHREEN,USB Queue Interrupt Threshold Enable Register"
|
|
bitfld.long 0x00 1. " QUEUE65_EN ,Queue 65 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " QUEUE63_EN ,Queue 63 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "QUETHRESHOLD0,USB Queue Threshold Register 0"
|
|
hexmask.long.byte 0x04 0.--7. 1. " THRSH_Q63 ,Programmable interrupt threshold"
|
|
wgroup.long 0xc8++0x03
|
|
line.long 0x00 "INTCLR0,USB Interrupt Clear Register 0"
|
|
group.long 0xd4++0x03
|
|
line.long 0x00 "QUETHRESHOLD1,USB Queue Threshold Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " THRSH_Q65 ,Programmable interrupt threshold"
|
|
wgroup.long 0xd8++0x03
|
|
line.long 0x00 "INTCLR1,USB Interrupt Clear Register 1"
|
|
width 18.
|
|
tree "CDMA Registers"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "TXGCR0,CDMA Tx Channel 0 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1800+0x08)++0x0b
|
|
line.long 0x00 "RXGCR0,CDMA Rx Channel 0 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA0,CDMA Rx Channel 0 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB0,CDMA Rx Channel 0 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1820++0x03
|
|
line.long 0x00 "TXGCR1,CDMA Tx Channel 1 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1820+0x08)++0x0b
|
|
line.long 0x00 "RXGCR1,CDMA Rx Channel 1 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA1,CDMA Rx Channel 1 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB1,CDMA Rx Channel 1 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "TXGCR2,CDMA Tx Channel 2 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1840+0x08)++0x0b
|
|
line.long 0x00 "RXGCR2,CDMA Rx Channel 2 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA2,CDMA Rx Channel 2 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB2,CDMA Rx Channel 2 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1860++0x03
|
|
line.long 0x00 "TXGCR3,CDMA Tx Channel 3 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1860+0x08)++0x0b
|
|
line.long 0x00 "RXGCR3,CDMA Rx Channel 3 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA3,CDMA Rx Channel 3 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB3,CDMA Rx Channel 3 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "TXGCR4,CDMA Tx Channel 4 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1880+0x08)++0x0b
|
|
line.long 0x00 "RXGCR4,CDMA Rx Channel 4 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA4,CDMA Rx Channel 4 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB4,CDMA Rx Channel 4 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "TXGCR5,CDMA Tx Channel 5 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x18A0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR5,CDMA Rx Channel 5 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA5,CDMA Rx Channel 5 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB5,CDMA Rx Channel 5 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "TXGCR6,CDMA Tx Channel 6 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x18C0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR6,CDMA Rx Channel 6 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA6,CDMA Rx Channel 6 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB6,CDMA Rx Channel 6 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "TXGCR7,CDMA Tx Channel 7 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x18E0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR7,CDMA Rx Channel 7 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA7,CDMA Rx Channel 7 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB7,CDMA Rx Channel 7 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1900++0x03
|
|
line.long 0x00 "TXGCR8,CDMA Tx Channel 8 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1900+0x08)++0x0b
|
|
line.long 0x00 "RXGCR8,CDMA Rx Channel 8 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA8,CDMA Rx Channel 8 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB8,CDMA Rx Channel 8 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1920++0x03
|
|
line.long 0x00 "TXGCR9,CDMA Tx Channel 9 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1920+0x08)++0x0b
|
|
line.long 0x00 "RXGCR9,CDMA Rx Channel 9 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA9,CDMA Rx Channel 9 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB9,CDMA Rx Channel 9 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1940++0x03
|
|
line.long 0x00 "TXGCR10,CDMA Tx Channel 10 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1940+0x08)++0x0b
|
|
line.long 0x00 "RXGCR10,CDMA Rx Channel 10 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA10,CDMA Rx Channel 10 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB10,CDMA Rx Channel 10 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1960++0x03
|
|
line.long 0x00 "TXGCR11,CDMA Tx Channel 11 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1960+0x08)++0x0b
|
|
line.long 0x00 "RXGCR11,CDMA Rx Channel 11 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA11,CDMA Rx Channel 11 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB11,CDMA Rx Channel 11 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1980++0x03
|
|
line.long 0x00 "TXGCR12,CDMA Tx Channel 12 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1980+0x08)++0x0b
|
|
line.long 0x00 "RXGCR12,CDMA Rx Channel 12 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA12,CDMA Rx Channel 12 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB12,CDMA Rx Channel 12 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x19A0++0x03
|
|
line.long 0x00 "TXGCR13,CDMA Tx Channel 13 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x19A0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR13,CDMA Rx Channel 13 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA13,CDMA Rx Channel 13 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB13,CDMA Rx Channel 13 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x19C0++0x03
|
|
line.long 0x00 "TXGCR14,CDMA Tx Channel 14 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x19C0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR14,CDMA Rx Channel 14 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA14,CDMA Rx Channel 14 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB14,CDMA Rx Channel 14 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x19E0++0x03
|
|
line.long 0x00 "TXGCR15,CDMA Tx Channel 15 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x19E0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR15,CDMA Rx Channel 15 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA15,CDMA Rx Channel 15 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB15,CDMA Rx Channel 15 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1A00++0x03
|
|
line.long 0x00 "TXGCR16,CDMA Tx Channel 16 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1A00+0x08)++0x0b
|
|
line.long 0x00 "RXGCR16,CDMA Rx Channel 16 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA16,CDMA Rx Channel 16 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB16,CDMA Rx Channel 16 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1A20++0x03
|
|
line.long 0x00 "TXGCR17,CDMA Tx Channel 17 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1A20+0x08)++0x0b
|
|
line.long 0x00 "RXGCR17,CDMA Rx Channel 17 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA17,CDMA Rx Channel 17 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB17,CDMA Rx Channel 17 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1A40++0x03
|
|
line.long 0x00 "TXGCR18,CDMA Tx Channel 18 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1A40+0x08)++0x0b
|
|
line.long 0x00 "RXGCR18,CDMA Rx Channel 18 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA18,CDMA Rx Channel 18 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB18,CDMA Rx Channel 18 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1A60++0x03
|
|
line.long 0x00 "TXGCR19,CDMA Tx Channel 19 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1A60+0x08)++0x0b
|
|
line.long 0x00 "RXGCR19,CDMA Rx Channel 19 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA19,CDMA Rx Channel 19 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB19,CDMA Rx Channel 19 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1A80++0x03
|
|
line.long 0x00 "TXGCR20,CDMA Tx Channel 20 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1A80+0x08)++0x0b
|
|
line.long 0x00 "RXGCR20,CDMA Rx Channel 20 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA20,CDMA Rx Channel 20 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB20,CDMA Rx Channel 20 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1AA0++0x03
|
|
line.long 0x00 "TXGCR21,CDMA Tx Channel 21 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1AA0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR21,CDMA Rx Channel 21 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA21,CDMA Rx Channel 21 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB21,CDMA Rx Channel 21 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1AC0++0x03
|
|
line.long 0x00 "TXGCR22,CDMA Tx Channel 22 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1AC0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR22,CDMA Rx Channel 22 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA22,CDMA Rx Channel 22 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB22,CDMA Rx Channel 22 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1AE0++0x03
|
|
line.long 0x00 "TXGCR23,CDMA Tx Channel 23 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1AE0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR23,CDMA Rx Channel 23 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA23,CDMA Rx Channel 23 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB23,CDMA Rx Channel 23 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1B00++0x03
|
|
line.long 0x00 "TXGCR24,CDMA Tx Channel 24 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1B00+0x08)++0x0b
|
|
line.long 0x00 "RXGCR24,CDMA Rx Channel 24 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA24,CDMA Rx Channel 24 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB24,CDMA Rx Channel 24 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1B20++0x03
|
|
line.long 0x00 "TXGCR25,CDMA Tx Channel 25 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1B20+0x08)++0x0b
|
|
line.long 0x00 "RXGCR25,CDMA Rx Channel 25 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA25,CDMA Rx Channel 25 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB25,CDMA Rx Channel 25 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1B40++0x03
|
|
line.long 0x00 "TXGCR26,CDMA Tx Channel 26 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1B40+0x08)++0x0b
|
|
line.long 0x00 "RXGCR26,CDMA Rx Channel 26 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA26,CDMA Rx Channel 26 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB26,CDMA Rx Channel 26 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1B60++0x03
|
|
line.long 0x00 "TXGCR27,CDMA Tx Channel 27 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1B60+0x08)++0x0b
|
|
line.long 0x00 "RXGCR27,CDMA Rx Channel 27 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA27,CDMA Rx Channel 27 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB27,CDMA Rx Channel 27 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1B80++0x03
|
|
line.long 0x00 "TXGCR28,CDMA Tx Channel 28 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1B80+0x08)++0x0b
|
|
line.long 0x00 "RXGCR28,CDMA Rx Channel 28 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA28,CDMA Rx Channel 28 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB28,CDMA Rx Channel 28 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1BA0++0x03
|
|
line.long 0x00 "TXGCR29,CDMA Tx Channel 29 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default Queue Manager Number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long (0x1BA0+0x08)++0x0b
|
|
line.long 0x00 "RXGCR29,CDMA Rx Channel 29 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
line.long 0x04 "RXHPCRA29,CDMA Rx Channel 29 Host Packet Configuration Register A"
|
|
bitfld.long 0x04 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
line.long 0x08 "RXHPCRB29,CDMA Rx Channel 29 Host Packet Configuration Register B"
|
|
bitfld.long 0x08 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
width 18.
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "DMA_SCHED_CTRL,CDMA Scheduler Control Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Enable bit for the scheduler and is encoded" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LAST_ENTRY ,Last valid entry in the scheduler table"
|
|
group.long 0x2800++0xff
|
|
line.long 0x0 "ENTRY[0],CDMA Scheduler Table Word 0 Register"
|
|
bitfld.long 0x0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "ENTRY[1],CDMA Scheduler Table Word 1 Register"
|
|
bitfld.long 0x4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "ENTRY[2],CDMA Scheduler Table Word 2 Register"
|
|
bitfld.long 0x8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "ENTRY[3],CDMA Scheduler Table Word 3 Register"
|
|
bitfld.long 0xC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "ENTRY[4],CDMA Scheduler Table Word 4 Register"
|
|
bitfld.long 0x10 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "ENTRY[5],CDMA Scheduler Table Word 5 Register"
|
|
bitfld.long 0x14 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "ENTRY[6],CDMA Scheduler Table Word 6 Register"
|
|
bitfld.long 0x18 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "ENTRY[7],CDMA Scheduler Table Word 7 Register"
|
|
bitfld.long 0x1C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "ENTRY[8],CDMA Scheduler Table Word 8 Register"
|
|
bitfld.long 0x20 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x24 "ENTRY[9],CDMA Scheduler Table Word 9 Register"
|
|
bitfld.long 0x24 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x28 "ENTRY[10],CDMA Scheduler Table Word 10 Register"
|
|
bitfld.long 0x28 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "ENTRY[11],CDMA Scheduler Table Word 11 Register"
|
|
bitfld.long 0x2C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "ENTRY[12],CDMA Scheduler Table Word 12 Register"
|
|
bitfld.long 0x30 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "ENTRY[13],CDMA Scheduler Table Word 13 Register"
|
|
bitfld.long 0x34 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "ENTRY[14],CDMA Scheduler Table Word 14 Register"
|
|
bitfld.long 0x38 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "ENTRY[15],CDMA Scheduler Table Word 15 Register"
|
|
bitfld.long 0x3C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "ENTRY[16],CDMA Scheduler Table Word 16 Register"
|
|
bitfld.long 0x40 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "ENTRY[17],CDMA Scheduler Table Word 17 Register"
|
|
bitfld.long 0x44 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "ENTRY[18],CDMA Scheduler Table Word 18 Register"
|
|
bitfld.long 0x48 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "ENTRY[19],CDMA Scheduler Table Word 19 Register"
|
|
bitfld.long 0x4C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x50 "ENTRY[20],CDMA Scheduler Table Word 20 Register"
|
|
bitfld.long 0x50 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x54 "ENTRY[21],CDMA Scheduler Table Word 21 Register"
|
|
bitfld.long 0x54 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x58 "ENTRY[22],CDMA Scheduler Table Word 22 Register"
|
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bitfld.long 0x58 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x58 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x58 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x58 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x58 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x58 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x58 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x58 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x5C "ENTRY[23],CDMA Scheduler Table Word 23 Register"
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bitfld.long 0x5C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x5C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x5C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x5C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x5C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x5C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x5C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x5C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x60 "ENTRY[24],CDMA Scheduler Table Word 24 Register"
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bitfld.long 0x60 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x60 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x60 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x60 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x60 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x60 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x60 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x60 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x64 "ENTRY[25],CDMA Scheduler Table Word 25 Register"
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bitfld.long 0x64 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x64 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x64 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x64 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x64 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x64 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x64 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x64 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x68 "ENTRY[26],CDMA Scheduler Table Word 26 Register"
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bitfld.long 0x68 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x68 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x68 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x68 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x68 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x68 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x68 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x68 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x6C "ENTRY[27],CDMA Scheduler Table Word 27 Register"
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bitfld.long 0x6C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x6C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x6C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x6C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x6C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x6C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x6C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x6C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x70 "ENTRY[28],CDMA Scheduler Table Word 28 Register"
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bitfld.long 0x70 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x70 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x70 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x70 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x70 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x70 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x70 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x70 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x74 "ENTRY[29],CDMA Scheduler Table Word 29 Register"
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bitfld.long 0x74 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x74 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x74 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x74 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x74 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x74 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x74 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x74 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x78 "ENTRY[30],CDMA Scheduler Table Word 30 Register"
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bitfld.long 0x78 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x78 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x78 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x78 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x78 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x78 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x78 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x78 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x7C "ENTRY[31],CDMA Scheduler Table Word 31 Register"
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bitfld.long 0x7C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x7C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x7C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x7C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x7C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x7C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x7C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x7C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x80 "ENTRY[32],CDMA Scheduler Table Word 32 Register"
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bitfld.long 0x80 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x80 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x80 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x80 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x80 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x80 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x80 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x80 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x84 "ENTRY[33],CDMA Scheduler Table Word 33 Register"
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bitfld.long 0x84 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x84 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x84 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x84 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x84 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x84 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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textline " "
|
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bitfld.long 0x84 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x84 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x88 "ENTRY[34],CDMA Scheduler Table Word 34 Register"
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bitfld.long 0x88 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
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bitfld.long 0x88 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
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bitfld.long 0x88 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
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bitfld.long 0x88 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
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bitfld.long 0x88 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
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bitfld.long 0x88 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x8C "ENTRY[35],CDMA Scheduler Table Word 35 Register"
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bitfld.long 0x8C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
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bitfld.long 0x8C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x90 "ENTRY[36],CDMA Scheduler Table Word 36 Register"
|
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bitfld.long 0x90 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x94 "ENTRY[37],CDMA Scheduler Table Word 37 Register"
|
|
bitfld.long 0x94 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x98 "ENTRY[38],CDMA Scheduler Table Word 38 Register"
|
|
bitfld.long 0x98 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x9C "ENTRY[39],CDMA Scheduler Table Word 39 Register"
|
|
bitfld.long 0x9C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA0 "ENTRY[40],CDMA Scheduler Table Word 40 Register"
|
|
bitfld.long 0xA0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA4 "ENTRY[41],CDMA Scheduler Table Word 41 Register"
|
|
bitfld.long 0xA4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA8 "ENTRY[42],CDMA Scheduler Table Word 42 Register"
|
|
bitfld.long 0xA8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xAC "ENTRY[43],CDMA Scheduler Table Word 43 Register"
|
|
bitfld.long 0xAC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB0 "ENTRY[44],CDMA Scheduler Table Word 44 Register"
|
|
bitfld.long 0xB0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB4 "ENTRY[45],CDMA Scheduler Table Word 45 Register"
|
|
bitfld.long 0xB4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB8 "ENTRY[46],CDMA Scheduler Table Word 46 Register"
|
|
bitfld.long 0xB8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xBC "ENTRY[47],CDMA Scheduler Table Word 47 Register"
|
|
bitfld.long 0xBC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC0 "ENTRY[48],CDMA Scheduler Table Word 48 Register"
|
|
bitfld.long 0xC0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC4 "ENTRY[49],CDMA Scheduler Table Word 49 Register"
|
|
bitfld.long 0xC4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC8 "ENTRY[50],CDMA Scheduler Table Word 50 Register"
|
|
bitfld.long 0xC8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xCC "ENTRY[51],CDMA Scheduler Table Word 51 Register"
|
|
bitfld.long 0xCC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD0 "ENTRY[52],CDMA Scheduler Table Word 52 Register"
|
|
bitfld.long 0xD0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD4 "ENTRY[53],CDMA Scheduler Table Word 53 Register"
|
|
bitfld.long 0xD4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD8 "ENTRY[54],CDMA Scheduler Table Word 54 Register"
|
|
bitfld.long 0xD8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xDC "ENTRY[55],CDMA Scheduler Table Word 55 Register"
|
|
bitfld.long 0xDC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE0 "ENTRY[56],CDMA Scheduler Table Word 56 Register"
|
|
bitfld.long 0xE0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE4 "ENTRY[57],CDMA Scheduler Table Word 57 Register"
|
|
bitfld.long 0xE4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE8 "ENTRY[58],CDMA Scheduler Table Word 58 Register"
|
|
bitfld.long 0xE8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xEC "ENTRY[59],CDMA Scheduler Table Word 59 Register"
|
|
bitfld.long 0xEC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF0 "ENTRY[60],CDMA Scheduler Table Word 60 Register"
|
|
bitfld.long 0xF0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF4 "ENTRY[61],CDMA Scheduler Table Word 61 Register"
|
|
bitfld.long 0xF4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF8 "ENTRY[62],CDMA Scheduler Table Word 62 Register"
|
|
bitfld.long 0xF8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xFC "ENTRY[63],CDMA Scheduler Table Word 63 Register"
|
|
bitfld.long 0xFC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
textline " "
|
|
width 16.
|
|
rgroup.long 0x3000++0x03
|
|
line.long 0x00 "INTDREVISION,INTD Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--29. 1. " MODID ,Module ID field"
|
|
hexmask.long.byte 0x00 11.--15. 1. " REVRTL ,RTL revision"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " REVMAJ ,Major revision"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision"
|
|
group.long 0x3010++0x03
|
|
line.long 0x00 "INTDEOI,INTD EOI Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EOI_VECTOR ,EOI Vector value"
|
|
rgroup.long 0x3014++0x03
|
|
line.long 0x00 "INTDEOIINTVECT,INTD EOI Interrupt Vector Register"
|
|
rgroup.long 0x3200++0x0f
|
|
line.long 0x00 "INTDSTATUS0,INTD Status Register 0"
|
|
bitfld.long 0x00 1. " RX_SBUF ,Rx MOP Descriptor Starvation Status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " RX_SDES ,Rx SOP Descriptor Starvation Status" "Not pending,Pending"
|
|
line.long 0x04 "INTDSTATUS1,INTD Status Register 1"
|
|
bitfld.long 0x04 9. " USB ,USB Core Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " USB_INT8 ,USB Interrupt 8 Status (DRVVBUS level change)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " USB_INT7 ,USB Interrupt 7 Status (VBUS < VBUS valid threshold)" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " USB_INT6 ,USB Interrupt 6 Status (SRP detected)" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " USB_INT5 ,USB Interrupt 5 Status (Device disconnected (host mode))" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " USB_INT4 ,USB Interrupt 4 Status (Device connected (host mode))" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 3. " USB_INT3 ,USB Interrupt 3 Status (SOF started)" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " USB_INT2 ,USB Interrupt 2 Status (Reset signaling detected (peripheral mode) Babble detected (host mode))" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " USB_INT1 ,USB Interrupt 1 Status (Resume signaling detected)" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " USB_INT0 ,USB Interrupt 0 Status (Suspend signaling detected)" "Not pending,Pending"
|
|
line.long 0x08 "INTDSTATUS2,INTD Status Register 2"
|
|
bitfld.long 0x08 30. " RX_EP15 ,USB RX EP15 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " RX_EP14 ,USB RX EP14 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 28. " RX_EP13 ,USB RX EP13 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " RX_EP12 ,USB RX EP12 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 26. " RX_EP11 ,USB RX EP11 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 25. " RX_EP10 ,USB RX EP10 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 24. " RX_EP9 ,USB RX EP9 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " RX_EP8 ,USB RX EP8 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 22. " RX_EP7 ,USB RX EP7 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 21. " RX_EP6 ,USB RX EP6 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RX_EP5 ,USB RX EP5 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 19. " RX_EP4 ,USB RX EP4 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 18. " RX_EP3 ,USB RX EP3 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " RX_EP2 ,USB RX EP2 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " RX_EP1 ,USB RX EP1 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " TX_EP15 ,USB TX EP15 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 14. " TX_EP14 ,USB TX EP14 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 13. " TX_EP13 ,USB TX EP13 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 12. " TX_EP12 ,USB TX EP12 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 11. " TX_EP11 ,USB TX EP11 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 10. " TX_EP10 ,USB TX EP10 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " TX_EP9 ,USB TX EP9 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 8. " TX_EP8 ,USB TX EP8 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 7. " TX_EP7 ,USB TX EP7 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 6. " TX_EP6 ,USB TX EP6 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 5. " TX_EP5 ,USB TX EP5 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TX_EP4 ,USB TX EP4 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " TX_EP3 ,USB TX EP3 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TX_EP2 ,USB TX EP2 Interrupt Status" "Not pending,Pending"
|
|
bitfld.long 0x08 1. " TX_EP1 ,USB TX EP1 Interrupt Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TX_EP0 ,USB TX EP0 Interrupt Status" "Not pending,Pending"
|
|
line.long 0x0c "INTDSTATUS3,INTD Status Register 3"
|
|
bitfld.long 0x0c 15. " COMP_INT[66] ,Completion Interrupts for Queues 66" "Not pending,Pending"
|
|
bitfld.long 0x0c 14. " COMP_INT[65] ,Completion Interrupts for Queues 65" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " COMP_INT[64] ,Completion Interrupts for Queues 64" "Not pending,Pending"
|
|
bitfld.long 0x0c 0. " COMP_INT[63] ,Completion Interrupts for Queues 63" "Not pending,Pending"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "INTDSTATUSCLR0,INTD Status Clear Register 0"
|
|
eventfld.long 0x00 1. " STATUS_CLR[1] ,RX MOP Descriptor interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " STATUS_CLR[0] ,RX SOP Descriptor Starve interrupt status" "Not pending,Pending"
|
|
width 15.
|
|
tree "Queue Manager (QMGR) Registers"
|
|
rgroup.long 0x4000++0x3
|
|
line.long 0x00 "QMGRREVID,Queue Manager Revision Identification Register"
|
|
hexmask.long.byte 0x00 30.--31. 1. " SCHEME ,Scheme"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Function"
|
|
hexmask.long.byte 0x00 11.--15. 1. " REVRTL ,RTL revision"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--10. 1. " REVMAJ ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " REVCUSTOM ,Custom revision"
|
|
hexmask.long.byte 0x00 0.--5. 1. " REVMIN ,Minor revision"
|
|
wgroup.long 0x4008++0x03
|
|
line.long 0x00 "DIVERSION,Queue Manager Queue Diversion Register"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number"
|
|
hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number"
|
|
hgroup.long 0x4020++0x03
|
|
hide.long 0x00 "FDBSC0,Queue Manager Free Descriptor/Buffer Starvation Count Register 0"
|
|
in
|
|
hgroup.long 0x4024++0x03
|
|
hide.long 0x00 "FDBSC1,Queue Manager Free Descriptor/Buffer Starvation Count Register 1"
|
|
in
|
|
hgroup.long 0x4028++0x03
|
|
hide.long 0x00 "FDBSC2,Queue Manager Free Descriptor/Buffer Starvation Count Register 2"
|
|
in
|
|
hgroup.long 0x402C++0x03
|
|
hide.long 0x00 "FDBSC3,Queue Manager Free Descriptor/Buffer Starvation Count Register 3"
|
|
in
|
|
hgroup.long 0x4030++0x03
|
|
hide.long 0x00 "FDBSC4,Queue Manager Free Descriptor/Buffer Starvation Count Register 4"
|
|
in
|
|
hgroup.long 0x4034++0x03
|
|
hide.long 0x00 "FDBSC5,Queue Manager Free Descriptor/Buffer Starvation Count Register 5"
|
|
in
|
|
hgroup.long 0x4038++0x03
|
|
hide.long 0x00 "FDBSC6,Queue Manager Free Descriptor/Buffer Starvation Count Register 6"
|
|
in
|
|
hgroup.long 0x403C++0x03
|
|
hide.long 0x00 "FDBSC7,Queue Manager Free Descriptor/Buffer Starvation Count Register 7"
|
|
in
|
|
group.long 0x4080++0xb
|
|
line.long 0x00 "LRAM0BASE,Queue Manager Linking RAM Region 0 Base Address Register"
|
|
line.long 0x04 "LRAM0SIZE,Queue Manager Linking RAM Region 0 Size Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " REGION0_SIZE ,Number of entries that are contained in the linking RAM region 0"
|
|
line.long 0x08 "LRAM1BASE,Queue Manager Linking RAM Region 1 Base Address Register"
|
|
rgroup.long 0x4090++0xb
|
|
line.long 0x00 "PEND0,Queue Manager Queue Pending Register 0"
|
|
line.long 0x04 "PEND1,Queue Manager Queue Pending Register 1"
|
|
line.long 0x08 "PEND2,Queue Manager Queue Pending Register 2"
|
|
group.long 0x5000++0x7
|
|
line.long 0x00 "QMEMRBASE[0],Queue Manager Memory Region 0 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[0],Queue Manager Memory Region 0 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5010++0x7
|
|
line.long 0x00 "QMEMRBASE[1],Queue Manager Memory Region 1 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[1],Queue Manager Memory Region 1 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5020++0x7
|
|
line.long 0x00 "QMEMRBASE[2],Queue Manager Memory Region 2 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[2],Queue Manager Memory Region 2 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5030++0x7
|
|
line.long 0x00 "QMEMRBASE[3],Queue Manager Memory Region 3 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[3],Queue Manager Memory Region 3 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5040++0x7
|
|
line.long 0x00 "QMEMRBASE[4],Queue Manager Memory Region 4 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[4],Queue Manager Memory Region 4 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5050++0x7
|
|
line.long 0x00 "QMEMRBASE[5],Queue Manager Memory Region 5 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[5],Queue Manager Memory Region 5 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5060++0x7
|
|
line.long 0x00 "QMEMRBASE[6],Queue Manager Memory Region 6 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[6],Queue Manager Memory Region 6 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5070++0x7
|
|
line.long 0x00 "QMEMRBASE[7],Queue Manager Memory Region 7 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[7],Queue Manager Memory Region 7 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5080++0x7
|
|
line.long 0x00 "QMEMRBASE[8],Queue Manager Memory Region 8 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[8],Queue Manager Memory Region 8 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5090++0x7
|
|
line.long 0x00 "QMEMRBASE[9],Queue Manager Memory Region 9 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[9],Queue Manager Memory Region 9 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50A0++0x7
|
|
line.long 0x00 "QMEMRBASE[10],Queue Manager Memory Region 10 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[10],Queue Manager Memory Region 10 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50B0++0x7
|
|
line.long 0x00 "QMEMRBASE[11],Queue Manager Memory Region 11 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[11],Queue Manager Memory Region 11 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50C0++0x7
|
|
line.long 0x00 "QMEMRBASE[12],Queue Manager Memory Region 12 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[12],Queue Manager Memory Region 12 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50D0++0x7
|
|
line.long 0x00 "QMEMRBASE[13],Queue Manager Memory Region 13 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[13],Queue Manager Memory Region 13 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50E0++0x7
|
|
line.long 0x00 "QMEMRBASE[14],Queue Manager Memory Region 14 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[14],Queue Manager Memory Region 14 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50F0++0x7
|
|
line.long 0x00 "QMEMRBASE[15],Queue Manager Memory Region 15 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[15],Queue Manager Memory Region 15 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
rgroup.long 0x6000++0x7
|
|
line.long 0x00 "QSTATA[0],Queue Manager Queue 0 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[0],Queue Manager Queue 0 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6000+0x08)++0x07
|
|
line.long 0x00 "QSTATC[0],Queue Manager Queue 0 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[0],Queue Manager Queue 0 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6800++0x0b
|
|
line.long 0x00 "QSTATA[0],Queue Manager Queue 0 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[0],Queue Manager Queue 0 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[0],Queue Manager Queue 0 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6010++0x7
|
|
line.long 0x00 "QSTATA[1],Queue Manager Queue 1 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[1],Queue Manager Queue 1 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6010+0x08)++0x07
|
|
line.long 0x00 "QSTATC[1],Queue Manager Queue 1 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[1],Queue Manager Queue 1 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6810++0x0b
|
|
line.long 0x00 "QSTATA[1],Queue Manager Queue 1 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[1],Queue Manager Queue 1 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[1],Queue Manager Queue 1 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6020++0x7
|
|
line.long 0x00 "QSTATA[2],Queue Manager Queue 2 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[2],Queue Manager Queue 2 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6020+0x08)++0x07
|
|
line.long 0x00 "QSTATC[2],Queue Manager Queue 2 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[2],Queue Manager Queue 2 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6820++0x0b
|
|
line.long 0x00 "QSTATA[2],Queue Manager Queue 2 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[2],Queue Manager Queue 2 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[2],Queue Manager Queue 2 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6030++0x7
|
|
line.long 0x00 "QSTATA[3],Queue Manager Queue 3 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[3],Queue Manager Queue 3 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6030+0x08)++0x07
|
|
line.long 0x00 "QSTATC[3],Queue Manager Queue 3 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[3],Queue Manager Queue 3 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6830++0x0b
|
|
line.long 0x00 "QSTATA[3],Queue Manager Queue 3 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[3],Queue Manager Queue 3 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[3],Queue Manager Queue 3 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6040++0x7
|
|
line.long 0x00 "QSTATA[4],Queue Manager Queue 4 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[4],Queue Manager Queue 4 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6040+0x08)++0x07
|
|
line.long 0x00 "QSTATC[4],Queue Manager Queue 4 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[4],Queue Manager Queue 4 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6840++0x0b
|
|
line.long 0x00 "QSTATA[4],Queue Manager Queue 4 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[4],Queue Manager Queue 4 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[4],Queue Manager Queue 4 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6050++0x7
|
|
line.long 0x00 "QSTATA[5],Queue Manager Queue 5 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[5],Queue Manager Queue 5 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6050+0x08)++0x07
|
|
line.long 0x00 "QSTATC[5],Queue Manager Queue 5 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[5],Queue Manager Queue 5 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6850++0x0b
|
|
line.long 0x00 "QSTATA[5],Queue Manager Queue 5 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[5],Queue Manager Queue 5 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[5],Queue Manager Queue 5 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6060++0x7
|
|
line.long 0x00 "QSTATA[6],Queue Manager Queue 6 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[6],Queue Manager Queue 6 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6060+0x08)++0x07
|
|
line.long 0x00 "QSTATC[6],Queue Manager Queue 6 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[6],Queue Manager Queue 6 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6860++0x0b
|
|
line.long 0x00 "QSTATA[6],Queue Manager Queue 6 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[6],Queue Manager Queue 6 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[6],Queue Manager Queue 6 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6070++0x7
|
|
line.long 0x00 "QSTATA[7],Queue Manager Queue 7 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[7],Queue Manager Queue 7 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6070+0x08)++0x07
|
|
line.long 0x00 "QSTATC[7],Queue Manager Queue 7 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[7],Queue Manager Queue 7 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6870++0x0b
|
|
line.long 0x00 "QSTATA[7],Queue Manager Queue 7 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[7],Queue Manager Queue 7 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[7],Queue Manager Queue 7 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6080++0x7
|
|
line.long 0x00 "QSTATA[8],Queue Manager Queue 8 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[8],Queue Manager Queue 8 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6080+0x08)++0x07
|
|
line.long 0x00 "QSTATC[8],Queue Manager Queue 8 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[8],Queue Manager Queue 8 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6880++0x0b
|
|
line.long 0x00 "QSTATA[8],Queue Manager Queue 8 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[8],Queue Manager Queue 8 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[8],Queue Manager Queue 8 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x6090++0x7
|
|
line.long 0x00 "QSTATA[9],Queue Manager Queue 9 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[9],Queue Manager Queue 9 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x6090+0x08)++0x07
|
|
line.long 0x00 "QSTATC[9],Queue Manager Queue 9 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[9],Queue Manager Queue 9 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6890++0x0b
|
|
line.long 0x00 "QSTATA[9],Queue Manager Queue 9 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[9],Queue Manager Queue 9 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[9],Queue Manager Queue 9 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x60A0++0x7
|
|
line.long 0x00 "QSTATA[10],Queue Manager Queue 10 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[10],Queue Manager Queue 10 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x60A0+0x08)++0x07
|
|
line.long 0x00 "QSTATC[10],Queue Manager Queue 10 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[10],Queue Manager Queue 10 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68A0++0x0b
|
|
line.long 0x00 "QSTATA[10],Queue Manager Queue 10 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[10],Queue Manager Queue 10 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[10],Queue Manager Queue 10 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x60B0++0x7
|
|
line.long 0x00 "QSTATA[11],Queue Manager Queue 11 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[11],Queue Manager Queue 11 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x60B0+0x08)++0x07
|
|
line.long 0x00 "QSTATC[11],Queue Manager Queue 11 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[11],Queue Manager Queue 11 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68B0++0x0b
|
|
line.long 0x00 "QSTATA[11],Queue Manager Queue 11 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[11],Queue Manager Queue 11 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[11],Queue Manager Queue 11 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x60C0++0x7
|
|
line.long 0x00 "QSTATA[12],Queue Manager Queue 12 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[12],Queue Manager Queue 12 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x60C0+0x08)++0x07
|
|
line.long 0x00 "QSTATC[12],Queue Manager Queue 12 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[12],Queue Manager Queue 12 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68C0++0x0b
|
|
line.long 0x00 "QSTATA[12],Queue Manager Queue 12 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[12],Queue Manager Queue 12 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[12],Queue Manager Queue 12 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x60D0++0x7
|
|
line.long 0x00 "QSTATA[13],Queue Manager Queue 13 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[13],Queue Manager Queue 13 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x60D0+0x08)++0x07
|
|
line.long 0x00 "QSTATC[13],Queue Manager Queue 13 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[13],Queue Manager Queue 13 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68D0++0x0b
|
|
line.long 0x00 "QSTATA[13],Queue Manager Queue 13 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[13],Queue Manager Queue 13 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[13],Queue Manager Queue 13 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x60E0++0x7
|
|
line.long 0x00 "QSTATA[14],Queue Manager Queue 14 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[14],Queue Manager Queue 14 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x60E0+0x08)++0x07
|
|
line.long 0x00 "QSTATC[14],Queue Manager Queue 14 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[14],Queue Manager Queue 14 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68E0++0x0b
|
|
line.long 0x00 "QSTATA[14],Queue Manager Queue 14 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[14],Queue Manager Queue 14 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[14],Queue Manager Queue 14 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
rgroup.long 0x60F0++0x7
|
|
line.long 0x00 "QSTATA[15],Queue Manager Queue 15 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[15],Queue Manager Queue 15 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
group.long (0x60F0+0x08)++0x07
|
|
line.long 0x00 "QSTATC[15],Queue Manager Queue 15 Status Register C"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATD[15],Queue Manager Queue 15 Status Register D"
|
|
hexmask.long 0x04 5.--31. 0x20 " DESC_PTR ,Descriptor pointer"
|
|
bitfld.long 0x04 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68F0++0x0b
|
|
line.long 0x00 "QSTATA[15],Queue Manager Queue 15 Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[15],Queue Manager Queue 15 Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[15],Queue Manager Queue 15 Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "High-Speed USB Host Subsystem"
|
|
tree "USBTLL"
|
|
base ad:0x48062000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "USBTLL_REVISION,OCP Standard Revision Number"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MINOR ,Minor revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "USBTLL_SYSCONFIG,OCP Standard System Configuration Register"
|
|
bitfld.long 0x00 8. " CACTIVITY ,Enable autogating of OCP-derived internal clocks" "Off,On"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Asynchronous wakeup generation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Module software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal autogating control" "Running,Cut off"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "USBTLL_SYSSTATUS,OCP Standard System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Indicates when the module has entirely come out of reset" "Ongoing,Done"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "USBTLL_IRQSTATUS,OCP Standard IRQ Status Vector"
|
|
bitfld.long 0x00 2. " ACCESS_ERROR ,Access error to ULPI register over OCP" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " FCLK_END ,Functional clock is no longer requested for USB clocking" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCLK_START ,Functional clock is requested for USB clocking" "Not pending,Pending"
|
|
line.long 0x04 "USBTLL_IRQENABLE,OCP Standard IRQ Enable Vector"
|
|
bitfld.long 0x04 2. " ACCESS_ERROR_EN ,Enable access error to ULPI register over OCP" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " FCLK_END_EN ,Enable functional clock is no longer requested for USB clocking" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FCLK_START_EN ,Enable functional clock is requested for USB clocking" "Masked,Enabled"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "TLL_SHARED_CONF,Common Control Register For All TLL Channels"
|
|
bitfld.long 0x00 6. " USB_90D_DDR_EN ,Software enable/disable of the 90-degree phase shift scheme" "Aligned with CLK,Delayed by 90"
|
|
bitfld.long 0x00 5. " USB_180D_SDR_EN ,Software enable/disable of the 180-degree phase shift scheme" "Aligned with CLK,Delayed by 180"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " USB_DIVRATIO ,division ratio from functional clock to USB clock" "2**0=1,2**1=2,2**2=4,2**3=8,2**4=16,2**5=32,2**6=64,2**7=128"
|
|
bitfld.long 0x00 1. " FCLK_REQ ,Functional clock request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCLK_IS_ON ,Status of the functional clock input" "Not guaranteed,Guaranteed"
|
|
tree "Channel 0"
|
|
width 21.
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TLL_CHANNEL_CONF_0,Control And Status Register For Channel 0"
|
|
bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/Low speed serial modes" "Single-ended 0,Full-speed J,Full-speed K,Single-ended 1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interfaces mode select" "6-pin unidirectional PHY i/f Dat/Se0,6-pin unidirectional PHY i/f Dp/Dm,3-pin bidirectional PHY i/f,4-pin bidirectional PHY i/f,6-pin unidirectional TLL Dat/Se0,6-pin unidirectional TLL Dp/Dm,3-pin bidirectional TLL,4-pin bidirectional TLL,Reserved,Reserved,2-pin bidirectional TLL Dat/Se0,2-pin bidirectional TLL Dp/Dm,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test" "Differential value,SE0"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test" "Full-speed K,Full-speed J"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test" "TestTXDat/Se0,TX Hiz"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial" "Not driven,Driven to 5V"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIAUTOIDLE ,Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIAUTOIDLE ,Allow the UTMI clock to be stopped when UTMII goes to suspended mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ULPIDDRMODE ,Select single/double data rate" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode" "LINK,PHY"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL" "Low speed,Full speed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect" "Unconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes" "Detach,Attach"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end seen by UTMI side of TLL" "UTMI peripheral/ULPI host,UTMI host/ULPI peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection" "UTMI-to-ULPI TLL,UTMI-to-serial,Transparent UTMI,No mode selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANEN ,Active-high channel enable" "Disabled,Enabled"
|
|
rgroup.byte 0x800++0x3
|
|
line.byte 0x00 "ULPI_VENDOR_ID_LO_0,Lower Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x01 "ULPI_VENDOR_ID_HI_0,Upper Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x02 "ULPI_PRODUCT_ID_LO_0,Lower Byte Of Vendor-Chosen Product ID Value"
|
|
line.byte 0x03 "ULPI_PRODUCT_ID_HI_0,Upper Byte Of Vendor-Chosen Product ID Value"
|
|
width 29.
|
|
group.byte (0x800+0x4)++0x2
|
|
line.byte 0x00 "ULPI_FUNCTION_CTRL_0,Controls UTMI Function Settings Of The PHY"
|
|
bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend" "Low-power,Not in low-power"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit" "Normal,Non-driving,Disable bit-stuff/NRZI encoding,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations" "HS,FS"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed" "HS,FS,LS,FS for LS packets"
|
|
line.byte 0x01 "ULPI_FUNCTION_CTRL_SET_0,Controls UTMI Function Settings Of The PHY"
|
|
line.byte 0x02 "ULPI_FUNCTION_CTRL_CLR_0,Controls UTMI Function Settings Of The PHY"
|
|
group.byte (0x800+0x7)++0x2
|
|
line.byte 0x00 "ULPI_INTERFACE_CTRL_0,Enables Alternative Interfaces And PHY Features"
|
|
bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin Serial Mode" "Normal,3-pin serial"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin Serial Mode" "Normal,6-pin serial"
|
|
line.byte 0x01 "ULPI_INTERFACE_CTRL_SET_0,Enables Alternative Interfaces And PHY Features"
|
|
line.byte 0x02 "ULPI_INTERFACE_CTRL_CLR_0,Enables Alternative Interfaces And PHY Features"
|
|
group.byte (0x800+0xA)++0x0
|
|
line.byte 0x00 "ULPI_OTG_CTRL_0,Controls UTMI+ OTG Functions Of The PHY"
|
|
bitfld.byte 0x00 5. " DRVVBUS ,Drive 5V on VBUS" "No action,Drive"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP" "No action,Charge"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor" "No action,Discharge"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k Ohm pull-down resistor on D-" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k Ohm pull-down resistor on D+" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IDPULLUP ,Pull-up to the (OTG) ID line to allow its sampling" "Disabled,Enabled"
|
|
group.byte (0x800+0xD)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_RISE_0,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_RISE_SET_0,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_RISE_CLR_0,Enables An Interrupt Event Notification"
|
|
group.byte (0x800+0x10)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_FALL_0,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_FALL_SET_0,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_FALL_CLR_0,Enables An Interrupt Event Notification"
|
|
rgroup.byte (0x800+0x13)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_STATUS_0,Indicates The Current Value Of The Interrupt Source Signal"
|
|
bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output" "Grounded,Floating"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output" "> Session-End,< Session-End"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output" "> Session-Valid,< Session-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output" "> Vbus-Valid,< Vbus-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output" "Not disconnected/Non-host mode,Disconnected"
|
|
hgroup.byte (0x800+0x14)++0x0
|
|
hide.byte 0x00 "ULPI_USB_INT_LATCH_0,ULPI Interrupt Status Register"
|
|
in
|
|
rgroup.byte (0x800+0x15)++0x0
|
|
line.byte 0x00 "ULPI_DEBUG_0,Indicates The Current Value Of Various Signals Useful For Debugging"
|
|
bitfld.byte 0x00 0.--1. " LINESTATE ,Current state of the USB line D+ (bit 0) and D- (bit 1)" "SE0 (LS/FS) Squelch (HS/Chirp),LS=K/FS=J/HS=!Squelch/Chirp=!Squelch & HS_DRO,LS=J/FS=K/HS=Invalid/Chirp=!Squelch & !HS_DRO,SE1 (LS/FS) Invalid (HS/Chirp)"
|
|
group.byte (0x800+0x16)++0x2
|
|
line.byte 0x00 "ULPI_SCRATCH_REGISTER_0,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x01 "ULPI_SCRATCH_REGISTER_SET_0,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x02 "ULPI_SCRATCH_REGISTER_CLR_0,Register Byte For Register Access Testing Purposes"
|
|
group.byte (0x800+0x30)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_EN_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " VC6_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VC4_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " VC2_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " VC0_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_UTMI_VCONTROL_EN_SET_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VCONTROL_EN_CLR_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
group.byte (0x800+0x33)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_STATUS_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x800+0x34)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_LATCH_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
group.byte (0x800+0x35)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VSTATUS_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x01 "ULPI_UTMI_VSTATUS_SET_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VSTATUS_CLR_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x800+0x38)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_LATCH_NOCLR_0,Set By Unmasked Changes On Status Bits To Generate The ULPI Interrupt"
|
|
group.byte (0x800+0x3B)++0x2
|
|
line.byte 0x00 "ULPI_VENDOR_INT_EN_0,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_EN_SET_0,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
line.byte 0x02 "ULPI_VENDOR_INT_EN_CLR_0,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
rgroup.byte (0x800+0x3E)++0x1
|
|
line.byte 0x00 "ULPI_VENDOR_INT_STATUS_0,Vendor-Specific Interrupt Sources For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status" "Suspended,Not suspended"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_LATCH_0,Vendor-Specific Interrupt Latches For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x01 0. " P2P_LATCH ,PHY-to-PHY ULPI wakeup event latch" "Not latched,Latched"
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 21.
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TLL_CHANNEL_CONF_1,Control And Status Register For Channel 1"
|
|
bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/Low speed serial modes" "Single-ended 0,Full-speed J,Full-speed K,Single-ended 1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interfaces mode select" "6-pin unidirectional PHY i/f Dat/Se0,6-pin unidirectional PHY i/f Dp/Dm,3-pin bidirectional PHY i/f,4-pin bidirectional PHY i/f,6-pin unidirectional TLL Dat/Se0,6-pin unidirectional TLL Dp/Dm,3-pin bidirectional TLL,4-pin bidirectional TLL,Reserved,Reserved,2-pin bidirectional TLL Dat/Se0,2-pin bidirectional TLL Dp/Dm,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test" "Differential value,SE0"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test" "Full-speed K,Full-speed J"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test" "TestTXDat/Se0,TX Hiz"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial" "Not driven,Driven to 5V"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIAUTOIDLE ,Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIAUTOIDLE ,Allow the UTMI clock to be stopped when UTMII goes to suspended mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ULPIDDRMODE ,Select single/double data rate" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode" "LINK,PHY"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL" "Low speed,Full speed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect" "Unconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes" "Detach,Attach"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end seen by UTMI side of TLL" "UTMI peripheral/ULPI host,UTMI host/ULPI peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection" "UTMI-to-ULPI TLL,UTMI-to-serial,Transparent UTMI,No mode selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANEN ,Active-high channel enable" "Disabled,Enabled"
|
|
rgroup.byte 0x900++0x3
|
|
line.byte 0x00 "ULPI_VENDOR_ID_LO_1,Lower Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x01 "ULPI_VENDOR_ID_HI_1,Upper Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x02 "ULPI_PRODUCT_ID_LO_1,Lower Byte Of Vendor-Chosen Product ID Value"
|
|
line.byte 0x03 "ULPI_PRODUCT_ID_HI_1,Upper Byte Of Vendor-Chosen Product ID Value"
|
|
width 29.
|
|
group.byte (0x900+0x4)++0x2
|
|
line.byte 0x00 "ULPI_FUNCTION_CTRL_1,Controls UTMI Function Settings Of The PHY"
|
|
bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend" "Low-power,Not in low-power"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit" "Normal,Non-driving,Disable bit-stuff/NRZI encoding,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations" "HS,FS"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed" "HS,FS,LS,FS for LS packets"
|
|
line.byte 0x01 "ULPI_FUNCTION_CTRL_SET_1,Controls UTMI Function Settings Of The PHY"
|
|
line.byte 0x02 "ULPI_FUNCTION_CTRL_CLR_1,Controls UTMI Function Settings Of The PHY"
|
|
group.byte (0x900+0x7)++0x2
|
|
line.byte 0x00 "ULPI_INTERFACE_CTRL_1,Enables Alternative Interfaces And PHY Features"
|
|
bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin Serial Mode" "Normal,3-pin serial"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin Serial Mode" "Normal,6-pin serial"
|
|
line.byte 0x01 "ULPI_INTERFACE_CTRL_SET_1,Enables Alternative Interfaces And PHY Features"
|
|
line.byte 0x02 "ULPI_INTERFACE_CTRL_CLR_1,Enables Alternative Interfaces And PHY Features"
|
|
group.byte (0x900+0xA)++0x0
|
|
line.byte 0x00 "ULPI_OTG_CTRL_1,Controls UTMI+ OTG Functions Of The PHY"
|
|
bitfld.byte 0x00 5. " DRVVBUS ,Drive 5V on VBUS" "No action,Drive"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP" "No action,Charge"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor" "No action,Discharge"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k Ohm pull-down resistor on D-" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k Ohm pull-down resistor on D+" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IDPULLUP ,Pull-up to the (OTG) ID line to allow its sampling" "Disabled,Enabled"
|
|
group.byte (0x900+0xD)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_RISE_1,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_RISE_SET_1,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_RISE_CLR_1,Enables An Interrupt Event Notification"
|
|
group.byte (0x900+0x10)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_FALL_1,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_FALL_SET_1,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_FALL_CLR_1,Enables An Interrupt Event Notification"
|
|
rgroup.byte (0x900+0x13)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_STATUS_1,Indicates The Current Value Of The Interrupt Source Signal"
|
|
bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output" "Grounded,Floating"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output" "> Session-End,< Session-End"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output" "> Session-Valid,< Session-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output" "> Vbus-Valid,< Vbus-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output" "Not disconnected/Non-host mode,Disconnected"
|
|
hgroup.byte (0x900+0x14)++0x0
|
|
hide.byte 0x00 "ULPI_USB_INT_LATCH_1,ULPI Interrupt Status Register"
|
|
in
|
|
rgroup.byte (0x900+0x15)++0x0
|
|
line.byte 0x00 "ULPI_DEBUG_1,Indicates The Current Value Of Various Signals Useful For Debugging"
|
|
bitfld.byte 0x00 0.--1. " LINESTATE ,Current state of the USB line D+ (bit 0) and D- (bit 1)" "SE0 (LS/FS) Squelch (HS/Chirp),LS=K/FS=J/HS=!Squelch/Chirp=!Squelch & HS_DRO,LS=J/FS=K/HS=Invalid/Chirp=!Squelch & !HS_DRO,SE1 (LS/FS) Invalid (HS/Chirp)"
|
|
group.byte (0x900+0x16)++0x2
|
|
line.byte 0x00 "ULPI_SCRATCH_REGISTER_1,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x01 "ULPI_SCRATCH_REGISTER_SET_1,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x02 "ULPI_SCRATCH_REGISTER_CLR_1,Register Byte For Register Access Testing Purposes"
|
|
group.byte (0x900+0x30)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_EN_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " VC6_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VC4_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " VC2_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " VC0_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_UTMI_VCONTROL_EN_SET_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VCONTROL_EN_CLR_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
group.byte (0x900+0x33)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_STATUS_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x900+0x34)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_LATCH_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
group.byte (0x900+0x35)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VSTATUS_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x01 "ULPI_UTMI_VSTATUS_SET_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VSTATUS_CLR_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x900+0x38)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_LATCH_NOCLR_1,Set By Unmasked Changes On Status Bits To Generate The ULPI Interrupt"
|
|
group.byte (0x900+0x3B)++0x2
|
|
line.byte 0x00 "ULPI_VENDOR_INT_EN_1,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_EN_SET_1,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
line.byte 0x02 "ULPI_VENDOR_INT_EN_CLR_1,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
rgroup.byte (0x900+0x3E)++0x1
|
|
line.byte 0x00 "ULPI_VENDOR_INT_STATUS_1,Vendor-Specific Interrupt Sources For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status" "Suspended,Not suspended"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_LATCH_1,Vendor-Specific Interrupt Latches For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x01 0. " P2P_LATCH ,PHY-to-PHY ULPI wakeup event latch" "Not latched,Latched"
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 21.
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "TLL_CHANNEL_CONF_2,Control And Status Register For Channel 2"
|
|
bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/Low speed serial modes" "Single-ended 0,Full-speed J,Full-speed K,Single-ended 1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interfaces mode select" "6-pin unidirectional PHY i/f Dat/Se0,6-pin unidirectional PHY i/f Dp/Dm,3-pin bidirectional PHY i/f,4-pin bidirectional PHY i/f,6-pin unidirectional TLL Dat/Se0,6-pin unidirectional TLL Dp/Dm,3-pin bidirectional TLL,4-pin bidirectional TLL,Reserved,Reserved,2-pin bidirectional TLL Dat/Se0,2-pin bidirectional TLL Dp/Dm,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test" "Differential value,SE0"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test" "Full-speed K,Full-speed J"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test" "TestTXDat/Se0,TX Hiz"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial" "Not driven,Driven to 5V"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIAUTOIDLE ,Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIAUTOIDLE ,Allow the UTMI clock to be stopped when UTMII goes to suspended mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ULPIDDRMODE ,Select single/double data rate" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode" "LINK,PHY"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL" "Low speed,Full speed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect" "Unconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes" "Detach,Attach"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end seen by UTMI side of TLL" "UTMI peripheral/ULPI host,UTMI host/ULPI peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection" "UTMI-to-ULPI TLL,UTMI-to-serial,Transparent UTMI,No mode selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANEN ,Active-high channel enable" "Disabled,Enabled"
|
|
rgroup.byte 0xA00++0x3
|
|
line.byte 0x00 "ULPI_VENDOR_ID_LO_2,Lower Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x01 "ULPI_VENDOR_ID_HI_2,Upper Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x02 "ULPI_PRODUCT_ID_LO_2,Lower Byte Of Vendor-Chosen Product ID Value"
|
|
line.byte 0x03 "ULPI_PRODUCT_ID_HI_2,Upper Byte Of Vendor-Chosen Product ID Value"
|
|
width 29.
|
|
group.byte (0xA00+0x4)++0x2
|
|
line.byte 0x00 "ULPI_FUNCTION_CTRL_2,Controls UTMI Function Settings Of The PHY"
|
|
bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend" "Low-power,Not in low-power"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit" "Normal,Non-driving,Disable bit-stuff/NRZI encoding,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations" "HS,FS"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed" "HS,FS,LS,FS for LS packets"
|
|
line.byte 0x01 "ULPI_FUNCTION_CTRL_SET_2,Controls UTMI Function Settings Of The PHY"
|
|
line.byte 0x02 "ULPI_FUNCTION_CTRL_CLR_2,Controls UTMI Function Settings Of The PHY"
|
|
group.byte (0xA00+0x7)++0x2
|
|
line.byte 0x00 "ULPI_INTERFACE_CTRL_2,Enables Alternative Interfaces And PHY Features"
|
|
bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin Serial Mode" "Normal,3-pin serial"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin Serial Mode" "Normal,6-pin serial"
|
|
line.byte 0x01 "ULPI_INTERFACE_CTRL_SET_2,Enables Alternative Interfaces And PHY Features"
|
|
line.byte 0x02 "ULPI_INTERFACE_CTRL_CLR_2,Enables Alternative Interfaces And PHY Features"
|
|
group.byte (0xA00+0xA)++0x0
|
|
line.byte 0x00 "ULPI_OTG_CTRL_2,Controls UTMI+ OTG Functions Of The PHY"
|
|
bitfld.byte 0x00 5. " DRVVBUS ,Drive 5V on VBUS" "No action,Drive"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP" "No action,Charge"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor" "No action,Discharge"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k Ohm pull-down resistor on D-" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k Ohm pull-down resistor on D+" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IDPULLUP ,Pull-up to the (OTG) ID line to allow its sampling" "Disabled,Enabled"
|
|
group.byte (0xA00+0xD)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_RISE_2,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_RISE_SET_2,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_RISE_CLR_2,Enables An Interrupt Event Notification"
|
|
group.byte (0xA00+0x10)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_FALL_2,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_FALL_SET_2,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_FALL_CLR_2,Enables An Interrupt Event Notification"
|
|
rgroup.byte (0xA00+0x13)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_STATUS_2,Indicates The Current Value Of The Interrupt Source Signal"
|
|
bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output" "Grounded,Floating"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output" "> Session-End,< Session-End"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output" "> Session-Valid,< Session-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output" "> Vbus-Valid,< Vbus-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output" "Not disconnected/Non-host mode,Disconnected"
|
|
hgroup.byte (0xA00+0x14)++0x0
|
|
hide.byte 0x00 "ULPI_USB_INT_LATCH_2,ULPI Interrupt Status Register"
|
|
in
|
|
rgroup.byte (0xA00+0x15)++0x0
|
|
line.byte 0x00 "ULPI_DEBUG_2,Indicates The Current Value Of Various Signals Useful For Debugging"
|
|
bitfld.byte 0x00 0.--1. " LINESTATE ,Current state of the USB line D+ (bit 0) and D- (bit 1)" "SE0 (LS/FS) Squelch (HS/Chirp),LS=K/FS=J/HS=!Squelch/Chirp=!Squelch & HS_DRO,LS=J/FS=K/HS=Invalid/Chirp=!Squelch & !HS_DRO,SE1 (LS/FS) Invalid (HS/Chirp)"
|
|
group.byte (0xA00+0x16)++0x2
|
|
line.byte 0x00 "ULPI_SCRATCH_REGISTER_2,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x01 "ULPI_SCRATCH_REGISTER_SET_2,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x02 "ULPI_SCRATCH_REGISTER_CLR_2,Register Byte For Register Access Testing Purposes"
|
|
group.byte (0xA00+0x30)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_EN_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " VC6_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VC4_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " VC2_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " VC0_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_UTMI_VCONTROL_EN_SET_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VCONTROL_EN_CLR_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
group.byte (0xA00+0x33)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_STATUS_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0xA00+0x34)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_LATCH_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
group.byte (0xA00+0x35)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VSTATUS_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x01 "ULPI_UTMI_VSTATUS_SET_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VSTATUS_CLR_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0xA00+0x38)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_LATCH_NOCLR_2,Set By Unmasked Changes On Status Bits To Generate The ULPI Interrupt"
|
|
group.byte (0xA00+0x3B)++0x2
|
|
line.byte 0x00 "ULPI_VENDOR_INT_EN_2,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_EN_SET_2,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
line.byte 0x02 "ULPI_VENDOR_INT_EN_CLR_2,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
rgroup.byte (0xA00+0x3E)++0x1
|
|
line.byte 0x00 "ULPI_VENDOR_INT_STATUS_2,Vendor-Specific Interrupt Sources For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status" "Suspended,Not suspended"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_LATCH_2,Vendor-Specific Interrupt Latches For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x01 0. " P2P_LATCH ,PHY-to-PHY ULPI wakeup event latch" "Not latched,Latched"
|
|
tree.end
|
|
tree.end
|
|
tree "UHH_config"
|
|
base ad:0x48064000
|
|
width 16.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "UHH_REVISION,Standard Revision Number"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJ_REV ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MIN_REV ,Minor revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UHH_SYSCONFIG,Standard System Configuration Register"
|
|
bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management control" "Force standby,No standby,Smart standby,?..."
|
|
bitfld.long 0x00 8. " CLOCKACTIVITY ,Control of clock internal gating while module is idle" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Asynchronous wakeup generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Module software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal autogating control" "Always running,Cut off"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "UHH_SYSSTATUS,Standard System Status Register"
|
|
bitfld.long 0x00 2. " EHCI_RESETDONE ,Indicated when the EHCI HS host is out of reset" "Ongoing,Done"
|
|
bitfld.long 0x00 1. " OHCI_RESETDONE ,Indicates when the OHCI FS/LS host is out of reset" "Ongoing,Done"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESETDONE ,Indicates when the USB Host has come out of reset" "Ongoing,Done"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "UHH_HOSTCONFIG,Static Configuration Of The OTG Controller Host"
|
|
bitfld.long 0x00 10. " P3_CONNECT_STATUS ,Connection status for port 3" "Not connected,Connected"
|
|
bitfld.long 0x00 9. " P2_CONNECT_STATUS ,Connection status for port 2" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P1_CONNECT_STATUS ,Connection status for port 1" "Not connected,Connected"
|
|
bitfld.long 0x00 5. " ENA_INCR_ALIGN ,Force alignment of bursts to the respective burst-size boundaries " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA_INCR16 ,Control the use of INCR16-type bursts (in AHB sense)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA_INCR8 ,Control the use of INCR8-type bursts (in AHB sense)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA_INCR4 ,Configure reaction upon port overcurrent condition" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P1_ULPI_BYPASS ,Host controller (root hub) port 1 control" "ULPI,UTMI"
|
|
line.long 0x04 "UHH_DEBUG_CSR,Debug Control And Status For The EHCI"
|
|
bitfld.long 0x04 19. " OHCI_CCS_3 ,Current Connect Status of port 3" "Not connected,Connected"
|
|
bitfld.long 0x04 18. " OHCI_CCS_2 ,Current Connect Status of port 2" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OHCI_CCS_1 ,Current Connect Status of port 1" "Not connected,Connected"
|
|
bitfld.long 0x04 16. " OHCI_GLOBALSUSPEND ,OHCI global suspend status" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OCHI_CNTSEL ,Selection of a shorter 1 ms counter in OHCI host" "Functional,Simulation"
|
|
bitfld.long 0x04 6. " EHCI_SIMULATION_MODE ,Sets the PHY to non-driving mode" "Functional,Non-driving"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--5. 1. " EHCI_FLADJ ,EHCI host frame length adjust"
|
|
width 0xb
|
|
tree.end
|
|
tree "OHCI"
|
|
base ad:0x48064400
|
|
width 21.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,OHCI Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI specification revision"
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "HCCONTROL,HC Operating Mode Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote wake-up connected" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IR ,Interrupt routing" "0,1"
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state" "Reset,Resume,Operational,Suspend"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLE ,Bulk list processing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control list processing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous ED processing enabled by host controller driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic list enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio" "1,2,3,4"
|
|
line.long 0x04 "HCCOMMANDSTATUS,HC Command and Status"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling overrun count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership change request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BLF ,Bulk list filled" "Not filled,Filled"
|
|
bitfld.long 0x04 1. " CLF ,Control list filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HCR ,Host controller reset" "No effect,Reset"
|
|
line.long 0x08 "HCINTERRUPTSTATUS,HC Interrupt Status"
|
|
eventfld.long 0x08 30. " OC ,Ownership change" "Not changed,Changed"
|
|
eventfld.long 0x08 6. " RHSC ,Root hub status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x08 5. " FNO ,Frame number overflow" "No effect,Overflow"
|
|
eventfld.long 0x08 4. " UE ,Unrecoverable error" "No effect,Error"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RD ,Resume detected" "No effect,Resume"
|
|
eventfld.long 0x08 2. " SF ,Start of frame" "No effect,SOF"
|
|
textline " "
|
|
eventfld.long 0x08 1. " WDH ,Write done head" "No effect,Written"
|
|
eventfld.long 0x08 0. " SO ,Scheduling overrun" "No effect,Overrun"
|
|
line.long 0x0c "HCINTERRUPTENABLE,HC Interrupt Enable"
|
|
bitfld.long 0x0C 31. " MIE ,Master interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " OC ,Ownership change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " RHSC ,Root hub status change" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " FNO ,Frame number overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " UE ,Unrecoverable error" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " RD ,Resume detected" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SF ,Start of frame" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " WDH ,Write done head" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " SO ,Scheduling overrun" "Disabled,Enabled"
|
|
line.long 0x10 "HCINTERRUPTDISABLE,HC Interrupt Disable"
|
|
bitfld.long 0x10 31. " MIE ,Master interrupt enable" "No effect,Disabled"
|
|
bitfld.long 0x10 30. " OC ,Ownership change" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " RHSC ,Root hub status change" "No effect,Disabled"
|
|
bitfld.long 0x10 5. " FNO ,Frame number overflow" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " UE ,Unrecoverable error" "No effect,Disabled"
|
|
bitfld.long 0x10 3. " RD ,Resume detected" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SF ,Start of frame" "No effect,Disabled"
|
|
bitfld.long 0x10 1. " WDH ,Write done head RW 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " SO ,Scheduling overrun" "No effect,Disabled"
|
|
line.long 0x14 "HCHCCA,HC HCCA Address Register"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. " HCCA ,Physical address of the beginning of the HCCA"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "HCPERIODCURRENTED,HC Current Periodic Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PCED ,Physical address of current ED on the periodic ED list"
|
|
group.long 0x20++0xf
|
|
line.long 0x00 "HCCONTROLHEADED,HC Head Control Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " CHED ,Physical address of head ED on the control ED list"
|
|
line.long 0x04 "HCCONTROLCURRENTED,HC Current Control Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " CCED ,Physical address of current ED on the control ED list"
|
|
line.long 0x08 "HCBULKHEADED,HC Head Bulk Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " BHED ,Physical address of head ED on the bulk ED list"
|
|
line.long 0x0c "HCBULKCURRENTED,HC Current Bulk Register"
|
|
hexmask.long 0x0C 4.--31. 0x10 " BCED ,Physical address of current ED on the bulk ED list"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,HC Head Done Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Physical address of last TD that was added to the Done queue"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,HC Frame Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame interval toggle" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet size for full-speed packets"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame interval"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,HC Frame Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame remaining toggle" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining"
|
|
line.long 0x04 "HCFMNUMBER,HC Frame Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame number"
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "HCPERIODICSTART,HC Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic start"
|
|
line.long 0x04 "HCLSTHRESHOLD,HC Low-speed Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,Low-speed threshold"
|
|
line.long 0x08 "HCRHDESCRIPTORA,HC Root Hub A Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " POTPG ,Power-on to power-good time"
|
|
bitfld.long 0x08 10. " DT ,Device type" "Not compound,?..."
|
|
textline " "
|
|
bitfld.long 0x08 9. " NPS ,No power switching" "Switching,No switching"
|
|
bitfld.long 0x08 8. " PSM ,Power switching mode" "Same,Individual"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " NDP ,Number of downstream ports"
|
|
line.long 0x0c "HCRHDESCRIPTORB,HC Root Hub B Register"
|
|
bitfld.long 0x0c 31. " PPCM[15] ,Ganged-power mask on port #15" "Global,Port"
|
|
bitfld.long 0x0c 30. " PPCM[14] ,Ganged-power mask on port #14" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " PPCM[13] ,Ganged-power mask on port #13" "Global,Port"
|
|
bitfld.long 0x0c 28. " PPCM[12] ,Ganged-power mask on port #12" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " PPCM[11] ,Ganged-power mask on port #11" "Global,Port"
|
|
bitfld.long 0x0c 26. " PPCM[10] ,Ganged-power mask on port #10" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " PPCM[9] ,Ganged-power mask on port #9" "Global,Port"
|
|
bitfld.long 0x0c 24. " PPCM[8] ,Ganged-power mask on port #8" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " PPCM[7] ,Ganged-power mask on port #7" "Global,Port"
|
|
bitfld.long 0x0c 22. " PPCM[6] ,Ganged-power mask on port #6" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " PPCM[5] ,Ganged-power mask on port #5" "Global,Port"
|
|
bitfld.long 0x0c 20. " PPCM[4] ,Ganged-power mask on port #4" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " PPCM[3] ,Ganged-power mask on port #3" "Global,Port"
|
|
bitfld.long 0x0c 18. " PPCM[2] ,Ganged-power mask on port #2" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " PPCM[1] ,Ganged-power mask on port #1" "Global,Port"
|
|
bitfld.long 0x0c 15. " DR[15] ,Device attached to port #15" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " DR[14] ,Device attached to port #14" "Removable,Not removable"
|
|
bitfld.long 0x0c 13. " DR[13] ,Device attached to port #13" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " DR[12] ,Device attached to port #12" "Removable,Not removable"
|
|
bitfld.long 0x0c 11. " DR[11] ,Device attached to port #11" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " DR[10] ,Device attached to port #10" "Removable,Not removable"
|
|
bitfld.long 0x0c 9. " DR[9] ,Device attached to port #9" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " DR[8] ,Device attached to port #8" "Removable,Not removable"
|
|
bitfld.long 0x0c 7. " DR[7] ,Device attached to port #7" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " DR[6] ,Device attached to port #6" "Removable,Not removable"
|
|
bitfld.long 0x0c 5. " DR[5] ,Device attached to port #5" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " DR[4] ,Device attached to port #4" "Removable,Not removable"
|
|
bitfld.long 0x0c 3. " DR[3] ,Device attached to port #3" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " DR[2] ,Device attached to port #2" "Removable,Not removable"
|
|
bitfld.long 0x0c 1. " DR[1] ,Device attached to port #1" "Removable,Not removable"
|
|
line.long 0x10 "HCRHSTATUS,HC Root Hub Status Register"
|
|
bitfld.long 0x10 31. " CRWE ,Clear remote wake-up enable" "No effect,Cleared"
|
|
bitfld.long 0x10 16. " LPSC ,Local power status change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DRWE ,Device remote wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " LPS ,Local power status" "No effect,Turned off"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_1,HC Port 1 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "No effect,Changed"
|
|
eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "No effect,Changed"
|
|
eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 1 low-speed device attached/clear port power" "Full,Low"
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 1 power status/set port power" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 1 reset status/set port reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 1 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 1 status/set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 1 current connection status/clear port enable" "No device,Device"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_2,HC Port 2 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 2 reset status change" "No effect,Changed"
|
|
eventfld.long 0x00 18. " PSSC ,Port 2 suspend status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 17. " PESC ,Port 2 enable status change" "No effect,Changed"
|
|
eventfld.long 0x00 16. " CSC ,Port 2 connect status change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 2 low-speed device attached/clear port power" "Full,Low"
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 2 power status/set port power" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 2 reset status/set port reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 2 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 2 status/set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 2 current connection status/clear port enable" "No device,Device"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_3,HC Port 3 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 3 reset status change" "No effect,Changed"
|
|
eventfld.long 0x00 18. " PSSC ,Port 3 suspend status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 17. " PESC ,Port 3 enable status change" "No effect,Changed"
|
|
eventfld.long 0x00 16. " CSC ,Port 3 connect status change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 3 low-speed device attached/clear port power" "Full,Low"
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 3 power status/set port power" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 3 reset status/set port reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 3 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 3 status/set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 3 current connection status/clear port enable" "No device,Device"
|
|
width 0xb
|
|
tree.end
|
|
tree "EHCI"
|
|
base ad:0x48064800
|
|
width 18.
|
|
rgroup.long 0x00++0xb
|
|
line.long 0x00 "HCCAPBASE,Host Controller Capability Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HCI VERSION"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,CAP LENGTH"
|
|
line.long 0x04 "HCSPARAMS,Host Controller Structural Parameters"
|
|
bitfld.long 0x04 16. " P_INDICATOR ,Port indicator support indication" "Not supported,Supported"
|
|
bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 7. " PRR ,Port Routing Rules" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PPC ,Port Power control" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "HCCPARAMS,Host Controller Capability Parameters"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x08 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ASPC ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PFLF ,Programmable Frame List Flag" "1024 elements,Smaller frame list"
|
|
textline " "
|
|
bitfld.long 0x08 0. " BIT64AC ,64-bit addressing capability" "32-bit,64-bit"
|
|
group.long 0x10++0xF
|
|
line.long 0x00 "USBCMD,USB Command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASPMC ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "1024 elements/4096 bytes,512 elements/2048 bytes,256 elements/1024 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop" "Run,Stop"
|
|
line.long 0x04 "USBSTS,USB Status"
|
|
bitfld.long 0x04 15. " ASS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " REC ,Reclamation detect" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " HCH ,Host Controller Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IAA ,Interrept on Async Advance" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " HSE ,Host System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLR ,Frame List Rollover" "No effect,Rollover"
|
|
bitfld.long 0x04 2. " PCD ,Port Change Detect" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " USBEI ,USB Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " USBI ,USB Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x08 5. " IAAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HSEE ,Host System Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FLRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PCIE ,Port Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " USBEIE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " USBIE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FRINDEX,USB Frame Index"
|
|
hexmask.long.word 0x0C 0.--13. 1. " FI ,Frame Index"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "CTRLDSSEGMENT,4G Segment Selector"
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "PERIODICLISTBASE,Frame List Base Address"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BAL ,Base Address (Low)"
|
|
line.long 0x04 "ASYNCLISTADDR,Next Asynchronous List Address"
|
|
hexmask.long 0x04 5.--31. 0x10 " LPL ,Link Pointer Low"
|
|
width 18.
|
|
group.long 0x50++0xF
|
|
line.long 0x00 "CONFIGFLAG,Configured Flag Register"
|
|
bitfld.long 0x00 0. " CF , Configure Flag" "Only implemented ports,All ports"
|
|
width 18.
|
|
line.long 0x4 "PORTSC_0,Port Status / Control 0"
|
|
bitfld.long 0x4 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--19. " PTC ,Port Test Control" "Disabled,Test J_STATE,Test K_STATE,Test SE0_NAK,Test Packet,Test FORCE_ENABLE,?..."
|
|
bitfld.long 0x4 14.--15. " PIC ,Port Indicator Control" "Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0x4 13. " PO ,Port Owner" "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " PP ,Port Power" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 10.--11. " LS ,Line Status" "SE0,K-state,J-state,Undefined"
|
|
bitfld.long 0x4 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 7. " SUS ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x4 6. " FPR ,Force Port Resume" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PEDC ,Port Enabled/Disabled Change" "No change,Changed"
|
|
bitfld.long 0x4 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " CSC ,Connect Status Change" "No change,Changed"
|
|
bitfld.long 0x4 0. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
line.long 0x8 "PORTSC_1,Port Status / Control 1"
|
|
bitfld.long 0x8 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--19. " PTC ,Port Test Control" "Disabled,Test J_STATE,Test K_STATE,Test SE0_NAK,Test Packet,Test FORCE_ENABLE,?..."
|
|
bitfld.long 0x8 14.--15. " PIC ,Port Indicator Control" "Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0x8 13. " PO ,Port Owner" "Disabled,Enabled"
|
|
bitfld.long 0x8 12. " PP ,Port Power" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 10.--11. " LS ,Line Status" "SE0,K-state,J-state,Undefined"
|
|
bitfld.long 0x8 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 7. " SUS ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x8 6. " FPR ,Force Port Resume" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PEDC ,Port Enabled/Disabled Change" "No change,Changed"
|
|
bitfld.long 0x8 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " CSC ,Connect Status Change" "No change,Changed"
|
|
bitfld.long 0x8 0. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
line.long 0xC "PORTSC_2,Port Status / Control 2"
|
|
bitfld.long 0xC 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--19. " PTC ,Port Test Control" "Disabled,Test J_STATE,Test K_STATE,Test SE0_NAK,Test Packet,Test FORCE_ENABLE,?..."
|
|
bitfld.long 0xC 14.--15. " PIC ,Port Indicator Control" "Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0xC 13. " PO ,Port Owner" "Disabled,Enabled"
|
|
bitfld.long 0xC 12. " PP ,Port Power" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 10.--11. " LS ,Line Status" "SE0,K-state,J-state,Undefined"
|
|
bitfld.long 0xC 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 7. " SUS ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0xC 6. " FPR ,Force Port Resume" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PEDC ,Port Enabled/Disabled Change" "No change,Changed"
|
|
bitfld.long 0xC 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " CSC ,Connect Status Change" "No change,Changed"
|
|
bitfld.long 0xC 0. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
width 18.
|
|
group.long 0x90++0x13
|
|
line.long 0x00 "INSNREG00,Implementation-Specific Register #0"
|
|
hexmask.long.word 0x00 1.--13. 1. " UFRAME_CNT ,1-microframe length value"
|
|
bitfld.long 0x00 0. " EN ,Enable of this register" "Disabled,Enabled"
|
|
line.long 0x04 "INSNREG01,Implementation-Specific Register #1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OUT_THRESHOLD ,Programmable output packet buffer threshold"
|
|
hexmask.long.word 0x04 0.--15. 1. " IN_THRESHOLD ,Programmable input packet buffer threshold"
|
|
line.long 0x08 "INSNREG02,Implementation-Specific Register #2"
|
|
hexmask.long.word 0x08 0.--11. 1. " BUF_DEPTH ,Programmable packet buffer depth"
|
|
line.long 0x0C "INSNREG03,Implementation-Specific Register #3"
|
|
bitfld.long 0x0C 0. " BRK_MEM_TRSF ,Break Memory Transfer" "Disabled,Enabled"
|
|
line.long 0x10 "INSNREG04,Implementation-Specific Register #4"
|
|
bitfld.long 0x10 4. " NAK_FIX_DIS ,Disable NAK fix" "No,Yes"
|
|
bitfld.long 0x10 2. " SHORT_PORT_ENUM ,Scale down Port enumeration time" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 1. " HCCPARAMS_WRE ,Make read-only HCCPARAMS register writable" "Read only,Writable"
|
|
bitfld.long 0x10 0. " HCSPARAMS_WRE ,Make read-only HCSPARAMS register writable" "Read only,Writable"
|
|
if (((d.l(ad:0x48064040))&0x1)==0x0)
|
|
;UHH_HOSTCONFIG[0] = ULPI
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "INSNREG05_ULPI,Implementation-Specific Register #5"
|
|
bitfld.long 0x00 31. " CONTROL ,Control/status of the ULPI register access" "Done,Start"
|
|
bitfld.long 0x00 24.--27. " PORTSEL ,Port selection" "Reserved,Port 1,Port 2,Port 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OPSEL ,Register access selection" "Reserved,Reserved,Write,Read"
|
|
hexmask.long.byte 0x00 16.--21. 1. " REGADD ,ULPI direct register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTREGADD ,Address for extended register accesses"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WRDATA ,Read/Write data of register access"
|
|
else
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "INSNREG05_UTMI,Implementation-Specific Register #5"
|
|
bitfld.long 0x00 17. " VBUSY ,Vendor interface busy" "Done/Inactive,Busy"
|
|
bitfld.long 0x00 13.--16. " VPORT ,Vendor interface port selection" "Reserved,Port 1,Port 2,Port 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " VCONTROLLOADM ,UTMI VcontrolLoadM output" "Load,No action"
|
|
bitfld.long 0x00 8.--11. " VCONTROL ,UTMI Vcontrol output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VSTATUS ,UTMI Vstatus input image"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "GPIO (General-Purpose Input/Output)"
|
|
tree "GPIO 1"
|
|
base ad:0x48310000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
|
|
group.long 0x3c++0x1b
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
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|
bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
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|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
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|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
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|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
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|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
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|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
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|
line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 2"
|
|
base ad:0x49050000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
|
|
group.long 0x3c++0x1b
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
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textline " "
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
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textline " "
|
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
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textline " "
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
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textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
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setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
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textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
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bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
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bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
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bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
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bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
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bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
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line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
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bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 3"
|
|
base ad:0x49052000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
rgroup.long 0x38++0x3
|
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
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textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
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|
textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
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textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
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|
textline " "
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
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|
textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
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textline " "
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
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|
textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
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|
textline " "
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|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
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textline " "
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|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
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textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
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|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
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|
textline " "
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|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
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textline " "
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|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
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|
bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
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|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
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|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
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|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
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|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
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|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
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|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
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|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
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|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
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|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
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|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
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line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
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bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
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bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
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bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
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|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
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|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
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|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
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bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
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line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
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bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 4"
|
|
base ad:0x49054000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x04 "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
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bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
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bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
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textline " "
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bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
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bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
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textline " "
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bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
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bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
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bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
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textline " "
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bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
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bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
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textline " "
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bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
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bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
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textline " "
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bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
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bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
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textline " "
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bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
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bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
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bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
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bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
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rgroup.long 0x38++0x3
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
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textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
|
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
|
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
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line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 5"
|
|
base ad:0x49056000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
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setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
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setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
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group.long 0x30++0x07
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line.long 0x00 "GPIO_CTRL,GPIO Control"
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bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
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bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
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line.long 0x04 "GPIO_OE,Output Data Enable"
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bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
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bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
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bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
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bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
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bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
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bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
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bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
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bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
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bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
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bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
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bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
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bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
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bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
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bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
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bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
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bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
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bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
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rgroup.long 0x38++0x3
|
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
|
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
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textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
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textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
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textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
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textline " "
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
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textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
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textline " "
|
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
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textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
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textline " "
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
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textline " "
|
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
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textline " "
|
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
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setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
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textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
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bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
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bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
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bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
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bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
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bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
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bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
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bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
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bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
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bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
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bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
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bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
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bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
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bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
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line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
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bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
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bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO 6"
|
|
base ad:0x49058000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
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setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
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setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
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setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
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setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
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setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
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setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
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setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
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setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
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setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
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setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
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group.long 0x30++0x07
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line.long 0x00 "GPIO_CTRL,GPIO Control"
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bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
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bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
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line.long 0x04 "GPIO_OE,Output Data Enable"
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bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
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bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
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bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
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bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
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bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
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bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
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bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
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bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
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bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
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bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
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bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
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bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
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bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
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bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
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bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
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bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
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textline " "
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bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
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bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
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rgroup.long 0x38++0x3
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
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textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
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textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
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textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
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textline " "
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
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textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
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textline " "
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
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textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
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textline " "
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
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textline " "
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
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textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
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setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
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textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
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bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
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bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
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bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
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bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
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bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
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bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
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bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
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bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
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bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
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bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
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bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
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bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
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bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
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bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
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line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
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bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
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bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
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bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
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tree.end
|
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tree.open "EMAC/MDIO (Ethernet Media Access Controller/Management Data Input/Output Module)"
|
|
tree "EMAC Control Module"
|
|
base ad:0x5c000000
|
|
width 17.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,EMAC Control Module Revision ID Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOFTRESET,EMAC Control Module Software Reset Register"
|
|
bitfld.long 0x00 0. " RESET ,Software reset bit for the EMAC Control Module" "No reset,Reset"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "INTCONTROL,EMAC Control Module Interrupt Control Register"
|
|
bitfld.long 0x00 21. " C2TXPACEEN ,Enable pacing for TX interrupt pulse generation on Interrupt Core 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " C2RXPACEEN ,Enable pacing for RX interrupt pulse generation on Interrupt Core 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " C1TXPACEEN ,Enable pacing for TX interrupt pulse generation on Interrupt Core 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " C1RXPACEEN ,Enable pacing for RX interrupt pulse generation on Interrupt Core 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " C0TXPACEEN ,Enable pacing for TX interrupt pulse generation on Interrupt Core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " C0RXPACEEN ,Enable pacing for RX interrupt pulse generation on Interrupt Core 0" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " INTPRESCALE ,Number of internal EMAC module reference clock periods within a 4 us time window"
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "C0RXTHRESHEN,EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "C0RXEN,EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register 0"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Enable C0RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Enable C0RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RXCH5EN ,Enable C0RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RXCH4EN ,Enable C0RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RXCH3EN ,Enable C0RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Enable C0RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Enable C0RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Enable C0RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "C0TXEN,EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register"
|
|
bitfld.long 0x08 7. " TXCH7EN ,Enable C0TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TXCH6EN ,Enable C0TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TXCH5EN ,Enable C0TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXCH4EN ,Enable C0TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TXCH3EN ,Enable C0TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXCH2EN ,Enable C0TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1EN ,Enable C0TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCH0EN ,Enable C0TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "C0MISCEN,EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " STATPENDEN ,Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HOSTPENDEN ,Enable C0MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LINKINT0EN ,Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts are generated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USERINT0EN ,Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts are generated" "Disabled,Enabled"
|
|
group.long 0x20++0x0f
|
|
line.long 0x00 "C1RXTHRESHEN,EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "C1RXEN,EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register 1"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Enable C1RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Enable C1RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RXCH5EN ,Enable C1RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RXCH4EN ,Enable C1RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RXCH3EN ,Enable C1RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Enable C1RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Enable C1RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Enable C1RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "C1TXEN,EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register"
|
|
bitfld.long 0x08 7. " TXCH7EN ,Enable C1TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TXCH6EN ,Enable C1TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TXCH5EN ,Enable C1TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXCH4EN ,Enable C1TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TXCH3EN ,Enable C1TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXCH2EN ,Enable C1TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1EN ,Enable C1TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCH0EN ,Enable C1TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "C1MISCEN,EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " STATPENDEN ,Enable C1MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HOSTPENDEN ,Enable C1MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LINKINT0EN ,Enable C1MISCPULSE interrupt generation when MDIO LINKINT0 interrupts are generated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USERINT0EN ,Enable C1MISCPULSE interrupt generation when MDIO USERINT0 interrupts are generated" "Disabled,Enabled"
|
|
group.long 0x30++0x0f
|
|
line.long 0x00 "C2RXTHRESHEN,EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "C2RXEN,EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register 2"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Enable C2RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Enable C2RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RXCH5EN ,Enable C2RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RXCH4EN ,Enable C2RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RXCH3EN ,Enable C2RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Enable C2RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Enable C2RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Enable C2RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "C2TXEN,EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register"
|
|
bitfld.long 0x08 7. " TXCH7EN ,Enable C2TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TXCH6EN ,Enable C2TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TXCH5EN ,Enable C2TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXCH4EN ,Enable C2TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TXCH3EN ,Enable C2TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXCH2EN ,Enable C2TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1EN ,Enable C2TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCH0EN ,Enable C2TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "C2MISCEN,EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " STATPENDEN ,Enable C2MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HOSTPENDEN ,Enable C2MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LINKINT0EN ,Enable C2MISCPULSE interrupt generation when MDIO LINKINT0 interrupts are generated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USERINT0EN ,Enable C2MISCPULSE interrupt generation when MDIO USERINT0 interrupts are generated" "Disabled,Enabled"
|
|
rgroup.long 0x40++0x0f
|
|
line.long 0x00 "C0RXTHRESHSTAT,EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
line.long 0x04 "C0RXSTAT,EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
line.long 0x08 "C0TXSTAT,EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
line.long 0x0c "C0MISCSTAT,EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register"
|
|
bitfld.long 0x0C 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
rgroup.long 0x50++0x0f
|
|
line.long 0x00 "C1RXTHRESHSTAT,EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
line.long 0x04 "C0RXSTAT,EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
line.long 0x08 "C1TXSTAT,EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
line.long 0x0c "C1MISCSTAT,EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register"
|
|
bitfld.long 0x0C 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
rgroup.long 0x60++0x0f
|
|
line.long 0x00 "C2RXTHRESHSTAT,EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
line.long 0x04 "C0RXSTAT,EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
line.long 0x08 "C2TXSTAT,EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
line.long 0x0c "C2MISCSTAT,EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register"
|
|
bitfld.long 0x0C 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
group.long 0x70--0x87
|
|
line.long 0x0 "C0RXIMAX,EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " RXIMAX ,Desired number of C0RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long (0x0+0x04) "C0TXIMAX,EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register"
|
|
bitfld.long (0x0+0x04) 0.--5. " TXIMAX ,Desired number of C0TXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "C1RXIMAX,EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register"
|
|
bitfld.long 0x8 0.--5. " RXIMAX ,Desired number of C1RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long (0x8+0x04) "C1TXIMAX,EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register"
|
|
bitfld.long (0x8+0x04) 0.--5. " TXIMAX ,Desired number of C1TXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "C2RXIMAX,EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register"
|
|
bitfld.long 0x10 0.--5. " RXIMAX ,Desired number of C2RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long (0x10+0x04) "C2TXIMAX,EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register"
|
|
bitfld.long (0x10+0x04) 0.--5. " TXIMAX ,Desired number of C2TXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree "MDIO"
|
|
base ad:0x5c030000
|
|
width 9.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,MDIO Revision ID Register"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "CONTROL,MDIO Control Register"
|
|
bitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE status" "Busy,Idle"
|
|
bitfld.long 0x00 30. " ENABLE ,MDIO state machine enable control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--28. 1. " HUC ,Highest User-access Channel"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PREAMBLE ,MDIO frame preamble disable" "No,Yes"
|
|
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Failure"
|
|
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
|
|
line.long 0x04 "ALIVE,MDIO PHY Alive Indication Register"
|
|
eventfld.long 0x04 31. " ALIVE[31] ,MDIO ALIVE bit 31" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 30. " ALIVE[30] ,MDIO ALIVE bit 30" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 29. " ALIVE[29] ,MDIO ALIVE bit 29" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 28. " ALIVE[28] ,MDIO ALIVE bit 28" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 27. " ALIVE[27] ,MDIO ALIVE bit 27" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 26. " ALIVE[26] ,MDIO ALIVE bit 26" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 25. " ALIVE[25] ,MDIO ALIVE bit 25" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 24. " ALIVE[24] ,MDIO ALIVE bit 24" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 23. " ALIVE[23] ,MDIO ALIVE bit 23" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 22. " ALIVE[22] ,MDIO ALIVE bit 22" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 21. " ALIVE[21] ,MDIO ALIVE bit 21" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 20. " ALIVE[20] ,MDIO ALIVE bit 20" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 19. " ALIVE[19] ,MDIO ALIVE bit 19" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 18. " ALIVE[18] ,MDIO ALIVE bit 18" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 17. " ALIVE[17] ,MDIO ALIVE bit 17" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 16. " ALIVE[16] ,MDIO ALIVE bit 16" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 15. " ALIVE[15] ,MDIO ALIVE bit 15" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 14. " ALIVE[14] ,MDIO ALIVE bit 14" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 13. " ALIVE[13] ,MDIO ALIVE bit 13" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 12. " ALIVE[12] ,MDIO ALIVE bit 12" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 11. " ALIVE[11] ,MDIO ALIVE bit 11" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 10. " ALIVE[10] ,MDIO ALIVE bit 10" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 9. " ALIVE[9] ,MDIO ALIVE bit 9" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 8. " ALIVE[8] ,MDIO ALIVE bit 8" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 7. " ALIVE[7] ,MDIO ALIVE bit 7" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 6. " ALIVE[6] ,MDIO ALIVE bit 6" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 5. " ALIVE[5] ,MDIO ALIVE bit 5" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 4. " ALIVE[4] ,MDIO ALIVE bit 4" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 3. " ALIVE[3] ,MDIO ALIVE bit 3" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 2. " ALIVE[2] ,MDIO ALIVE bit 2" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 1. " ALIVE[1] ,MDIO ALIVE bit 1" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 0. " ALIVE[0] ,MDIO ALIVE bit 0" "Not acknowledged,Acknowledged"
|
|
rgroup.long 0x0c++0x3
|
|
line.long 0x00 "LINK,MDIO PHY Link Status Register"
|
|
bitfld.long 0x00 31. " LINK[31] ,MDIO link state bit 31" "No link,Link"
|
|
bitfld.long 0x00 30. " LINK[30] ,MDIO link state bit 30" "No link,Link"
|
|
bitfld.long 0x00 29. " LINK[29] ,MDIO link state bit 29" "No link,Link"
|
|
bitfld.long 0x00 28. " LINK[28] ,MDIO link state bit 28" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LINK[27] ,MDIO link state bit 27" "No link,Link"
|
|
bitfld.long 0x00 26. " LINK[26] ,MDIO link state bit 26" "No link,Link"
|
|
bitfld.long 0x00 25. " LINK[25] ,MDIO link state bit 25" "No link,Link"
|
|
bitfld.long 0x00 24. " LINK[24] ,MDIO link state bit 24" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LINK[23] ,MDIO link state bit 23" "No link,Link"
|
|
bitfld.long 0x00 22. " LINK[22] ,MDIO link state bit 22" "No link,Link"
|
|
bitfld.long 0x00 21. " LINK[21] ,MDIO link state bit 21" "No link,Link"
|
|
bitfld.long 0x00 20. " LINK[20] ,MDIO link state bit 20" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LINK[19] ,MDIO link state bit 19" "No link,Link"
|
|
bitfld.long 0x00 18. " LINK[18] ,MDIO link state bit 18" "No link,Link"
|
|
bitfld.long 0x00 17. " LINK[17] ,MDIO link state bit 17" "No link,Link"
|
|
bitfld.long 0x00 16. " LINK[16] ,MDIO link state bit 16" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LINK[15] ,MDIO link state bit 15" "No link,Link"
|
|
bitfld.long 0x00 14. " LINK[14] ,MDIO link state bit 14" "No link,Link"
|
|
bitfld.long 0x00 13. " LINK[13] ,MDIO link state bit 13" "No link,Link"
|
|
bitfld.long 0x00 12. " LINK[12] ,MDIO link state bit 12" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LINK[11] ,MDIO link state bit 11" "No link,Link"
|
|
bitfld.long 0x00 10. " LINK[10] ,MDIO link state bit 10" "No link,Link"
|
|
bitfld.long 0x00 9. " LINK[9] ,MDIO link state bit 9" "No link,Link"
|
|
bitfld.long 0x00 8. " LINK[8] ,MDIO link state bit 8" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LINK[7] ,MDIO link state bit 7" "No link,Link"
|
|
bitfld.long 0x00 6. " LINK[6] ,MDIO link state bit 6" "No link,Link"
|
|
bitfld.long 0x00 5. " LINK[5] ,MDIO link state bit 5" "No link,Link"
|
|
bitfld.long 0x00 4. " LINK[4] ,MDIO link state bit 4" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LINK[3] ,MDIO link state bit 3" "No link,Link"
|
|
bitfld.long 0x00 2. " LINK[2] ,MDIO link state bit 2" "No link,Link"
|
|
bitfld.long 0x00 1. " LINK[1] ,MDIO link state bit 1" "No link,Link"
|
|
bitfld.long 0x00 0. " LINK[0] ,MDIO link state bit 0" "No link,Link"
|
|
width 18.
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "LINKINTRAW,MDIO Link Status Change Interrupt Register"
|
|
eventfld.long 0x00 1. " USERPHY1 ,MDIO link change event" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " USERPHY0 ,MDIO link change event" "Not changed,Changed"
|
|
line.long 0x04 "LINKINTMASKED,MDIO Link Status Change Interrupt (Masked) Register"
|
|
eventfld.long 0x04 1. " USERPHY1 ,MDIO link change interrupt" "Not changed,Changed"
|
|
eventfld.long 0x04 0. " USERPHY0 ,MDIO link change interrupt" "Not changed,Changed"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "USERINTRAW,MDIO User Command Complete Interrupt Register"
|
|
eventfld.long 0x00 1. " USERACCESS1 ,MDIO user command complete event" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " USERACCESS0 ,MDIO user command complete event" "Not completed,Completed"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "USERINTMASKED,MDIO User Command Complete Interrupt (Masked) Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
|
|
group.long 0x80++0x0f
|
|
line.long 0x00 "USERACCESS0,MDIO User Access Register 0"
|
|
bitfld.long 0x00 31. " GO ,GO bit" "No effect,MDIO accessed"
|
|
bitfld.long 0x00 30. " WRITE ,Write enable" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
|
|
hexmask.long.word 0x00 21.--25. 0x20 " REGADR ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data"
|
|
line.long 0x04 "USERPHYSEL0,MDIO User PHY Select Register 0"
|
|
bitfld.long 0x04 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
|
|
bitfld.long 0x04 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
|
|
line.long 0x08 "USERACCESS1,MDIO User Access Register 1"
|
|
bitfld.long 0x08 31. " GO ,GO bit" "No effect,MDIO accessed"
|
|
bitfld.long 0x08 30. " WRITE ,Write enable" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
|
|
hexmask.long.word 0x08 21.--25. 0x20 " REGADR ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x08 0.--15. 1. " DATA ,User data"
|
|
line.long 0x0c "USERPHYSEL1,MDIO User PHY Select Register 1"
|
|
bitfld.long 0x0c 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
|
|
bitfld.long 0x0c 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMAC Module"
|
|
base ad:0x5c010000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "TXREVID,Transmit Revision ID Register"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "TXCONTROL,Transmit Control Register"
|
|
bitfld.long 0x00 0. " TXEN ,Transmit enable" "Disabled,Enabled"
|
|
line.long 0x04 "TXTEARDOWN,Transmit Teardown Register"
|
|
bitfld.long 0x04 0.--2. " TXTDNCH ,Transmit teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RXREVID,Receive Revision ID Register"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "RXCONTROL,Receive Control Register"
|
|
bitfld.long 0x00 0. " RXEN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "RXTEARDOWN,Receive Teardown Register"
|
|
bitfld.long 0x04 31. " RXTNRDY ,Teardown Ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0.--2. " RXTDNCH ,Receive teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "TXINTSTATRAW,Transmit Interrupt Status (Unmasked) Register"
|
|
bitfld.long 0x00 7. " TX7PEND ,TX7PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " TX6PEND ,TX6PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX5PEND ,TX5PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " TX4PEND ,TX4PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX3PEND ,TX3PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TX2PEND ,TX2PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1PEND ,TX1PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TX0PEND ,TX0PEND raw interrupt read" "No interrupt,Interrupt"
|
|
line.long 0x04 "TXINTSTATMASKED,Transmit Interrupt Status (Masked) Register"
|
|
bitfld.long 0x04 7. " TX7PEND ,TX7PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " TX6PEND ,TX6PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX5PEND ,TX5PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " TX4PEND ,TX4PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TX3PEND ,TX3PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " TX2PEND ,TX2PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX1PEND ,TX1PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TX0PEND ,TX0PEND masked interrupt read" "No interrupt,Interrupt"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "TXINTMASKSET,Transmit Interrupt Status Mask Set Register"
|
|
bitfld.long 0x00 23. " TX7PULSEMASK ,Transmit channel 7 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " TX6PULSEMASK ,Transmit channel 6 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 21. " TX5PULSEMASK ,Transmit channel 5 Pulse mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TX4PULSEMASK ,Transmit channel 4 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 19. " TX3PULSEMASK ,Transmit channel 3 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " TX2PULSEMASK ,Transmit channel 2 Pulse mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TX1PULSEMASK ,Transmit channel 1 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " TX0PULSEMASK ,Transmit channel 0 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 7. " TX7PENDMASK ,Transmit channel 7 pend interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TX6PENDMASK ,Transmit channel 6 pend interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 5. " TX5PENDMASK ,Transmit channel 5 pend interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " TX4PENDMASK ,Transmit channel 4 pend interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX3PENDMASK ,Transmit channel 3 pend interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " TX2PENDMASK ,Transmit channel 2 pend interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " TX1PENDMASK ,Transmit channel 1 pend interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX0PENDMASK ,Transmit channel 0 pend interrupt mask set" "No effect,Enabled"
|
|
line.long 0x04 "TXINTMASKCLEAR,Transmit Interrupt Status Mask Clear Register"
|
|
eventfld.long 0x04 23. " TX7PULSEMASK ,Transmit channel 7 Pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 22. " TX6PULSEMASK ,Transmit channel 6 Pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 21. " TX5PULSEMASK ,Transmit channel 5 Pulse mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 20. " TX4PULSEMASK ,Transmit channel 4 Pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 19. " TX3PULSEMASK ,Transmit channel 3 Pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 18. " TX2PULSEMASK ,Transmit channel 2 Pulse mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 17. " TX1PULSEMASK ,Transmit channel 1 Pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 16. " TX0PULSEMASK ,Transmit channel 0 Pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 7. " TX7PENDMASK ,Transmit channel 7 pend interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 6. " TX6PENDMASK ,Transmit channel 6 pend interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 5. " TX5PENDMASK ,Transmit channel 5 pend interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 4. " TX4PENDMASK ,Transmit channel 4 pend interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " TX3PENDMASK ,Transmit channel 3 pend interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 2. " TX2PENDMASK ,Transmit channel 2 pend interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 1. " TX1PENDMASK ,Transmit channel 1 pend interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " TX0PENDMASK ,Transmit channel 0 pend interrupt mask clear" "No effect,Cleared"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "MACINVECTOR,MAC Input Vector Register"
|
|
bitfld.long 0x00 27. " STATPEND ,EMAC module statistics interrupt (STATPEND) pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " HOSTPEND ,EMAC module host error interrupt (HOSTPEND) pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINKINT0 ,MDIO module USERPHYSEL0 (LINKINT0) status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " USERINT0 ,MDIO module USERACCESS0 (USERINT0) status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TX7PEND ,Transmit channel interrupt 7 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " TX6PEND ,Transmit channel interrupt 6 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TX5PEND ,Transmit channel interrupt 5 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TX4PEND ,Transmit channel interrupt 4 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TX3PEND ,Transmit channel interrupt 3 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " TX2PEND ,Transmit channel interrupt 2 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TX1PEND ,Transmit channel interrupt 1 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " TX0PEND ,Transmit channel interrupt 0 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RX7THRESHPEND ,Receive channel 7 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " RX6THRESHPEND ,Receive channel 6 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5THRESHPEND ,Receive channel 5 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " RX4THRESHPEND ,Receive channel 4 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3THRESHPEND ,Receive channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " RX2THRESHPEND ,Receive channel 2 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1THRESHPEND ,Receive channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " RX0THRESHPEND ,Receive channel 0 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7PEND ,Receive channel 7 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " RX6PEND ,Receive channel 6 interrupt pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5PEND ,Receive channel 5 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " RX4PEND ,Receive channel 4 interrupt pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3PEND ,Receive channel 3 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " RX2PEND ,Receive channel 2 interrupt pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1PEND ,Receive channel 1 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " RX0PEND ,Receive channel 0 interrupt pending status" "Not pending,Pending"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MACEOIVECTOR,MAC End Of Interrupt Vector Register"
|
|
bitfld.long 0x00 0.--4. " INTVECT ,Acknowledge EMAC Control Module Interrupts" "C0RXTHRESH,C0RX,C0TX,C0MISC,C1RXTHRESH,C1RX,C1TX,C1MISC,C2RXTHRESH,C2RX,C2TX,C2MISC,?..."
|
|
rgroup.long 0xa0++0x7
|
|
line.long 0x00 "RXINTSTATRAW,Receive Interrupt Status (Unmasked) Register"
|
|
bitfld.long 0x00 15. " RX7THRESHPEND ,RX7THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RX6THRESHPEND ,RX6THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5THRESHPEND ,RX5THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RX4THRESHPEND ,RX4THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3THRESHPEND ,RX3THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RX2THRESHPEND ,RX2THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1THRESHPEND ,RX1THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RX0THRESHPEND ,RX0THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7PEND ,RX7PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RX6PEND ,RX6PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5PEND ,RX5PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RX4PEND ,RX4PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3PEND ,RX3PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RX2PEND ,RX2PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1PEND ,RX1PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RX0PEND ,RX0PEND raw interrupt read" "No interrupt,Interrupt"
|
|
line.long 0x04 "RXINTSTATMASKED,Receive Interrupt Status (Masked) Register"
|
|
bitfld.long 0x04 15. " RX7THRESHPEND ,RX7THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " RX6THRESHPEND ,RX6THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RX5THRESHPEND ,RX5THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " RX4THRESHPEND ,RX4THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RX3THRESHPEND ,RX3THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " RX2THRESHPEND ,RX2THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX1THRESHPEND ,RX1THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RX0THRESHPEND ,RX0THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RX7PEND ,RX7PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RX6PEND ,RX6PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RX5PEND ,RX5PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RX4PEND ,RX4PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX3PEND ,RX3PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RX2PEND ,RX2PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RX1PEND ,RX1PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RX0PEND ,RX0PEND masked interrupt read" "No interrupt,Interrupt"
|
|
group.long 0xa8++0x7
|
|
line.long 0x00 "RXINTMASKSET,Receive Interrupt Status Mask Set Register"
|
|
bitfld.long 0x00 23. " RX7PULSEMASK ,Receive channel 7 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " RX6PULSEMASK ,Receive channel 6 Pulse mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX5PULSEMASK ,Receive channel 5 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " RX4PULSEMASK ,Receive channel 4 Pulse mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX3PULSEMASK ,Receive channel 3 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " RX2PULSEMASK ,Receive channel 2 Pulse mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX1PULSEMASK ,Receive channel 1 Pulse mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " RX0PULSEMASK ,Receive channel 0 Pulse mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RX7THRESHMASK ,Receive channel 7 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " RX6THRESHMASK ,Receive channel 6 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5THRESHMASK ,Receive channel 5 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " RX4THRESHMASK ,Receive channel 4 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3THRESHMASK ,Receive channel 3 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " RX2THRESHMASK ,Receive channel 2 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1THRESHMASK ,Receive channel 1 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " RX0THRESHMASK ,Receive channel 0 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7PENDMASK ,Receive channel 7 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " RX6PENDMASK ,Receive channel 6 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5PENDMASK ,Receive channel 5 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " RX4PENDMASK ,Receive channel 4 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3PENDMASK ,Receive channel 3 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " RX2PENDMASK ,Receive channel 2 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1PENDMASK ,Receive channel 1 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " RX0PENDMASK ,Receive channel 0 interrupt mask set" "No effect,Enabled"
|
|
line.long 0x04 "RXINTMASKCLEAR,Receive Interrupt Mask Clear Register"
|
|
eventfld.long 0x04 23. " RX7PULSEMASK ,Receive channel 7 pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 22. " RX6PULSEMASK ,Receive channel 6 pulse mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 21. " RX5PULSEMASK ,Receive channel 5 pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 20. " RX4PULSEMASK ,Receive channel 4 pulse mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 19. " RX3PULSEMASK ,Receive channel 3 pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 18. " RX2PULSEMASK ,Receive channel 2 pulse mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 17. " RX1PULSEMASK ,Receive channel 1 pulse mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 16. " RX0PULSEMASK ,Receive channel 0 pulse mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 15. " RX7THRESHMASK ,Receive channel 7 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 14. " RX6THRESHMASK ,Receive channel 6 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 13. " RX5THRESHMASK ,Receive channel 5 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 12. " RX4THRESHMASK ,Receive channel 4 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 11. " RX3THRESHMASK ,Receive channel 3 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 10. " RX2THRESHMASK ,Receive channel 2 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 9. " RX1THRESHMASK ,Receive channel 1 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 8. " RX0THRESHMASK ,Receive channel 0 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 7. " RX7PENDMASK ,Receive channel 7 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 6. " RX6PENDMASK ,Receive channel 6 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 5. " RX5PENDMASK ,Receive channel 5 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 4. " RX4PENDMASK ,Receive channel 4 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " RX3PENDMASK ,Receive channel 3 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 2. " RX2PENDMASK ,Receive channel 2 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 1. " RX1PENDMASK ,Receive channel 1 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " RX0PENDMASK ,Receive channel 0 interrupt mask set" "No effect,Cleared"
|
|
rgroup.long 0xb0++0x7
|
|
line.long 0x00 "MACINTSTATRAW,MAC Interrupt Status (Unmasked) Register"
|
|
bitfld.long 0x00 1. " HOSTPEND ,Host pending interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " STATPEND ,Statistics pending interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "MACINTSTATMASKED,MAC Interrupt Status (Masked) Register"
|
|
bitfld.long 0x04 1. " HOSTPEND ,Host pending interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " STATPEND ,Statistics pending interrupt" "No interrupt,Interrupt"
|
|
group.long 0xb8++0x7
|
|
line.long 0x00 "MACINTSTATMASKSET,MAC Interrupt Status Mask Set Register"
|
|
bitfld.long 0x00 1. " HOSTMASK ,Host error interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " STATMASK ,Statistics interrupt mask set" "No effect,Enabled"
|
|
line.long 0x04 "MACINTSTATMASKCLEAR,MAC Interrupt Status Mask Clear Register"
|
|
eventfld.long 0x04 1. " HOSTMASK ,Host error interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " STATMASK ,Statistics interrupt mask clear" "No effect,Cleared"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "RXMBPENABLE,Receive Multicast/Broadcast/Promiscuous Channel Enable Register"
|
|
bitfld.long 0x00 30. " RXPASSCRC ,Pass received CRC enable" "Discarded,Transferred"
|
|
bitfld.long 0x00 29. " RXQOSEN ,Receive quality of service enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single"
|
|
bitfld.long 0x00 24. " RXCMFEN ,Receive copy MAC control frames enable" "Filtered,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RXCSFEN ,Receive copy short frames enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 22. " RXCEFEN ,Receive copy error frames enable" "Filtered,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RXCAFEN ,Receive copy all frames enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 16.--18. " RXPROMCH ,Receive promiscuous channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXBROADEN ,Receive broadcast enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 8.--10. " RXBROADCH ,Receive broadcast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXMULTEN ,Receive multicast enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 0.--2. " RXMULTCH ,Receive multicast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
line.long 0x04 "RXUNICASTSET,Receive Unicast Set Register"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Receive channel 7 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Receive channel 6 unicast enable set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5EN ,Receive channel 5 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 4. " RXCH4EN ,Receive channel 4 unicast enable set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3EN ,Receive channel 3 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Receive channel 2 unicast enable set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Receive channel 1 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Receive channel 0 unicast enable set" "No effect,Enabled"
|
|
line.long 0x08 "RXUNICASTCLEAR,Receive Unicast Clear Register"
|
|
eventfld.long 0x08 7. " RXCH7CLEAR ,Receive channel 7 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 6. " RXCH6CLEAR ,Receive channel 6 unicast enable clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 5. " RXCH5CLEAR ,Receive channel 5 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 4. " RXCH4CLEAR ,Receive channel 4 unicast enable clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RXCH3CLEAR ,Receive channel 3 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 2. " RXCH2CLEAR ,Receive channel 2 unicast enable clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 1. " RXCH1CLEAR ,Receive channel 1 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 0. " RXCH0CLEAR ,Receive channel 0 unicast enable clear" "No effect,Cleared"
|
|
line.long 0x0c "RXMAXLEN,Receive Maximum Length Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RXMAXLEN ,Received maximum frame length"
|
|
line.long 0x10 "RXBUFFEROFFSET,Receive Buffer Offset Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " BUFFEROFFSET ,Receive buffer offset"
|
|
line.long 0x14 "RXFILTERLOWTHRESH,Receive Filter Low Priority Frame Threshold Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RXFILTERTHRESH ,Receive filter low threshold"
|
|
group.long 0x120++0x1f
|
|
line.long 0x0 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX0FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x4 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " RX1FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x8 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " RX2FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0xC "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. " RX3FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x10 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " RX4FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x14 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RX5FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x18 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " RX6FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x1C "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " RX7FLOWTHRESH ,Receive flow threshold"
|
|
wgroup.long 0x140++0x1f
|
|
line.long 0x0 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX0FREEBUF ,Receive free buffer count"
|
|
line.long 0x4 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " RX1FREEBUF ,Receive free buffer count"
|
|
line.long 0x8 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " RX2FREEBUF ,Receive free buffer count"
|
|
line.long 0xC "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " RX3FREEBUF ,Receive free buffer count"
|
|
line.long 0x10 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " RX4FREEBUF ,Receive free buffer count"
|
|
line.long 0x14 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RX5FREEBUF ,Receive free buffer count"
|
|
line.long 0x18 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " RX6FREEBUF ,Receive free buffer count"
|
|
line.long 0x1C "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RX7FREEBUF ,Receive free buffer count"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "MACCONTROL,MAC Control Register"
|
|
bitfld.long 0x00 18. " MACEXTEN ,External Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GIGFORCE ,Gigabit Mode Force" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MACIFCTL_B ,GMII Interface Control B" "10 Mbps,100 Mbps"
|
|
bitfld.long 0x00 15. " MACIFCTL_A ,RMII interface transmit and receive speed select" "10 Mbps,100 Mbps"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RXOFFLENBLOCK ,Receive offset / length word write block" "Not blocked,Blocked"
|
|
bitfld.long 0x00 13. " RXOWNERSHIP ,Receive ownership write bit value" "Zero,One"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CMDIDLE ,Command Idle" "Not commanded,Commanded"
|
|
bitfld.long 0x00 10. " TXSHORTGAPEN ,Transmit Short Gap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXPTYPE ,Transmit queue priority type" "Round-robin,Fixed-priority"
|
|
bitfld.long 0x00 8. " MEMTEST ,FIFO RAM processor read/write enable (ram test mode)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GMIIEN ,GMII enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXBUFFERFLOWEN ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loopback mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full-duplex mode enable" "Half-duplex,Full-duplex"
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "MACSTATUS,MAC Status Register"
|
|
bitfld.long 0x00 31. " IDLE ,EMAC idle" "Busy,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TXERRCODE ,Transmit host error code" "No error,SOP error,Ownership bit not set in SOP buffer,Zero next buffer descriptor pointer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TXERRCH ,Transmit host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " RXERRCODE ,Receive host error code" "No error,Reserved,Ownership bit not set in SOP buffer,Reserved,Zero buffer pointer,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RXERRCH ,Receive host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
bitfld.long 0x00 4. " EXTGIGSEL ,External GIG" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EXTFULLDUPLEXSEL ,External Fullduplex" "Low,High"
|
|
bitfld.long 0x00 2. " RXQOSACT ,Receive quality of service (QOS) active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXFLOWACT ,Receive flow control active" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXFLOWACT ,Transmit flow control active" "Disabled,Enabled"
|
|
group.long 0x168++0x07
|
|
line.long 0x00 "EMCONTROL,Emulation Control Register"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation soft" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FREE ,Emulation free" "Disabled,Enabled"
|
|
line.long 0x04 "FIFOCONTROL,FIFO Control Register"
|
|
bitfld.long 0x04 0.--1. " TXCELLTHRESH ,Transmit FIFO cell threshold" "Not valid,Not valid,2 cells,3 cells"
|
|
rgroup.long 0x170++0x3
|
|
line.long 0x00 "MACCONFIG,MAC Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TXCELLDEPTH ,Transmit cell depth"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCELLDEPTH ,Receive cell depth"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ADDRESSTYPE ,Address type"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACCFIG ,MAC configuration value"
|
|
group.long 0x174++0x3
|
|
line.long 0x00 "SOFTRESET,Soft Reset Register"
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x1d0++0xf
|
|
line.long 0x00 "MACSRCADDRLO,MAC Source Address Low Bytes Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits (byte 0)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15-8 (byte 1)"
|
|
line.long 0x04 "MACSRCADDRHI,MAC Source Address High Bytes Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23-16 (byte 2)"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31-24 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39-32 (byte 4)"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47-40 (byte 5)"
|
|
line.long 0x08 "MACHASH1,MAC Address Hash 1 Register"
|
|
line.long 0x0c "MACHASH2,MAC Address Hash 2 Register"
|
|
rgroup.long 0x1e0++0xf
|
|
line.long 0x00 "BOFFTEST,Backoff Test Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " RNDNUM ,Backoff random number generator"
|
|
hexmask.long.byte 0x00 12.--15. 1. " COLLCOUNT ,Collision count"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " TXBACKOFF ,Backoff count"
|
|
line.long 0x04 "TPACETEST,Transmit Pacing Test Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " PACEVAL ,Pacing register current value"
|
|
line.long 0x08 "RXPAUSE,Receive Pause Timer Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PAUSETIMER ,Receive pause timer value"
|
|
line.long 0x0c "TXPAUSE,Transmit Pause Timer Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " PAUSETIMER ,Transmit pause timer value"
|
|
group.long 0x500++0xb
|
|
line.long 0x00 "MACADDRLO,MAC Address Low Bytes Register"
|
|
bitfld.long 0x00 20. " VALID ,Address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 19. " MATCHFILT ,Match or filter" "Filter,Match"
|
|
bitfld.long 0x00 16.--18. " CHANNEL ,Channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MACADDR0 ,MAC address lower 8 bits (byte 0)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACADDR1 ,MAC address bits 15-8 (byte 1)"
|
|
line.long 0x04 "MACADDRHI,MAC Address High Bytes Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MACADDR2 ,MAC source address bits 23-16 (byte 2)"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MACADDR3 ,MAC source address bits 31-24 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " MACADDR4 ,MAC source address bits 39-32 (byte 4)"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MACADDR5 ,MAC source address bits 47-40 (byte 5)"
|
|
line.long 0x08 "MACINDEX,MAC Index Register"
|
|
hexmask.long.byte 0x08 0.--4. 1. " MACINDEX ,MAC address index"
|
|
group.long 0x600--0x67f
|
|
line.long 0x0 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register"
|
|
line.long 0x4 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register"
|
|
line.long 0x8 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register"
|
|
line.long 0xC "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register"
|
|
line.long 0x10 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register"
|
|
line.long 0x14 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register"
|
|
line.long 0x18 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register"
|
|
line.long 0x1C "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register"
|
|
line.long 0x20 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register"
|
|
line.long 0x24 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register"
|
|
line.long 0x28 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register"
|
|
line.long 0x2C "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register"
|
|
line.long 0x30 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register"
|
|
line.long 0x34 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register"
|
|
line.long 0x38 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register"
|
|
line.long 0x3C "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register"
|
|
line.long 0x40 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x44 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x48 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x4C "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x50 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x54 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x58 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x5C "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x60 "RX0CP,Receive Channel 0 Completion Pointer Register"
|
|
line.long 0x64 "RX1CP,Receive Channel 1 Completion Pointer Register"
|
|
line.long 0x68 "RX2CP,Receive Channel 2 Completion Pointer Register"
|
|
line.long 0x6C "RX3CP,Receive Channel 3 Completion Pointer Register"
|
|
line.long 0x70 "RX4CP,Receive Channel 4 Completion Pointer Register"
|
|
line.long 0x74 "RX5CP,Receive Channel 5 Completion Pointer Register"
|
|
line.long 0x78 "RX6CP,Receive Channel 6 Completion Pointer Register"
|
|
line.long 0x7C "RX7CP,Receive Channel 7 Completion Pointer Register"
|
|
group.long 0x200++0x8f "Network Statistics Registers"
|
|
line.long 0x00 "RXGOODFRAMES,Good Receive Frames Register"
|
|
line.long 0x04 "RXBCASTFRAMES,Broadcast Receive Frames Register"
|
|
line.long 0x08 "RXMCASTFRAMES,Multicast Receive Frames Register"
|
|
line.long 0x0c "RXPAUSEFRAMES,Pause Receive Frames Register"
|
|
line.long 0x10 "RXCRCERRORS,Receive CRC Errors Register"
|
|
line.long 0x14 "RXALIGNCODEERRORS,Receive Alignment/Code Errors Register"
|
|
line.long 0x18 "RXOVERSIZED,Receive Oversized Frames Register"
|
|
line.long 0x1c "RXJABBER,Receive Jabber Frames Register"
|
|
line.long 0x20 "RXUNDERSIZED,Receive Undersized Frames Register"
|
|
line.long 0x24 "RXFRAGMENTS,Receive Frame Fragments Register"
|
|
line.long 0x28 "RXFILTERED,Filtered Receive Frames Register"
|
|
line.long 0x2c "RXQOSFILTERED,Receive QOS Filtered Frames Register"
|
|
line.long 0x30 "RXOCTETS,Receive Octet Frames Register"
|
|
line.long 0x34 "TXGOODFRAMES,Good Transmit Frames Register"
|
|
line.long 0x38 "TXBCASTFRAMES,Broadcast Transmit Frames Register"
|
|
line.long 0x3c "TXMCASTFRAMES,Multicast Transmit Frames Register"
|
|
line.long 0x40 "TXPAUSEFRAMES,Pause Transmit Frames Register"
|
|
line.long 0x44 "TXDEFERRED,Deferred Transmit Frames Register"
|
|
line.long 0x48 "TXCOLLISION,Transmit Collision Frames Register"
|
|
line.long 0x4c "TXSINGLECOLL,Transmit Single Collision Frames Register"
|
|
line.long 0x50 "TXMULTICOLL,Transmit Multiple Collision Frames Register"
|
|
line.long 0x54 "TXEXCESSIVECOLL,Transmit Excessive Collision Frames Register"
|
|
line.long 0x58 "TXLATECOLL,Transmit Late Collision Frames Register"
|
|
line.long 0x5c "TXUNDERRUN,Transmit Underrun Error Register"
|
|
line.long 0x60 "TXCARRIERSENSE,Transmit Carrier Sense Errors Register"
|
|
line.long 0x64 "TXOCTETS,Transmit Octet Frames Register"
|
|
line.long 0x68 "FRAME64,Transmit and Receive 64 Octet Frames Register"
|
|
line.long 0x6c "FRAME65T127,Transmit and Receive 65 to 127 Octet Frames Register"
|
|
line.long 0x70 "FRAME128T255,Transmit and Receive 128 to 255 Octet Frames Register"
|
|
line.long 0x74 "FRAME256T511,Transmit and Receive 256 to 511 Octet Frames Register"
|
|
line.long 0x78 "FRAME512T1023,Transmit and Receive 512 to 1023 Octet Frames Register"
|
|
line.long 0x7c "FRAME1024TUP,Transmit and Receive 1024 to RXMAXLEN Octet Frames Register"
|
|
line.long 0x80 "NETOCTETS,Network Octet Frames Register"
|
|
line.long 0x84 "RXSOFOVERRUNS,Receive FIFO or DMA Start of Frame Overruns Register"
|
|
line.long 0x88 "RXMOFOVERRUNS,Receive FIFO or DMA Middle of Frame Overruns Register"
|
|
line.long 0x8c "RXDMAOVERRUNS,Receive DMA Overruns Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "HECC (High-End CAN Controller)"
|
|
tree "SSC/HECC Control Registers"
|
|
base ad:0x5c050000
|
|
width 8.
|
|
group.long 0x0++0x23
|
|
line.long 0x00 "CANME,Mailbox Enable Register"
|
|
bitfld.long 0x0 31. " ME31 ,Mailbox 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " ME30 ,Mailbox 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " ME29 ,Mailbox 29 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " ME28 ,Mailbox 28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " ME27 ,Mailbox 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " ME26 ,Mailbox 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " ME25 ,Mailbox 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " ME24 ,Mailbox 24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " ME23 ,Mailbox 23 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " ME22 ,Mailbox 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " ME21 ,Mailbox 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " ME20 ,Mailbox 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " ME19 ,Mailbox 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " ME18 ,Mailbox 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " ME17 ,Mailbox 17 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " ME16 ,Mailbox 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " ME15 ,Mailbox 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " ME14 ,Mailbox 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " ME13 ,Mailbox 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " ME12 ,Mailbox 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " ME11 ,Mailbox 11 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " ME10 ,Mailbox 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " ME9 ,Mailbox 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " ME8 ,Mailbox 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ME7 ,Mailbox 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " ME6 ,Mailbox 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " ME5 ,Mailbox 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " ME4 ,Mailbox 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " ME3 ,Mailbox 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " ME2 ,Mailbox 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ME1 ,Mailbox 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " ME0 ,Mailbox 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "CANMD,Mailbox Direction Register"
|
|
bitfld.long 0x4 31. " MD31 ,Mailbox 31 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 30. " MD30 ,Mailbox 30 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 29. " MD29 ,Mailbox 29 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 28. " MD28 ,Mailbox 28 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 27. " MD27 ,Mailbox 27 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 26. " MD26 ,Mailbox 26 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 25. " MD25 ,Mailbox 25 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 24. " MD24 ,Mailbox 24 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 23. " MD23 ,Mailbox 23 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 22. " MD22 ,Mailbox 22 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 21. " MD21 ,Mailbox 21 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 20. " MD20 ,Mailbox 20 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 19. " MD19 ,Mailbox 19 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 18. " MD18 ,Mailbox 18 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 17. " MD17 ,Mailbox 17 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 16. " MD16 ,Mailbox 16 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 15. " MD15 ,Mailbox 15 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 14. " MD14 ,Mailbox 14 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 13. " MD13 ,Mailbox 13 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 12. " MD12 ,Mailbox 12 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 11. " MD11 ,Mailbox 11 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 10. " MD10 ,Mailbox 10 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 9. " MD9 ,Mailbox 9 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 8. " MD8 ,Mailbox 8 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 7. " MD7 ,Mailbox 7 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 6. " MD6 ,Mailbox 6 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 5. " MD5 ,Mailbox 5 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 4. " MD4 ,Mailbox 4 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 3. " MD3 ,Mailbox 3 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 2. " MD2 ,Mailbox 2 direction" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.long 0x4 1. " MD1 ,Mailbox 1 direction" "Transmit,Receive"
|
|
bitfld.long 0x4 0. " MD0 ,Mailbox 0 direction" "Transmit,Receive"
|
|
line.long 0x08 "CANTRS,Transmission Request Set Register"
|
|
bitfld.long 0x8 31. " TRS31 ,Mailbox 31 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 30. " TRS30 ,Mailbox 30 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 29. " TRS29 ,Mailbox 29 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 28. " TRS28 ,Mailbox 28 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 27. " TRS27 ,Mailbox 27 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 26. " TRS26 ,Mailbox 26 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 25. " TRS25 ,Mailbox 25 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 24. " TRS24 ,Mailbox 24 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 23. " TRS23 ,Mailbox 23 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 22. " TRS22 ,Mailbox 22 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 21. " TRS21 ,Mailbox 21 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 20. " TRS20 ,Mailbox 20 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 19. " TRS19 ,Mailbox 19 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 18. " TRS18 ,Mailbox 18 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 17. " TRS17 ,Mailbox 17 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 16. " TRS16 ,Mailbox 16 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 15. " TRS15 ,Mailbox 15 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 14. " TRS14 ,Mailbox 14 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 13. " TRS13 ,Mailbox 13 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 12. " TRS12 ,Mailbox 12 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 11. " TRS11 ,Mailbox 11 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 10. " TRS10 ,Mailbox 10 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 9. " TRS9 ,Mailbox 9 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 8. " TRS8 ,Mailbox 8 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 7. " TRS7 ,Mailbox 7 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 6. " TRS6 ,Mailbox 6 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 5. " TRS5 ,Mailbox 5 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 4. " TRS4 ,Mailbox 4 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 3. " TRS3 ,Mailbox 3 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 2. " TRS2 ,Mailbox 2 transmission request" "No operation,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRS1 ,Mailbox 1 transmission request" "No operation,Requested"
|
|
bitfld.long 0x8 0. " TRS0 ,Mailbox 0 transmission request" "No operation,Requested"
|
|
line.long 0x0c "CANTRR,Transmission Request Reset Register"
|
|
bitfld.long 0xc 31. " TRR31 ,Mailbox 31 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 30. " TRR30 ,Mailbox 30 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 29. " TRR29 ,Mailbox 29 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 28. " TRR28 ,Mailbox 28 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 27. " TRR27 ,Mailbox 27 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 26. " TRR26 ,Mailbox 26 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 25. " TRR25 ,Mailbox 25 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 24. " TRR24 ,Mailbox 24 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 23. " TRR23 ,Mailbox 23 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 22. " TRR22 ,Mailbox 22 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 21. " TRR21 ,Mailbox 21 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 20. " TRR20 ,Mailbox 20 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 19. " TRR19 ,Mailbox 19 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 18. " TRR18 ,Mailbox 18 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 17. " TRR17 ,Mailbox 17 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 16. " TRR16 ,Mailbox 16 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 15. " TRR15 ,Mailbox 15 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 14. " TRR14 ,Mailbox 14 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 13. " TRR13 ,Mailbox 13 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 12. " TRR12 ,Mailbox 12 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 11. " TRR11 ,Mailbox 11 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 10. " TRR10 ,Mailbox 10 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 9. " TRR9 ,Mailbox 9 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 8. " TRR8 ,Mailbox 8 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 7. " TRR7 ,Mailbox 7 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 6. " TRR6 ,Mailbox 6 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 5. " TRR5 ,Mailbox 5 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 4. " TRR4 ,Mailbox 4 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 3. " TRR3 ,Mailbox 3 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 2. " TRR2 ,Mailbox 2 transmission request reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xc 1. " TRR1 ,Mailbox 1 transmission request reset" "No reset,Reset"
|
|
bitfld.long 0xc 0. " TRR0 ,Mailbox 0 transmission request reset" "No reset,Reset"
|
|
line.long 0x10 "CANTA,Transmission Acknowledge Register"
|
|
eventfld.long 0x10 31. " TA31 ,Mailbox 31 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 30. " TA30 ,Mailbox 30 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 29. " TA29 ,Mailbox 29 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 28. " TA28 ,Mailbox 28 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 27. " TA27 ,Mailbox 27 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 26. " TA26 ,Mailbox 26 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 25. " TA25 ,Mailbox 25 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 24. " TA24 ,Mailbox 24 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 23. " TA23 ,Mailbox 23 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 22. " TA22 ,Mailbox 22 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 21. " TA21 ,Mailbox 21 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 20. " TA20 ,Mailbox 20 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 19. " TA19 ,Mailbox 19 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 18. " TA18 ,Mailbox 18 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 17. " TA17 ,Mailbox 17 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 16. " TA16 ,Mailbox 16 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 15. " TA15 ,Mailbox 15 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 14. " TA14 ,Mailbox 14 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 13. " TA13 ,Mailbox 13 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 12. " TA12 ,Mailbox 12 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 11. " TA11 ,Mailbox 11 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 10. " TA10 ,Mailbox 10 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 9. " TA9 ,Mailbox 9 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 8. " TA8 ,Mailbox 8 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 7. " TA7 ,Mailbox 7 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 6. " TA6 ,Mailbox 6 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 5. " TA5 ,Mailbox 5 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 4. " TA4 ,Mailbox 4 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 3. " TA3 ,Mailbox 3 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 2. " TA2 ,Mailbox 2 message success transmission acknowledge" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x10 1. " TA1 ,Mailbox 1 message success transmission acknowledge" "Not sent,Sent"
|
|
eventfld.long 0x10 0. " TA0 ,Mailbox 0 message success transmission acknowledge" "Not sent,Sent"
|
|
line.long 0x14 "CANAA,Abort Acknowledge Register"
|
|
eventfld.long 0x14 31. " AA31 ,Mailbox 31 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 30. " AA30 ,Mailbox 30 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 29. " AA29 ,Mailbox 29 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 28. " AA28 ,Mailbox 28 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 27. " AA27 ,Mailbox 27 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 26. " AA26 ,Mailbox 26 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 25. " AA25 ,Mailbox 25 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 24. " AA24 ,Mailbox 24 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 23. " AA23 ,Mailbox 23 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 22. " AA22 ,Mailbox 22 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 21. " AA21 ,Mailbox 21 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 20. " AA20 ,Mailbox 20 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 19. " AA19 ,Mailbox 19 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 18. " AA18 ,Mailbox 18 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 17. " AA17 ,Mailbox 17 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 16. " AA16 ,Mailbox 16 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 15. " AA15 ,Mailbox 15 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 14. " AA14 ,Mailbox 14 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 13. " AA13 ,Mailbox 13 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 12. " AA12 ,Mailbox 12 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 11. " AA11 ,Mailbox 11 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 10. " AA10 ,Mailbox 10 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 9. " AA9 ,Mailbox 9 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 8. " AA8 ,Mailbox 8 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 7. " AA7 ,Mailbox 7 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 6. " AA6 ,Mailbox 6 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 5. " AA5 ,Mailbox 5 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 4. " AA4 ,Mailbox 4 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 3. " AA3 ,Mailbox 3 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 2. " AA2 ,Mailbox 2 message abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x14 1. " AA1 ,Mailbox 1 message abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.long 0x14 0. " AA0 ,Mailbox 0 message abort acknowledge" "Not aborted,Aborted"
|
|
line.long 0x18 "CANRMP,Receive Message Pending Register"
|
|
eventfld.long 0x18 31. " RMP31 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 30. " RMP30 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 29. " RMP29 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 28. " RMP28 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 27. " RMP27 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 26. " RMP26 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 25. " RMP25 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 24. " RMP24 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 23. " RMP23 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 22. " RMP22 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 21. " RMP21 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 20. " RMP20 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 19. " RMP19 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 18. " RMP18 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 17. " RMP17 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 16. " RMP16 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 15. " RMP15 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 14. " RMP14 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 13. " RMP13 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 12. " RMP12 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 11. " RMP11 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 10. " RMP10 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 9. " RMP9 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 8. " RMP8 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 7. " RMP7 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 6. " RMP6 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 5. " RMP5 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 4. " RMP4 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 3. " RMP3 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 2. " RMP2 ,Message receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x18 1. " RMP1 ,Message receive" "Not received,Received"
|
|
eventfld.long 0x18 0. " RMP0 ,Message receive" "Not received,Received"
|
|
line.long 0x1c "CANRML,Receive Message Lost Register"
|
|
eventfld.long 0x1c 31. " RML31 ,Mailbox 31 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 30. " RML30 ,Mailbox 30 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 29. " RML29 ,Mailbox 29 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 28. " RML28 ,Mailbox 28 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 27. " RML27 ,Mailbox 27 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 26. " RML26 ,Mailbox 26 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 25. " RML25 ,Mailbox 25 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 24. " RML24 ,Mailbox 24 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 23. " RML23 ,Mailbox 23 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 22. " RML22 ,Mailbox 22 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 21. " RML21 ,Mailbox 21 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 20. " RML20 ,Mailbox 20 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 19. " RML19 ,Mailbox 19 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 18. " RML18 ,Mailbox 18 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 17. " RML17 ,Mailbox 17 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 16. " RML16 ,Mailbox 16 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 15. " RML15 ,Mailbox 15 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 14. " RML14 ,Mailbox 14 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 13. " RML13 ,Mailbox 13 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 12. " RML12 ,Mailbox 12 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 11. " RML11 ,Mailbox 11 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 10. " RML10 ,Mailbox 10 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 9. " RML9 ,Mailbox 9 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 8. " RML8 ,Mailbox 8 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 7. " RML7 ,Mailbox 7 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 6. " RML6 ,Mailbox 6 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 5. " RML5 ,Mailbox 5 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 4. " RML4 ,Mailbox 4 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 3. " RML3 ,Mailbox 3 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 2. " RML2 ,Mailbox 2 message overwritten and lost" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x1c 1. " RML1 ,Mailbox 1 message overwritten and lost" "Not lost,Lost"
|
|
eventfld.long 0x1c 0. " RML0 ,Mailbox 0 message overwritten and lost" "Not lost,Lost"
|
|
line.long 0x20 "CANRFP,Remote Frame Pending Register"
|
|
eventfld.long 0x20 31. " RFP31 ,Mailbox 31 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 30. " RFP30 ,Mailbox 30 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 29. " RFP29 ,Mailbox 29 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 28. " RFP28 ,Mailbox 28 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 27. " RFP27 ,Mailbox 27 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 26. " RFP26 ,Mailbox 26 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 25. " RFP25 ,Mailbox 25 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 24. " RFP24 ,Mailbox 24 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 23. " RFP23 ,Mailbox 23 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 22. " RFP22 ,Mailbox 22 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 21. " RFP21 ,Mailbox 21 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 20. " RFP20 ,Mailbox 20 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 19. " RFP19 ,Mailbox 19 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 18. " RFP18 ,Mailbox 18 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 17. " RFP17 ,Mailbox 17 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 16. " RFP16 ,Mailbox 16 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 15. " RFP15 ,Mailbox 15 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 14. " RFP14 ,Mailbox 14 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 13. " RFP13 ,Mailbox 13 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 12. " RFP12 ,Mailbox 12 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 11. " RFP11 ,Mailbox 11 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 10. " RFP10 ,Mailbox 10 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 9. " RFP9 ,Mailbox 9 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 8. " RFP8 ,Mailbox 8 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 7. " RFP7 ,Mailbox 7 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 6. " RFP6 ,Mailbox 6 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 5. " RFP5 ,Mailbox 5 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 4. " RFP4 ,Mailbox 4 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 3. " RFP3 ,Mailbox 3 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 2. " RFP2 ,Mailbox 2 remote frame request receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x20 1. " RFP1 ,Mailbox 1 remote frame request receive" "Not received,Received"
|
|
eventfld.long 0x20 0. " RFP0 ,Mailbox 0 remote frame request receive" "Not received,Received"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CANGAM,Global Acceptance Mask Register"
|
|
bitfld.long 0x0 31. " AMI ,Acceptance Mask Identifier Extension" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 28. " GAM ,Global Acceptance Mask bit28" "0,1"
|
|
bitfld.long 0x0 27. ",Global Acceptance Mask bit27" "0,1"
|
|
bitfld.long 0x0 26. ",Global Acceptance Mask bit26" "0,1"
|
|
bitfld.long 0x0 25. ",Global Acceptance Mask bit25" "0,1"
|
|
bitfld.long 0x0 24. ",Global Acceptance Mask bit24" "0,1"
|
|
bitfld.long 0x0 23. ",Global Acceptance Mask bit23" "0,1"
|
|
bitfld.long 0x0 22. ",Global Acceptance Mask bit22" "0,1"
|
|
bitfld.long 0x0 21. ",Global Acceptance Mask bit21" "0,1"
|
|
bitfld.long 0x0 20. ",Global Acceptance Mask bit20" "0,1"
|
|
bitfld.long 0x0 19. ",Global Acceptance Mask bit19" "0,1"
|
|
bitfld.long 0x0 18. ",Global Acceptance Mask bit18" "0,1"
|
|
bitfld.long 0x0 17. ",Global Acceptance Mask bit17" "0,1"
|
|
bitfld.long 0x0 16. ",Global Acceptance Mask bit16" "0,1"
|
|
bitfld.long 0x0 15. ",Global Acceptance Mask bit15" "0,1"
|
|
bitfld.long 0x0 14. ",Global Acceptance Mask bit14" "0,1"
|
|
bitfld.long 0x0 13. ",Global Acceptance Mask bit13" "0,1"
|
|
bitfld.long 0x0 12. ",Global Acceptance Mask bit12" "0,1"
|
|
bitfld.long 0x0 11. ",Global Acceptance Mask bit11" "0,1"
|
|
bitfld.long 0x0 10. ",Global Acceptance Mask bit10" "0,1"
|
|
bitfld.long 0x0 9. ",Global Acceptance Mask bit9" "0,1"
|
|
bitfld.long 0x0 8. ",Global Acceptance Mask bit8" "0,1"
|
|
bitfld.long 0x0 7. ",Global Acceptance Mask bit7" "0,1"
|
|
bitfld.long 0x0 6. ",Global Acceptance Mask bit6" "0,1"
|
|
bitfld.long 0x0 5. ",Global Acceptance Mask bit5" "0,1"
|
|
bitfld.long 0x0 4. ",Global Acceptance Mask bit4" "0,1"
|
|
bitfld.long 0x0 3. ",Global Acceptance Mask bit3" "0,1"
|
|
bitfld.long 0x0 2. ",Global Acceptance Mask bit2" "0,1"
|
|
bitfld.long 0x0 1. ",Global Acceptance Mask bit1" "0,1"
|
|
bitfld.long 0x0 0. ",Global Acceptance Mask bit0" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "CANMC,Master Control Register"
|
|
bitfld.long 0x0 15. " LNTC ,Local Network Time Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x0 14. " LNTM ,Local Network Time MSB Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SCM ,SCC-Compatibility Mode" "SCC-Compatibility,Normal"
|
|
bitfld.long 0x0 12. " CCR ,Change Configuration Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 11. " PDR ,Power-Down-Mode Request" "Not requested,Requested"
|
|
bitfld.long 0x0 10. " DBO ,Data Byte Order" "MSB first,LSB first"
|
|
textline " "
|
|
bitfld.long 0x0 9. " WUBA ,Wake Up on Bus Activity" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " CDR ,Change Data Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ABO ,Auto Bus On" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " STM ,Self-Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SRES ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x0 0.--4. " MBNR ,Mailbox Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x4 "CANBTC,Bit-Timing Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BRP ,Time Quantum Prescaler"
|
|
bitfld.long 0x4 10. " ERM ,Edge Resynchronization Mode" "Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x4 8.--9. " SJW ,Synchronization Jump Width" "1 TQ,2 TQ,3 TQ,4 TQ"
|
|
bitfld.long 0x4 7. " SAM ,Number of samples to determine CAN bus level" "1 time,3 times"
|
|
textline " "
|
|
bitfld.long 0x4 3.--6. " TSEG1 ,Time Segment 1" "1 TQ,2 TQ,3 TQ,4 TQ,5 TQ,6 TQ,7 TQ,8 TQ,9 TQ,10 TQ,11 TQ,12 TQ,13 TQ,14 TQ,15 TQ,16 TQ"
|
|
bitfld.long 0x4 0.--2. " TSEG2 ,Time Segment 2" "1 TQ,2 TQ,3 TQ,4 TQ,5 TQ,6 TQ,7 TQ,8 TQ"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CANES,Error and Status Register"
|
|
eventfld.long 0x0 24. " FE ,Form Error Flag" "No error,Error"
|
|
eventfld.long 0x0 23. " BE ,Bit Error Flag" "No error,Error"
|
|
eventfld.long 0x0 22. " SA1 ,Stuck at dominant error" "Detected,Not detected"
|
|
textline " "
|
|
eventfld.long 0x0 21. " CRCE ,CRC Error" "No error,Error"
|
|
eventfld.long 0x0 20. " SE ,Stuff Error" "No error,Error"
|
|
eventfld.long 0x0 19. " ACKE ,Acknowledge Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0 18. " BO ,Bus-Off State" "Normal,Bus-Off"
|
|
eventfld.long 0x0 17. " EP ,Error Passive State" "Error-active,Error-passive"
|
|
eventfld.long 0x0 16. " EW ,Warning Status" "No warning,Warning"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SMA ,Suspend Mode Acknowledge" "Normal,Suspend"
|
|
bitfld.long 0x0 4. " CCE ,Change Configuration Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PDA ,Power Down Mode Acknowledge" "Normal,Power-down"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RM ,CAN protocol kernel (CPK) Receive Mode" "Not receiving,Receiving"
|
|
bitfld.long 0x0 0. " TM ,CAN protocol kernel (CPK) Transmit Mode" "Not transmitting,Transmitting"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "CANTEC,Transmit Error Counter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " TEC ,Transmit error counter"
|
|
line.long 0x4 "CANREC,Receive Error Counter Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " REC ,Receive error counter"
|
|
group.long 0x3c++0x3
|
|
line.long 0x0 "CANGIF0,Global Interrupt Flag 0 Register"
|
|
eventfld.long 0x0 17. " MAIF0 ,Message Alarm Flag" "No alarm,Alarm"
|
|
eventfld.long 0x0 16. " TCOIF0 ,Local Network Time Counter Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x0 15. " GMIF0 ,Global Mailbox Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 14. " AAIF0 ,Abort-Acknowledge Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 13. " WDIF0 ,Write-Denied Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 12. " WUIF0 ,Wake-Up Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 11. " RMLIF0 ,Receive-Message-Lost Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 10. " BOIF0 ,Bus-Off Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 9. " EPIF0 ,Error-Passive Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 8. " WLIF0 ,Warning Level Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0.--4. " MIV0[4:0] ,Message Interrupt Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CANGIM,Global Interrupt Mask Register"
|
|
bitfld.long 0x0 17. " MAIM ,Message Alarm Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " TCOIM ,Local Network Time Counter Overflow Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " AAIM ,Abort Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " WDIM ,Write Denied Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " WUIM ,Wake-Up Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " RMLIM ,Receive Message Lost Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " BOIM ,Bus Off Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " EPIM ,Error Passive Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " WLIM ,Warning Level Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SIL ,System Interrupt Level" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x0 1. " I1EN ,Interrupt Line 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " I0EN ,Interrupt Line 0 Enable" "Disabled,Enabled"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "CANGIF1,Global Interrupt Flag 0 Register"
|
|
eventfld.long 0x0 17. " MAIF1 ,Message Alarm Flag" "No alarm,Alarm"
|
|
eventfld.long 0x0 16. " TCOIF1 ,Local Network Time Counter Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x0 15. " GMIF1 ,Global Mailbox Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 14. " AAIF1 ,Abort-Acknowledge Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 13. " WDIF1 ,Write-Denied Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 12. " WUIF1 ,Wake-Up Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 11. " RMLIF1 ,Receive-Message-Lost Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 10. " BOIF1 ,Bus-Off Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 9. " EPIF1 ,Error-Passive Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 8. " WLIF1 ,Warning Level Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0.--4. " MIV1[4:0] ,Message Interrupt Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x48++0x13
|
|
line.long 0x0 "CANMIM,Mailbox Interrupt Mask Register"
|
|
bitfld.long 0x0 31. " MIM31 ,Mailbox Interrupt Mask bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " MIM30 ,Mailbox Interrupt Mask bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " MIM29 ,Mailbox Interrupt Mask bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " MIM28 ,Mailbox Interrupt Mask bit 28" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " MIM27 ,Mailbox Interrupt Mask bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " MIM26 ,Mailbox Interrupt Mask bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MIM25 ,Mailbox Interrupt Mask bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " MIM24 ,Mailbox Interrupt Mask bit 24" "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " MIM23 ,Mailbox Interrupt Mask bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " MIM22 ,Mailbox Interrupt Mask bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " MIM21 ,Mailbox Interrupt Mask bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " MIM20 ,Mailbox Interrupt Mask bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " MIM19 ,Mailbox Interrupt Mask bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " MIM18 ,Mailbox Interrupt Mask bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " MIM17 ,Mailbox Interrupt Mask bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " MIM16 ,Mailbox Interrupt Mask bit 16" "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " MIM15 ,Mailbox Interrupt Mask bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " MIM14 ,Mailbox Interrupt Mask bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " MIM13 ,Mailbox Interrupt Mask bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " MIM12 ,Mailbox Interrupt Mask bit 12" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " MIM11 ,Mailbox Interrupt Mask bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " MIM10 ,Mailbox Interrupt Mask bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " MIM9 ,Mailbox Interrupt Mask bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " MIM8 ,Mailbox Interrupt Mask bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " MIM7 ,Mailbox Interrupt Mask bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " MIM6 ,Mailbox Interrupt Mask bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " MIM5 ,Mailbox Interrupt Mask bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " MIM4 ,Mailbox Interrupt Mask bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " MIM3 ,Mailbox Interrupt Mask bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " MIM2 ,Mailbox Interrupt Mask bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " MIM1 ,Mailbox Interrupt Mask bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MIM0 ,Mailbox Interrupt Mask bit 0" "Disabled,Enabled"
|
|
line.long 0x4 "CANMIL,Mailbox Interrupt Level Register"
|
|
bitfld.long 0x4 31. " MIL31 ,Mailbox Interrupt Level bit 31" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 30. " MIL30 ,Mailbox Interrupt Level bit 30" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 29. " MIL29 ,Mailbox Interrupt Level bit 29" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 28. " MIL28 ,Mailbox Interrupt Level bit 28" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 27. " MIL27 ,Mailbox Interrupt Level bit 27" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 26. " MIL26 ,Mailbox Interrupt Level bit 26" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 25. " MIL25 ,Mailbox Interrupt Level bit 25" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 24. " MIL24 ,Mailbox Interrupt Level bit 24" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 23. " MIL23 ,Mailbox Interrupt Level bit 23" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 22. " MIL22 ,Mailbox Interrupt Level bit 22" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 21. " MIL21 ,Mailbox Interrupt Level bit 21" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 20. " MIL20 ,Mailbox Interrupt Level bit 20" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 19. " MIL19 ,Mailbox Interrupt Level bit 19" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 18. " MIL18 ,Mailbox Interrupt Level bit 18" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 17. " MIL17 ,Mailbox Interrupt Level bit 17" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 16. " MIL16 ,Mailbox Interrupt Level bit 16" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 15. " MIL15 ,Mailbox Interrupt Level bit 15" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 14. " MIL14 ,Mailbox Interrupt Level bit 14" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 13. " MIL13 ,Mailbox Interrupt Level bit 13" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 12. " MIL12 ,Mailbox Interrupt Level bit 12" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 11. " MIL11 ,Mailbox Interrupt Level bit 11" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 10. " MIL10 ,Mailbox Interrupt Level bit 10" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 9. " MIL9 ,Mailbox Interrupt Level bit 9" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 8. " MIL8 ,Mailbox Interrupt Level bit 8" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 7. " MIL7 ,Mailbox Interrupt Level bit 7" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 6. " MIL6 ,Mailbox Interrupt Level bit 6" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 5. " MIL5 ,Mailbox Interrupt Level bit 5" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 4. " MIL4 ,Mailbox Interrupt Level bit 4" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 3. " MIL3 ,Mailbox Interrupt Level bit 3" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 2. " MIL2 ,Mailbox Interrupt Level bit 2" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
textline " "
|
|
bitfld.long 0x4 1. " MIL1 ,Mailbox Interrupt Level bit 1" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
bitfld.long 0x4 0. " MIL0 ,Mailbox Interrupt Level bit 0" "HECC0INT/SCC0INT,HECC1INT/SCC1INT"
|
|
line.long 0x8 "CANOPC,Overwrite Protection Control Register"
|
|
bitfld.long 0x8 31. " OPC31 ,Overwrite Protection Control bit 31" "Not protected,Protected"
|
|
bitfld.long 0x8 30. " OPC30 ,Overwrite Protection Control bit 30" "Not protected,Protected"
|
|
bitfld.long 0x8 29. " OPC29 ,Overwrite Protection Control bit 29" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OPC28 ,Overwrite Protection Control bit 28" "Not protected,Protected"
|
|
bitfld.long 0x8 27. " OPC27 ,Overwrite Protection Control bit 27" "Not protected,Protected"
|
|
bitfld.long 0x8 26. " OPC26 ,Overwrite Protection Control bit 26" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OPC25 ,Overwrite Protection Control bit 25" "Not protected,Protected"
|
|
bitfld.long 0x8 24. " OPC24 ,Overwrite Protection Control bit 24" "Not protected,Protected"
|
|
bitfld.long 0x8 23. " OPC23 ,Overwrite Protection Control bit 23" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 22. " OPC22 ,Overwrite Protection Control bit 22" "Not protected,Protected"
|
|
bitfld.long 0x8 21. " OPC21 ,Overwrite Protection Control bit 21" "Not protected,Protected"
|
|
bitfld.long 0x8 20. " OPC20 ,Overwrite Protection Control bit 20" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 19. " OPC19 ,Overwrite Protection Control bit 19" "Not protected,Protected"
|
|
bitfld.long 0x8 18. " OPC18 ,Overwrite Protection Control bit 18" "Not protected,Protected"
|
|
bitfld.long 0x8 17. " OPC17 ,Overwrite Protection Control bit 17" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 16. " OPC16 ,Overwrite Protection Control bit 16" "Not protected,Protected"
|
|
bitfld.long 0x8 15. " OPC15 ,Overwrite Protection Control bit 15" "Not protected,Protected"
|
|
bitfld.long 0x8 14. " OPC14 ,Overwrite Protection Control bit 14" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OPC13 ,Overwrite Protection Control bit 13" "Not protected,Protected"
|
|
bitfld.long 0x8 12. " OPC12 ,Overwrite Protection Control bit 12" "Not protected,Protected"
|
|
bitfld.long 0x8 11. " OPC11 ,Overwrite Protection Control bit 11" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OPC10 ,Overwrite Protection Control bit 10" "Not protected,Protected"
|
|
bitfld.long 0x8 9. " OPC9 ,Overwrite Protection Control bit 9" "Not protected,Protected"
|
|
bitfld.long 0x8 8. " OPC8 ,Overwrite Protection Control bit 8" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 7. " OPC7 ,Overwrite Protection Control bit 7" "Not protected,Protected"
|
|
bitfld.long 0x8 6. " OPC6 ,Overwrite Protection Control bit 6" "Not protected,Protected"
|
|
bitfld.long 0x8 5. " OPC5 ,Overwrite Protection Control bit 5" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 4. " OPC4 ,Overwrite Protection Control bit 4" "Not protected,Protected"
|
|
bitfld.long 0x8 3. " OPC3 ,Overwrite Protection Control bit 3" "Not protected,Protected"
|
|
bitfld.long 0x8 2. " OPC2 ,Overwrite Protection Control bit 2" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x8 1. " OPC1 ,Overwrite Protection Control bit 1" "Not protected,Protected"
|
|
bitfld.long 0x8 0. " OPC0 ,Overwrite Protection Control bit 0" "Not protected,Protected"
|
|
line.long 0xc "CANTIOC,Transmit I/O Control Register"
|
|
bitfld.long 0xc 3. " TXFUNC ,External Pin I/O Enable" "Disabled,Enabled"
|
|
bitfld.long 0xc 2. " TXDIR ,Transmit Pin Direction" "Input,Output"
|
|
bitfld.long 0xc 1. " TXOUT ,Output value for CANTX pin" "Low,High"
|
|
bitfld.long 0xc 0. " TXIN ,Reflects the value on the CANTX pin" "Low,High"
|
|
line.long 0x10 "CANRIOC,Receive I/O Control Registers"
|
|
bitfld.long 0x10 3. " RXFUNC ,External Pin I/O Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " RXDIR ,Receive Pin Direction" "Input,Output"
|
|
bitfld.long 0x10 1. " RXOUT ,Output value for CANTX pin" "Low,High"
|
|
bitfld.long 0x10 0. " RXIN ,Reflects the value on the CANTX pin" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "Time Stamp Registers"
|
|
width 11.
|
|
group.long 0x5c++0x3
|
|
line.long 0x0 "CANLNT,Local Network Time Register"
|
|
group.long 0x100++0x7f "Message Object Time Stamp Registers"
|
|
line.long 0x0 "CANMOTS0,Message Object Time Stamp Register For Mailbox 0"
|
|
line.long 0x4 "CANMOTS1,Message Object Time Stamp Register For Mailbox 1"
|
|
line.long 0x8 "CANMOTS2,Message Object Time Stamp Register For Mailbox 2"
|
|
line.long 0xC "CANMOTS3,Message Object Time Stamp Register For Mailbox 3"
|
|
line.long 0x10 "CANMOTS4,Message Object Time Stamp Register For Mailbox 4"
|
|
line.long 0x14 "CANMOTS5,Message Object Time Stamp Register For Mailbox 5"
|
|
line.long 0x18 "CANMOTS6,Message Object Time Stamp Register For Mailbox 6"
|
|
line.long 0x1C "CANMOTS7,Message Object Time Stamp Register For Mailbox 7"
|
|
line.long 0x20 "CANMOTS8,Message Object Time Stamp Register For Mailbox 8"
|
|
line.long 0x24 "CANMOTS9,Message Object Time Stamp Register For Mailbox 9"
|
|
line.long 0x28 "CANMOTS10,Message Object Time Stamp Register For Mailbox 10"
|
|
line.long 0x2C "CANMOTS11,Message Object Time Stamp Register For Mailbox 11"
|
|
line.long 0x30 "CANMOTS12,Message Object Time Stamp Register For Mailbox 12"
|
|
line.long 0x34 "CANMOTS13,Message Object Time Stamp Register For Mailbox 13"
|
|
line.long 0x38 "CANMOTS14,Message Object Time Stamp Register For Mailbox 14"
|
|
line.long 0x3C "CANMOTS15,Message Object Time Stamp Register For Mailbox 15"
|
|
line.long 0x40 "CANMOTS16,Message Object Time Stamp Register For Mailbox 16"
|
|
line.long 0x44 "CANMOTS17,Message Object Time Stamp Register For Mailbox 17"
|
|
line.long 0x48 "CANMOTS18,Message Object Time Stamp Register For Mailbox 18"
|
|
line.long 0x4C "CANMOTS19,Message Object Time Stamp Register For Mailbox 19"
|
|
line.long 0x50 "CANMOTS20,Message Object Time Stamp Register For Mailbox 20"
|
|
line.long 0x54 "CANMOTS21,Message Object Time Stamp Register For Mailbox 21"
|
|
line.long 0x58 "CANMOTS22,Message Object Time Stamp Register For Mailbox 22"
|
|
line.long 0x5C "CANMOTS23,Message Object Time Stamp Register For Mailbox 23"
|
|
line.long 0x60 "CANMOTS24,Message Object Time Stamp Register For Mailbox 24"
|
|
line.long 0x64 "CANMOTS25,Message Object Time Stamp Register For Mailbox 25"
|
|
line.long 0x68 "CANMOTS26,Message Object Time Stamp Register For Mailbox 26"
|
|
line.long 0x6C "CANMOTS27,Message Object Time Stamp Register For Mailbox 27"
|
|
line.long 0x70 "CANMOTS28,Message Object Time Stamp Register For Mailbox 28"
|
|
line.long 0x74 "CANMOTS29,Message Object Time Stamp Register For Mailbox 29"
|
|
line.long 0x78 "CANMOTS30,Message Object Time Stamp Register For Mailbox 30"
|
|
line.long 0x7C "CANMOTS31,Message Object Time Stamp Register For Mailbox 31"
|
|
width 0xb
|
|
tree.end
|
|
tree "Time-Out Registers"
|
|
width 11.
|
|
group.long 0x180++0x7f "Message Object Time-Out Registers"
|
|
line.long 0x0 "CANMOTO0,Message Object Time-Out Register For Mailbox 0"
|
|
line.long 0x4 "CANMOTO1,Message Object Time-Out Register For Mailbox 1"
|
|
line.long 0x8 "CANMOTO2,Message Object Time-Out Register For Mailbox 2"
|
|
line.long 0xC "CANMOTO3,Message Object Time-Out Register For Mailbox 3"
|
|
line.long 0x10 "CANMOTO4,Message Object Time-Out Register For Mailbox 4"
|
|
line.long 0x14 "CANMOTO5,Message Object Time-Out Register For Mailbox 5"
|
|
line.long 0x18 "CANMOTO6,Message Object Time-Out Register For Mailbox 6"
|
|
line.long 0x1C "CANMOTO7,Message Object Time-Out Register For Mailbox 7"
|
|
line.long 0x20 "CANMOTO8,Message Object Time-Out Register For Mailbox 8"
|
|
line.long 0x24 "CANMOTO9,Message Object Time-Out Register For Mailbox 9"
|
|
line.long 0x28 "CANMOTO10,Message Object Time-Out Register For Mailbox 10"
|
|
line.long 0x2C "CANMOTO11,Message Object Time-Out Register For Mailbox 11"
|
|
line.long 0x30 "CANMOTO12,Message Object Time-Out Register For Mailbox 12"
|
|
line.long 0x34 "CANMOTO13,Message Object Time-Out Register For Mailbox 13"
|
|
line.long 0x38 "CANMOTO14,Message Object Time-Out Register For Mailbox 14"
|
|
line.long 0x3C "CANMOTO15,Message Object Time-Out Register For Mailbox 15"
|
|
line.long 0x40 "CANMOTO16,Message Object Time-Out Register For Mailbox 16"
|
|
line.long 0x44 "CANMOTO17,Message Object Time-Out Register For Mailbox 17"
|
|
line.long 0x48 "CANMOTO18,Message Object Time-Out Register For Mailbox 18"
|
|
line.long 0x4C "CANMOTO19,Message Object Time-Out Register For Mailbox 19"
|
|
line.long 0x50 "CANMOTO20,Message Object Time-Out Register For Mailbox 20"
|
|
line.long 0x54 "CANMOTO21,Message Object Time-Out Register For Mailbox 21"
|
|
line.long 0x58 "CANMOTO22,Message Object Time-Out Register For Mailbox 22"
|
|
line.long 0x5C "CANMOTO23,Message Object Time-Out Register For Mailbox 23"
|
|
line.long 0x60 "CANMOTO24,Message Object Time-Out Register For Mailbox 24"
|
|
line.long 0x64 "CANMOTO25,Message Object Time-Out Register For Mailbox 25"
|
|
line.long 0x68 "CANMOTO26,Message Object Time-Out Register For Mailbox 26"
|
|
line.long 0x6C "CANMOTO27,Message Object Time-Out Register For Mailbox 27"
|
|
line.long 0x70 "CANMOTO28,Message Object Time-Out Register For Mailbox 28"
|
|
line.long 0x74 "CANMOTO29,Message Object Time-Out Register For Mailbox 29"
|
|
line.long 0x78 "CANMOTO30,Message Object Time-Out Register For Mailbox 30"
|
|
line.long 0x7C "CANMOTO31,Message Object Time-Out Register For Mailbox 31"
|
|
textline " "
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CANTOC,Time-Out Control Register"
|
|
bitfld.long 0x0 31. " TOC31 ,Time-Out Control bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " TOC30 ,Time-Out Control bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " TOC29 ,Time-Out Control bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " TOC28 ,Time-Out Control bit 28" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " TOC27 ,Time-Out Control bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " TOC26 ,Time-Out Control bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " TOC25 ,Time-Out Control bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " TOC24 ,Time-Out Control bit 24" "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " TOC23 ,Time-Out Control bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " TOC22 ,Time-Out Control bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " TOC21 ,Time-Out Control bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " TOC20 ,Time-Out Control bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " TOC19 ,Time-Out Control bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " TOC18 ,Time-Out Control bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " TOC17 ,Time-Out Control bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " TOC16 ,Time-Out Control bit 16" "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " TOC15 ,Time-Out Control bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TOC14 ,Time-Out Control bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " TOC13 ,Time-Out Control bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " TOC12 ,Time-Out Control bit 12" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " TOC11 ,Time-Out Control bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " TOC10 ,Time-Out Control bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " TOC9 ,Time-Out Control bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " TOC8 ,Time-Out Control bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " TOC7 ,Time-Out Control bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TOC6 ,Time-Out Control bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " TOC5 ,Time-Out Control bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TOC4 ,Time-Out Control bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " TOC3 ,Time-Out Control bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TOC2 ,Time-Out Control bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TOC1 ,Time-Out Control bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TOC0 ,Time-Out Control bit 0" "Disabled,Enabled"
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "CANTOS,Time-Out Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "Message Mailbox Registers"
|
|
width 10.
|
|
tree "Mailboxes 0 - 7"
|
|
if (((data.long(ad:0x5c050000+0x200))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x200)++0x3 "Mailbox 0"
|
|
line.long 0x0 "CANMID0,Message Identifier Register For Mailbox 0"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x200)++0x3 "Mailbox 0"
|
|
line.long 0x0 "CANMID0,Message Identifier Register For Mailbox 0"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x200+0x4)++0x3
|
|
line.long 0x0 "CANMCF0,Message Control Field Register For Mailbox 0"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x200+0x8)++0x7
|
|
line.long 0x0 "CANMDL0,Message Data Low Register For Mailbox 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH0,Message Data High Register For Mailbox 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x200+0x8)++0x7
|
|
line.long 0x0 "CANMDL0,Message Data Low Register For Mailbox 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH0,Message Data High Register For Mailbox 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x210))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x210)++0x3 "Mailbox 1"
|
|
line.long 0x0 "CANMID1,Message Identifier Register For Mailbox 1"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x210)++0x3 "Mailbox 1"
|
|
line.long 0x0 "CANMID1,Message Identifier Register For Mailbox 1"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x210+0x4)++0x3
|
|
line.long 0x0 "CANMCF1,Message Control Field Register For Mailbox 1"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x210+0x8)++0x7
|
|
line.long 0x0 "CANMDL1,Message Data Low Register For Mailbox 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH1,Message Data High Register For Mailbox 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x210+0x8)++0x7
|
|
line.long 0x0 "CANMDL1,Message Data Low Register For Mailbox 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH1,Message Data High Register For Mailbox 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x220))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x220)++0x3 "Mailbox 2"
|
|
line.long 0x0 "CANMID2,Message Identifier Register For Mailbox 2"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x220)++0x3 "Mailbox 2"
|
|
line.long 0x0 "CANMID2,Message Identifier Register For Mailbox 2"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x220+0x4)++0x3
|
|
line.long 0x0 "CANMCF2,Message Control Field Register For Mailbox 2"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x220+0x8)++0x7
|
|
line.long 0x0 "CANMDL2,Message Data Low Register For Mailbox 2"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH2,Message Data High Register For Mailbox 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x220+0x8)++0x7
|
|
line.long 0x0 "CANMDL2,Message Data Low Register For Mailbox 2"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH2,Message Data High Register For Mailbox 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x230))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x230)++0x3 "Mailbox 3"
|
|
line.long 0x0 "CANMID3,Message Identifier Register For Mailbox 3"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x230)++0x3 "Mailbox 3"
|
|
line.long 0x0 "CANMID3,Message Identifier Register For Mailbox 3"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x230+0x4)++0x3
|
|
line.long 0x0 "CANMCF3,Message Control Field Register For Mailbox 3"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x230+0x8)++0x7
|
|
line.long 0x0 "CANMDL3,Message Data Low Register For Mailbox 3"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH3,Message Data High Register For Mailbox 3"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x230+0x8)++0x7
|
|
line.long 0x0 "CANMDL3,Message Data Low Register For Mailbox 3"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH3,Message Data High Register For Mailbox 3"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x240))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x240)++0x3 "Mailbox 4"
|
|
line.long 0x0 "CANMID4,Message Identifier Register For Mailbox 4"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x240)++0x3 "Mailbox 4"
|
|
line.long 0x0 "CANMID4,Message Identifier Register For Mailbox 4"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x240+0x4)++0x3
|
|
line.long 0x0 "CANMCF4,Message Control Field Register For Mailbox 4"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x240+0x8)++0x7
|
|
line.long 0x0 "CANMDL4,Message Data Low Register For Mailbox 4"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH4,Message Data High Register For Mailbox 4"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x240+0x8)++0x7
|
|
line.long 0x0 "CANMDL4,Message Data Low Register For Mailbox 4"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH4,Message Data High Register For Mailbox 4"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x250))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x250)++0x3 "Mailbox 5"
|
|
line.long 0x0 "CANMID5,Message Identifier Register For Mailbox 5"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x250)++0x3 "Mailbox 5"
|
|
line.long 0x0 "CANMID5,Message Identifier Register For Mailbox 5"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x250+0x4)++0x3
|
|
line.long 0x0 "CANMCF5,Message Control Field Register For Mailbox 5"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x250+0x8)++0x7
|
|
line.long 0x0 "CANMDL5,Message Data Low Register For Mailbox 5"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH5,Message Data High Register For Mailbox 5"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x250+0x8)++0x7
|
|
line.long 0x0 "CANMDL5,Message Data Low Register For Mailbox 5"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH5,Message Data High Register For Mailbox 5"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x260))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x260)++0x3 "Mailbox 6"
|
|
line.long 0x0 "CANMID6,Message Identifier Register For Mailbox 6"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x260)++0x3 "Mailbox 6"
|
|
line.long 0x0 "CANMID6,Message Identifier Register For Mailbox 6"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x260+0x4)++0x3
|
|
line.long 0x0 "CANMCF6,Message Control Field Register For Mailbox 6"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x260+0x8)++0x7
|
|
line.long 0x0 "CANMDL6,Message Data Low Register For Mailbox 6"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH6,Message Data High Register For Mailbox 6"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x260+0x8)++0x7
|
|
line.long 0x0 "CANMDL6,Message Data Low Register For Mailbox 6"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH6,Message Data High Register For Mailbox 6"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x270))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x270)++0x3 "Mailbox 7"
|
|
line.long 0x0 "CANMID7,Message Identifier Register For Mailbox 7"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x270)++0x3 "Mailbox 7"
|
|
line.long 0x0 "CANMID7,Message Identifier Register For Mailbox 7"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x270+0x4)++0x3
|
|
line.long 0x0 "CANMCF7,Message Control Field Register For Mailbox 7"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x270+0x8)++0x7
|
|
line.long 0x0 "CANMDL7,Message Data Low Register For Mailbox 7"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH7,Message Data High Register For Mailbox 7"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x270+0x8)++0x7
|
|
line.long 0x0 "CANMDL7,Message Data Low Register For Mailbox 7"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH7,Message Data High Register For Mailbox 7"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
tree.end
|
|
tree "Mailboxes 8 - 15"
|
|
if (((data.long(ad:0x5c050000+0x280))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x280)++0x3 "Mailbox 8"
|
|
line.long 0x0 "CANMID8,Message Identifier Register For Mailbox 8"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x280)++0x3 "Mailbox 8"
|
|
line.long 0x0 "CANMID8,Message Identifier Register For Mailbox 8"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x280+0x4)++0x3
|
|
line.long 0x0 "CANMCF8,Message Control Field Register For Mailbox 8"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x280+0x8)++0x7
|
|
line.long 0x0 "CANMDL8,Message Data Low Register For Mailbox 8"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH8,Message Data High Register For Mailbox 8"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x280+0x8)++0x7
|
|
line.long 0x0 "CANMDL8,Message Data Low Register For Mailbox 8"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH8,Message Data High Register For Mailbox 8"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x290))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x290)++0x3 "Mailbox 9"
|
|
line.long 0x0 "CANMID9,Message Identifier Register For Mailbox 9"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x290)++0x3 "Mailbox 9"
|
|
line.long 0x0 "CANMID9,Message Identifier Register For Mailbox 9"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x290+0x4)++0x3
|
|
line.long 0x0 "CANMCF9,Message Control Field Register For Mailbox 9"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x290+0x8)++0x7
|
|
line.long 0x0 "CANMDL9,Message Data Low Register For Mailbox 9"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH9,Message Data High Register For Mailbox 9"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x290+0x8)++0x7
|
|
line.long 0x0 "CANMDL9,Message Data Low Register For Mailbox 9"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH9,Message Data High Register For Mailbox 9"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2A0))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x2A0)++0x3 "Mailbox 10"
|
|
line.long 0x0 "CANMID10,Message Identifier Register For Mailbox 10"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x2A0)++0x3 "Mailbox 10"
|
|
line.long 0x0 "CANMID10,Message Identifier Register For Mailbox 10"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x2A0+0x4)++0x3
|
|
line.long 0x0 "CANMCF10,Message Control Field Register For Mailbox 10"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x2A0+0x8)++0x7
|
|
line.long 0x0 "CANMDL10,Message Data Low Register For Mailbox 10"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH10,Message Data High Register For Mailbox 10"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x2A0+0x8)++0x7
|
|
line.long 0x0 "CANMDL10,Message Data Low Register For Mailbox 10"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH10,Message Data High Register For Mailbox 10"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2B0))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x2B0)++0x3 "Mailbox 11"
|
|
line.long 0x0 "CANMID11,Message Identifier Register For Mailbox 11"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x2B0)++0x3 "Mailbox 11"
|
|
line.long 0x0 "CANMID11,Message Identifier Register For Mailbox 11"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x2B0+0x4)++0x3
|
|
line.long 0x0 "CANMCF11,Message Control Field Register For Mailbox 11"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x2B0+0x8)++0x7
|
|
line.long 0x0 "CANMDL11,Message Data Low Register For Mailbox 11"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH11,Message Data High Register For Mailbox 11"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x2B0+0x8)++0x7
|
|
line.long 0x0 "CANMDL11,Message Data Low Register For Mailbox 11"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH11,Message Data High Register For Mailbox 11"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2C0))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x2C0)++0x3 "Mailbox 12"
|
|
line.long 0x0 "CANMID12,Message Identifier Register For Mailbox 12"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x2C0)++0x3 "Mailbox 12"
|
|
line.long 0x0 "CANMID12,Message Identifier Register For Mailbox 12"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x2C0+0x4)++0x3
|
|
line.long 0x0 "CANMCF12,Message Control Field Register For Mailbox 12"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x2C0+0x8)++0x7
|
|
line.long 0x0 "CANMDL12,Message Data Low Register For Mailbox 12"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH12,Message Data High Register For Mailbox 12"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x2C0+0x8)++0x7
|
|
line.long 0x0 "CANMDL12,Message Data Low Register For Mailbox 12"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH12,Message Data High Register For Mailbox 12"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2D0))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x2D0)++0x3 "Mailbox 13"
|
|
line.long 0x0 "CANMID13,Message Identifier Register For Mailbox 13"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x2D0)++0x3 "Mailbox 13"
|
|
line.long 0x0 "CANMID13,Message Identifier Register For Mailbox 13"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x2D0+0x4)++0x3
|
|
line.long 0x0 "CANMCF13,Message Control Field Register For Mailbox 13"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x2D0+0x8)++0x7
|
|
line.long 0x0 "CANMDL13,Message Data Low Register For Mailbox 13"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH13,Message Data High Register For Mailbox 13"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x2D0+0x8)++0x7
|
|
line.long 0x0 "CANMDL13,Message Data Low Register For Mailbox 13"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH13,Message Data High Register For Mailbox 13"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2E0))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x2E0)++0x3 "Mailbox 14"
|
|
line.long 0x0 "CANMID14,Message Identifier Register For Mailbox 14"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x2E0)++0x3 "Mailbox 14"
|
|
line.long 0x0 "CANMID14,Message Identifier Register For Mailbox 14"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x2E0+0x4)++0x3
|
|
line.long 0x0 "CANMCF14,Message Control Field Register For Mailbox 14"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x2E0+0x8)++0x7
|
|
line.long 0x0 "CANMDL14,Message Data Low Register For Mailbox 14"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH14,Message Data High Register For Mailbox 14"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x2E0+0x8)++0x7
|
|
line.long 0x0 "CANMDL14,Message Data Low Register For Mailbox 14"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH14,Message Data High Register For Mailbox 14"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2F0))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x2F0)++0x3 "Mailbox 15"
|
|
line.long 0x0 "CANMID15,Message Identifier Register For Mailbox 15"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x2F0)++0x3 "Mailbox 15"
|
|
line.long 0x0 "CANMID15,Message Identifier Register For Mailbox 15"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x2F0+0x4)++0x3
|
|
line.long 0x0 "CANMCF15,Message Control Field Register For Mailbox 15"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x2F0+0x8)++0x7
|
|
line.long 0x0 "CANMDL15,Message Data Low Register For Mailbox 15"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH15,Message Data High Register For Mailbox 15"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x2F0+0x8)++0x7
|
|
line.long 0x0 "CANMDL15,Message Data Low Register For Mailbox 15"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH15,Message Data High Register For Mailbox 15"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
tree.end
|
|
tree "Mailboxes 16 - 23"
|
|
if (((data.long(ad:0x5c050000+0x300))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x300)++0x3 "Mailbox 16"
|
|
line.long 0x0 "CANMID16,Message Identifier Register For Mailbox 16"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x300)++0x3 "Mailbox 16"
|
|
line.long 0x0 "CANMID16,Message Identifier Register For Mailbox 16"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x300+0x4)++0x3
|
|
line.long 0x0 "CANMCF16,Message Control Field Register For Mailbox 16"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x300+0x8)++0x7
|
|
line.long 0x0 "CANMDL16,Message Data Low Register For Mailbox 16"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH16,Message Data High Register For Mailbox 16"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x300+0x8)++0x7
|
|
line.long 0x0 "CANMDL16,Message Data Low Register For Mailbox 16"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH16,Message Data High Register For Mailbox 16"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x310))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x310)++0x3 "Mailbox 17"
|
|
line.long 0x0 "CANMID17,Message Identifier Register For Mailbox 17"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x310)++0x3 "Mailbox 17"
|
|
line.long 0x0 "CANMID17,Message Identifier Register For Mailbox 17"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x310+0x4)++0x3
|
|
line.long 0x0 "CANMCF17,Message Control Field Register For Mailbox 17"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x310+0x8)++0x7
|
|
line.long 0x0 "CANMDL17,Message Data Low Register For Mailbox 17"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH17,Message Data High Register For Mailbox 17"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x310+0x8)++0x7
|
|
line.long 0x0 "CANMDL17,Message Data Low Register For Mailbox 17"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH17,Message Data High Register For Mailbox 17"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x320))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x320)++0x3 "Mailbox 18"
|
|
line.long 0x0 "CANMID18,Message Identifier Register For Mailbox 18"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x320)++0x3 "Mailbox 18"
|
|
line.long 0x0 "CANMID18,Message Identifier Register For Mailbox 18"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x320+0x4)++0x3
|
|
line.long 0x0 "CANMCF18,Message Control Field Register For Mailbox 18"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x320+0x8)++0x7
|
|
line.long 0x0 "CANMDL18,Message Data Low Register For Mailbox 18"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH18,Message Data High Register For Mailbox 18"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x320+0x8)++0x7
|
|
line.long 0x0 "CANMDL18,Message Data Low Register For Mailbox 18"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH18,Message Data High Register For Mailbox 18"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x330))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x330)++0x3 "Mailbox 19"
|
|
line.long 0x0 "CANMID19,Message Identifier Register For Mailbox 19"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x330)++0x3 "Mailbox 19"
|
|
line.long 0x0 "CANMID19,Message Identifier Register For Mailbox 19"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x330+0x4)++0x3
|
|
line.long 0x0 "CANMCF19,Message Control Field Register For Mailbox 19"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x330+0x8)++0x7
|
|
line.long 0x0 "CANMDL19,Message Data Low Register For Mailbox 19"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH19,Message Data High Register For Mailbox 19"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x330+0x8)++0x7
|
|
line.long 0x0 "CANMDL19,Message Data Low Register For Mailbox 19"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH19,Message Data High Register For Mailbox 19"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x340))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x340)++0x3 "Mailbox 20"
|
|
line.long 0x0 "CANMID20,Message Identifier Register For Mailbox 20"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x340)++0x3 "Mailbox 20"
|
|
line.long 0x0 "CANMID20,Message Identifier Register For Mailbox 20"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x340+0x4)++0x3
|
|
line.long 0x0 "CANMCF20,Message Control Field Register For Mailbox 20"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x340+0x8)++0x7
|
|
line.long 0x0 "CANMDL20,Message Data Low Register For Mailbox 20"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH20,Message Data High Register For Mailbox 20"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x340+0x8)++0x7
|
|
line.long 0x0 "CANMDL20,Message Data Low Register For Mailbox 20"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH20,Message Data High Register For Mailbox 20"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x350))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x350)++0x3 "Mailbox 21"
|
|
line.long 0x0 "CANMID21,Message Identifier Register For Mailbox 21"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x350)++0x3 "Mailbox 21"
|
|
line.long 0x0 "CANMID21,Message Identifier Register For Mailbox 21"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x350+0x4)++0x3
|
|
line.long 0x0 "CANMCF21,Message Control Field Register For Mailbox 21"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x350+0x8)++0x7
|
|
line.long 0x0 "CANMDL21,Message Data Low Register For Mailbox 21"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH21,Message Data High Register For Mailbox 21"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x350+0x8)++0x7
|
|
line.long 0x0 "CANMDL21,Message Data Low Register For Mailbox 21"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH21,Message Data High Register For Mailbox 21"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x360))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x360)++0x3 "Mailbox 22"
|
|
line.long 0x0 "CANMID22,Message Identifier Register For Mailbox 22"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x360)++0x3 "Mailbox 22"
|
|
line.long 0x0 "CANMID22,Message Identifier Register For Mailbox 22"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x360+0x4)++0x3
|
|
line.long 0x0 "CANMCF22,Message Control Field Register For Mailbox 22"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x360+0x8)++0x7
|
|
line.long 0x0 "CANMDL22,Message Data Low Register For Mailbox 22"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH22,Message Data High Register For Mailbox 22"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x360+0x8)++0x7
|
|
line.long 0x0 "CANMDL22,Message Data Low Register For Mailbox 22"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH22,Message Data High Register For Mailbox 22"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x370))&0x80000000)==(0x0))
|
|
; IDE -> standard
|
|
group.long (0x370)++0x3 "Mailbox 23"
|
|
line.long 0x0 "CANMID23,Message Identifier Register For Mailbox 23"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x370)++0x3 "Mailbox 23"
|
|
line.long 0x0 "CANMID23,Message Identifier Register For Mailbox 23"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x370+0x4)++0x3
|
|
line.long 0x0 "CANMCF23,Message Control Field Register For Mailbox 23"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x370+0x8)++0x7
|
|
line.long 0x0 "CANMDL23,Message Data Low Register For Mailbox 23"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH23,Message Data High Register For Mailbox 23"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x370+0x8)++0x7
|
|
line.long 0x0 "CANMDL23,Message Data Low Register For Mailbox 23"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH23,Message Data High Register For Mailbox 23"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
tree.end
|
|
tree "Mailboxes 24 - 31"
|
|
if (((data.long(ad:0x5c050000+0x380)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x380)++0x3 "Mailbox 24"
|
|
line.long 0x0 "CANMID24,Message Identifier Register For Mailbox 24"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x380)++0x3 "Mailbox 24"
|
|
line.long 0x0 "CANMID24,Message Identifier Register For Mailbox 24"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x380+0x4)++0x3
|
|
line.long 0x0 "CANMCF24,Message Control Field Register For Mailbox 24"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x380+0x8)++0x7
|
|
line.long 0x0 "CANMDL24,Message Data Low Register For Mailbox 24"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH24,Message Data High Register For Mailbox 24"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x380+0x8)++0x7
|
|
line.long 0x0 "CANMDL24,Message Data Low Register For Mailbox 24"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH24,Message Data High Register For Mailbox 24"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x390)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x390)++0x3 "Mailbox 25"
|
|
line.long 0x0 "CANMID25,Message Identifier Register For Mailbox 25"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x390)++0x3 "Mailbox 25"
|
|
line.long 0x0 "CANMID25,Message Identifier Register For Mailbox 25"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x390+0x4)++0x3
|
|
line.long 0x0 "CANMCF25,Message Control Field Register For Mailbox 25"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x390+0x8)++0x7
|
|
line.long 0x0 "CANMDL25,Message Data Low Register For Mailbox 25"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH25,Message Data High Register For Mailbox 25"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x390+0x8)++0x7
|
|
line.long 0x0 "CANMDL25,Message Data Low Register For Mailbox 25"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH25,Message Data High Register For Mailbox 25"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3A0)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x3A0)++0x3 "Mailbox 26"
|
|
line.long 0x0 "CANMID26,Message Identifier Register For Mailbox 26"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x3A0)++0x3 "Mailbox 26"
|
|
line.long 0x0 "CANMID26,Message Identifier Register For Mailbox 26"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x3A0+0x4)++0x3
|
|
line.long 0x0 "CANMCF26,Message Control Field Register For Mailbox 26"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x3A0+0x8)++0x7
|
|
line.long 0x0 "CANMDL26,Message Data Low Register For Mailbox 26"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH26,Message Data High Register For Mailbox 26"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x3A0+0x8)++0x7
|
|
line.long 0x0 "CANMDL26,Message Data Low Register For Mailbox 26"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH26,Message Data High Register For Mailbox 26"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3B0)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x3B0)++0x3 "Mailbox 27"
|
|
line.long 0x0 "CANMID27,Message Identifier Register For Mailbox 27"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x3B0)++0x3 "Mailbox 27"
|
|
line.long 0x0 "CANMID27,Message Identifier Register For Mailbox 27"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x3B0+0x4)++0x3
|
|
line.long 0x0 "CANMCF27,Message Control Field Register For Mailbox 27"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x3B0+0x8)++0x7
|
|
line.long 0x0 "CANMDL27,Message Data Low Register For Mailbox 27"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH27,Message Data High Register For Mailbox 27"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x3B0+0x8)++0x7
|
|
line.long 0x0 "CANMDL27,Message Data Low Register For Mailbox 27"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH27,Message Data High Register For Mailbox 27"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3C0)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x3C0)++0x3 "Mailbox 28"
|
|
line.long 0x0 "CANMID28,Message Identifier Register For Mailbox 28"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x3C0)++0x3 "Mailbox 28"
|
|
line.long 0x0 "CANMID28,Message Identifier Register For Mailbox 28"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x3C0+0x4)++0x3
|
|
line.long 0x0 "CANMCF28,Message Control Field Register For Mailbox 28"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x3C0+0x8)++0x7
|
|
line.long 0x0 "CANMDL28,Message Data Low Register For Mailbox 28"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH28,Message Data High Register For Mailbox 28"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x3C0+0x8)++0x7
|
|
line.long 0x0 "CANMDL28,Message Data Low Register For Mailbox 28"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH28,Message Data High Register For Mailbox 28"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3D0)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x3D0)++0x3 "Mailbox 29"
|
|
line.long 0x0 "CANMID29,Message Identifier Register For Mailbox 29"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x3D0)++0x3 "Mailbox 29"
|
|
line.long 0x0 "CANMID29,Message Identifier Register For Mailbox 29"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x3D0+0x4)++0x3
|
|
line.long 0x0 "CANMCF29,Message Control Field Register For Mailbox 29"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x3D0+0x8)++0x7
|
|
line.long 0x0 "CANMDL29,Message Data Low Register For Mailbox 29"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH29,Message Data High Register For Mailbox 29"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x3D0+0x8)++0x7
|
|
line.long 0x0 "CANMDL29,Message Data Low Register For Mailbox 29"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH29,Message Data High Register For Mailbox 29"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3E0)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x3E0)++0x3 "Mailbox 30"
|
|
line.long 0x0 "CANMID30,Message Identifier Register For Mailbox 30"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x3E0)++0x3 "Mailbox 30"
|
|
line.long 0x0 "CANMID30,Message Identifier Register For Mailbox 30"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x3E0+0x4)++0x3
|
|
line.long 0x0 "CANMCF30,Message Control Field Register For Mailbox 30"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x3E0+0x8)++0x7
|
|
line.long 0x0 "CANMDL30,Message Data Low Register For Mailbox 30"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH30,Message Data High Register For Mailbox 30"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x3E0+0x8)++0x7
|
|
line.long 0x0 "CANMDL30,Message Data Low Register For Mailbox 30"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH30,Message Data High Register For Mailbox 30"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3F0)&0x80000000)==(0x0)))
|
|
; IDE -> standard
|
|
group.long (0x3F0)++0x3 "Mailbox 31"
|
|
line.long 0x0 "CANMID31,Message Identifier Register For Mailbox 31"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long.word 0x0 18.--28. 1. " ID[11:0] ,Message Identifier"
|
|
else
|
|
group.long (0x3F0)++0x3 "Mailbox 31"
|
|
line.long 0x0 "CANMID31,Message Identifier Register For Mailbox 31"
|
|
bitfld.long 0x0 31. " IDE ,Identifier Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " AME ,Acceptance Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AAM ,Auto Answer Mode" "Normal,Auto answer"
|
|
textline " "
|
|
hexmask.long 0x0 0.--28. 1. " ID[28:0] ,Message Identifier"
|
|
endif
|
|
group.long (0x3F0+0x4)++0x3
|
|
line.long 0x0 "CANMCF31,Message Control Field Register For Mailbox 31"
|
|
hexmask.long.byte 0x0 8.--13. 1. " TPL ,Transmit Priority Level"
|
|
bitfld.long 0x0 4. " RTR ,Remote Transmission Request" "Not requested,Requested"
|
|
bitfld.long 0x0 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((data.long(ad:0x5c050000+0x28))&0x400)==0x000)
|
|
; CANMC,Master Control Register -> DBO == 0 MSB first
|
|
group.long (0x3F0+0x8)++0x7
|
|
line.long 0x0 "CANMDL31,Message Data Low Register For Mailbox 31"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE0 ,Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE1 ,Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE2 ,Byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE3 ,Byte 3"
|
|
line.long 0x4 "CANMDH31,Message Data High Register For Mailbox 31"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE4 ,Byte 4"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE5 ,Byte 5"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE6 ,Byte 6"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE7 ,Byte 7"
|
|
else
|
|
group.long (0x3F0+0x8)++0x7
|
|
line.long 0x0 "CANMDL31,Message Data Low Register For Mailbox 31"
|
|
hexmask.long.byte 0x0 24.--31. 1. " BYTE3 ,Byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " BYTE2 ,Byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " BYTE1 ,Byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " BYTE0 ,Byte 0"
|
|
line.long 0x4 "CANMDH31,Message Data High Register For Mailbox 31"
|
|
hexmask.long.byte 0x4 24.--31. 1. " BYTE7 ,Byte 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. " BYTE6 ,Byte 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. " BYTE5 ,Byte 5"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " BYTE4 ,Byte 4"
|
|
endif
|
|
tree.end
|
|
base ad:0x5c050000+0x2f80
|
|
tree "Local Acceptance Mask Registers"
|
|
if (((data.long(ad:0x5c050000+0x200))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x80+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CANLAM0,Local Acceptance Mask Register For Mailbox 0"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CANLAM0,Local Acceptance Mask Register For Mailbox 0"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x210))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x84+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CANLAM1,Local Acceptance Mask Register For Mailbox 1"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CANLAM1,Local Acceptance Mask Register For Mailbox 1"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x220))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x88+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CANLAM2,Local Acceptance Mask Register For Mailbox 2"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CANLAM2,Local Acceptance Mask Register For Mailbox 2"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x240))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x90+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CANLAM4,Local Acceptance Mask Register For Mailbox 4"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CANLAM4,Local Acceptance Mask Register For Mailbox 4"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x250))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x94+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CANLAM5,Local Acceptance Mask Register For Mailbox 5"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CANLAM5,Local Acceptance Mask Register For Mailbox 5"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x260))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x98+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CANLAM6,Local Acceptance Mask Register For Mailbox 6"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CANLAM6,Local Acceptance Mask Register For Mailbox 6"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x270))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0x9C+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CANLAM7,Local Acceptance Mask Register For Mailbox 7"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CANLAM7,Local Acceptance Mask Register For Mailbox 7"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x280))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xA0+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CANLAM8,Local Acceptance Mask Register For Mailbox 8"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CANLAM8,Local Acceptance Mask Register For Mailbox 8"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x290))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xA4+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CANLAM9,Local Acceptance Mask Register For Mailbox 9"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CANLAM9,Local Acceptance Mask Register For Mailbox 9"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2A0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xA8+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CANLAM10,Local Acceptance Mask Register For Mailbox 10"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CANLAM10,Local Acceptance Mask Register For Mailbox 10"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2B0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xAC+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CANLAM11,Local Acceptance Mask Register For Mailbox 11"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CANLAM11,Local Acceptance Mask Register For Mailbox 11"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2C0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xB0+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CANLAM12,Local Acceptance Mask Register For Mailbox 12"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CANLAM12,Local Acceptance Mask Register For Mailbox 12"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2D0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xB4+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CANLAM13,Local Acceptance Mask Register For Mailbox 13"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CANLAM13,Local Acceptance Mask Register For Mailbox 13"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2E0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xB8+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CANLAM14,Local Acceptance Mask Register For Mailbox 14"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CANLAM14,Local Acceptance Mask Register For Mailbox 14"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x2F0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xBC+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CANLAM15,Local Acceptance Mask Register For Mailbox 15"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CANLAM15,Local Acceptance Mask Register For Mailbox 15"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x300))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xC0+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CANLAM16,Local Acceptance Mask Register For Mailbox 16"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CANLAM16,Local Acceptance Mask Register For Mailbox 16"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x310))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xC4+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CANLAM17,Local Acceptance Mask Register For Mailbox 17"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CANLAM17,Local Acceptance Mask Register For Mailbox 17"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x320))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xC8+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CANLAM18,Local Acceptance Mask Register For Mailbox 18"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CANLAM18,Local Acceptance Mask Register For Mailbox 18"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x330))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xCC+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CANLAM19,Local Acceptance Mask Register For Mailbox 19"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CANLAM19,Local Acceptance Mask Register For Mailbox 19"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x340))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xD0+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CANLAM20,Local Acceptance Mask Register For Mailbox 20"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CANLAM20,Local Acceptance Mask Register For Mailbox 20"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x350))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xD4+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CANLAM21,Local Acceptance Mask Register For Mailbox 21"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CANLAM21,Local Acceptance Mask Register For Mailbox 21"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x360))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xD8+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CANLAM22,Local Acceptance Mask Register For Mailbox 22"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CANLAM22,Local Acceptance Mask Register For Mailbox 22"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x370))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xDC+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CANLAM23,Local Acceptance Mask Register For Mailbox 23"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CANLAM23,Local Acceptance Mask Register For Mailbox 23"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x380))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xE0+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CANLAM24,Local Acceptance Mask Register For Mailbox 24"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CANLAM24,Local Acceptance Mask Register For Mailbox 24"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x390))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xE4+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CANLAM25,Local Acceptance Mask Register For Mailbox 25"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CANLAM25,Local Acceptance Mask Register For Mailbox 25"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3A0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xE8+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CANLAM26,Local Acceptance Mask Register For Mailbox 26"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CANLAM26,Local Acceptance Mask Register For Mailbox 26"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3B0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xEC+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CANLAM27,Local Acceptance Mask Register For Mailbox 27"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CANLAM27,Local Acceptance Mask Register For Mailbox 27"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3C0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xF0+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CANLAM28,Local Acceptance Mask Register For Mailbox 28"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CANLAM28,Local Acceptance Mask Register For Mailbox 28"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3D0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xF4+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CANLAM29,Local Acceptance Mask Register For Mailbox 29"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CANLAM29,Local Acceptance Mask Register For Mailbox 29"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3E0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xF8+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CANLAM30,Local Acceptance Mask Register For Mailbox 30"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CANLAM30,Local Acceptance Mask Register For Mailbox 30"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
if (((data.long(ad:0x5c050000+0x3F0))&0x80000000)==0x00)&&(((data.long(ad:0x5c050000+0xFC+0x2f80))&0x80000000)==0x00)
|
|
;CANMID->IDE=="Standard" && this->LAMI=="Determined by mailbox"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CANLAM31,Local Acceptance Mask Register For Mailbox 31"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CANLAM31,Local Acceptance Mask Register For Mailbox 31"
|
|
bitfld.long 0x00 31. " LAMI ,Local Acceptance Mask Identifier Extension Bit" "Determined by mailbox,Both"
|
|
bitfld.long 0x00 28. " LAM ,Local Acceptance Mask bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Local Acceptance Mask bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Local Acceptance Mask bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Local Acceptance Mask bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Local Acceptance Mask bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Local Acceptance Mask bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Local Acceptance Mask bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Local Acceptance Mask bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Local Acceptance Mask bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Local Acceptance Mask bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Local Acceptance Mask bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Local Acceptance Mask bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Local Acceptance Mask bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Local Acceptance Mask bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Local Acceptance Mask bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Local Acceptance Mask bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Local Acceptance Mask bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Local Acceptance Mask bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Local Acceptance Mask bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Local Acceptance Mask bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Local Acceptance Mask bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Local Acceptance Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Local Acceptance Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Local Acceptance Mask bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Local Acceptance Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Local Acceptance Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Local Acceptance Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Local Acceptance Mask bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Local Acceptance Mask bit 0" "0,1"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
textline ""
|