81814 lines
4.9 MiB
81814 lines
4.9 MiB
; --------------------------------------------------------------------------------
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; @Title: ADSP-SC57x SHARC Processor On-Chip Peripherals
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; @Props: Released
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; @Author: KMB PCC DPR MHM
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; @Changelog: 2018-06-04 KMB
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; @Manufacturer: Analog Devices
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; @Doc: adsp-sc57x-2157x_hwr_rev02.pdf (Rev. 0.2, June 2017)
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; @Chip: ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573
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; @Core: Cortex-A5
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peradspsc57x.per 15242 2022-09-20 16:38:14Z kwisniewski $
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; Known problems
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; MODULE REGISTER DESCRIPTION
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; DAI DAI0 Missing descriptions for values stats 49 (0x31) and 50 (0x32) in Serial Data Signals Group B
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; HADC HADC_CTL[DOUTOREOCB] Descriptions values bit is reserved
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; MEPU MEC_PEIRQ_GCTL Too many possible values for 4 bits field
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; MEPU MEC_PEIRQ_GSTAT Too many possible values for 4 bits field
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "Core Registers (Cortex-A5)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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textline " "
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup.long c15:0x200++0x0
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 1. " TLB_SIZE ,TLB Size" "64,128"
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textline " "
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bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,Separate"
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3"
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " OSS ,Outer Shareable Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
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bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup.long c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup.long c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group.long c15:0x1++0x0
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
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textline " "
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
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group.long c15:0x101++0x0
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes"
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bitfld.long 0x00 18. " BTDIS ,Disable indirect Branch Target Address Cache" "No,Yes"
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bitfld.long 0x00 17. " RSDIS ,Disable return stack operation" "No,Yes"
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textline " "
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bitfld.long 0x00 15.--16. " BP ,Branch prediction policy" "Normal,Taken,Not taken,?..."
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bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 prefetch,2 prefetches,3 prefetches"
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bitfld.long 0x00 12. " RADIS ,Disable Data Cache read-allocate mode" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DWBST ,Disable data write bursts to normal non-cacheable memory" "No,Yes"
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bitfld.long 0x00 10. " DODMBS ,Disable optimized Data Memory Barrier behavior" "No,Yes"
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bitfld.long 0x00 7. " EXCL ,Exclusive L1/L2 cache control" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 6. " SMP ,Data requests with Inner Cacheable Shared attributes are treated as cacheable" "Disabled,Enabled"
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bitfld.long 0x00 0. " FW ,FW" "Low,High"
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group.long c15:0x201++0x0
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
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bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group.long c15:0x11++0x0
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 6. " NET ,Not early termination" "Not early,Early"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
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bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
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textline " "
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bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
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bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
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bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
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textline " "
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bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
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group.long c15:0x111++0x0
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line.long 0x0 "SDER,Secure Debug Enable Register"
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bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
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bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
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group.long c15:0x0211++0x00
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
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bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "Denied,Permitted"
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
group.long c15:0x0311++0x00
|
|
line.long 0x00 "VCR,Virtualization Control Register"
|
|
bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1"
|
|
bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1"
|
|
bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1"
|
|
textline " "
|
|
group.long c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group.long c15:0x10c++0x00
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
rgroup.long c15:0x1C++0x0
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
group.long c15:0x11c++0x0
|
|
line.long 0x00 "VIR,Virtualization Interrupt Register"
|
|
bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1"
|
|
group.long c15:0x400f++0x0
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address"
|
|
tree.end
|
|
width 0x08
|
|
tree "Memory Management Unit"
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 6. 0. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 6. 0. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group.long c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address"
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status"
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status"
|
|
textline " "
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,PA Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress"
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back"
|
|
bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful"
|
|
textline " "
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group.long c15:0x500f++0x0
|
|
line.long 0x00 "TLBHR,TLB Hitmap Register"
|
|
bitfld.long 0x00 3. " 16MB ,16MB supersections are present in the TLB" "no,yes"
|
|
bitfld.long 0x00 2. " 1MB ,1MB sections are present in the TLB" "no,yes"
|
|
bitfld.long 0x00 1. " 16kB ,16kB pages are present in the TLB" "no,yes"
|
|
bitfld.long 0x00 0. " 4kB ,4kB pages are present in the TLB" "no,yes"
|
|
textline " "
|
|
group.long c15:0x10d++0x0
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group.long c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group.long c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group.long c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0x8
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup.long c15:0x1700++0x0
|
|
line.long 0x0 "AIDR,Auxiliary ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " AID ,Auxiliary ID"
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Preload Engine"
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEIDR,PLE Identification Register 0"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLESR,PLE Status Register"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x040b++0x00
|
|
line.long 0x00 "PLEFSR,PLE FIFO Status Register"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x011b++0x00
|
|
line.long 0x00 "PLEPCR,PLE Parameters Control Register"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xC9++0x0
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1C9++0x0
|
|
line.long 0x0 "PMCNTENSET,Count Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x2C9++0x0
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x3C9++0x0
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
wgroup.long c15:0x4C9++0x0
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5C9++0x0
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..."
|
|
group.long c15:0xD9++0x0
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group.long c15:0xE9++0x0
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group.long c15:0x1E9++0x0
|
|
line.long 0x0 "PMINTENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2E9++0x0
|
|
line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xb
|
|
tree "Debug"
|
|
width 10.
|
|
tree "Debug Registers"
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " Context ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " Security ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " nSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " uExt ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
if (((per.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
rgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCSV ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " MPCSV ,Meaning of PC sample value" "ARM,Thumb,Jazelle,Thumb"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
rgroup c14:0x28++0x00
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCSV ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " MPCSV ,Meaning of PC sample value" "ARM,Thumb,Jazelle,Thumb"
|
|
rgroup c14:0x29++0x00
|
|
line.long 0x00 "DBGCIDSR,Context ID Sampling Register"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "Not held,Held"
|
|
bitfld.long 0x00 0. " DBGNOPWRDWN ,DBGNOPWRDWN output signal" "Low,High"
|
|
group c14:0xc5++0x00
|
|
line.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
|
|
bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128"
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " OSS ,Outer Shareable Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5 (Reserved)"
|
|
tree.end
|
|
width 17.
|
|
tree "Coresight Management Registers"
|
|
textline " "
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " nDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " nDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 6.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
sif corename()=="CORTEXA5MPCORE"
|
|
width 9.
|
|
base ad:(d.l(c15:0x400f))
|
|
tree "Snoop Control Unit (SCU)"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCUCR,SCU Control Register"
|
|
bitfld.long 0x00 2. " PON ,Parity ON" "Off,On"
|
|
bitfld.long 0x00 1. " AFEN ,Address filtering enable" "Off,On"
|
|
bitfld.long 0x00 0. " SCUEN ,SCU enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SCUCON,SCU Configuration Register"
|
|
bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCUSTAT,SCU CPU Power Status Register"
|
|
bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "INV,SCU Invalidate All Register"
|
|
bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FSAR,Filtering Start Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FEAR,Filtering End Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SAC,SCU Access Control Register"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SSAC,SCU Secure Access Control Register"
|
|
bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
tree.end
|
|
width 0xb
|
|
width 8.
|
|
tree "Timer and Watchdog Blocks"
|
|
base ad:(d.l(c15:0x400f))+0x600
|
|
group.long 0x00++0xb "Timer"
|
|
line.long 0x00 "TLR,Timer Load Register"
|
|
line.long 0x04 "TCR,Timer Counter Register"
|
|
line.long 0x08 "TCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TISR,Timer Interrupt Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x20++0x13 "Watchdog"
|
|
line.long 0x00 "WLR,Watchdog Load Register"
|
|
line.long 0x04 "WCR,Watchdog Counter Register"
|
|
line.long 0x08 "WCONR,Watchdog Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog"
|
|
bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled"
|
|
line.long 0x0c "WISR,Watchdog Interrupt Status Register"
|
|
eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1"
|
|
line.long 0x10 "WRSR,Watchdog Reset Sent Register"
|
|
eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "WDR,Watchdog Disable Register"
|
|
base ad:(d.l(c15:0x400f))+0x200
|
|
group.long 0x00++0xb "Global Timer"
|
|
line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register"
|
|
line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register"
|
|
line.long 0x08 "GTCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "GTSR,Timer Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x10++0xb
|
|
line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register"
|
|
line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register"
|
|
line.long 0x08 "GTINCR,Auto-increment Register for Comparator"
|
|
tree.end
|
|
width 11.
|
|
endif
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree "CGU (Clock Generation Unit)"
|
|
tree "CGU0"
|
|
base ad:0x3108D000
|
|
width 19.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU0_STAT,CGU0 Status Register"
|
|
eventfld.long 0x00 21. " PCFGERR ,PLL configuration error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 15. " OSCWDSTATF ,Oscillator watchdog status fault" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " OSCWDSTATFC ,Oscillator watchdog status fault code bit" "No fault,No Input clock,Sub harmonic CLKIN,Harmonic CLKIN,No AUX_CLK,CLKIN>BOUF,,Multiple limit faults"
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU0_STAT,CGU0 Status Register"
|
|
eventfld.long 0x00 22. " PLOCKERR ,PLL lock error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " DIVERR ,DIV error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " OCBF ,OUTCLK buffer status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " DCBF ,DCLK buffer status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " CCBF0 ,CCLK0 buffer status" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU0_STAT,CGU0 Status Register"
|
|
eventfld.long 0x00 21. " PCFGERR ,PLL configuration error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,PLL clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,PLL clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,Align"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 Divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,Align"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,,,,,,,SCLK1_0,,SCLK0_0,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,,,,,,,SCLK1_0,,SCLK0_0,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,CLKO8,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,CLKO8,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Low,High"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Low,High"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's clock divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's clock divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's Clock Divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load Counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's clock divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CGU0_TSVALUE0,CGU0 Time Stamp Counter Initial 32 LSB Value Register"
|
|
line.long 0x04 "CGU0_TSVALUE1,CGU0 Time Stamp Counter Initial MSB Value Register"
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "CGU0_TSCOUNT0,CGU0 Time Stamp Counter 32 LSB Register"
|
|
line.long 0x04 "CGU0_TSCOUNT1,CGU0 Time Stamp Counter 32 MSB Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CGU0_CCBF_STAT,CGU0 Core Clock Buffer Status Register"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108D000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108D000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CGU0_SCBF_STAT,CGU0 System Clock Buffer Status Register"
|
|
bitfld.long 0x00 3. " OCLKBF ,Output clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DClock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CGU0_REVID,CGU0 Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CGU1"
|
|
base ad:0x3108E000
|
|
width 19.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108E000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CGU1_CTL,CGU1 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CGU1_CTL,CGU1 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108E000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CGU1_CTL,CGU1 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CGU1_CTL,CGU1 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108E000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CGU1_PLLCTL,CGU1 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CGU1_PLLCTL,CGU1 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108E000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CGU1_PLLCTL,CGU1 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CGU1_PLLCTL,CGU1 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU1_STAT,CGU1 Status Register"
|
|
eventfld.long 0x00 21. " PCFGERR ,PLL configuration error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 15. " OSCWDSTATF ,Oscillator watchdog status fault" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " OSCWDSTATFC ,Oscillator watchdog status fault code bit" "No fault,No Input clock,Sub harmonic CLKIN,Harmonic CLKIN,No AUX_CLK,CLKIN>BOUF,,Multiple limit faults"
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU1_STAT,CGU1 Status Register"
|
|
eventfld.long 0x00 22. " PLOCKERR ,PLL lock error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " DIVERR ,DIV error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " OCBF ,OUTCLK buffer status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " DCBF ,DCLK buffer status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " CCBF0 ,CCLK0 buffer status" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU1_STAT,CGU1 Status Register"
|
|
eventfld.long 0x00 21. " PCFGERR ,PLL configuration error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108E000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CGU1_DIV,CGU1 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,PLL clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CGU1_DIV,CGU1 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,PLL clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108E000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CGU1_DIV,CGU1 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,Align"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 Divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CGU1_DIV,CGU1 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,Align"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108E000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CGU1_OSCWDCTL,CGU1 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CGU1_OSCWDCTL,CGU1 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108E000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CGU1_OSCWDCTL,CGU1 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Low,High"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CGU1_OSCWDCTL,CGU1 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Low,High"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108E000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CGU1_CCBF_DIS,CGU1 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CGU1_CCBF_DIS,CGU1 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108E000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CGU1_CCBF_DIS,CGU1 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CGU1_CCBF_DIS,CGU1 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CGU1_CCBF_STAT,CGU1 Core Clock Buffer Status Register"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108E000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CGU1_SCBF_DIS,CGU1 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CGU1_SCBF_DIS,CGU1 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108E000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CGU1_SCBF_DIS,CGU1 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CGU1_SCBF_DIS,CGU1 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CGU1_SCBF_STAT,CGU1 System Clock Buffer Status Register"
|
|
bitfld.long 0x00 3. " OCLKBF ,Output clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DClock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CGU1_REVID,CGU1 Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CDU (Clock Distribution Unit)"
|
|
base ad:0x3108F000
|
|
width 14.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "CDU_CFG0,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO0,IN1_CLKO0,IN2_CLKO0,IN3_CLKO0"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "CDU_CFG0,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO0,IN1_CLKO0,IN2_CLKO0,IN3_CLKO0"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "CDU_CFG0,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO0,IN1_CLKO0,IN2_CLKO0,IN3_CLKO0"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "CDU_CFG0,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO0,IN1_CLKO0,IN2_CLKO0,IN3_CLKO0"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "CDU_CFG1,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO1,IN1_CLKO1,IN2_CLKO1,IN3_CLKO1"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "CDU_CFG1,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO1,IN1_CLKO1,IN2_CLKO1,IN3_CLKO1"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "CDU_CFG1,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO1,IN1_CLKO1,IN2_CLKO1,IN3_CLKO1"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "CDU_CFG1,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO1,IN1_CLKO1,IN2_CLKO1,IN3_CLKO1"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "CDU_CFG2,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO2,IN1_CLKO2,IN2_CLKO2,IN3_CLKO2"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "CDU_CFG2,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO2,IN1_CLKO2,IN2_CLKO2,IN3_CLKO2"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "CDU_CFG2,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO2,IN1_CLKO2,IN2_CLKO2,IN3_CLKO2"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "CDU_CFG2,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO2,IN1_CLKO2,IN2_CLKO2,IN3_CLKO2"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "CDU_CFG3,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO3,IN1_CLKO3,IN2_CLKO3,IN3_CLKO3"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "CDU_CFG3,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO3,IN1_CLKO3,IN2_CLKO3,IN3_CLKO3"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "CDU_CFG3,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO3,IN1_CLKO3,IN2_CLKO3,IN3_CLKO3"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "CDU_CFG3,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO3,IN1_CLKO3,IN2_CLKO3,IN3_CLKO3"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CDU_CFG4,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO4,IN1_CLKO4,IN2_CLKO4,IN3_CLKO4"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CDU_CFG4,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO4,IN1_CLKO4,IN2_CLKO4,IN3_CLKO4"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CDU_CFG4,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO4,IN1_CLKO4,IN2_CLKO4,IN3_CLKO4"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CDU_CFG4,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO4,IN1_CLKO4,IN2_CLKO4,IN3_CLKO4"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "CDU_CFG5,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO5,IN1_CLKO5,IN2_CLKO5,IN3_CLKO5"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CDU_CFG5,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO5,IN1_CLKO5,IN2_CLKO5,IN3_CLKO5"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "CDU_CFG5,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO5,IN1_CLKO5,IN2_CLKO5,IN3_CLKO5"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CDU_CFG5,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO5,IN1_CLKO5,IN2_CLKO5,IN3_CLKO5"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "CDU_CFG6,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO6,IN1_CLKO6,IN2_CLKO6,IN3_CLKO6"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CDU_CFG6,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO6,IN1_CLKO6,IN2_CLKO6,IN3_CLKO6"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "CDU_CFG6,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO6,IN1_CLKO6,IN2_CLKO6,IN3_CLKO6"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CDU_CFG6,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO6,IN1_CLKO6,IN2_CLKO6,IN3_CLKO6"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "CDU_CFG7,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO7,IN1_CLKO7,IN2_CLKO7,IN3_CLKO7"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "CDU_CFG7,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO7,IN1_CLKO7,IN2_CLKO7,IN3_CLKO7"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "CDU_CFG7,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO7,IN1_CLKO7,IN2_CLKO7,IN3_CLKO7"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "CDU_CFG7,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO7,IN1_CLKO7,IN2_CLKO7,IN3_CLKO7"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "CDU_CFG8,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO8,IN1_CLKO8,IN2_CLKO8,IN3_CLKO8"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CDU_CFG8,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO8,IN1_CLKO8,IN2_CLKO8,IN3_CLKO8"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "CDU_CFG8,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO8,IN1_CLKO8,IN2_CLKO8,IN3_CLKO8"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CDU_CFG8,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO8,IN1_CLKO8,IN2_CLKO8,IN3_CLKO8"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "CDU_CFG9,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO9,IN1_CLKO9,IN2_CLKO9,IN3_CLKO9"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "CDU_CFG9,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO9,IN1_CLKO9,IN2_CLKO9,IN3_CLKO9"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "CDU_CFG9,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO9,IN1_CLKO9,IN2_CLKO9,IN3_CLKO9"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "CDU_CFG9,CDU Configuration"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1.--2. " SEL ,Select clock input" "IN0_CLKO9,IN1_CLKO9,IN2_CLKO9,IN3_CLKO9"
|
|
bitfld.long 0x00 0. " EN ,Clock output enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "CDU_STAT,CDU CDU Status"
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 9. " CLKO9 ,CDU_CLKO9 Configuration change status" "Not in progress,In progress"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " CLKO8 ,CDU_CLKO8 Configuration change status" "Not in progress,In progress"
|
|
rbitfld.long 0x00 7. " CLKO7 ,CDU_CLKO7 Configuration shange status" "Not in progress,In progress"
|
|
rbitfld.long 0x00 6. " CLKO6 ,CDU_CLKO6 Configuration change status" "Not in progress,In progress"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CLKO5 ,CDU_CLKO5 Configuration change status" "Not in progress,In progress"
|
|
rbitfld.long 0x00 4. " CLKO4 ,CDU_CLKO4 Configuration change status" "Not in progress,In progress"
|
|
rbitfld.long 0x00 3. " CLKO3 ,CDU_CLKO3 Configuration change status" "Not in progress,In progress"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " CLKO2 ,CDU_CLKO2 Configuration change status" "Not in progress,In progress"
|
|
rbitfld.long 0x00 1. " CLKO1 ,CDU_CLKO1 Configuration change status" "Not in progress,In progress"
|
|
rbitfld.long 0x00 0. " CLKO0 ,CDU_CLKO0 Configuration change status" "Not in progress,In progress"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108F000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "CDU_CLKINSEL,CDU CLKIN Select"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CGU1 ,CGU1 CLKINn select" "CLKIN0,CLKIN1"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "CDU_CLKINSEL,CDU CLKIN Select"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CGU1 ,CGU1 CLKINn select" "CLKIN0,CLKIN1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108F000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "CDU_CLKINSEL,CDU CLKIN Select"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CGU1 ,CGU1 CLKINn select" "CLKIN0,CLKIN1"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "CDU_CLKINSEL,CDU CLKIN Select"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CGU1 ,CGU1 CLKINn select" "CLKIN0,CLKIN1"
|
|
endif
|
|
endif
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "CDU_REVID,CDU Revision ID"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPM (Dynamic Power Management)"
|
|
base ad:0x31090000
|
|
width 25.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 3. " DEEPSLEEP ,Deep sleep" "No action,Deep sleep"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No,Yes"
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No action,Set"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 3. " DEEPSLEEP ,Deep sleep" "No action,Deep sleep"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No,Yes"
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No action,Set"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31090000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPM_STAT,DPM Status Register"
|
|
eventfld.long 0x00 19. " PLLCFGERR ,PLL configuration error" "Inactive,Active"
|
|
eventfld.long 0x00 18. " HVBSYERR ,HV Busy Error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock Write Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ADDRERR ,Address Error" "No error,Error"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HVBSY ,HV busy" "Ready,Busy"
|
|
rbitfld.long 0x00 8. " CCLKDIS ,Core clocks disabled" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--7. " PRVMODE ,Previous Mode" "Reset,Full-On,Active,Active with PLL disabled,Deep sleep,?..."
|
|
rbitfld.long 0x00 0.--3. " CURMODE ,Current Mode" ",Full-On,Active,Active with PLL disabled,?..."
|
|
else
|
|
textline " "
|
|
rbitfld.long 0x00 4.--7. " PRVMODE ,Previous Mode" "Reset,Full-On,?..."
|
|
rbitfld.long 0x00 0.--3. " CURMODE ,Current Mode" ",Full-On,?..."
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x08))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DPM0_CCBF_DIS,DPM0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPM0_CCBF_DIS,DPM0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DPM0_CCBF_EN,DPM0 Core Clock Buffer Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DPM0_CCBF_EN,DPM0 Core Clock Buffer Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DPM0_CCBF_STAT,DPM0 Core Clock Buffer Status Register"
|
|
rbitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "Buffer Enabled,Buffer Disabled"
|
|
line.long 0x04 "DPM0_CCBF_STAT_STKY,DPM0 Core Clock Buffer Status Sticky Register"
|
|
eventfld.long 0x04 0. " CCBF0 ,Core clock buffer 0 disable" "Buffer Enabled,Buffer Disabled"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x18))&0x80000000)==0x80000000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DPM0_SCBF_DIS,DPM0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--1. " SCBF ,System clock buffer disable" "Buffer enabled,,,Buffer Disabled"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "DPM0_SCBF_DIS,DPM0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--1. " SCBF ,System clock buffer disable" "Buffer enabled,,,Buffer Disabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DPM0_WAKE_EN,DPM0 Wakeup Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPM0_WAKE_EN,DPM0 Wakeup Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DPM0_WAKE_POL,DPM0 Wakeup Polarity Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DPM0_WAKE_POL,DPM0 Wakeup Polarity Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPM0_WAKE_STAT,DPM0 Wakeup Status Register"
|
|
eventfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "No action,Enabled"
|
|
eventfld.long 0x00 3. " [3] ,Wakeup source enable 3" "No action,Enabled"
|
|
eventfld.long 0x00 2. " [2] ,Wakeup source enable 2" "No action,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,Wakeup source enable 1" "No action,Enabled"
|
|
eventfld.long 0x00 0. " [0] ,Wakeup source enable 0" "No action,Enabled"
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " CAN1 ,CAN1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " CAN0 ,CAN0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SMPU-DMC0 ,SMPU-DMC0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 21. " SMPU-L2CTL-DL2-0 ,SMPU-L2CTL-DL2-0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 20. " SMPU-L2CTL-CL2-0 ,SMPU-L2CTL-CL2-0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SMPU-SMC ,SMPU-SMC Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 17. " EIP-93/PKP ,CRYPTO ACCELERATOR-1 (EIP-93/PKP) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EIP-150/PKP ,CRYPTO ACCELERATOR-0 (EIP-150/PKP) Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLMDMA1 ,DLMDMA1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DLMDMA0 ,DLMDMA0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " MSI0 ,MSI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMAC0 ,EMAC0 (GigE) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " MLB0 ,MLB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DAI0 ,DAI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IIR0 ,IIR0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FIR0 ,FIR0 Value Peripheral Disable" "No,Yes"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " CAN1 ,CAN1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " CAN0 ,CAN0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SMPU-DMC0 ,SMPU-DMC0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 21. " SMPU-L2CTL-DL2-0 ,SMPU-L2CTL-DL2-0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 20. " SMPU-L2CTL-CL2-0 ,SMPU-L2CTL-CL2-0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SMPU-SMC ,SMPU-SMC Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 17. " EIP-93/PKP ,CRYPTO ACCELERATOR-1 (EIP-93/PKP) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EIP-150/PKP ,CRYPTO ACCELERATOR-0 (EIP-150/PKP) Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLMDMA1 ,DLMDMA1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DLMDMA0 ,DLMDMA0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " MSI0 ,MSI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMAC0 ,EMAC0 (GigE) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " MLB0 ,MLB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DAI0 ,DAI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IIR0 ,IIR0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FIR0 ,FIR0 Value Peripheral Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31090000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--30. 1. " VALUE ,Peripheral Disable"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--30. 1. " VALUE ,Peripheral Disable"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31090000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 15. " C0 ,C0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " C2_L1BK3 ,C2_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " C2_L1BK2 ,C2_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " C2_L1BK1 ,C2_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " C2_L1BK0 ,C2_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C2_L1CBTB ,C2_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " C1_L1BK3 ,C1_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " C1_L1BK2 ,C1_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " C1_L1BK1 ,C1_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " C1_L1BK0 ,C1_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " C1_L1CBTB ,C1_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB0 ,USB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TWI2 ,TWI2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " TWI1 ,TWI1 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TWI0 ,TWI0 Value Peripheral Disable" "No,Yes"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 15. " C0 ,C0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " C2_L1BK3 ,C2_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " C2_L1BK2 ,C2_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " C2_L1BK1 ,C2_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " C2_L1BK0 ,C2_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C2_L1CBTB ,C2_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " C1_L1BK3 ,C1_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " C1_L1BK2 ,C1_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " C1_L1BK1 ,C1_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " C1_L1BK0 ,C1_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " C1_L1CBTB ,C1_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB0 ,USB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TWI2 ,TWI2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " TWI1 ,TWI1 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TWI0 ,TWI0 Value Peripheral Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31090000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " VALUE ,Peripheral Disable"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " VALUE ,Peripheral Disable"
|
|
endif
|
|
endif
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPM_REVID,DPM Revision ID"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RCU (Reset Control Unit)"
|
|
base ad:0x3108C000
|
|
width 17.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 10. " CRSTMSKSEL ,Core reset system reset mask select" "No reset,Reset"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert RSTOUT"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Assert RSTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 10. " CRSTMSKSEL ,Core reset system reset mask select" "No reset,Reset"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert RSTOUT"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Assert RSTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108C000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,RCU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Deassert"
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,RCU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Deassert"
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCU_STAT,RCU Status Register"
|
|
eventfld.long 0x00 18. " RSTOUTERR ,Reset out error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " BMODE ,Boot mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 5. " RSTOUT ,Reset out status" "No reset,Reset"
|
|
eventfld.long 0x00 3. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " SSRST ,System source reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " HWRST ,Hardware reset" "No reset,Reset"
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x08))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " CR[3] ,Core reset outputs 3" "Deasserted,Asserted"
|
|
bitfld.long 0x00 2. " [2] ,Core reset outputs 2" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core reset outputs 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " [0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR[0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " CR[3] ,Core reset outputs 3" "Deasserted,Asserted"
|
|
bitfld.long 0x00 2. " [2] ,Core reset outputs 2" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core reset outputs 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " [0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR[0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108C000+0x08))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Low,High"
|
|
bitfld.long 0x00 2. " CR2 ,Core reset outputs" "Deasserted,Asserted"
|
|
bitfld.long 0x00 1. " CR1 ,Core reset outputs" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR0 ,Core reset outputs" "Deasserted,Asserted"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Low,High"
|
|
bitfld.long 0x00 2. " CR2 ,Core reset outputs" "Deasserted,Asserted"
|
|
bitfld.long 0x00 1. " CR1 ,Core reset outputs" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR0 ,Core reset outputs" "Deasserted,Asserted"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RCU_CRSTAT,RCU Core Reset Outputs Status Register"
|
|
eventfld.long 0x00 3. " CR[3] ,Core reset outputs 3" "Deasserted,Asserted"
|
|
eventfld.long 0x00 2. " [2] ,Core reset outputs 2" "Deasserted,Asserted"
|
|
eventfld.long 0x00 1. " [1] ,Core reset outputs 1" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RCU_CRSTAT,RCU Core Reset Outputs Status Register"
|
|
eventfld.long 0x00 0. " CR[0] , Core reset outputs 0" "Deasserted,Asserted"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RCU_CRSTAT,RCU Core Reset outputs Status Register"
|
|
eventfld.long 0x00 2. " CR2 ,Core reset outputs" "Deasserted,Asserted"
|
|
eventfld.long 0x00 1. " CR1 ,Core reset outputs" "Deasserted,Asserted"
|
|
eventfld.long 0x00 0. " CR0 ,Core reset outputs" "Deasserted,Asserted"
|
|
endif
|
|
sif (!cpuis("ADSP-SC57*")||!cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108C000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RCU_SIDIS,RCU System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SI1 ,System interface disable request" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " SI0 ,System interface disable request" "Not asserted,Asserted"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RCU_SIDIS,RCU System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SI1 ,System interface disable request" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " SI0 ,System Interface disable request" "Not asserted,Asserted"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RCU_SISTAT,RCU System Interface Status Register"
|
|
bitfld.long 0x00 1. " SI1 ,System interface disable acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " SI0 ,System interface disable acknowledge" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCU_SRRQSTAT,System Reset Request Status"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
eventfld.long 0x00 7. " SRRQ[7] ,System reset triggered by system reset request 7" "Deasserted,Asserted"
|
|
eventfld.long 0x00 6. " [6] ,System reset triggered by system reset request 6" "Deasserted,Asserted"
|
|
eventfld.long 0x00 5. " [5] ,System reset triggered by system reset request 5" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 4. " [4] ,System reset triggered by system reset request 4" "Deasserted,Asserted"
|
|
eventfld.long 0x00 3. " [3] ,System reset triggered by system reset request 3" "Deasserted,Asserted"
|
|
eventfld.long 0x00 2. " [2] ,System reset triggered by system reset request 2" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,System reset triggered by system reset request 1" "Deasserted,Asserted"
|
|
eventfld.long 0x00 0. " [0] ,System reset triggered by system reset request 0" "Deasserted,Asserted"
|
|
else
|
|
eventfld.long 0x00 3. " SRRQ[3] ,System reset triggered by system reset request 3" "Deasserted,Asserted"
|
|
eventfld.long 0x00 2. " [2] ,System reset triggered by system reset request 2" "Deasserted,Asserted"
|
|
eventfld.long 0x00 1. " [1] ,System reset triggered by system reset request 1" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,System reset triggered by system reset request 0" "Deasserted,Asserted"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108C000+0x18))&0x80000000)==0x80000000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,RCU SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 2. " SVECT2 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SVECT1 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT0 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,RCU SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 2. " SVECT2 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SVECT1 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT0 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RCU_SIDIS,System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SI[1] ,System interface disable request 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " SI[0] ,System interface disable request 0" "Deasserted,Asserted"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCU_SIDIS,System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SI[1] ,System interface disable request 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " SI[0] ,System interface disable request 0" "Deasserted,Asserted"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108C000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RCU_BCODE,RCU Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Do not enter,Enter"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 configuration" "Configure,Do not configure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,No hook" "Hook,No hook"
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Preboot,No preboot"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No faults" "Fault initialization,No fault initialization"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Enable and initialize,Do not initialize or enable"
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Memory initialization,No memory initialization"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute wakeup" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Do not execute,Execute"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "Vector,Do not Vector"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "Execute,Do not execute"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCU_BCODE,RCU Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Do not enter,Enter"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 configuration" "Configure,Do not configure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,No hook" "Hook,No hook"
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Preboot,No preboot"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No faults" "Fault initialization,No fault initialization"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Enable and initialize,Do not initialize or enable"
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Memory initialization,No memory initialization"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute wakeup" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Do not execute,Execute"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "Vector,Do not Vector"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "Execute,Do not execute"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RCU_SISTAT,System Interface Status Register"
|
|
bitfld.long 0x00 1. " SI[1] ,System interface disable acknowledge 1" "No Acknowledge,Asserted"
|
|
bitfld.long 0x00 0. " SI[0] ,System interface disable acknowledge 0" "No Acknowledge,Asserted"
|
|
else
|
|
if (((per.l(ad:0x3108C000+0x18))&0x01)==0x01)&&(((per.l(ad:0x3108C000))&0x01)==0x01)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RCU_SVECT0,RCU Software Vector Register 0"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCU_SVECT0,RCU Software Vector Register 0"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " SVECT[2] ,Lock SVECT2 registers" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SVECT[1] ,Lock SVECT1 registers" "Unlocked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT[0] ,Lock SVECT0 registers" "Unlocked,Locked"
|
|
textline " "
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " SVECT[2] ,Lock SVECT2 registers" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SVECT[1] ,Lock SVECT1 registers" "Unlocked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT[0] ,Lock SVECT0 registers" "Unlocked,Locked"
|
|
textline " "
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108C000+0x18))&0x02)==0x02)&&(((per.l(ad:0x3108C000))&0x01)==0x01)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT1,RCU Software Vector Register 1"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT1,RCU Software Vector Register 1"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RCU_BCODE,Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOCORE3 ,No core 3 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Not idle,Idle"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 configuration" "Configure,Not configure"
|
|
bitfld.long 0x00 10. " NOHOOK ,No hook" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Perform,Not perform"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No faults" "Perform,Not perform"
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Initialize,Not initialize"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Perform,Not perform"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute Wakeup" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Not execute,Execute"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "No,Yes"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "No,Yes"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RCU_BCODE,Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOCORE3 ,No core 3 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Not idle,Idle"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 Configuration" "Configure,Not configure"
|
|
bitfld.long 0x00 10. " NOHOOK ,No Hook" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Perform,Not perform"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No Faults" "Perform,Not perform"
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Initialize,Not initialize"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Perform,Not perform"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute wakeup" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Not execute,Execute"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "No,Yes"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108C000+0x18))&0x04)==0x04)&&(((per.l(ad:0x3108C000))&0x01)==0x01)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RCU_SVECT2,RCU Software Vector Register 2"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RCU_SVECT2,RCU Software Vector Register 2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x24))&0x01)==0x01)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RCU_SVECT0,Software Vector Register 0"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCU_SVECT0,Software Vector Register 0"
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x24))&0x02)==0x02)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RCU_SVECT1,Software Vector Register 1"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCU_SVECT1,Software Vector Register 1"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108C000+0x24))&0x04)==0x04)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "RCU_SVECT2,Software Vector Register 2"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RCU_SVECT2,Software Vector Register 2"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RCU_MSG_SET/CLR,RCU Message Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CALLERR ,Call Error Flag" "Not set,Set"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CALLBACK ,Callback call flag" "Not set,Set"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " CALLINIT ,Call initcode flag" "Not set,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " CALLAPP ,Call application flag" "Not set,Set"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " HALTONERR ,Halt on Error Call" "Not generate,Generate"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HALTONCALL ,Halt on callback call" "Not generate,Generate"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " HALTONINIT ,Halt on initcode call" "Not generate,Generate"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " HALTONAPP ,Halt on application call" "Not generate,Generate"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " L2INIT ,L2 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SECINIT ,SEC initialized" "Not initialized,Initialized"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " C2ACTIVATE ,Core 2 activated" "Not activated,Activated"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " C1ACTIVATE ,Core 1 activated" "Not activated,Activated"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " C2L1INIT ,Core 2 L1 initialized" "Not initialized,Initialized"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " C1L1INIT ,Core 1 L1 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " C0L1INIT ,Core 0 L1 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " C2IDLE ,Core 2 idle" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " C1IDLE ,Core 1 idle" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " C0IDLE ,Core 0 idle" "No,Yes"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERRCODE ,ROM Error Code"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RCU_MSG_SET/CLR,RCU Message Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CALLERR ,Call Error Flag" "Not set,Set"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CALLBACK ,Callback call flag" "Not set,Set"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " CALLINIT ,Call initcode flag" "Not set,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " CALLAPP ,Call application flag" "Not set,Set"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " HALTONERR ,Halt on Error Call" "Not generate,Generate"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HALTONCALL ,Halt on callback call" "Not generate,Generate"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " HALTONINIT ,Halt on initcode call" "Not generate,Generate"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " HALTONAPP ,Halt on application call" "Not generate,Generate"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " L3INIT ,L3 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " L2INIT ,L2 initialized" "Not initialized,Initialized"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " C0L1INIT ,Core 0 L1 initialized" "Not initialized,Initialized"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RCU_MSG,RCU Message Register"
|
|
bitfld.long 0x00 31. " CALLERR ,Call error flag" "Not set,Set"
|
|
bitfld.long 0x00 30. " CALLBACK ,Callback call flag" "Not set,Set"
|
|
bitfld.long 0x00 29. " CALLINIT ,Call initcode flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CALLAPP ,Call application flag" "Not set,Set"
|
|
bitfld.long 0x00 27. " HALTONERR ,Halt on error call" "Do not generate,Generate"
|
|
bitfld.long 0x00 26. " HALTONCALL ,Halt on callback call" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HALTONINIT ,Halt on initcode call" "Do not generate,Generate"
|
|
bitfld.long 0x00 24. " HALTONAPP ,Halt on application call" "Do not generate,Generate"
|
|
bitfld.long 0x00 23. " L3INIT ,L3 Initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " L2INIT ,L2 Initialized" "Not initialized,Initialized"
|
|
bitfld.long 0x00 20. " C2ACTIVATE ,Core 2 activated" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " C1ACTIVATE ,Core 1 activated" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " C2L1INIT ,Core 2 L1 initialized" "Not initialized,Initialized"
|
|
bitfld.long 0x00 17. " C1L1INIT ,Core 1 L1 initialized" "Not initialized,Initialized"
|
|
bitfld.long 0x00 16. " C0L1INIT ,Core 0 L1 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C2IDLE ,Indicates that core 2 is in a safe idle state in ROM" "Not idle,Idle"
|
|
bitfld.long 0x00 9. " C1IDLE ,Indicates that core 1 is in a safe idle state in ROM" "Not idle,Idle"
|
|
bitfld.long 0x00 8. " C0IDLE ,Indicates that core 0 is in a safe idle state in ROM" "Not idle,Idle"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERRCODE ,ERRCODE"
|
|
endif
|
|
sif (!cpuis("ADSP-SC57*")&&!cpuis("ADSPCM40*"))
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "RCU_MSG_SET,RCU Message Set Bits Register"
|
|
bitfld.long 0x00 31. " SET[31] , Set message bit 31" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] , Set message bit 30" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] , Set message bit 29" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [28] , Set message bit 28" "No effect,Set"
|
|
bitfld.long 0x00 27. " [27] , Set message bit 27" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] , Set Message Bit 26" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] , Set message bit 25" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] , Set Message Bit 24" "No effect,Set"
|
|
bitfld.long 0x00 23. " [23] , Set Message Bit 23" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] , Set message bit 22" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] , Set message bit 21" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] , Set message bit 20" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] , Set message bit 19" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] , Set message bit 18" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] , Set message bit 17" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] , Set message bit 16" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] , Set message bit 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] , Set message bit 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] , Set message bit 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] , Set message bit 12" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] , Set message bit 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] , Set message bit 10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] , Set message bit 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] , Set message bit 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] , Set message bit 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] , Set message bit 6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] , Set message bit 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] , Set Message Bit 4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] , Set message bit 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] , Set message bit 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] , Set message bit 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] , Set message bit 0" "No effect,Set"
|
|
line.long 0x04 "RCU_MSG_CLR,RCU Message Clear Bits Register"
|
|
bitfld.long 0x04 31. " CLR[31] ,Clear MSG register bit 31" "No effect,Clear"
|
|
bitfld.long 0x04 30. " [30] ,Clear MSG register bit 30 " "No effect,Clear"
|
|
bitfld.long 0x04 29. " [29] ,Clear MSG register bit 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " [28] ,Clear MSG register bit 28" "No effect,Clear"
|
|
bitfld.long 0x04 27. " [27] ,Clear MSG register bit 27" "No effect,Clear"
|
|
bitfld.long 0x04 26. " [26] ,Clear MSG register bit 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " [25] ,Clear MSG register bit 25" "No effect,Clear"
|
|
bitfld.long 0x04 24. " [24] ,Clear MSG register bit 24" "No effect,Clear"
|
|
bitfld.long 0x04 23. " [23] ,Clear MSG register bit 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " [22] ,Clear MSG register bit 22" "No effect,Clear"
|
|
bitfld.long 0x04 21. " [21] ,Clear MSG register bit 21" "No effect,Clear"
|
|
bitfld.long 0x04 20. " [20] ,Clear MSG register bit 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,Clear MSG register bit 19" "No effect,Clear"
|
|
bitfld.long 0x04 18. " [18] ,Clear MSG register bit 18" "No effect,Clear"
|
|
bitfld.long 0x04 17. " [17] ,Clear MSG register bit 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " [16] ,Clear MSG register bit 16" "No effect,Clear"
|
|
bitfld.long 0x04 15. " [15] ,Clear MSG register bit 15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Clear MSG register bit 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [13] ,Clear MSG register bit 13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Clear MSG register bit 12" "No effect,Clear"
|
|
bitfld.long 0x04 11. " [11] ,Clear MSG register bit 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " [10] ,Clear MSG register bit 10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Clear MSG register bit 9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Clear MSG register bit 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Clear MSG register bit 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Clear MSG register bit 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Clear MSG register bit 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " [4] ,Clear MSG register bit 4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " [3] ,Clear MSG register bit 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Clear MSG register bit 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [1] ,Clear MSG register bit 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Clear MSG register bit 0" "No effect,Clear"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RCU_REVID,RCU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental version ID"
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "RCU_REVID,RCU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental version ID"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SEC (System Event Controller)"
|
|
base ad:0x31089000
|
|
width 16.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,SEC Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,SEC Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "SEC_GSTAT,SEC Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Lock Write Error" "No error,Error"
|
|
eventfld.long 0x00 30. " ADRERR ,Address Error" "No error,Error"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " SID ,Source ID for SSI Error"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " SCI ,SCI ID for SCI Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "SFI,,SSI,?..."
|
|
else
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "SFI,SCI,SSI,?..."
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
line.long 0x04 "SEC_RAISE,SEC Global Raise Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SID ,Source ID"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SEC_END,SEC Global End Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID IRQ to End"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Active mode,Pending mode"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Active mode,Pending mode"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,SEC Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Fault active,Fault pending"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SEC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,SEC Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Fault active,Fault pending"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SEC enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SEC_FSTAT,SEC Fault Status Register"
|
|
rbitfld.long 0x00 10. " NPND ,Next pending fault" "Not pending,Pending"
|
|
rbitfld.long 0x00 9. " ACT ,Fault active" "Not active,Active"
|
|
rbitfld.long 0x00 8. " PND ,Pending fault" "Not pending,Pending"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*")||cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow error,,End error,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" ",,End error,?..."
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SEC_FSID,SEC Fault Source ID Register"
|
|
bitfld.long 0x00 16. " FEXT ,Fault external" "Internal,External"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SEC_FEND,SEC Fault End Register"
|
|
bitfld.long 0x00 16. " FEXT ,Fault external" "Internal,External"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SEC_FDLY,SEC Fault Delay Register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SEC_FDLY_CUR,SEC Fault Delay Current Register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SEC_FSRDLY,SEC Fault System Reset Delay Register"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SEC_FSRDLY_CUR,SEC Fault System Reset Delay Current Register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SEC_FCOPP,SEC Fault COP Period Register"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SEC_FCOPP_CUR,SEC Fault COP Period Current Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x440))&0x80000000)==0x80000000)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x440))&0x80000000)==0x80000000)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x440+0x04)++0x03
|
|
line.long 0x00 "SEC_CSTAT1,SEC SCI Status Register 1"
|
|
eventfld.long 0x00 16. " NMI ,NMI" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " WFI ,Wait for idle" "Not waiting,Waiting"
|
|
rbitfld.long 0x00 10. " SIDV ,SID valid" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " ACTV ,ACT valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 8. " PNDV ,PND valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" ",ACK error,?..."
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
rgroup.long (0x440+0x08)++0x03
|
|
line.long 0x00 "SEC_CPND1,SEC Core Pending Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest pending IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest pending IRQ source ID"
|
|
rgroup.long (0x440+0x0C)++0x03
|
|
line.long 0x00 "SEC_CACT1,SEC SCI Active Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest active IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest active IRQ source ID"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x440+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x440+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x454))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x440+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x440+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x440+0x18)++0x3
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x440+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x440+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
endif
|
|
rgroup.long (0x440+0x1C)++0x03
|
|
line.long 0x00 "SEC_CSID1,SEC SCI Source ID Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x480))&0x80000000)==0x80000000)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x480))&0x80000000)==0x80000000)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x480+0x04)++0x03
|
|
line.long 0x00 "SEC_CSTAT2,SEC SCI Status Register 2"
|
|
eventfld.long 0x00 16. " NMI ,NMI" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " WFI ,Wait for idle" "Not waiting,Waiting"
|
|
rbitfld.long 0x00 10. " SIDV ,SID valid" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " ACTV ,ACT valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 8. " PNDV ,PND valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" ",ACK error,?..."
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
rgroup.long (0x480+0x08)++0x03
|
|
line.long 0x00 "SEC_CPND2,SEC Core Pending Register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest pending IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest pending IRQ source ID"
|
|
rgroup.long (0x480+0x0C)++0x03
|
|
line.long 0x00 "SEC_CACT2,SEC SCI Active Register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest active IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest active IRQ source ID"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x480+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x480+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x454))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x480+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x480+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x480+0x18)++0x3
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x480+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x480+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
endif
|
|
rgroup.long (0x480+0x1C)++0x03
|
|
line.long 0x00 "SEC_CSID2,SEC SCI Source ID Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x800+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT0,SEC Source Status Register 0"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x808))&0x80000000)==0x80000000)
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x808+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT1,SEC Source Status Register 1"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x810))&0x80000000)==0x80000000)
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x810+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT2,SEC Source Status Register 2"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x818))&0x80000000)==0x80000000)
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x818+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT3,SEC Source Status Register 3"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x820))&0x80000000)==0x80000000)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x820+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT4,SEC Source Status Register 4"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x828))&0x80000000)==0x80000000)
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x828+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT5,SEC Source Status Register 5"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x830))&0x80000000)==0x80000000)
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x830+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT6,SEC Source Status Register 6"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x838))&0x80000000)==0x80000000)
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x838+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT7,SEC Source Status Register 7"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x840))&0x80000000)==0x80000000)
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x840+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT8,SEC Source Status Register 8"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x848))&0x80000000)==0x80000000)
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x848+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT9,SEC Source Status Register 9"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x850))&0x80000000)==0x80000000)
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x850+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT10,SEC Source Status Register 10"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x858))&0x80000000)==0x80000000)
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x858+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT11,SEC Source Status Register 11"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x860))&0x80000000)==0x80000000)
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x860+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT12,SEC Source Status Register 12"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x868))&0x80000000)==0x80000000)
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x868+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT13,SEC Source Status Register 13"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x870))&0x80000000)==0x80000000)
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x870+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT14,SEC Source Status Register 14"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x878))&0x80000000)==0x80000000)
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x878+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT15,SEC Source Status Register 15"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x880))&0x80000000)==0x80000000)
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x880+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT16,SEC Source Status Register 16"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x888))&0x80000000)==0x80000000)
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x888+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT17,SEC Source Status Register 17"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x890))&0x80000000)==0x80000000)
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x890+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT18,SEC Source Status Register 18"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x898))&0x80000000)==0x80000000)
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x898+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT19,SEC Source Status Register 19"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT20,SEC Source Status Register 20"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT21,SEC Source Status Register 21"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT22,SEC Source Status Register 22"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT23,SEC Source Status Register 23"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT24,SEC Source Status Register 24"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT25,SEC Source Status Register 25"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT26,SEC Source Status Register 26"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT27,SEC Source Status Register 27"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT28,SEC Source Status Register 28"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT29,SEC Source Status Register 29"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT30,SEC Source Status Register 30"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT31,SEC Source Status Register 31"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x900))&0x80000000)==0x80000000)
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x900+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT32,SEC Source Status Register 32"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x908))&0x80000000)==0x80000000)
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x908+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT33,SEC Source Status Register 33"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x910))&0x80000000)==0x80000000)
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x910+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT34,SEC Source Status Register 34"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x918))&0x80000000)==0x80000000)
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x918+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT35,SEC Source Status Register 35"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x920))&0x80000000)==0x80000000)
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x920+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT36,SEC Source Status Register 36"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x928))&0x80000000)==0x80000000)
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x928+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT37,SEC Source Status Register 37"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x930))&0x80000000)==0x80000000)
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x930+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT38,SEC Source Status Register 38"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x938))&0x80000000)==0x80000000)
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x938+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT39,SEC Source Status Register 39"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x940))&0x80000000)==0x80000000)
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x940+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT40,SEC Source Status Register 40"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x948))&0x80000000)==0x80000000)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x948+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT41,SEC Source Status Register 41"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x950))&0x80000000)==0x80000000)
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x950+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT42,SEC Source Status Register 42"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x958))&0x80000000)==0x80000000)
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x958+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT43,SEC Source Status Register 43"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x960))&0x80000000)==0x80000000)
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x960+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT44,SEC Source Status Register 44"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x968))&0x80000000)==0x80000000)
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x968+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT45,SEC Source Status Register 45"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x970))&0x80000000)==0x80000000)
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x970+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT46,SEC Source Status Register 46"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x978))&0x80000000)==0x80000000)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x978+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT47,SEC Source Status Register 47"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x980))&0x80000000)==0x80000000)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x980+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT48,SEC Source Status Register 48"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x988))&0x80000000)==0x80000000)
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x988+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT49,SEC Source Status Register 49"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x990))&0x80000000)==0x80000000)
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x990+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT50,SEC Source Status Register 50"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x998))&0x80000000)==0x80000000)
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x998+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT51,SEC Source Status Register 51"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT52,SEC Source Status Register 52"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT53,SEC Source Status Register 53"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT54,SEC Source Status Register 54"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT55,SEC Source Status Register 55"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT56,SEC Source Status Register 56"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT57,SEC Source Status Register 57"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT58,SEC Source Status Register 58"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT59,SEC Source Status Register 59"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT60,SEC Source Status Register 60"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT61,SEC Source Status Register 61"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT62,SEC Source Status Register 62"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT63,SEC Source Status Register 63"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT64,SEC Source Status Register 64"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT65,SEC Source Status Register 65"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT66,SEC Source Status Register 66"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT67,SEC Source Status Register 67"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT68,SEC Source Status Register 68"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT69,SEC Source Status Register 69"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT70,SEC Source Status Register 70"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT71,SEC Source Status Register 71"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT72,SEC Source Status Register 72"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT73,SEC Source Status Register 73"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT74,SEC Source Status Register 74"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT75,SEC Source Status Register 75"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT76,SEC Source Status Register 76"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT77,SEC Source Status Register 77"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT78,SEC Source Status Register 78"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT79,SEC Source Status Register 79"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT80,SEC Source Status Register 80"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT81,SEC Source Status Register 81"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT82,SEC Source Status Register 82"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT83,SEC Source Status Register 83"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT84,SEC Source Status Register 84"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT85,SEC Source Status Register 85"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT86,SEC Source Status Register 86"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT87,SEC Source Status Register 87"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT88,SEC Source Status Register 88"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT89,SEC Source Status Register 89"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT90,SEC Source Status Register 90"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT91,SEC Source Status Register 91"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT92,SEC Source Status Register 92"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT93,SEC Source Status Register 93"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT94,SEC Source Status Register 94"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT95,SEC Source Status Register 95"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT96,SEC Source Status Register 96"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT97,SEC Source Status Register 97"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT98,SEC Source Status Register 98"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT99,SEC Source Status Register 99"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT100,SEC Source Status Register 100"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT101,SEC Source Status Register 101"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT102,SEC Source Status Register 102"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT103,SEC Source Status Register 103"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT104,SEC Source Status Register 104"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT105,SEC Source Status Register 105"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT106,SEC Source Status Register 106"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT107,SEC Source Status Register 107"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT108,SEC Source Status Register 108"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT109,SEC Source Status Register 109"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT110,SEC Source Status Register 110"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT111,SEC Source Status Register 111"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT112,SEC Source Status Register 112"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT113,SEC Source Status Register 113"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT114,SEC Source Status Register 114"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT115,SEC Source Status Register 115"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT116,SEC Source Status Register 116"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT117,SEC Source Status Register 117"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT118,SEC Source Status Register 118"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT119,SEC Source Status Register 119"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT120,SEC Source Status Register 120"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT121,SEC Source Status Register 121"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT122,SEC Source Status Register 122"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT123,SEC Source Status Register 123"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT124,SEC Source Status Register 124"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT125,SEC Source Status Register 125"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT126,SEC Source Status Register 126"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT127,SEC Source Status Register 127"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT128,SEC Source Status Register 128"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
else
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x800+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT0,SEC Source Status Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x808))&0x80000000)==0x80000000)
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x808))&0x80000000)==0x80000000)
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x808+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT1,SEC Source Status Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x810))&0x80000000)==0x80000000)
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x810))&0x80000000)==0x80000000)
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x810+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT2,SEC Source Status Register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x818))&0x80000000)==0x80000000)
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x818))&0x80000000)==0x80000000)
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x818+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT3,SEC Source Status Register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x820))&0x80000000)==0x80000000)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x820))&0x80000000)==0x80000000)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x820+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT4,SEC Source Status Register 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x828))&0x80000000)==0x80000000)
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x828))&0x80000000)==0x80000000)
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x828+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT5,SEC Source Status Register 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x830))&0x80000000)==0x80000000)
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x830))&0x80000000)==0x80000000)
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x830+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT6,SEC Source Status Register 6"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x838))&0x80000000)==0x80000000)
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x838))&0x80000000)==0x80000000)
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x838+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT7,SEC Source Status Register 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x840))&0x80000000)==0x80000000)
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x840))&0x80000000)==0x80000000)
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x840+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT8,SEC Source Status Register 8"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x848))&0x80000000)==0x80000000)
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x848))&0x80000000)==0x80000000)
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x848+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT9,SEC Source Status Register 9"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x850))&0x80000000)==0x80000000)
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x850))&0x80000000)==0x80000000)
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x850+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT10,SEC Source Status Register 10"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x858))&0x80000000)==0x80000000)
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x858))&0x80000000)==0x80000000)
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x858+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT11,SEC Source Status Register 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x860))&0x80000000)==0x80000000)
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x860))&0x80000000)==0x80000000)
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x860+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT12,SEC Source Status Register 12"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x868))&0x80000000)==0x80000000)
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x868))&0x80000000)==0x80000000)
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x868+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT13,SEC Source Status Register 13"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x870))&0x80000000)==0x80000000)
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x870))&0x80000000)==0x80000000)
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x870+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT14,SEC Source Status Register 14"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x878))&0x80000000)==0x80000000)
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x878))&0x80000000)==0x80000000)
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x878+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT15,SEC Source Status Register 15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x880))&0x80000000)==0x80000000)
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x880))&0x80000000)==0x80000000)
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x880+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT16,SEC Source Status Register 16"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x888))&0x80000000)==0x80000000)
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x888))&0x80000000)==0x80000000)
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x888+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT17,SEC Source Status Register 17"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x890))&0x80000000)==0x80000000)
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x890))&0x80000000)==0x80000000)
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x890+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT18,SEC Source Status Register 18"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x898))&0x80000000)==0x80000000)
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x898))&0x80000000)==0x80000000)
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x898+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT19,SEC Source Status Register 19"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT20,SEC Source Status Register 20"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT21,SEC Source Status Register 21"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT22,SEC Source Status Register 22"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT23,SEC Source Status Register 23"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT24,SEC Source Status Register 24"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT25,SEC Source Status Register 25"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT26,SEC Source Status Register 26"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT27,SEC Source Status Register 27"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT28,SEC Source Status Register 28"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT29,SEC Source Status Register 29"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT30,SEC Source Status Register 30"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x8F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x8F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT31,SEC Source Status Register 31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x900))&0x80000000)==0x80000000)
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x900))&0x80000000)==0x80000000)
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x900+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT32,SEC Source Status Register 32"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x908))&0x80000000)==0x80000000)
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x908))&0x80000000)==0x80000000)
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x908+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT33,SEC Source Status Register 33"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x910))&0x80000000)==0x80000000)
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x910))&0x80000000)==0x80000000)
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x910+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT34,SEC Source Status Register 34"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x918))&0x80000000)==0x80000000)
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x918))&0x80000000)==0x80000000)
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x918+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT35,SEC Source Status Register 35"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x920))&0x80000000)==0x80000000)
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x920))&0x80000000)==0x80000000)
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x920+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT36,SEC Source Status Register 36"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x928))&0x80000000)==0x80000000)
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x928))&0x80000000)==0x80000000)
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x928+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT37,SEC Source Status Register 37"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x930))&0x80000000)==0x80000000)
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x930))&0x80000000)==0x80000000)
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x930+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT38,SEC Source Status Register 38"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x938))&0x80000000)==0x80000000)
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x938))&0x80000000)==0x80000000)
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x938+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT39,SEC Source Status Register 39"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x940))&0x80000000)==0x80000000)
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x940))&0x80000000)==0x80000000)
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x940+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT40,SEC Source Status Register 40"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x948))&0x80000000)==0x80000000)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x948))&0x80000000)==0x80000000)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x948+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT41,SEC Source Status Register 41"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x950))&0x80000000)==0x80000000)
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x950))&0x80000000)==0x80000000)
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x950+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT42,SEC Source Status Register 42"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x958))&0x80000000)==0x80000000)
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x958))&0x80000000)==0x80000000)
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x958+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT43,SEC Source Status Register 43"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x960))&0x80000000)==0x80000000)
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x960))&0x80000000)==0x80000000)
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x960+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT44,SEC Source Status Register 44"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x968))&0x80000000)==0x80000000)
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x968))&0x80000000)==0x80000000)
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x968+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT45,SEC Source Status Register 45"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x970))&0x80000000)==0x80000000)
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x970))&0x80000000)==0x80000000)
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x970+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT46,SEC Source Status Register 46"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x978))&0x80000000)==0x80000000)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x978))&0x80000000)==0x80000000)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x978+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT47,SEC Source Status Register 47"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x980))&0x80000000)==0x80000000)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x980))&0x80000000)==0x80000000)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x980+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT48,SEC Source Status Register 48"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x988))&0x80000000)==0x80000000)
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x988))&0x80000000)==0x80000000)
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x988+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT49,SEC Source Status Register 49"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x990))&0x80000000)==0x80000000)
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x990))&0x80000000)==0x80000000)
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x990+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT50,SEC Source Status Register 50"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x998))&0x80000000)==0x80000000)
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x998))&0x80000000)==0x80000000)
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x998+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT51,SEC Source Status Register 51"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT52,SEC Source Status Register 52"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT53,SEC Source Status Register 53"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT54,SEC Source Status Register 54"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT55,SEC Source Status Register 55"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT56,SEC Source Status Register 56"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT57,SEC Source Status Register 57"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT58,SEC Source Status Register 58"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT59,SEC Source Status Register 59"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT60,SEC Source Status Register 60"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT61,SEC Source Status Register 61"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT62,SEC Source Status Register 62"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0x9F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0x9F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT63,SEC Source Status Register 63"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT64,SEC Source Status Register 64"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT65,SEC Source Status Register 65"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT66,SEC Source Status Register 66"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT67,SEC Source Status Register 67"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT68,SEC Source Status Register 68"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT69,SEC Source Status Register 69"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT70,SEC Source Status Register 70"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT71,SEC Source Status Register 71"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT72,SEC Source Status Register 72"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT73,SEC Source Status Register 73"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT74,SEC Source Status Register 74"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT75,SEC Source Status Register 75"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT76,SEC Source Status Register 76"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT77,SEC Source Status Register 77"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT78,SEC Source Status Register 78"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT79,SEC Source Status Register 79"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT80,SEC Source Status Register 80"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT81,SEC Source Status Register 81"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT82,SEC Source Status Register 82"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xA98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xA98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT83,SEC Source Status Register 83"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT84,SEC Source Status Register 84"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT85,SEC Source Status Register 85"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT86,SEC Source Status Register 86"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT87,SEC Source Status Register 87"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT88,SEC Source Status Register 88"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT89,SEC Source Status Register 89"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT90,SEC Source Status Register 90"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT91,SEC Source Status Register 91"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT92,SEC Source Status Register 92"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT93,SEC Source Status Register 93"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT94,SEC Source Status Register 94"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xAF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xAF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT95,SEC Source Status Register 95"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT96,SEC Source Status Register 96"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT97,SEC Source Status Register 97"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT98,SEC Source Status Register 98"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT99,SEC Source Status Register 99"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT100,SEC Source Status Register 100"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT101,SEC Source Status Register 101"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT102,SEC Source Status Register 102"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT103,SEC Source Status Register 103"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT104,SEC Source Status Register 104"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT105,SEC Source Status Register 105"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT106,SEC Source Status Register 106"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT107,SEC Source Status Register 107"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT108,SEC Source Status Register 108"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT109,SEC Source Status Register 109"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT110,SEC Source Status Register 110"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT111,SEC Source Status Register 111"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT112,SEC Source Status Register 112"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT113,SEC Source Status Register 113"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT114,SEC Source Status Register 114"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xB98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xB98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT115,SEC Source Status Register 115"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT116,SEC Source Status Register 116"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT117,SEC Source Status Register 117"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT118,SEC Source Status Register 118"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT119,SEC Source Status Register 119"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT120,SEC Source Status Register 120"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT121,SEC Source Status Register 121"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT122,SEC Source Status Register 122"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT123,SEC Source Status Register 123"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT124,SEC Source Status Register 124"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT125,SEC Source Status Register 125"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT126,SEC Source Status Register 126"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xBF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xBF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT127,SEC Source Status Register 127"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT128,SEC Source Status Register 128"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT129,SEC Source Status Register 129"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT130,SEC Source Status Register 130"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT131,SEC Source Status Register 131"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT132,SEC Source Status Register 132"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT133,SEC Source Status Register 133"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT134,SEC Source Status Register 134"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT135,SEC Source Status Register 135"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT136,SEC Source Status Register 136"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT137,SEC Source Status Register 137"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT138,SEC Source Status Register 138"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT139,SEC Source Status Register 139"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT140,SEC Source Status Register 140"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT141,SEC Source Status Register 141"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT142,SEC Source Status Register 142"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT143,SEC Source Status Register 143"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT144,SEC Source Status Register 144"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT145,SEC Source Status Register 145"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT146,SEC Source Status Register 146"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xC98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xC98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT147,SEC Source Status Register 147"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT148,SEC Source Status Register 148"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT149,SEC Source Status Register 149"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT150,SEC Source Status Register 150"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT151,SEC Source Status Register 151"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT152,SEC Source Status Register 152"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT153,SEC Source Status Register 153"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT154,SEC Source Status Register 154"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT155,SEC Source Status Register 155"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT156,SEC Source Status Register 156"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT157,SEC Source Status Register 157"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT158,SEC Source Status Register 158"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xCF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xCF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT159,SEC Source Status Register 159"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT160,SEC Source Status Register 160"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT161,SEC Source Status Register 161"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT162,SEC Source Status Register 162"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT163,SEC Source Status Register 163"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT164,SEC Source Status Register 164"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT165,SEC Source Status Register 165"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT166,SEC Source Status Register 166"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT167,SEC Source Status Register 167"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT168,SEC Source Status Register 168"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT169,SEC Source Status Register 169"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT170,SEC Source Status Register 170"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT171,SEC Source Status Register 171"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT172,SEC Source Status Register 172"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT173,SEC Source Status Register 173"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT174,SEC Source Status Register 174"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT175,SEC Source Status Register 175"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT176,SEC Source Status Register 176"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT177,SEC Source Status Register 177"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT178,SEC Source Status Register 178"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xD98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xD98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT179,SEC Source Status Register 179"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT180,SEC Source Status Register 180"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT181,SEC Source Status Register 181"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT182,SEC Source Status Register 182"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT183,SEC Source Status Register 183"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT184,SEC Source Status Register 184"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT185,SEC Source Status Register 185"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT186,SEC Source Status Register 186"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT187,SEC Source Status Register 187"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT188,SEC Source Status Register 188"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT189,SEC Source Status Register 189"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT190,SEC Source Status Register 190"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xDF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xDF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT191,SEC Source Status Register 191"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT192,SEC Source Status Register 192"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT193,SEC Source Status Register 193"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT194,SEC Source Status Register 194"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT195,SEC Source Status Register 195"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT196,SEC Source Status Register 196"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT197,SEC Source Status Register 197"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT198,SEC Source Status Register 198"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT199,SEC Source Status Register 199"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT200,SEC Source Status Register 200"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT201,SEC Source Status Register 201"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT202,SEC Source Status Register 202"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT203,SEC Source Status Register 203"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT204,SEC Source Status Register 204"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT205,SEC Source Status Register 205"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT206,SEC Source Status Register 206"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT207,SEC Source Status Register 207"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT208,SEC Source Status Register 208"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT209,SEC Source Status Register 209"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT210,SEC Source Status Register 210"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31089000+0xE98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31089000+0xE98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT211,SEC Source Status Register 211"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GIC (Generic Interrupt Controller)"
|
|
base ad:0x310B4000
|
|
width 22.
|
|
tree "GICCPU1"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "ICCICR,CPU Interface Control Register"
|
|
line.long 0x04 "ICCIPMR,Priority Mask Register"
|
|
line.long 0x08 "ICCBPR,Binary Point Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICCIAR,Interrupt Acknowledge Register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ICCEOIR,End of Interrupt Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ICCRPR,Running Priority Register"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ICCHPIR,Highest Pending Interrupt Register"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ICCABPR,Aliased Binary Point Register"
|
|
else
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "GICCPU1_CTL,GICCPU1 Control N"
|
|
line.long 0x04 "GICCPU1_PRIO_MSK,GICCPU1 Pri Msk C N"
|
|
line.long 0x08 "GICCPU1_BIN_PT,GICCPU1 Bp C N"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "GICCPU1_INT_ACK,GICCPU1 Int Ack N"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GICCPU1_EOI,GICCPU1 Eoi N"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GICCPU1_RUN_PRIO,GICCPU1 Run Priority N"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "GICCPU1_PND_HI,GICCPU1 Hi Pend N"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GICCPU1_BIN_PT_ALIAS,GICCPU1 Alias Nsbp C N"
|
|
endif
|
|
tree.end
|
|
base ad:0x310B2000
|
|
width 23.
|
|
tree "GICDST0"
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "GICDST0_EN,GICDST0 GIC Port 0 Enable"
|
|
bitfld.long 0x00 0. " VALUE ,Global enable" "Disabled,Enabled"
|
|
group.word 0x80++0x1
|
|
line.word 0x00 "GICDST0_SGI_SECURITY,GICDST0 Software Generated Interrupt Security Register"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY0,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY1,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY2,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY3,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY4,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY5,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY6,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "GICDST0_SPI_SECURITY7,GICDST0 Shared Peripheral Interrupt Security Register"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET0,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET1,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET2,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET3,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET4,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET5,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET6,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_SET7,GICDST0 Shared Peripheral Interrupt Enable Set Register"
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR0,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR1,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR2,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR3,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR4,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR5,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR6,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "GICDST0_SPI_EN_CLR7,GICDST0 Shared Peripheral Interrupt Enable Clear Register"
|
|
rgroup.word 0x200++0x1
|
|
line.word 0x00 "GICDST0_SGI_PND_SET,GICDST0 Software Generated Interrupt Pending Set Register"
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET0,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET1,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x20C++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET2,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET3,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x214++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET4,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET5,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x21C++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET6,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_SET7,GICDST0 Shared Peripheral Interrupt Pending Set Register"
|
|
rgroup.word 0x280++0x1
|
|
line.word 0x00 "GICDST0_SGI_PND_CLR,GICDST0 Software Generated Interrupt Pending Clear Register"
|
|
group.long 0x284++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR0,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x288++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR1,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x28C++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR2,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x290++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR3,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x294++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR4,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x298++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR5,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x29C++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR6,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x00 "GICDST0_SPI_PND_CLR7,GICDST0 Shared Peripheral Interrupt Pending Clear Register"
|
|
rgroup.word 0x300++0x1
|
|
line.word 0x00 "GICDST0_SGI_ACTIVE,GICDST0 Software Generated Interrupt Active Register"
|
|
group.long 0x304++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE0,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x308++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE1,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x30C++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE2,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x310++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE3,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x314++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE4,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x318++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE5,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x31C++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE6,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.long 0x320++0x3
|
|
line.long 0x00 "GICDST0_SPI_ACTIVE7,GICDST0 Shared Peripheral Interrupt Active Register"
|
|
group.byte 0x400++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO0,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x401++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO1,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x402++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO2,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x403++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO3,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x404++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO4,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x405++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO5,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x406++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO6,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x407++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO7,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x408++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO8,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x409++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO9,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x40A++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO10,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x40B++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO11,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x40C++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO12,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x40D++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO13,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x40E++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO14,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x40F++0x0
|
|
line.byte 0x00 "GICDST0_SGI_PRIO15,GICDST0 Software Generated Interrupt Priority Register"
|
|
group.byte 0x420++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO0,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x421++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO1,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x422++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO2,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x423++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO3,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x424++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO4,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x425++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO5,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x426++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO6,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x427++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO7,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x428++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO8,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x429++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO9,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x42A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO10,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x42B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO11,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x42C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO12,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x42D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO13,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x42E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO14,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x42F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO15,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x430++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO16,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x431++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO17,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x432++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO18,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x433++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO19,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x434++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO20,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x435++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO21,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x436++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO22,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x437++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO23,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x438++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO24,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x439++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO25,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x43A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO26,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x43B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO27,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x43C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO28,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x43D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO29,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x43E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO30,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x43F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO31,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x440++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO32,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x441++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO33,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x442++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO34,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x443++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO35,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x444++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO36,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x445++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO37,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x446++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO38,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x447++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO39,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x448++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO40,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x449++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO41,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x44A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO42,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x44B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO43,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x44C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO44,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x44D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO45,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x44E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO46,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x44F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO47,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x450++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO48,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x451++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO49,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x452++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO50,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x453++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO51,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x454++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO52,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x455++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO53,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x456++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO54,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x457++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO55,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x458++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO56,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x459++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO57,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x45A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO58,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x45B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO59,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x45C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO60,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x45D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO61,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x45E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO62,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x45F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO63,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x460++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO64,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x461++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO65,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x462++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO66,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x463++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO67,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x464++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO68,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x465++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO69,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x466++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO70,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x467++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO71,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x468++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO72,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x469++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO73,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x46A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO74,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x46B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO75,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x46C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO76,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x46D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO77,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x46E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO78,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x46F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO79,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x470++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO80,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x471++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO81,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x472++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO82,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x473++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO83,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x474++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO84,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x475++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO85,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x476++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO86,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x477++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO87,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x478++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO88,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x479++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO89,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x47A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO90,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x47B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO91,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x47C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO92,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x47D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO93,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x47E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO94,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x47F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO95,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x480++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO96,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x481++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO97,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x482++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO98,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x483++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO99,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x484++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO100,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x485++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO101,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x486++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO102,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x487++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO103,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x488++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO104,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x489++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO105,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x48A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO106,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x48B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO107,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x48C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO108,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x48D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO109,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x48E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO110,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x48F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO111,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x490++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO112,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x491++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO113,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x492++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO114,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x493++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO115,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x494++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO116,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x495++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO117,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x496++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO118,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x497++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO119,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x498++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO120,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x499++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO121,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x49A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO122,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x49B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO123,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x49C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO124,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x49D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO125,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x49E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO126,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x49F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO127,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO128,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO129,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO130,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO131,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO132,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO133,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO134,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO135,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO136,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4A9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO137,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4AA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO138,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4AB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO139,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4AC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO140,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4AD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO141,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4AE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO142,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4AF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO143,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO144,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO145,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO146,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO147,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO148,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO149,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO150,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO151,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO152,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4B9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO153,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4BA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO154,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4BB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO155,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4BC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO156,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4BD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO157,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4BE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO158,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4BF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO159,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO160,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO161,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO162,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO163,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO164,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO165,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO166,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO167,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO168,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4C9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO169,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4CA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO170,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4CB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO171,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4CC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO172,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4CD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO173,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4CE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO174,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4CF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO175,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO176,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO177,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO178,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO179,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO180,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO181,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO182,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO183,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO184,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4D9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO185,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4DA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO186,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4DB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO187,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4DC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO188,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4DD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO189,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4DE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO190,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4DF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO191,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO192,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO193,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO194,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO195,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO196,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO197,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO198,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO199,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO200,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4E9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO201,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4EA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO202,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4EB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO203,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4EC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO204,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4ED++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO205,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4EE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO206,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4EF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO207,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO208,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO209,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO210,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO211,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO212,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO213,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO214,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO215,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO216,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4F9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO217,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4FA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO218,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4FB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO219,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4FC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO220,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4FD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO221,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4FE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO222,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x4FF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO223,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x500++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO224,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x501++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO225,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x502++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO226,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x503++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO227,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x504++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO228,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x505++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO229,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x506++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO230,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x507++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO231,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x508++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO232,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x509++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO233,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x50A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO234,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x50B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO235,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x50C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO236,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x50D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO237,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x50E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO238,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x50F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO239,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x510++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO240,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x511++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO241,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x512++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO242,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x513++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO243,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x514++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO244,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x515++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO245,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x516++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO246,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x517++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO247,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x518++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO248,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x519++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO249,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x51A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO250,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x51B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO251,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x51C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO252,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x51D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO253,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x51E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO254,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x51F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_PRIO255,GICDST0 Shared Peripheral Interrupt Priority Register"
|
|
bitfld.byte 0x00 0. " VALUE ,Priority, byte offset 3 to byte offset 0" "Low,High"
|
|
group.byte 0x820++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT0,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x821++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT1,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x822++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT2,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x823++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT3,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x824++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT4,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x825++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT5,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x826++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT6,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x827++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT7,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x828++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT8,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x829++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT9,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x82A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT10,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x82B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT11,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x82C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT12,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x82D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT13,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x82E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT14,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x82F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT15,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x830++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT16,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x831++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT17,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x832++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT18,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x833++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT19,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x834++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT20,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x835++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT21,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x836++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT22,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x837++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT23,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x838++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT24,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x839++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT25,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x83A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT26,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x83B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT27,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x83C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT28,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x83D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT29,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x83E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT30,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x83F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT31,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x840++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT32,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x841++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT33,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x842++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT34,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x843++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT35,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x844++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT36,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x845++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT37,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x846++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT38,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x847++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT39,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x848++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT40,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x849++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT41,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x84A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT42,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x84B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT43,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x84C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT44,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x84D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT45,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x84E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT46,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x84F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT47,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x850++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT48,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x851++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT49,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x852++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT50,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x853++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT51,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x854++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT52,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x855++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT53,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x856++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT54,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x857++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT55,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x858++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT56,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x859++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT57,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x85A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT58,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x85B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT59,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x85C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT60,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x85D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT61,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x85E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT62,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x85F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT63,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x860++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT64,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x861++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT65,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x862++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT66,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x863++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT67,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x864++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT68,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x865++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT69,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x866++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT70,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x867++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT71,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x868++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT72,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x869++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT73,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x86A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT74,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x86B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT75,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x86C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT76,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x86D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT77,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x86E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT78,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x86F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT79,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x870++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT80,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x871++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT81,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x872++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT82,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x873++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT83,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x874++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT84,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x875++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT85,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x876++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT86,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x877++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT87,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x878++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT88,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x879++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT89,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x87A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT90,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x87B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT91,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x87C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT92,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x87D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT93,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x87E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT94,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x87F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT95,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x880++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT96,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x881++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT97,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x882++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT98,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x883++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT99,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x884++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT100,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x885++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT101,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x886++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT102,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x887++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT103,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x888++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT104,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x889++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT105,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x88A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT106,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x88B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT107,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x88C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT108,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x88D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT109,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x88E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT110,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x88F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT111,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x890++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT112,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x891++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT113,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x892++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT114,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x893++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT115,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x894++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT116,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x895++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT117,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x896++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT118,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x897++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT119,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x898++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT120,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x899++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT121,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x89A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT122,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x89B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT123,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x89C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT124,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x89D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT125,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x89E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT126,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x89F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT127,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT128,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT129,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT130,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT131,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT132,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT133,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT134,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT135,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT136,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8A9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT137,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8AA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT138,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8AB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT139,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8AC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT140,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8AD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT141,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8AE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT142,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8AF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT143,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT144,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT145,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT146,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT147,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT148,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT149,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT150,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT151,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT152,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8B9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT153,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8BA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT154,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8BB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT155,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8BC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT156,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8BD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT157,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8BE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT158,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8BF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT159,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT160,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT161,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT162,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT163,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT164,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT165,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT166,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT167,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT168,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8C9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT169,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8CA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT170,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8CB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT171,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8CC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT172,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8CD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT173,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8CE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT174,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8CF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT175,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT176,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT177,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT178,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT179,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT180,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT181,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT182,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT183,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT184,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8D9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT185,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8DA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT186,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8DB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT187,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8DC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT188,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8DD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT189,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8DE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT190,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8DF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT191,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT192,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT193,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT194,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT195,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT196,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT197,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT198,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT199,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT200,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8E9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT201,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8EA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT202,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8EB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT203,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8EC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT204,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8ED++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT205,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8EE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT206,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8EF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT207,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F0++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT208,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F1++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT209,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F2++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT210,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F3++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT211,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F4++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT212,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F5++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT213,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F6++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT214,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F7++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT215,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F8++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT216,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8F9++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT217,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8FA++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT218,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8FB++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT219,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8FC++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT220,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8FD++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT221,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8FE++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT222,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x8FF++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT223,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x900++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT224,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x901++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT225,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x902++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT226,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x903++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT227,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x904++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT228,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x905++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT229,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x906++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT230,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x907++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT231,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x908++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT232,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x909++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT233,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x90A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT234,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x90B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT235,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x90C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT236,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x90D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT237,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x90E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT238,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x90F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT239,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x910++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT240,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x911++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT241,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x912++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT242,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x913++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT243,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x914++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT244,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x915++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT245,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x916++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT246,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x917++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT247,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x918++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT248,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x919++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT249,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x91A++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT250,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x91B++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT251,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x91C++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT252,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x91D++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT253,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x91E++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT254,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.byte 0x91F++0x0
|
|
line.byte 0x00 "GICDST0_SPI_TRGT255,GICDST0 Shared Peripheral Interrupt Processor Targets Register"
|
|
group.long 0xC08++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG0,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC0C++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG1,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC10++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG2,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC14++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG3,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC18++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG4,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC1C++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG5,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC20++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG6,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC24++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG7,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC28++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG8,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC2C++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG9,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC30++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG10,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC34++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG11,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC38++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG12,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC3C++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG13,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC40++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG14,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
group.long 0xC44++0x3
|
|
line.long 0x00 "GICDST0_SPI_CFG15,GICDST0 Shared Peripheral Interrupt Configuration Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI0,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI1,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI2,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI3,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI4,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI5,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI6,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI7,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI8,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI9,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI10,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI11,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI12,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI13,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI14,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI15,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI16,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI17,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI18,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI19,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI20,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI21,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI22,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI23,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI24,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI25,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI26,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI27,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI28,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI29,GICDST0 Shared Peripheral Interrupt Register"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "GICDST0_SPI30,GICDST0 Shared Peripheral Interrupt Register"
|
|
group.long 0xF00++0x3
|
|
line.long 0x00 "GICDST0_SGI_CTL,GICDST0 Software Generated Interrupt Control Register"
|
|
bitfld.long 0x00 24.--25. " TRGLSTFILT ,Target list filter" "CPUTargetList field,CPU interfaces except,only to the CPU interface,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTRGTLST ,CPU Target list"
|
|
bitfld.long 0x00 15. " SATT ,Security value of the SGI" "0,1"
|
|
bitfld.long 0x00 0.--3. " SGIINTID ,The Interrupt ID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRU (Trigger Routing Unit)"
|
|
base ad:0x3108A000
|
|
width 13.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x30))&0x80000000)==0x80000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x34))&0x80000000)==0x80000000)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x3C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x48))&0x80000000)==0x80000000)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x4C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x50))&0x80000000)==0x80000000)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x54))&0x80000000)==0x80000000)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x58))&0x80000000)==0x80000000)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x5C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x60))&0x80000000)==0x80000000)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x64))&0x80000000)==0x80000000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x68))&0x80000000)==0x80000000)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x6C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x78))&0x80000000)==0x80000000)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x7C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x84))&0x80000000)==0x80000000)
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x88))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x8C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x90))&0x80000000)==0x80000000)
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x94))&0x80000000)==0x80000000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x98))&0x80000000)==0x80000000)
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x9C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xA4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xAC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xB4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xBC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xCC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xD4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xDC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xE4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xF4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xFC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x104))&0x80000000)==0x80000000)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x108))&0x80000000)==0x80000000)
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x10C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x110))&0x80000000)==0x80000000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
endif
|
|
else
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x30))&0x80000000)==0x80000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x30))&0x80000000)==0x80000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x34))&0x80000000)==0x80000000)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x34))&0x80000000)==0x80000000)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x3C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x3C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x48))&0x80000000)==0x80000000)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x48))&0x80000000)==0x80000000)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x4C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x4C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x50))&0x80000000)==0x80000000)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x50))&0x80000000)==0x80000000)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x54))&0x80000000)==0x80000000)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x54))&0x80000000)==0x80000000)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x58))&0x80000000)==0x80000000)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x58))&0x80000000)==0x80000000)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x5C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x5C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x60))&0x80000000)==0x80000000)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x60))&0x80000000)==0x80000000)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x64))&0x80000000)==0x80000000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x64))&0x80000000)==0x80000000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x68))&0x80000000)==0x80000000)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x68))&0x80000000)==0x80000000)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x6C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x6C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x78))&0x80000000)==0x80000000)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x78))&0x80000000)==0x80000000)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x7C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x7C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x84))&0x80000000)==0x80000000)
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x84))&0x80000000)==0x80000000)
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x88))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x88))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x8C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x8C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x90))&0x80000000)==0x80000000)
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x90))&0x80000000)==0x80000000)
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x94))&0x80000000)==0x80000000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x94))&0x80000000)==0x80000000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x98))&0x80000000)==0x80000000)
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x98))&0x80000000)==0x80000000)
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x9C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x9C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xA4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xA4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xAC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xAC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xB4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xB4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xBC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xBC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xC4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xCC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xCC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xD4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xD4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xDC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xDC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xE4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xE4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xF4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xF4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0xFC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0xFC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x104))&0x80000000)==0x80000000)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x104))&0x80000000)==0x80000000)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x108))&0x80000000)==0x80000000)
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x108))&0x80000000)==0x80000000)
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x10C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x10C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x110))&0x80000000)==0x80000000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x110))&0x80000000)==0x80000000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x114))&0x80000000)==0x80000000)
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x114))&0x80000000)==0x80000000)
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x118))&0x80000000)==0x80000000)
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x118))&0x80000000)==0x80000000)
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x11C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x11C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x120))&0x80000000)==0x80000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x120))&0x80000000)==0x80000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x124))&0x80000000)==0x80000000)
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x124))&0x80000000)==0x80000000)
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x128))&0x80000000)==0x80000000)
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x128))&0x80000000)==0x80000000)
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x12C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x12C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x130))&0x80000000)==0x80000000)
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x130))&0x80000000)==0x80000000)
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x134))&0x80000000)==0x80000000)
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x134))&0x80000000)==0x80000000)
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x138))&0x80000000)==0x80000000)
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x138))&0x80000000)==0x80000000)
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x13C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
else
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x13C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
else
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x144))&0x80000000)==0x80000000)
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x144))&0x80000000)==0x80000000)
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x148))&0x80000000)==0x80000000)
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x148))&0x80000000)==0x80000000)
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x14C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x14C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x150))&0x80000000)==0x80000000)
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x150))&0x80000000)==0x80000000)
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x154))&0x80000000)==0x80000000)
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x154))&0x80000000)==0x80000000)
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x158))&0x80000000)==0x80000000)
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x158))&0x80000000)==0x80000000)
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x15C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x15C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x160))&0x80000000)==0x80000000)
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x160))&0x80000000)==0x80000000)
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x164))&0x80000000)==0x80000000)
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x164))&0x80000000)==0x80000000)
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x168))&0x80000000)==0x80000000)
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x168))&0x80000000)==0x80000000)
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x16C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x16C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x170))&0x80000000)==0x80000000)
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
else
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x170))&0x80000000)==0x80000000)
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
else
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x174))&0x80000000)==0x80000000)
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x174))&0x80000000)==0x80000000)
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x178))&0x80000000)==0x80000000)
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
else
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x178))&0x80000000)==0x80000000)
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
else
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x17C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
else
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x17C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
else
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x180))&0x80000000)==0x80000000)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x180))&0x80000000)==0x80000000)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x184))&0x80000000)==0x80000000)
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
else
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x184))&0x80000000)==0x80000000)
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
else
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x188))&0x80000000)==0x80000000)
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x188))&0x80000000)==0x80000000)
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x18C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x18C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x190))&0x80000000)==0x80000000)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x190))&0x80000000)==0x80000000)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x194))&0x80000000)==0x80000000)
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x194))&0x80000000)==0x80000000)
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x198))&0x80000000)==0x80000000)
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x198))&0x80000000)==0x80000000)
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x19C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
else
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x19C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
else
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1A4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
else
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1A4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
else
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
else
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
else
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1AC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1AC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
else
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
else
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1B4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1B4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
else
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
else
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1BC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
else
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1BC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
else
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1C4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1C4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
else
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
else
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1CC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1CC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
else
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
else
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1D4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1D4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
else
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
else
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1DC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
else
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1DC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
else
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1E4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
else
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1E4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
else
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
else
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
else
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x1EC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
else
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x1EC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
else
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108A000+0x7F4))&0x04)==0x04)
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
else
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x7F4))&0x04)==0x04)
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,TRU Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
else
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,TRU Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long 0x7E8++0x07
|
|
line.long 0x00 "TRU_ERRADDR,TRU Error Address Register"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " ADDR ,Error address"
|
|
line.long 0x04 "TRU_STAT,TRU Status Information Register"
|
|
eventfld.long 0x04 1. " ADDRERR ,Address error status" "No error,Error"
|
|
eventfld.long 0x04 0. " LWERR ,Lock write error status" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108A000))&0xFF)!=0xAD)&&(((per.l(ad:0x3108B000+0x7F4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108A000+0x7F4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "L2CTL (L2 Memory Controller)"
|
|
base ad:0x31080000
|
|
width 17.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31080000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "L2CTL0_CTL,L2CTL0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 28. " DISURP ,Disable Urgent Request Priority" "No,Yes"
|
|
bitfld.long 0x00 8. " BK8EDIS ,Bank 8 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 7. " BK7EDIS ,Bank 7 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BK6EDIS ,Bank 6 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " BK5EDIS ,Bank 5 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " BK4EDIS ,Bank 4 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " BK3EDIS ,Bank 3 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BK2EDIS ,Bank 2 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " BK1EDIS ,Bank 1 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BK0EDIS ,Bank 0 ECC Disable" "No,Yes"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "L2CTL0_CTL,L2CTL0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 28. " DISURP ,Disable Urgent Request Priority" "No,Yes"
|
|
bitfld.long 0x00 8. " BK8EDIS ,Bank 8 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 7. " BK7EDIS ,Bank 7 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BK6EDIS ,Bank 6 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " BK5EDIS ,Bank 5 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " BK4EDIS ,Bank 4 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " BK3EDIS ,Bank 3 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BK2EDIS ,Bank 2 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " BK1EDIS ,Bank 1 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BK0EDIS ,Bank 0 ECC Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31080000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "L2CTL0_CTL,L2CTL0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " DISURP ,Disable Urgent Request Priority" "No,Yes"
|
|
bitfld.long 0x00 15. " ECCMAP7 ,ECC Map Bank 7" "Data,ECC"
|
|
bitfld.long 0x00 14. " ECCMAP6 ,ECC Map Bank 6" "Data,ECC"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ECCMAP5 ,ECC Map Bank 5" "Data,ECC"
|
|
bitfld.long 0x00 12. " ECCMAP4 ,ECC Map Bank 4" "Data,ECC"
|
|
bitfld.long 0x00 11. " ECCMAP3 ,ECC Map Bank 3" "Data,ECC"
|
|
bitfld.long 0x00 10. " ECCMAP2 ,ECC Map Bank 2" "Data,ECC"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ECCMAP1 ,ECC Map Bank 1" "Data,ECC"
|
|
bitfld.long 0x00 8. " ECCMAP0 ,ECC Map Bank 0" "Data,ECC"
|
|
bitfld.long 0x00 7. " BK7EDIS ,Bank 7 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " BK6EDIS ,Bank 6 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BK5EDIS ,Bank 5 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " BK4EDIS ,Bank 4 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " BK3EDIS ,Bank 3 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " BK2EDIS ,Bank 2 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BK1EDIS ,Bank 1 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BK0EDIS ,Bank 0 ECC Disable" "No,Yes"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "L2CTL0_CTL,L2CTL0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " DISURP ,Disable Urgent Request Priority" "No,Yes"
|
|
bitfld.long 0x00 15. " ECCMAP7 ,ECC Map Bank 7" "Data,ECC"
|
|
bitfld.long 0x00 14. " ECCMAP6 ,ECC Map Bank 6" "Data,ECC"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ECCMAP5 ,ECC Map Bank 5" "Data,ECC"
|
|
bitfld.long 0x00 12. " ECCMAP4 ,ECC Map Bank 4" "Data,ECC"
|
|
bitfld.long 0x00 11. " ECCMAP3 ,ECC Map Bank 3" "Data,ECC"
|
|
bitfld.long 0x00 10. " ECCMAP2 ,ECC Map Bank 2" "Data,ECC"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ECCMAP1 ,ECC Map Bank 1" "Data,ECC"
|
|
bitfld.long 0x00 8. " ECCMAP0 ,ECC Map Bank 0" "Data,ECC"
|
|
bitfld.long 0x00 7. " BK7EDIS ,Bank 7 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " BK6EDIS ,Bank 6 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BK5EDIS ,Bank 5 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " BK4EDIS ,Bank 4 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " BK3EDIS ,Bank 3 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " BK2EDIS ,Bank 2 ECC Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BK1EDIS ,Bank 1 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BK0EDIS ,Bank 0 ECC Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "L2CTL0_STAT,L2CTL0 Status Register"
|
|
eventfld.long 0x00 16. " ECCERR8 ,ECC Error Bank 8 (ROM)" "No status,Error"
|
|
eventfld.long 0x00 15. " ECCERR7 ,ECC Error Bank 7" "No status,Error"
|
|
eventfld.long 0x00 14. " ECCERR6 ,ECC Error Bank 6" "No status,Error"
|
|
eventfld.long 0x00 13. " ECCERR5 ,ECC Error Bank 5" "No status,Error"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ECCERR4 ,ECC Error Bank 4" "No status,Error"
|
|
eventfld.long 0x00 11. " ECCERR3 ,ECC Error Bank 3" "No status,Error"
|
|
eventfld.long 0x00 10. " ECCERR2 ,ECC Error Bank 2" "No status,Error"
|
|
eventfld.long 0x00 9. " ECCERR1 ,ECC Error Bank 1" "No status,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ECCERR0 ,ECC Error Bank 0" "No status,Error"
|
|
eventfld.long 0x00 5. " INITDN ,Initialization Status" "Not Complete,Completed"
|
|
eventfld.long 0x00 4. " SCRBDN ,Scrub Status" "Not Complete,Completed"
|
|
eventfld.long 0x00 1. " ERR1 ,Error Port 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERR0 ,Error Port 0" "No error,Error"
|
|
line.long 0x04 "L2CTL0_RPCR,L2CTL0 Read Priority Count Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RPC1 ,Read Priority Count 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RPC0 ,Read Priority Count 0"
|
|
line.long 0x08 "L2CTL0_WPCR,L2CTL0 Write Priority Count Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " WPC1 ,Write Priority Count 1"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WPC0 ,Write Priority Count 0"
|
|
else
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "L2CTL0_STAT,L2CTL0 Status Register"
|
|
eventfld.long 0x00 15. " ECCERR7 ,ECC Error Bank 7" "No error,Error"
|
|
eventfld.long 0x00 14. " ECCERR6 ,ECC Error Bank 6" "No error,Error"
|
|
eventfld.long 0x00 13. " ECCERR5 ,ECC Error Bank 5" "No error,Error"
|
|
eventfld.long 0x00 12. " ECCERR4 ,ECC Error Bank 4" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ECCERR3 ,ECC Error Bank 3" "No error,Error"
|
|
eventfld.long 0x00 10. " ECCERR2 ,ECC Error Bank 2" "No error,Error"
|
|
eventfld.long 0x00 9. " ECCERR1 ,ECC Error Bank 1" "No error,Error"
|
|
eventfld.long 0x00 8. " ECCERR0 ,ECC Error Bank 0" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " RFRS ,Refresh Register Status" "Not in progress,In progress"
|
|
eventfld.long 0x00 1. " ERR1 ,Error Port 1" "No error,Error"
|
|
eventfld.long 0x00 0. " ERR0 ,Error Port 0" "No error,Error"
|
|
line.long 0x04 "L2CTL0_RPCR,L2CTL0 Read Priority Count Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RPC1 ,Read Priority Count 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RPC0 ,Read Priority Count 0"
|
|
line.long 0x08 "L2CTL0_WPCR,L2CTL0 Write Priority Count Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " WPC1 ,Write Priority Count 1"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WPC0 ,Write Priority Count 0"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "L2CTL0_INIT,L2CTL0 Initialization Register"
|
|
bitfld.long 0x00 7. " BK7 ,Initialize Bank 7" "No action,Initialized"
|
|
bitfld.long 0x00 6. " BK6 ,Initialize Bank 6" "No action,Initialized"
|
|
bitfld.long 0x00 5. " BK5 ,Initialize Bank 5" "No action,Initialized"
|
|
bitfld.long 0x00 4. " BK4 ,Initialize Bank 4" "No action,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BK3 ,Initialize Bank 3" "No action,Initialized"
|
|
bitfld.long 0x00 2. " BK2 ,Initialize Bank 2" "No action,Initialized"
|
|
bitfld.long 0x00 1. " BK1 ,Initialize Bank 1" "No action,Initialized"
|
|
bitfld.long 0x00 0. " BK0 ,Initialize Bank 0" "No action,Initialized"
|
|
else
|
|
if (((per.l(ad:0x31080000+0x10))&0x10)==0x10)
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "L2CTL0_RFA,L2CTL0 Refresh Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ADDRHI ,Address High"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRLO ,Address Low"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "L2CTL0_RFA,L2CTL0 Refresh Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ADDRHI ,Address High"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRLO ,Address Low"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "L2CTL0_ISTAT,L2CTL0 Initialization Status Register"
|
|
bitfld.long 0x00 7. " BK7 ,Bank 7 Initialization Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BK6 ,Bank 6 Initialization Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BK5 ,Bank 5 Initialization Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BK4 ,Bank 4 Initialization Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BK3 ,Bank 3 Initialization Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BK2 ,Bank 2 Initialization Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BK1 ,Bank 1 Initialization Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BK0 ,Bank 0 Initialization Status" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x40++0x1F
|
|
line.long 0x00 "L2CTL0_ERRADDR0,L2CTL0 ECC Error Address 0 Register"
|
|
line.long 0x04 "L2CTL0_ERRADDR1,L2CTL0 ECC Error Address 1 Register"
|
|
line.long 0x08 "L2CTL0_ERRADDR2,L2CTL0 ECC Error Address 2 Register"
|
|
line.long 0x0C "L2CTL0_ERRADDR3,L2CTL0 ECC Error Address 3 Register"
|
|
line.long 0x10 "L2CTL0_ERRADDR4,L2CTL0 ECC Error Address 4 Register"
|
|
line.long 0x14 "L2CTL0_ERRADDR5,L2CTL0 ECC Error Address 5 Register"
|
|
line.long 0x18 "L2CTL0_ERRADDR6,L2CTL0 ECC Error Address 6 Register"
|
|
line.long 0x1C "L2CTL0_ERRADDR7,L2CTL0 ECC Error Address 7 Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "L2CTL0_ERRADDR8,L2CTL0 ECC Error Address 8 Register"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x00 "L2CTL0_ET0,L2CTL0 Error Type 0 Register"
|
|
hexmask.long.word 0x00 8.--19. 1. " ID ,Error ID"
|
|
bitfld.long 0x00 4. " RDWR ,Read/Write Error" "Read error,Write error"
|
|
bitfld.long 0x00 3. " ECCERR ,ECC Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCERR ,Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROMERR ,ROM error" "No error,Error"
|
|
line.long 0x04 "L2CTL0_EADDR0,L2CTL0 Error Type 0 Address Register"
|
|
line.long 0x08 "L2CTL0_ET1,L2CTL0 Error Type 1 Register"
|
|
hexmask.long.word 0x08 8.--20. 1. " ID ,Error ID"
|
|
bitfld.long 0x08 4. " RDWR ,Read/Write Error" "Read error,Write error"
|
|
bitfld.long 0x08 3. " ECCERR ,ECC Error" "No error,Error"
|
|
bitfld.long 0x08 2. " ACCERR ,Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ROMERR ,ROM error" "No error,Error"
|
|
line.long 0x0C "L2CTL0_EADDR1,L2CTL0 Error Type 1 Address Register"
|
|
else
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x00 "L2CTL0_ET0,L2CTL0 Error Type 0 Register"
|
|
hexmask.long.word 0x00 8.--20. 1. " ID ,Error ID"
|
|
bitfld.long 0x00 4. " RDWR ,Read/Write Error" "Read error,Write error"
|
|
bitfld.long 0x00 3. " ECCERR ,ECC Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCERR ,Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RSVERR ,Reserved Error" "No error,Error"
|
|
bitfld.long 0x00 0. " ROMERR ,ROM Error" "No error,Error"
|
|
line.long 0x04 "L2CTL0_EADDR0,L2CTL0 Error Type 0 Address Register"
|
|
line.long 0x08 "L2CTL0_ET1,L2CTL0 Error Type 1 Register"
|
|
hexmask.long.word 0x08 8.--20. 1. " ID ,Error ID"
|
|
bitfld.long 0x08 4. " RDWR ,Read/Write Error" "Read error,Write error"
|
|
bitfld.long 0x08 3. " ECCERR ,ECC Error" "No error,Error"
|
|
bitfld.long 0x08 2. " ACCERR ,Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RSVERR ,Reserved Error" "No error,Error"
|
|
bitfld.long 0x08 0. " ROMERR ,ROM Error" "No error,Error"
|
|
line.long 0x0C "L2CTL0_EADDR1,L2CTL0 Error Type 1 Address Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31080000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "L2CTL0_SCTL,L2CTL0 Scrub Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " SEN ,Scrub Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " SRT ,Scrub Rate"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "L2CTL0_SCTL,L2CTL0 Scrub Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " SEN ,Scrub Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " SRT ,Scrub Rate"
|
|
endif
|
|
group.long 0xF0++0x07
|
|
line.long 0x00 "L2CTL0_SADR,L2CTL0 Scrub Start Address Register"
|
|
line.long 0x04 "L2CTL0_SCNT,L2CTL0 Scrub Count Register"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " VALUE ,Scrub Count"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "L2CTL0_REVID,L2CTL0 Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMC (Dynamic Memory Controller)"
|
|
base ad:0x31070004
|
|
width 15.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DMC0_CTL,DMC0 Control Register"
|
|
bitfld.long 0x00 25. " ZQCL ,ZQ Calibration Long" "No effect,Trigger"
|
|
bitfld.long 0x00 24. " ZQCS ,ZQ Calibration Short" "No effect,trigger"
|
|
bitfld.long 0x00 13. " DLLCAL ,DLL Calibration Start" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PPREF ,Postpone Refresh" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " RDTOWR ,Read-to-Write Cycle" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 8. " ADDRMODE ,Addressing (Page/Bank) Mode" "Page,Bank"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RESET ,Reset SDRAM" "No effect,Reset"
|
|
bitfld.long 0x00 6. " PREC ,Precharge" "No effect,Enable"
|
|
bitfld.long 0x00 5. " DPDREQ ,Deep Power Down Request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDREQ ,Power Down Request" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SRREQ ,Self Refresh Request" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INIT ,Initialize DRAM Start" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPDDR ,Low Power DDR Mode" "DDR2,LPDDR"
|
|
bitfld.long 0x00 0. " DDR3EN ,DDR3 Mode" "DDR2,DDR3"
|
|
if (((per.l(ad:0x31070004))&0x2)==0x2)
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "DMC0_STAT,DMC0 Status Register"
|
|
bitfld.long 0x00 25. " ZQCLDONE ,ZQ Calibration Long Done" "Not done,Done"
|
|
bitfld.long 0x00 24. " ZQCSDONE ,ZQ Calibration Short Done" "Not done,Done"
|
|
bitfld.long 0x00 20.--23. " PHYRDPHASE ,PHY Read Phase" ",,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PENDREF ,Pending Refresh" "0,1,2,3,?..."
|
|
bitfld.long 0x00 13. " DLLCALDONE ,DLL Calibration Done" "Not done,Done"
|
|
bitfld.long 0x00 7. " RESETDONE ,Reset Done" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DPDACK ,Deep Power Down Acknowledge" "Not active,Active"
|
|
bitfld.long 0x00 4. " PDACK ,Power Down Acknowledge" "Not active,Active"
|
|
bitfld.long 0x00 3. " SRACK ,Self Refresh Acknowledge" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INITDONE ,Initialization Done" "Not done,Done"
|
|
bitfld.long 0x00 0. " IDLE ,Idle State" "Busy,Idle"
|
|
else
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "DMC0_STAT,DMC0 Status Register"
|
|
bitfld.long 0x00 25. " ZQCLDONE ,ZQ Calibration Long Done" "Not done,Done"
|
|
bitfld.long 0x00 24. " ZQCSDONE ,ZQ Calibration Short Done" "Not done,Done"
|
|
bitfld.long 0x00 20.--23. " PHYRDPHASE ,PHY Read Phase" ",,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PENDREF ,Pending Refresh" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 13. " DLLCALDONE ,DLL Calibration Done" "Not done,Done"
|
|
bitfld.long 0x00 7. " RESETDONE ,Reset Done" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDACK ,Power Down Acknowledge" "Not active,Active"
|
|
bitfld.long 0x00 3. " SRACK ,Self Refresh Acknowledge" "Not active,Active"
|
|
bitfld.long 0x00 2. " INITDONE ,Initialization Done" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDLE ,Idle State" "Busy,Idle"
|
|
endif
|
|
group.long 0x8++0x13
|
|
line.long 0x00 "DMC0_EFFCTL,DMC0 Efficiency Control Register"
|
|
bitfld.long 0x00 20.--23. " IDLECYC ,Idle Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " NUMREF ,Number of Refresh Commands" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 15. " PRECBANK7 , Precharge Bank 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PRECBANK6 ,Precharge Bank 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PRECBANK5 ,Precharge Bank 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRECBANK4 ,Precharge Bank 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRECBANK3 ,Precharge Bank 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PRECBANK2 ,Precharge Bank 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PRECBANK1 ,Precharge Bank 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PRECBANK0 ,Precharge Bank 0" "Disabled,Enabled"
|
|
line.long 0x04 "DMC0_PRIO,DMC0 Priority ID Register 1"
|
|
line.long 0x08 "DMC0_PRIOMSK,DMC0 Priority ID Mask Register 1"
|
|
line.long 0x0C "DMC0_PRIO2,DMC0 Priority ID Register 2"
|
|
line.long 0x10 "DMC0_PRIOMSK2,DMC0 Priority ID Mask Register 2"
|
|
textline " "
|
|
group.long 0x3C++0xF
|
|
line.long 0x00 "DMC0_CFG,DMC0 Configuration Register"
|
|
bitfld.long 0x00 12.--15. " EXTBANK ,External Banks" "1,?..."
|
|
bitfld.long 0x00 8.--11. " SDRSIZE ,SDRAM Size" "64Mb,128Mb,256Mb,512Mb,1Gb,2Gb,4Gb,8Gb,?..."
|
|
bitfld.long 0x00 4.--7. " SDRWID ,SDRAM Width" ",,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IFWID ,Interface Width" ",,16-bit,?..."
|
|
line.long 0x04 "DMC0_TR0,DMC0 Timing 0 Register"
|
|
bitfld.long 0x04 28.--31. " TMRD ,Timing Mode Register Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--25. " TRC ,Timing Row Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 12.--16. " TRAS ,Timing Row Active Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " TRP ,Timing RAS Precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " TWTR ,Timing Write to Read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " TRCD ,Timing RAS to CAS Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "DMC0_TR1,DMC0 Timing 1 Register"
|
|
bitfld.long 0x08 28.--30. " TRRD ,Timing Read-Read Delay" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TRFC ,Timing Refresh-to-Command"
|
|
hexmask.long.word 0x08 0.--13. 1. " TREF ,Timing Refresh Interval"
|
|
line.long 0x0C "DMC0_TR2,DMC0 Timing 2 Register"
|
|
bitfld.long 0x0C 20.--23. " TCKE ,Timing Clock Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. " TXP ,Timing Exit Power Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--15. " TWR ,Timing Write Recovery" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--11. " TRTP ,Timing Read-to-Precharge" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--4. " TFAW ,Timing Four-Activated-Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.l(ad:0x31070004))&0x2)==0x2)
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "DMC0_MSK,DMC0 Mask (Mode Register Shadow) Register"
|
|
bitfld.long 0x00 11. " EMR3 ,Shadow EMR3 Unmask" "Masked,?..."
|
|
bitfld.long 0x00 10. " EMR2 ,Shadow EMR2 Unmask" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " EMR1 ,Shadow EMR1 Unmask" "Masked,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR ,Shadow MR Unmask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "DMC0_MSK,DMC0 Mask (Mode Register Shadow) Register"
|
|
bitfld.long 0x00 11. " EMR3 ,Shadow EMR3 Unmask" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " EMR2 ,Shadow EMR2 Unmask" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " EMR1 ,Shadow EMR1 Unmask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR ,Shadow MR Unmask" "Masked,Unmasked"
|
|
endif
|
|
if (((per.l(ad:0x31070004))&0x2)==0x2)&&(((per.l(ad:0x31070004))&0x1)==0x0)
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "DMC0_MR,DMC0 Shadow MR Register (LPDDR)"
|
|
bitfld.long 0x00 4.--6. " CL ,CAS Latency" ",,,3,,,,?..."
|
|
bitfld.long 0x00 0.--1. " BLEN ,Burst Length" ",,4-bit,8-bit"
|
|
elif (((per.l(ad:0x31070004))&0x2)==0x0)&&(((per.l(ad:0x31070004))&0x1)==0x0)
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "DMC0_MR,DMC0 Shadow MR Register (DDR2)"
|
|
bitfld.long 0x00 12. " PD ,Active Power Down Mode" "Fast exit,Slow exit"
|
|
bitfld.long 0x00 9.--11. " WRRECOV ,Write Recovery" ",2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 8. " DLLRST ,DLL Reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CL ,CAS Latency" ",,,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " BLEN ,Burst Length" ",,4-bit,8-bit"
|
|
else
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "DMC0_MR,Shadow MR0 Register (DDR3)"
|
|
bitfld.long 0x00 12. " PD ,Active Power Down Mode" "Fast exit,Slow exit"
|
|
bitfld.long 0x00 9.--11. " WRRECOV ,Write Recovery" "16,5,6,7,8,10,12,14"
|
|
bitfld.long 0x00 8. " DLLRST ,DLL Reset" "Normal,Reset"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 2. 4.--6. " CL ,CAS Latency" ",12,5,13,6,14,7,,8,,9,,10,,11,?..."
|
|
else
|
|
bitfld.long 0x00 2. 4.--6. " CL ,CAS Latency" ",12,5,13,6,14,7,,8,,9,,10,,11,15"
|
|
endif
|
|
bitfld.long 0x00 0.--1. " BLEN ,Burst Length" "8-bit,,,?..."
|
|
endif
|
|
if (((per.l(ad:0x31070004))&0x2)==0x0)&&(((per.l(ad:0x31070004))&0x1)==0x0)
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "DMC0_EMR1,DMC0 Shadow EMR1 Register"
|
|
bitfld.long 0x00 12. " QOFF ,Output Buffer Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DQS ,LDQS/UDQS Enable" "Enabled,Disabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 3.--5. " AL ,Additive Latency" "0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " AL ,Additive Latency" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. 6. " RTT ,Termination Resistance" "No ODT,75 Ohm,150 Ohm,50 Ohm"
|
|
bitfld.long 0x00 1. " DIC ,Output Driver Impedance Control" "Full,Reduced"
|
|
bitfld.long 0x00 0. " DLLEN ,DLL Enable" "Enabled,Disabled"
|
|
elif (((per.l(ad:0x31070004))&0x2)==0x2)&&(((per.l(ad:0x31070004))&0x1)==0x0)
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x00 "DMC0_EMR1,DMC0 Shadow EMR1 Register"
|
|
else
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "DMC0_MR1,DMC0 Shadow MR1 Register (DDR3)"
|
|
bitfld.long 0x00 12. " QOFF ,Output Buffer Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " TDQS ,Termination Data Strobe" "Enabled,Disabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 2. 6. 9. " RTT ,Rtt_nom" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..."
|
|
else
|
|
bitfld.long 0x00 2. 6. 9. " RTT ,Rtt_nom" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12*4,RZQ/8*4,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. 5. " DIC ,Output Driver Impedance Control" "RZQ/6,RZQ/7,?..."
|
|
bitfld.long 0x00 3.--4. " AL ,Additive Latency" "Disabled,CL-1,CL-2,?..."
|
|
bitfld.long 0x00 0. " DLLEN ,DLL Enable" "Enabled,Disabled"
|
|
endif
|
|
if (((per.l(ad:0x31070004))&0x2)==0x2)&&(((per.l(ad:0x31070004))&0x1)==0x0)
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "DMC0_EMR2,Shadow EMR Register (LPDDR)"
|
|
bitfld.long 0x00 5.--6. " DS ,Drive Strength" "Full,1/2,3/4,1/4"
|
|
bitfld.long 0x00 3.--4. " TCSR ,Temperature Compensated Self Refresh" "70 deg C,45 deg C,15 deg C,85 deg C"
|
|
bitfld.long 0x00 0.--2. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,,,1/8,1/16,?..."
|
|
elif (((per.l(ad:0x31070004))&0x2)==0x0)&&(((per.l(ad:0x31070004))&0x1)==0x0)
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "DMC0_EMR2,DMC0 Shadow EMR2 Register (DDR2)"
|
|
bitfld.long 0x00 7. " SRF ,High Temperature Self Refresh" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
|
|
else
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "DMC0_MR2,DMC0 Shadow MR2 Register (DDR3)"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 9.--10. " RTTWR ,Dynamic ODT Write" "Off,RZQ/4,RZQ/2,?..."
|
|
endif
|
|
bitfld.long 0x00 7. " SRT ,Self Refresh Temperature Range" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASR ,Auto Self Refresh" "Manual,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CWL ,CAS Write Latency" "5,6,7,8,9,10,11,12"
|
|
bitfld.long 0x00 0.--2. " PASR ,Partial Array Self refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
|
|
endif
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "DMC0_DLLCTL,DMC0 DLL Control Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 8.--11. " DATACYC ,Data Cycles" ",,,,,,,,,9,?..."
|
|
else
|
|
bitfld.long 0x00 8.--11. " DATACYC ,Data Cycles" ",,2,3,4,5,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLCALRDCNT ,DLL Calibration RD Count"
|
|
textline " "
|
|
width 26.
|
|
group.long 0x8C++0xB
|
|
line.long 0x00 "DMC0_DT_CALIB_ADDR,DMC0 Data Calibration Address Register"
|
|
line.long 0x04 "DMC0_DT_DATA_CALIB_DATA0,DMC0 Data Calibration Data 0 Register"
|
|
line.long 0x08 "DMC0_DT_DATA_CALIB_DATA1,DMC0 Data Calibration Data 1 Register"
|
|
group.long 0xFC++0xF
|
|
line.long 0x00 "DMC0_RDDATABUFID1,DMC0 DMC Read Data Buffer ID Register 1"
|
|
line.long 0x04 "DMC0_RDDATABUFMSK1,DMC0 DMC Read Data Buffer Mask Register 1"
|
|
line.long 0x08 "DMC0_RDDATABUFID2,DMC0 DMC Read Data Buffer ID Register 2"
|
|
line.long 0x0C "DMC0_RDDATABUFMSK2,DMC0 DMC Read Data Buffer Mask Register 2"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
wgroup.long 0x1BC++0x7
|
|
line.long 0x00 "DMC0_CPHY_CTL,Controller to PHY Interface Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
tree "DMCPHY"
|
|
group.long 0xFFC++0x3
|
|
line.long 0x00 "DMC0_PHY_CTL0,DMC0 PHY Control 0 Register"
|
|
bitfld.long 0x00 12. " RESETDAT ,Reset Data capture logic" "No action,Reset"
|
|
bitfld.long 0x00 11. " RESETDLL ,Reset DLL" "No action,Reset"
|
|
hgroup.long 0x1000++0x3
|
|
hide.long 0x00 "DMC0_PHY_CTL1,DMC0 PHY Control 1 Register"
|
|
group.long 0x1004++0x7
|
|
line.long 0x00 "DMC0_PHY_CTL2,DMC0 PHY Control 2 Register"
|
|
line.long 0x04 "DMC0_PHY_CTL3,DMC0 PHY Control 3 Register"
|
|
group.long 0x100C++0x3
|
|
line.long 0x00 "DMC0_PHY_CTL4,DMC0 PHY Control 4 Register"
|
|
bitfld.long 0x00 2. " CLKDIS ,Clock Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " DDRMODE ,DDR Mode Select" "DDR3,DDR2,,LPDDR"
|
|
group.long 0x1030++0x3
|
|
line.long 0x00 "DMC0_CAL_PADCTL0,DMC0 Calibration PAD Control 0 Register"
|
|
bitfld.long 0x00 31. " RTTCALEN ,RTT Calibration Enable" ",Enabled"
|
|
bitfld.long 0x00 30. " PDCALEN ,PULLDOWN Calibration Enable" ",Enabled"
|
|
bitfld.long 0x00 29. " PUCALEN ,PULLUP Calibration Enable" ",Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CALSTRT ,Start New Calibration" "Not started,Started"
|
|
group.long 0x1038++0x3
|
|
line.long 0x00 "DMC0_CAL_PADCTL2,DMC0 Calibration PAD Control 2 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IMPRTT ,Impedance RTT Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " IMPWRDQ ,Impedance for DQ"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IMPWRAD ,Impedance for ADDR_CMD PADS"
|
|
tree.end
|
|
else
|
|
group.long 0xFFC++0x7
|
|
line.long 0x00 "DMC0_PHY_CTL0,DMC0 PHY Control 0 Register"
|
|
bitfld.long 0x00 12. " RESETDAT ,Reset Data capture logic" "No action,Reset"
|
|
bitfld.long 0x00 11. " RESETDLL ,Reset DLL" "No action,Reset"
|
|
line.long 0x04 "DMC0_PHY_CTL1,DMC0 PHY Control 1 Register"
|
|
bitfld.long 0x04 19. " BYPODTEN ,Bypass ODTEN for DQ and DQS" "75 Ohms,150 Ohms"
|
|
group.long 0x100C++0x3
|
|
line.long 0x00 "DMC0_PHY_CTL4,DMC0 PHY Control 4 Register"
|
|
bitfld.long 0x00 2. " CLKDIS ,Clock Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " DDRMODE ,DDR Mode Select" "DDR3,DDR2,INVALID,LPDDR"
|
|
group.long 0x1030++0x3
|
|
line.long 0x00 "DMC0_CAL_PADCTL0,DMC0 Calibration PAD Control 0 Register"
|
|
bitfld.long 0x00 31. " RTTCALEN ,RTT Calibration Enable" ",Enabled"
|
|
bitfld.long 0x00 30. " PDCALEN ,PULLDOWN Calibration Enable" ",Enabled"
|
|
bitfld.long 0x00 29. " PUCALEN ,PULLUP Calibration Enable" ",Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CALSTRT ,Start New Calibration" "Not started,Started"
|
|
group.long 0x1038++0x3
|
|
line.long 0x00 "DMC0_CAL_PADCTL2,DMC0 Calibration PAD Control 2 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IMPRTT ,Impedance RTT Value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " IMPWRDQ ,Impedance for DQ"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IMPWRAD ,Impedance for ADDR_CMD PADS"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMC (Static Memory Controller)"
|
|
base ad:0x3100600C
|
|
width 13.
|
|
group.long 0x0++0x0B "BANK 0"
|
|
line.long 0x00 "SMC_B0CTL,SMC Bank 0 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS0,AMS0 ORed with ARE,AMS0 ORed with AOE,AMS0 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B0TIM,SMC Bank 0 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B0ETIM,SMC Bank 0 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
group.long 0x10++0x0B "BANK 1"
|
|
line.long 0x00 "SMC_B1CTL,SMC Bank 1 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS1,AMS1 ORed with ARE,AMS1 ORed with AOE,AMS1 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B1TIM,SMC Bank 1 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B1ETIM,SMC Bank 1 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
group.long 0x20++0x0B "BANK 2"
|
|
line.long 0x00 "SMC_B2CTL,SMC Bank 2 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS2,AMS2 ORed with ARE,AMS2 ORed with AOE,AMS2 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B2TIM,SMC Bank 2 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B2ETIM,SMC Bank 2 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
group.long 0x30++0x0B "BANK 3"
|
|
line.long 0x00 "SMC_B3CTL,SMC Bank 3 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS3,AMS3 ORed with ARE,AMS3 ORed with AOE,AMS3 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B3TIM,SMC Bank 3 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B3ETIM,SMC Bank 3 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "OTPC (OTP Controller)"
|
|
base ad:0x31011004
|
|
width 17.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "OTPC_STAT,OTPC OTP Status Register"
|
|
bitfld.long 0x00 13.--14. " ADDRERR ,OTP Address Error" "No error,Out of range,8-bit,Protected"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "OTPC_SECU_STATE,OTPC OTP Security State Register"
|
|
bitfld.long 0x00 0.--1. " PARTLOCK ,Part Locked" "OPEN,Locked,Unlocked,?..."
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "OTPC_STAT,OTPC OTP Status Register"
|
|
rbitfld.long 0x00 27.--28. " PMCMODE , PMC Mode" "BOOT,PROGRAM,?..."
|
|
hexmask.long.word 0x00 15.--26. 1. " BOOTCNT ,BOOT Counter Value"
|
|
rbitfld.long 0x00 13.--14. " ADDRERR ,OTP Address Error" "No error,Out of range,8-bit,Protected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " DEDUP16 ,Dual Error Detection for Upper 16-bit Data" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7.--11. " PROTUP16 ,Protect Upper 16-bit Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 6. " DEDLO16 ,Dual Error Detection for Lower 16-bit Data" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 1.--5. " PROTLO16 ,Protect Lower 16-bit Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0. " FLG ,FLAG Status" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "OTPC_SECU_STATE,OTPC OTP Security State Register"
|
|
bitfld.long 0x00 0.--1. " PARTLOCK ,Part Locked" "OPEN,Locked,?..."
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree.open "SMPU (System Memory Protection Unit)"
|
|
tree "SMC"
|
|
base ad:0x31007000
|
|
width 18.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31007000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "SMPU_STAT,SMPU SMPU Status Register"
|
|
eventfld.long 0x00 17. " LWERR ,Lock Write Error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADRERR ,Address Error" "No error,Error"
|
|
eventfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " BERR ,Bus Error" "No error,Error"
|
|
eventfld.long 0x00 1. " IOVR ,Interrupt Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " IRQ ,Interrupt Request" "No interrupt,Interrupt"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
else
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
endif
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "SMPU_IDTLS,SMPU Interrupt Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x00 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x00 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x00 0. " SECURE ,Secure Status" "Non-secure,Secure"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "SMPU_BADDR,SMPU Bus Error Address Register"
|
|
line.long 0x04 "SMPU_BDTLS,SMPU Bus Error Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x04 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x04 0. " SECURE ,Secure Status Register" "Non-secure,Secure"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000))&0x10)==0x10)
|
|
rgroup.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "SMPU_REVID,SMPU Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "SMPU_REVID,SMPU SMPU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental Version ID"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31007000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31007000+0x800))&0x8)==0x8)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long 0x820++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL0,SMPU Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x824++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL1,SMPU Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x828++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL2,SMPU Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x82C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL3,SMPU Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x830++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL4,SMPU Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x834++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL5,SMPU Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x838++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL6,SMPU Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x83C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL7,SMPU Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "Core_L2"
|
|
base ad:0x31083000
|
|
width 18.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31083000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "SMPU_STAT,SMPU SMPU Status Register"
|
|
eventfld.long 0x00 17. " LWERR ,Lock Write Error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADRERR ,Address Error" "No error,Error"
|
|
eventfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " BERR ,Bus Error" "No error,Error"
|
|
eventfld.long 0x00 1. " IOVR ,Interrupt Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " IRQ ,Interrupt Request" "No interrupt,Interrupt"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
else
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
endif
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "SMPU_IDTLS,SMPU Interrupt Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x00 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x00 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x00 0. " SECURE ,Secure Status" "Non-secure,Secure"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "SMPU_BADDR,SMPU Bus Error Address Register"
|
|
line.long 0x04 "SMPU_BDTLS,SMPU Bus Error Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x04 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x04 0. " SECURE ,Secure Status Register" "Non-secure,Secure"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000))&0x10)==0x10)
|
|
rgroup.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
rgroup.long 0x1A0++0x7
|
|
line.long 0x00 "SMPU_EXACADD0,SMPU Exclusive Access ID0 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT0,SMPU Exclusive 0 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
rgroup.long 0x1A4++0x7
|
|
line.long 0x00 "SMPU_EXACADD1,SMPU Exclusive Access ID1 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT1,SMPU Exclusive 1 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
rgroup.long 0x1A8++0x7
|
|
line.long 0x00 "SMPU_EXACADD2,SMPU Exclusive Access ID2 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT2,SMPU Exclusive 2 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
rgroup.long 0x1AC++0x7
|
|
line.long 0x00 "SMPU_EXACADD3,SMPU Exclusive Access ID3 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT3,SMPU Exclusive 3 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "SMPU_REVID,SMPU Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "SMPU_REVID,SMPU SMPU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental Version ID"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31083000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31083000+0x800))&0x8)==0x8)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long 0x820++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL0,SMPU Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x824++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL1,SMPU Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x828++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL2,SMPU Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x82C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL3,SMPU Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x830++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL4,SMPU Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x834++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL5,SMPU Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x838++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL6,SMPU Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x83C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL7,SMPU Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "DMA_L2"
|
|
base ad:0x31084000
|
|
width 18.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31084000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "SMPU_STAT,SMPU SMPU Status Register"
|
|
eventfld.long 0x00 17. " LWERR ,Lock Write Error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADRERR ,Address Error" "No error,Error"
|
|
eventfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " BERR ,Bus Error" "No error,Error"
|
|
eventfld.long 0x00 1. " IOVR ,Interrupt Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " IRQ ,Interrupt Request" "No interrupt,Interrupt"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
else
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
endif
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "SMPU_IDTLS,SMPU Interrupt Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x00 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x00 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x00 0. " SECURE ,Secure Status" "Non-secure,Secure"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "SMPU_BADDR,SMPU Bus Error Address Register"
|
|
line.long 0x04 "SMPU_BDTLS,SMPU Bus Error Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x04 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x04 0. " SECURE ,Secure Status Register" "Non-secure,Secure"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000))&0x10)==0x10)
|
|
rgroup.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "SMPU_REVID,SMPU Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "SMPU_REVID,SMPU SMPU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental Version ID"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31084000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x31084000+0x800))&0x8)==0x8)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long 0x820++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL0,SMPU Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x824++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL1,SMPU Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x828++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL2,SMPU Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x82C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL3,SMPU Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x830++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL4,SMPU Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x834++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL5,SMPU Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x838++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL6,SMPU Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x83C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL7,SMPU Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "DMC0"
|
|
base ad:0x310A0000
|
|
width 18.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SMPU_CTL,SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 4. " RLOCK ,Registers Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310A0000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "SMPU_CTL,SMPU SMPU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "Decode error,Save error"
|
|
bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "SMPU_STAT,SMPU SMPU Status Register"
|
|
eventfld.long 0x00 17. " LWERR ,Lock Write Error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADRERR ,Address Error" "No error,Error"
|
|
eventfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " BERR ,Bus Error" "No error,Error"
|
|
eventfld.long 0x00 1. " IOVR ,Interrupt Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " IRQ ,Interrupt Request" "No interrupt,Interrupt"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
else
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "SMPU_IADDR,SMPU Interrupt Address Register"
|
|
endif
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "SMPU_IDTLS,SMPU Interrupt Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x00 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x00 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x00 0. " SECURE ,Secure Status" "Non-secure,Secure"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "SMPU_BADDR,SMPU Bus Error Address Register"
|
|
line.long 0x04 "SMPU_BDTLS,SMPU Bus Error Details Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ID ,ID of Transaction"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ID ,ID of Transaction"
|
|
endif
|
|
bitfld.long 0x04 1. " RNW ,Read/Write Status" "Write,Read"
|
|
bitfld.long 0x04 0. " SECURE ,Secure Status Register" "Non-secure,Secure"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SMPU_RCTL0,SMPU Region 0 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR0,SMPU Region 0 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA0,SMPU Region 0 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA0,SMPU Region 0 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB0,SMPU Region 0 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB0,SMPU Region 0 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "SMPU_RCTL1,SMPU Region 1 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR1,SMPU Region 1 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA1,SMPU Region 1 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA1,SMPU Region 1 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB1,SMPU Region 1 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB1,SMPU Region 1 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x28++0x17
|
|
line.long 0x00 "SMPU_RCTL2,SMPU Region 2 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR2,SMPU Region 2 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA2,SMPU Region 2 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA2,SMPU Region 2 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB2,SMPU Region 2 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB2,SMPU Region 2 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "SMPU_RCTL3,SMPU Region 3 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR3,SMPU Region 3 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA3,SMPU Region 3 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA3,SMPU Region 3 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB3,SMPU Region 3 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB3,SMPU Region 3 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SMPU_RCTL4,SMPU Region 4 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR4,SMPU Region 4 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA4,SMPU Region 4 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA4,SMPU Region 4 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB4,SMPU Region 4 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB4,SMPU Region 4 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "SMPU_RCTL5,SMPU Region 5 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR5,SMPU Region 5 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA5,SMPU Region 5 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA5,SMPU Region 5 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB5,SMPU Region 5 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB5,SMPU Region 5 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "SMPU_RCTL6,SMPU Region 6 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR6,SMPU Region 6 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA6,SMPU Region 6 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA6,SMPU Region 6 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB6,SMPU Region 6 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB6,SMPU Region 6 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000))&0x10)==0x10)
|
|
rgroup.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
else
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "SMPU_RCTL7,SMPU Region 7 Control Register"
|
|
bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4MB,8MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,?..."
|
|
bitfld.long 0x00 0. " EN ,Region Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMPU_RADDR7,SMPU Region 7 Address Register"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits"
|
|
line.long 0x08 "SMPU_RIDA7,SMPU Region 7 ID A Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " ID ,Region n ID Register A"
|
|
line.long 0x0C "SMPU_RIDMSKA7,SMPU Region 7 ID Mask A Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " MSK ,Region n ID Mask Register A"
|
|
line.long 0x10 "SMPU_RIDB7,SMPU Region 7 ID B Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " ID ,Region n ID Register B"
|
|
line.long 0x14 "SMPU_RIDMSKB7,SMPU Region 7 ID Mask B Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " MSK ,Region n ID Mask Register B"
|
|
endif
|
|
rgroup.long 0x1A0++0x7
|
|
line.long 0x00 "SMPU_EXACADD0,SMPU Exclusive Access ID0 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT0,SMPU Exclusive 0 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
rgroup.long 0x1A4++0x7
|
|
line.long 0x00 "SMPU_EXACADD1,SMPU Exclusive Access ID1 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT1,SMPU Exclusive 1 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
rgroup.long 0x1A8++0x7
|
|
line.long 0x00 "SMPU_EXACADD2,SMPU Exclusive Access ID2 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT2,SMPU Exclusive 2 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
rgroup.long 0x1AC++0x7
|
|
line.long 0x00 "SMPU_EXACADD3,SMPU Exclusive Access ID3 Address"
|
|
line.long 0x04 "SMPU_EXACSTAT3,SMPU Exclusive 3 Access Status"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x04 8.--19. 1. " ARID ,Exclusive Access ID"
|
|
else
|
|
hexmask.long.word 0x04 8.--20. 1. " ARID ,Exclusive Access ID"
|
|
endif
|
|
bitfld.long 0x04 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VALID ,Valid Exclusive Access Read" "0,1"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "SMPU_REVID,SMPU Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "SMPU_REVID,SMPU SMPU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental Version ID"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Not write-protected,Write-protected"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "Decode,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310A0000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
else
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "SMPU_SECURECTL,SMPU SMPU Control Secure Accesses Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlock,Lock"
|
|
bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "No,Yes"
|
|
bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A0000+0x800))&0x8)==0x8)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[0],Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[1],Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[2],Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[3],Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[4],Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[5],Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[6],Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "SMPU_SECURERCTL[7],Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long 0x820++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL0,SMPU Region 0 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x824++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL1,SMPU Region 1 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x828++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL2,SMPU Region 2 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x82C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL3,SMPU Region 3 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x830++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL4,SMPU Region 4 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x834++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL5,SMPU Region 5 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x838++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL6,SMPU Region 6 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
group.long 0x83C++0x3
|
|
line.long 0x00 "SMPU_SECURERCTL7,SMPU Region 7 Control Secure Accesses Register"
|
|
bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "No,Yes"
|
|
bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "No,Yes"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree.open "PORT (General-Purpose Ports)"
|
|
tree "PORT A"
|
|
base ad:0x31004000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTA_FER,Port A Function Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 mode" "Peripheral,GPIO"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTA_DATA,Port A GPIO Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port A bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port A bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port A bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port A bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port A bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port A bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port A bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port A bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port A bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port A bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port A bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port A bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port A bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port A bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port A bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port A bit 0 data" "Set,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTA_DIR,Port A GPIO Direction Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port A bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port A bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port A bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port A bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port A bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port A bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port A bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port A bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port A bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port A bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port A bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port A bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port A bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port A bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port A bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port A bit 0 direction" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTA_INEN,Port A GPIO Input Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port A bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port A bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port A bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port A bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port A bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port A bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port A bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port A bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port A bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port A bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port A bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port A bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port A bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port A bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port A bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port A bit 0 input enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTA_MUX,Port A Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port A bit 15" "ETH0_PTPPPS2,SINC0_D1,,SMC0_A09"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port A bit 14" "ETH0_PTPPPS3,SINC0_D0,,SMC0_A10"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port A bit 13" "ETH0_TXD3,,,SMC0_A13"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port A bit 12" "ETH0_TXD2,,,SMC0_A14"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port A bit 11" "ETH0_TXCLK,,,SMC0_A15"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port A bit 10" "ETH0_TXEN,,,SMC0_A22"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port A bit 9" "ETH0_RXD3,,,SMC0_A11"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port A bit 8" "ETH0_RXD2,,,SMC0_A12"
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port A bit 7" "ETH0_CRS,,,SMC0_A16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port A bit 6" "ETH0_RXCLK_REFCLK,,,SMC0_A17"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port A bit 5" "ETH0_RXD1,,,SMC0_A18"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port A bit 4" "ETH0_RXD0,,,SMC0_A19"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port A bit 3" "ETH0_MDIO,,,SMC0_A23"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port A bit 2" "ETH0_MDC,,,SMC0_A24"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port A bit 1" "ETH0_TXD1,,,SMC0_A20"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port A bit 0" "ETH0_TXD0,,,SMC0_A21"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTA_DATA_TGL,Port A GPIO Output Toggle Register"
|
|
bitfld.long 0x00 15. " PX15 ,Port A bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port A bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port A bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port A bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port A bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port A bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port A bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port A bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port A bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port A bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port A bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port A bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port A bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port A bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port A bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port A bit 0 toggle" "No effect,Toggle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTA_POL,Port A GPIO Polarity Invert Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port A bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port A bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port A bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port A bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port A bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port A bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port A bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port A bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port A bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port A bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port A bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port A bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port A bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port A bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port A bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port A bit 0 polarity invert" "Enabled,Disabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTA_LOCK,Port A GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT B"
|
|
base ad:0x31004080
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTB_FER,Port B Function Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 mode" "Peripheral,GPIO"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTB_DATA,Port B GPIO Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port B bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port B bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port B bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port B bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port B bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port B bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port B bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port B bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port B bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port B bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port B bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port B bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port B bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port B bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port B bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port B bit 0 data" "Set,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTB_DIR,Port B GPIO Direction Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port B bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port B bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port B bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port B bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port B bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port B bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port B bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port B bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port B bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port B bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port B bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port B bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port B bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port B bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port B bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port B bit 0 direction" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTB_INEN,Port B GPIO Input Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port B bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port B bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port B bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port B bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port B bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port B bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port B bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port B bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port B bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port B bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port B bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port B bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port B bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port B bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port B bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port B bit 0 input enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTB_MUX,Port B Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port B bit 15" "LP1_ACK,PWM0_TRIP0,TM0_TMR1,SMC0_AWE"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port B bit 14" "LP1_D7,TM0_TMR5,PWM0_CL,SMC0_D08"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port B bit 13" "LP1_D6,,PWM0_CH,SMC0_D09"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port B bit 12" "LP1_D5,,PWM0_DL,SMC0_D10"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port B bit 11" "LP1_D4,,PWM0_DH,SMC0_D11"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port B bit 10" "LP1_D3,TM0_TMR2,CAN1_RX,SMC0_D12"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port B bit 9" "LP1_D2,,CAN1_TX,SMC0_D13"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port B bit 8" "LP1_D1,PWM0_AL,TM0_TMR4,SMC0_D14"
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port B bit 7" "LP1_D0,PWM0_AH,TM0_TMR3,SMC0_D15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port B bit 6" "MLB0_DAT,,PWM0_BH,SMC0_A02"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port B bit 5" "MLB0_SIG,,PPI0_D13,SMC0_A01"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port B bit 4" "MLB0_CLK,SINC0_D3,PPI0_D12,SMC0_ARDY"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port B bit 3" "ETH0_PTPAUXIN0,UART1_RX,PPI0_D17,SMC0_A03"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port B bit 2" "ETH0_PTPCLKIN0,UART1_TX,PPI0_D16,SMC0_A04"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port B bit 1" "ETH0_PTPPPS0,SINC0_CLK0,PPI0_D15,SMC0_A07"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port B bit 0" "ETH0_PTPPPS1,SINC0_D2,PPI0_D14,SMC0_A08"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTB_DATA_TGL,Port B GPIO Output Toggle Register"
|
|
bitfld.long 0x00 15. " PX15 ,Port B bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port B bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port B bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port B bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port B bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port B bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port B bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port B bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port B bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port B bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port B bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port B bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port B bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port B bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port B bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port B bit 0 toggle" "No effect,Toggle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTB_POL,Port B GPIO Polarity Invert Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port B bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port B bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port B bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port B bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port B bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port B bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port B bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port B bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port B bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port B bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port B bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port B bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port B bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port B bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port B bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port B bit 0 polarity invert" "Enabled,Disabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTB_LOCK,Port B GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT C"
|
|
base ad:0x31004100
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTC_FER,Port C Function Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port C bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port C bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port C bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port C bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port C bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port C bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port C bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port C bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 mode" "Peripheral,GPIO"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTC_DATA,Port C GPIO Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port C bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port C bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port C bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port C bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port C bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port C bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port C bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port C bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port C bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port C bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port C bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port C bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port C bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port C bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port C bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port C bit 0 data" "Set,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTC_DIR,Port C GPIO Direction Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port C bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port C bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port C bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port C bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port C bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port C bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port C bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port C bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port C bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port C bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port C bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port C bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port C bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port C bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port C bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port C bit 0 direction" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTC_INEN,Port C GPIO Input Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port C bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port C bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port C bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port C bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port C bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port C bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port C bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port C bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port C bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port C bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port C bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port C bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port C bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port C bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port C bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port C bit 0 input enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTC_MUX,Port C Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port C bit 15" "UART0_RTS,PPI0_FS3,ACM0_A2,SMC0_AMS0"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port C bit 14" "UART0_RX,,ACM0_A1,"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port C bit 13" "UART0_TX,SPI1_SEL1,ACM0_A0,"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port C bit 12" "SPI0_SEL3,SPI0_RDY,ACM0_T0,SMC0_A25"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port C bit 11" "SPI0_MOSI,?..."
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port C bit 10" "SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port C bit 9" "SPI0_CLK,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port C bit 8" "CAN0_TX,,SMC0_AMS3,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port C bit 7" "CAN0_RX,SPI0_SEL1,,SMC0_AMS2"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port C bit 6" "SPI2_SEL1,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port C bit 5" "SPI2_D3,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port C bit 4" "SPI2_D2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port C bit 3" "SPI2_MOSI,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port C bit 2" "SPI2_MISO,?..."
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port C bit 1" "SPI2_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port C bit 0" "LP1_CLK,PWM0_BL,SPI0_SEL4,SMC0_ARE"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTC_DATA_TGL,Port C GPIO Output Toggle Register"
|
|
bitfld.long 0x00 15. " PX15 ,Port C bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port C bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port C bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port C bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port C bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port C bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port C bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port C bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port C bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port C bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port C bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port C bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port C bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port C bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port C bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port C bit 0 toggle" "No effect,Toggle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTC_POL,Port C GPIO Polarity Invert Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port C bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port C bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port C bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port C bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port C bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port C bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port C bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port C bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port C bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port C bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port C bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port C bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port C bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port C bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port C bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port C bit 0 polarity invert" "Enabled,Disabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTC_LOCK,Port C GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT D"
|
|
base ad:0x31004180
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTD_FER,Port D Function Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 mode" "Peripheral,GPIO"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTD_DATA,Port D GPIO Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port D bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port D bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port D bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port D bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port D bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port D bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port D bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port D bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port D bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port D bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port D bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port D bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port D bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port D bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port D bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port D bit 0 data" "Set,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTD_DIR,Port D GPIO Direction Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port D bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port D bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port D bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port D bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port D bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port D bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port D bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port D bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port D bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port D bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port D bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port D bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port D bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port D bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port D bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port D bit 0 direction" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTD_INEN,Port D GPIO Input Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port D bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port D bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port D bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port D bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port D bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port D bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port D bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port D bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port D bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port D bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port D bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port D bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port D bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port D bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port D bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port D bit 0 input enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTD_MUX,Port D Multiplexer Control Register"
|
|
sif cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port D bit 15" "PPI0_D10,PWM2_CH,,SMC0_D05"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port D bit 14" "PPI0_D11,PWM2_TRIP0,MLB0_CLKOUT,SMC0_D06"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port D bit 13" "UART2_RX,,PPI0_D18,SMC0_A05"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port D bit 15" "PPI0_D10,,,SMC0_D05"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port D bit 14" "PPI0_D11,,MLB0_CLKOUT,SMC0_D06"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port D bit 13" "UART2_RX,,PPI0_D18,SMC0_A05"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port D bit 12" "UART2_TX,,PPI0_D19,SMC0_A06"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port D bit 11" "LP0_ACK,PWM1_SYNC,?..."
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port D bit 10" "LP0_CLK,PWM1_DL,TRACE0_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port D bit 9" "LP0_D7,PWM1_DH,TRACE0_D07,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port D bit 8" "LP0_D6,PWM1_CL,TRACE0_D06,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port D bit 7" "LP0_D5,PWM1_CH,TRACE0_D05,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port D bit 6" "LP0_D4,PWM1_BL,TRACE0_D04,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port D bit 5" "LP0_D3,PWM1_BH,TRACE0_D03,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port D bit 4" "LP0_D2,PWM1_AL,TRACE0_D02,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port D bit 3" "LP0_D1,PWM1_AH,TRACE0_D01,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port D bit 2" "LP0_D0,PWM1_TRIP0,TRACE0_D00,?..."
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port D bit 1" "SPI0_SEL2,,ACM0_A4,SMC0_AOE"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port D bit 0" "UART0_CTS,PPI0_D23,ACM0_A3,SMC0_D07"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTD_DATA_TGL,Port D GPIO Output Toggle Register"
|
|
bitfld.long 0x00 15. " PX15 ,Port D bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port D bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port D bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port D bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port D bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port D bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port D bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port D bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port D bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port D bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port D bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port D bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port D bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port D bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port D bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port D bit 0 toggle" "No effect,Toggle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTD_POL,Port D GPIO Polarity Invert Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port D bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port D bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port D bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port D bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port D bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port D bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port D bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port D bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port D bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port D bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port D bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port D bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port D bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port D bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port D bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port D bit 0 polarity invert" "Enabled,Disabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTD_LOCK,Port D GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT E"
|
|
base ad:0x31004200
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTE_FER,Port E Function Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 mode" "Peripheral,GPIO"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTE_DATA,Port E GPIO Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port E bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port E bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port E bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port E bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port E bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port E bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port E bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port E bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port E bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port E bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port E bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port E bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port E bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port E bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port E bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port E bit 0 data" "Set,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTE_DIR,Port E GPIO Direction Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port E bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port E bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port E bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port E bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port E bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port E bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port E bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port E bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port E bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port E bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port E bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port E bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port E bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port E bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port E bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port E bit 0 direction" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTE_INEN,Port E GPIO Input Enable Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port E bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port E bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port E bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port E bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port E bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port E bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port E bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port E bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port E bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port E bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port E bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port E bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port E bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port E bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port E bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port E bit 0 input enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTE_MUX,Port E Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port E bit 15" "SPI1_MOSI,,PPI0_D22,SMC0_ABE1"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port E bit 14" "SPI1_MISO,,PPI0_D21,SMC0_ABE0"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port E bit 13" "SPI1_CLK,,PPI0_D20,SMC0_AMS1"
|
|
sif cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port E bit 12" "PPI0_D00,SPI1_SEL4,SPI2_RDY,SMC0_D00"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port E bit 11" "PPI0_D01,SPI1_SEL3,UART2_CTS,SMC0_D01"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port E bit 10" "PPI0_D02,PWM2_DL,UART2_RTS,SMC0_D02"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port E bit 12" "PPI0_D00,SPI1_SEL4,SPI2_RDY,SMC0_D00"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port E bit 11" "PPI0_D01,SPI1_SEL3,UART2_CTS,SMC0_D01"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port E bit 10" "PPI0_D02,,UART2_RTS,SMC0_D02"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port E bit 9" "PPI0_D03,PWM0_SYNC,TM0_TMR0,SMC0_D03"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port E bit 8" "PPI0_D04,SPI1_SEL5,SPI1_RDY,C2_FLG3"
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port E bit 7" "PPI0_D05,,SPI1_SEL2,C1_FLG3"
|
|
textline " "
|
|
sif cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port E bit 6" "PPI0_D06,,SPI2_SEL5,C2_FLG2"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port E bit 5" "PPI0_D07,PWM2_SYNC,SPI2_SEL4,C1_FLG2"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port E Bit 4" "PPI0_D08,PWM2_DH,SPI2_SEL3,C2_FLG1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port E bit 6" "PPI0_D06,,SPI2_SEL5,C2_FLG2"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port E bit 5" "PPI0_D07,,SPI2_SEL4,C1_FLG2"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port E bit 4" "PPI0_D08,,SPI2_SEL3,C2_FLG1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port E bit 3" "PPI0_CLK,SPI0_SEL7,SPI2_SEL2,C1_FLG1"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port E bit 2" "PPI0_FS1,SPI0_SEL6,UART1_RTS,C2_FLG0"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port E bit 1" "PPI0_FS2,SPI0_SEL5,UART1_CTS,C1_FLG0"
|
|
sif cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port E bit 0" "PPI0_D09,PWM2_CL,,SMC0_D04"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port E bit 0" "PPI0_D09,,,SMC0_D04"
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTE_DATA_TGL,Port E GPIO Output Toggle Register"
|
|
bitfld.long 0x00 15. " PX15 ,Port E bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port E bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port E bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port E bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port E bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port E bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port E bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port E bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port E bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port E bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port E bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port E bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port E bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port E bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port E bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port E bit 0 toggle" "No effect,Toggle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTE_POL,Port E GPIO Polarity Invert Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15_set/clr ,Port E bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14_set/clr ,Port E bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13_set/clr ,Port E bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12_set/clr ,Port E bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port E bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port E bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port E bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port E bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port E bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port E bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port E bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port E bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port E bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port E bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port E bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port E bit 0 polarity invert" "Enabled,Disabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTE_LOCK,Port E GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT F"
|
|
base ad:0x31004280
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTF_FER,Port F Function Enable Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 mode" "Peripheral,GPIO"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTF_DATA,Port F GPIO Data Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port F bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port F bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port F bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port F bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port F bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port F bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port F bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port F bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port F bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port F bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port F bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port F bit 0 data" "Set,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTF_DIR,Port F GPIO Direction Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port F bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port F bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port F bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port F bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port F bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port F bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port F bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port F bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port F bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port F bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port F bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port F bit 0 direction" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTF_INEN,Port F GPIO Input Enable Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port F bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port F bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port F bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port F bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port F bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port F bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port F bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port F bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port F bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port F bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port F bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port F bit 0 input enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTF_MUX,Port F Multiplexer Control Register"
|
|
sif (!cpuis("ADSP-SC587*"))
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port F bit 15" "ETH1_MDIO,TRACE0_D10,TRACE0_D02,?..."
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port F bit 14" "ETH1_MDC,TRACE0_D09,TRACE0_D01,?..."
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port F bit 13" "ETH1_CRS,TRACE0_D08,TRACE0_D00,MSI0_INT"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port F bit 12" "MSI0_CD,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port F bit 11" "MSI0_CLK,?..."
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port F bit 10" "MSI0_CMD,?..."
|
|
sif cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port F bit 9" "MSI0_D7,PWM2_BH,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port F bit 8" "MSI0_D6,PWM2_BL,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port F bit 7" "MSI0_D5,PWM2_AH,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port F bit 6" "MSI0_D4,PWM2_AL,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port F bit 5" "MSI0_D3,HADC0_MUX0,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port F bit 4" "MSI0_D2,HADC0_MUX1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port F bit 9" "MSI0_D7,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port F bit 8" "MSI0_D6,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port F bit 7" "MSI0_D5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port F bit 6" "MSI0_D4,,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port F bit 5" "MSI0_D3,HADC0_MUX0,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port F bit 4" "MSI0_D2,HADC0_MUX1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port F bit 3" "MSI0_D1,HADC0_MUX2,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port F bit 2" "MSI0_D0,HADC0_EOC_DOUT,?..."
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port F bit 1" "TM0_TMR7,SPI1_SEL7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port F bit 0" "TM0_TMR6,SPI1_SEL6,?..."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTF_DATA_TGL,Port F GPIO Output Toggle Register"
|
|
bitfld.long 0x00 11. " PX11 ,Port F bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port F bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port F bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port F bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port F bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port F bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port F bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port F bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port F bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port F bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port F bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port F bit 0 toggle" "No effect,Toggle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTF_POL,Port F GPIO Polarity Invert Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11_set/clr ,Port F bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10_set/clr ,Port F bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9_set/clr ,Port F bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8_set/clr ,Port F bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7_set/clr ,Port F bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6_set/clr ,Port F bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5_set/clr ,Port F bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4_set/clr ,Port F bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3_set/clr ,Port F bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2_set/clr ,Port F bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1_set/clr ,Port F bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0_set/clr ,Port F bit 0 polarity invert" "Enabled,Disabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTF_LOCK,Port F GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PINT"
|
|
base ad:0x31005000
|
|
width 16.
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "PINT0_ASSIGN,PINT0 Assign Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " B3MAP ,Byte 3 mapping"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B2MAP ,Byte 2 mapping"
|
|
hexmask.long.byte 0x00 8.--15. 1. " B1MAP ,Byte 1 mapping"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B0MAP ,Byte 0 mapping"
|
|
group.long (0x0+0x10)++0x03
|
|
line.long 0x00 "PINT0_EDGE,PINT0 Edge Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 level" "Low level,High level"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 level" "Low level,High level"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 level" "Low level,High level"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 level" "Low level,High level"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 level" "Low level,High level"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 level" "Low level,High level"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 level" "Low level,High level"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 level" "Low level,High level"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 level" "Low level,High level"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 level" "Low level,High level"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 level" "Low level,High level"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 level" "Low level,High level"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 level" "Low level,High level"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 level" "Low level,High level"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 level" "Low level,High level"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 level" "Low level,High level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 level" "Low level,High level"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 level" "Low level,High level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 level" "Low level,High level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 level" "Low level,High level"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 level" "Low level,High level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 level" "Low level,High level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 level" "Low level,High level"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 level" "Low level,High level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 level" "Low level,High level"
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "PINT0_INVERT,PINT0 Invert Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 no invert" "No,Yes"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 no invert" "No,Yes"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 no invert" "No,Yes"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 no invert" "No,Yes"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 no invert" "No,Yes"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 no invert" "No,Yes"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 no invert" "No,Yes"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 no invert" "No,Yes"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 no invert" "No,Yes"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 no invert" "No,Yes"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 no invert" "No,Yes"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 no invert" "No,Yes"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 no invert" "No,Yes"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 no invert" "No,Yes"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 no invert" "No,Yes"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 no invert" "No,Yes"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 no invert" "No,Yes"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 no invert" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 no invert" "No,Yes"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 no invert" "No,Yes"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 no invert" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 no invert" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 no invert" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 no invert" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 no invert" "No,Yes"
|
|
group.long (0x0+0x24)++0x03
|
|
line.long 0x00 "PINT0_LATCH,PINT0 Latch Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 latch" "No effect,Clear"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 latch" "No effect,Clear"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 latch" "No effect,Clear"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 latch" "No effect,Clear"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 latch" "No effect,Clear"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 latch" "No effect,Clear"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 latch" "No effect,Clear"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 latch" "No effect,Clear"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 latch" "No effect,Clear"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 latch" "No effect,Clear"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 latch" "No effect,Clear"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 latch" "No effect,Clear"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 latch" "No effect,Clear"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 latch" "No effect,Clear"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 latch" "No effect,Clear"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 latch" "No effect,Clear"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 latch" "No effect,Clear"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 latch" "No effect,Clear"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 latch" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 latch" "No effect,Clear"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PINT0_MASK,PINT0 Mask Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 mask" "No masked,Masked"
|
|
rgroup.long (0x0+0x20)++0x03
|
|
line.long 0x00 "PINT0_STATE,PINT0 Pin State Register"
|
|
bitfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 state" "No interrupt,Interrupt"
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "PINT0_REQUEST,PINT0 Request Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 request" "No pending,Pending"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 request" "No pending,Pending"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 request" "No pending,Pending"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 request" "No pending,Pending"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 request" "No pending,Pending"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 request" "No pending,Pending"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 request" "No pending,Pending"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 request" "No pending,Pending"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 request" "No pending,Pending"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 request" "No pending,Pending"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 request" "No pending,Pending"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 request" "No pending,Pending"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 request" "No pending,Pending"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 request" "No pending,Pending"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 request" "No pending,Pending"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 request" "No pending,Pending"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 request" "No pending,Pending"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 request" "No pending,Pending"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 request" "No pending,Pending"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 request" "No pending,Pending"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 request" "No pending,Pending"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 request" "No pending,Pending"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 request" "No pending,Pending"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 request" "No pending,Pending"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 request" "No pending,Pending"
|
|
group.long (0x100+0x0C)++0x03
|
|
line.long 0x00 "PINT1_ASSIGN,PINT1 Assign Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " B3MAP ,Byte 3 mapping"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B2MAP ,Byte 2 mapping"
|
|
hexmask.long.byte 0x00 8.--15. 1. " B1MAP ,Byte 1 mapping"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B0MAP ,Byte 0 mapping"
|
|
group.long (0x100+0x10)++0x03
|
|
line.long 0x00 "PINT1_EDGE,PINT1 Edge Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 level" "Low level,High level"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 level" "Low level,High level"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 level" "Low level,High level"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 level" "Low level,High level"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 level" "Low level,High level"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 level" "Low level,High level"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 level" "Low level,High level"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 level" "Low level,High level"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 level" "Low level,High level"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 level" "Low level,High level"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 level" "Low level,High level"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 level" "Low level,High level"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 level" "Low level,High level"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 level" "Low level,High level"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 level" "Low level,High level"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 level" "Low level,High level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 level" "Low level,High level"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 level" "Low level,High level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 level" "Low level,High level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 level" "Low level,High level"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 level" "Low level,High level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 level" "Low level,High level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 level" "Low level,High level"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 level" "Low level,High level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 level" "Low level,High level"
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "PINT1_INVERT,PINT1 Invert Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 no invert" "No,Yes"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 no invert" "No,Yes"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 no invert" "No,Yes"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 no invert" "No,Yes"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 no invert" "No,Yes"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 no invert" "No,Yes"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 no invert" "No,Yes"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 no invert" "No,Yes"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 no invert" "No,Yes"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 no invert" "No,Yes"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 no invert" "No,Yes"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 no invert" "No,Yes"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 no invert" "No,Yes"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 no invert" "No,Yes"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 no invert" "No,Yes"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 no invert" "No,Yes"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 no invert" "No,Yes"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 no invert" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 no invert" "No,Yes"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 no invert" "No,Yes"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 no invert" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 no invert" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 no invert" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 no invert" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 no invert" "No,Yes"
|
|
group.long (0x100+0x24)++0x03
|
|
line.long 0x00 "PINT1_LATCH,PINT1 Latch Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 latch" "No effect,Clear"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 latch" "No effect,Clear"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 latch" "No effect,Clear"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 latch" "No effect,Clear"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 latch" "No effect,Clear"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 latch" "No effect,Clear"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 latch" "No effect,Clear"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 latch" "No effect,Clear"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 latch" "No effect,Clear"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 latch" "No effect,Clear"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 latch" "No effect,Clear"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 latch" "No effect,Clear"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 latch" "No effect,Clear"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 latch" "No effect,Clear"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 latch" "No effect,Clear"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 latch" "No effect,Clear"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 latch" "No effect,Clear"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 latch" "No effect,Clear"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 latch" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 latch" "No effect,Clear"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PINT1_MASK,PINT1 Mask Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 mask" "No masked,Masked"
|
|
rgroup.long (0x100+0x20)++0x03
|
|
line.long 0x00 "PINT1_STATE,PINT1 Pin State Register"
|
|
bitfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 state" "No interrupt,Interrupt"
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "PINT1_REQUEST,PINT1 Request Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 request" "No pending,Pending"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 request" "No pending,Pending"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 request" "No pending,Pending"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 request" "No pending,Pending"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 request" "No pending,Pending"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 request" "No pending,Pending"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 request" "No pending,Pending"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 request" "No pending,Pending"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 request" "No pending,Pending"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 request" "No pending,Pending"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 request" "No pending,Pending"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 request" "No pending,Pending"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 request" "No pending,Pending"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 request" "No pending,Pending"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 request" "No pending,Pending"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 request" "No pending,Pending"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 request" "No pending,Pending"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 request" "No pending,Pending"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 request" "No pending,Pending"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 request" "No pending,Pending"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 request" "No pending,Pending"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 request" "No pending,Pending"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 request" "No pending,Pending"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 request" "No pending,Pending"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 request" "No pending,Pending"
|
|
group.long (0x200+0x0C)++0x03
|
|
line.long 0x00 "PINT2_ASSIGN,PINT2 Assign Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " B3MAP ,Byte 3 mapping"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B2MAP ,Byte 2 mapping"
|
|
hexmask.long.byte 0x00 8.--15. 1. " B1MAP ,Byte 1 mapping"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B0MAP ,Byte 0 mapping"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "PINT2_EDGE,PINT2 Edge Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 level" "Low level,High level"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 level" "Low level,High level"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 level" "Low level,High level"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 level" "Low level,High level"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 level" "Low level,High level"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 level" "Low level,High level"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 level" "Low level,High level"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 level" "Low level,High level"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 level" "Low level,High level"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 level" "Low level,High level"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 level" "Low level,High level"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 level" "Low level,High level"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 level" "Low level,High level"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 level" "Low level,High level"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 level" "Low level,High level"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 level" "Low level,High level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 level" "Low level,High level"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 level" "Low level,High level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 level" "Low level,High level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 level" "Low level,High level"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 level" "Low level,High level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 level" "Low level,High level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 level" "Low level,High level"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 level" "Low level,High level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 level" "Low level,High level"
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "PINT2_INVERT,PINT2 Invert Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 no invert" "No,Yes"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 no invert" "No,Yes"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 no invert" "No,Yes"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 no invert" "No,Yes"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 no invert" "No,Yes"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 no invert" "No,Yes"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 no invert" "No,Yes"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 no invert" "No,Yes"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 no invert" "No,Yes"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 no invert" "No,Yes"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 no invert" "No,Yes"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 no invert" "No,Yes"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 no invert" "No,Yes"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 no invert" "No,Yes"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 no invert" "No,Yes"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 no invert" "No,Yes"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 no invert" "No,Yes"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 no invert" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 no invert" "No,Yes"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 no invert" "No,Yes"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 no invert" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 no invert" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 no invert" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 no invert" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 no invert" "No,Yes"
|
|
group.long (0x200+0x24)++0x03
|
|
line.long 0x00 "PINT2_LATCH,PINT2 Latch Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 latch" "No effect,Clear"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 latch" "No effect,Clear"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 latch" "No effect,Clear"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 latch" "No effect,Clear"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 latch" "No effect,Clear"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 latch" "No effect,Clear"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 latch" "No effect,Clear"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 latch" "No effect,Clear"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 latch" "No effect,Clear"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 latch" "No effect,Clear"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 latch" "No effect,Clear"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 latch" "No effect,Clear"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 latch" "No effect,Clear"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 latch" "No effect,Clear"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 latch" "No effect,Clear"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 latch" "No effect,Clear"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 latch" "No effect,Clear"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 latch" "No effect,Clear"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 latch" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 latch" "No effect,Clear"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PINT2_MASK,PINT2 Mask Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 mask" "No masked,Masked"
|
|
rgroup.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PINT2_STATE,PINT2 Pin State Register"
|
|
bitfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 state" "No interrupt,Interrupt"
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "PINT2_REQUEST,PINT2 Request Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 request" "No pending,Pending"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 request" "No pending,Pending"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 request" "No pending,Pending"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 request" "No pending,Pending"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 request" "No pending,Pending"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 request" "No pending,Pending"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 request" "No pending,Pending"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 request" "No pending,Pending"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 request" "No pending,Pending"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 request" "No pending,Pending"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 request" "No pending,Pending"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 request" "No pending,Pending"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 request" "No pending,Pending"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 request" "No pending,Pending"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 request" "No pending,Pending"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 request" "No pending,Pending"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 request" "No pending,Pending"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 request" "No pending,Pending"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 request" "No pending,Pending"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 request" "No pending,Pending"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 request" "No pending,Pending"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 request" "No pending,Pending"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 request" "No pending,Pending"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 request" "No pending,Pending"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 request" "No pending,Pending"
|
|
group.long (0x300+0x0C)++0x03
|
|
line.long 0x00 "PINT3_ASSIGN,PINT3 Assign Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " B3MAP ,Byte 3 mapping"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B2MAP ,Byte 2 mapping"
|
|
hexmask.long.byte 0x00 8.--15. 1. " B1MAP ,Byte 1 mapping"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B0MAP ,Byte 0 mapping"
|
|
group.long (0x300+0x10)++0x03
|
|
line.long 0x00 "PINT3_EDGE,PINT3 Edge Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 level" "Low level,High level"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 level" "Low level,High level"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 level" "Low level,High level"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 level" "Low level,High level"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 level" "Low level,High level"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 level" "Low level,High level"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 level" "Low level,High level"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 level" "Low level,High level"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 level" "Low level,High level"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 level" "Low level,High level"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 level" "Low level,High level"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 level" "Low level,High level"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 level" "Low level,High level"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 level" "Low level,High level"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 level" "Low level,High level"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 level" "Low level,High level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 level" "Low level,High level"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 level" "Low level,High level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 level" "Low level,High level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 level" "Low level,High level"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 level" "Low level,High level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 level" "Low level,High level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 level" "Low level,High level"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 level" "Low level,High level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 level" "Low level,High level"
|
|
group.long (0x300+0x18)++0x03
|
|
line.long 0x00 "PINT3_INVERT,PINT3 Invert Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 no invert" "No,Yes"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 no invert" "No,Yes"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 no invert" "No,Yes"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 no invert" "No,Yes"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 no invert" "No,Yes"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 no invert" "No,Yes"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 no invert" "No,Yes"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 no invert" "No,Yes"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 no invert" "No,Yes"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 no invert" "No,Yes"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 no invert" "No,Yes"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 no invert" "No,Yes"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 no invert" "No,Yes"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 no invert" "No,Yes"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 no invert" "No,Yes"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 no invert" "No,Yes"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 no invert" "No,Yes"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 no invert" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 no invert" "No,Yes"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 no invert" "No,Yes"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 no invert" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 no invert" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 no invert" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 no invert" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 no invert" "No,Yes"
|
|
group.long (0x300+0x24)++0x03
|
|
line.long 0x00 "PINT3_LATCH,PINT3 Latch Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 latch" "No effect,Clear"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 latch" "No effect,Clear"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 latch" "No effect,Clear"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 latch" "No effect,Clear"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 latch" "No effect,Clear"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 latch" "No effect,Clear"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 latch" "No effect,Clear"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 latch" "No effect,Clear"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 latch" "No effect,Clear"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 latch" "No effect,Clear"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 latch" "No effect,Clear"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 latch" "No effect,Clear"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 latch" "No effect,Clear"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 latch" "No effect,Clear"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 latch" "No effect,Clear"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 latch" "No effect,Clear"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 latch" "No effect,Clear"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 latch" "No effect,Clear"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 latch" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 latch" "No effect,Clear"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PINT3_MASK,PINT3 Mask Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 mask" "No masked,Masked"
|
|
rgroup.long (0x300+0x20)++0x03
|
|
line.long 0x00 "PINT3_STATE,PINT3 Pin State Register"
|
|
bitfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 state" "No interrupt,Interrupt"
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "PINT3_REQUEST,PINT3 Request Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 request" "No pending,Pending"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 request" "No pending,Pending"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 request" "No pending,Pending"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 request" "No pending,Pending"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 request" "No pending,Pending"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 request" "No pending,Pending"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 request" "No pending,Pending"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 request" "No pending,Pending"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 request" "No pending,Pending"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 request" "No pending,Pending"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 request" "No pending,Pending"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 request" "No pending,Pending"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 request" "No pending,Pending"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 request" "No pending,Pending"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 request" "No pending,Pending"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 request" "No pending,Pending"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 request" "No pending,Pending"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 request" "No pending,Pending"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 request" "No pending,Pending"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 request" "No pending,Pending"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 request" "No pending,Pending"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 request" "No pending,Pending"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 request" "No pending,Pending"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 request" "No pending,Pending"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 request" "No pending,Pending"
|
|
group.long (0x400+0x0C)++0x03
|
|
line.long 0x00 "PINT4_ASSIGN,PINT4 Assign Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " B3MAP ,Byte 3 mapping"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B2MAP ,Byte 2 mapping"
|
|
hexmask.long.byte 0x00 8.--15. 1. " B1MAP ,Byte 1 mapping"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B0MAP ,Byte 0 mapping"
|
|
group.long (0x400+0x10)++0x03
|
|
line.long 0x00 "PINT4_EDGE,PINT4 Edge Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 level" "Low level,High level"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 level" "Low level,High level"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 level" "Low level,High level"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 level" "Low level,High level"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 level" "Low level,High level"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 level" "Low level,High level"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 level" "Low level,High level"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 level" "Low level,High level"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 level" "Low level,High level"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 level" "Low level,High level"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 level" "Low level,High level"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 level" "Low level,High level"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 level" "Low level,High level"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 level" "Low level,High level"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 level" "Low level,High level"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 level" "Low level,High level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 level" "Low level,High level"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 level" "Low level,High level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 level" "Low level,High level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 level" "Low level,High level"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 level" "Low level,High level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 level" "Low level,High level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 level" "Low level,High level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 level" "Low level,High level"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 level" "Low level,High level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 level" "Low level,High level"
|
|
group.long (0x400+0x18)++0x03
|
|
line.long 0x00 "PINT4_INVERT,PINT4 Invert Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 no invert" "No,Yes"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 no invert" "No,Yes"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 no invert" "No,Yes"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 no invert" "No,Yes"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 no invert" "No,Yes"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 no invert" "No,Yes"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 no invert" "No,Yes"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 no invert" "No,Yes"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 no invert" "No,Yes"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 no invert" "No,Yes"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 no invert" "No,Yes"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 no invert" "No,Yes"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 no invert" "No,Yes"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 no invert" "No,Yes"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 no invert" "No,Yes"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 no invert" "No,Yes"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 no invert" "No,Yes"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 no invert" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 no invert" "No,Yes"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 no invert" "No,Yes"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 no invert" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 no invert" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 no invert" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 no invert" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 no invert" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 no invert" "No,Yes"
|
|
group.long (0x400+0x24)++0x03
|
|
line.long 0x00 "PINT4_LATCH,PINT4 Latch Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 latch" "No effect,Clear"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 latch" "No effect,Clear"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 latch" "No effect,Clear"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 latch" "No effect,Clear"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 latch" "No effect,Clear"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 latch" "No effect,Clear"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 latch" "No effect,Clear"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 latch" "No effect,Clear"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 latch" "No effect,Clear"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 latch" "No effect,Clear"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 latch" "No effect,Clear"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 latch" "No effect,Clear"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 latch" "No effect,Clear"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 latch" "No effect,Clear"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 latch" "No effect,Clear"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 latch" "No effect,Clear"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 latch" "No effect,Clear"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 latch" "No effect,Clear"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 latch" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 latch" "No effect,Clear"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PINT4_MASK,PINT4 Mask Set/clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " PIQ31_SET/CLR ,Pin interrupt 31 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PIQ30_SET/CLR ,Pin interrupt 30 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " PIQ29_SET/CLR ,Pin interrupt 29 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " PIQ28_SET/CLR ,Pin interrupt 28 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " PIQ27_SET/CLR ,Pin interrupt 27 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " PIQ26_SET/CLR ,Pin interrupt 26 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " PIQ25_SET/CLR ,Pin interrupt 25 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PIQ24_SET/CLR ,Pin interrupt 24 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " PIQ23_SET/CLR ,Pin interrupt 23 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " PIQ22_SET/CLR ,Pin interrupt 22 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PIQ21_SET/CLR ,Pin interrupt 21 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PIQ20_SET/CLR ,Pin interrupt 20 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PIQ19_SET/CLR ,Pin interrupt 19 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PIQ18_SET/CLR ,Pin interrupt 18 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PIQ17_SET/CLR ,Pin interrupt 17 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PIQ16_SET/CLR ,Pin interrupt 16 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PIQ15_SET/CLR ,Pin interrupt 15 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PIQ14_SET/CLR ,Pin interrupt 14 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " PIQ13_SET/CLR ,Pin interrupt 13 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " PIQ12_SET/CLR ,Pin interrupt 12 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " PIQ11_SET/CLR ,Pin interrupt 11 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " PIQ10_SET/CLR ,Pin interrupt 10 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " PIQ9_SET/CLR ,Pin interrupt 9 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " PIQ8_SET/CLR ,Pin interrupt 8 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PIQ7_SET/CLR ,Pin interrupt 7 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " PIQ6_SET/CLR ,Pin interrupt 6 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " PIQ5_SET/CLR ,Pin interrupt 5 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " PIQ4_SET/CLR ,Pin interrupt 4 mask" "No masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PIQ3_SET/CLR ,Pin interrupt 3 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PIQ2_SET/CLR ,Pin interrupt 2 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " PIQ1_SET/CLR ,Pin interrupt 1 mask" "No masked,Masked"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PIQ0_SET/CLR ,Pin interrupt 0 mask" "No masked,Masked"
|
|
rgroup.long (0x400+0x20)++0x03
|
|
line.long 0x00 "PINT4_STATE,PINT4 Pin State Register"
|
|
bitfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 state" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 state" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 state" "No interrupt,Interrupt"
|
|
group.long (0x400+0x08)++0x03
|
|
line.long 0x00 "PINT4_REQUEST,PINT4 Request Register"
|
|
eventfld.long 0x00 31. " PIQ31 ,Pin interrupt 31 request" "No pending,Pending"
|
|
eventfld.long 0x00 30. " PIQ30 ,Pin interrupt 30 request" "No pending,Pending"
|
|
eventfld.long 0x00 29. " PIQ29 ,Pin interrupt 29 request" "No pending,Pending"
|
|
eventfld.long 0x00 28. " PIQ28 ,Pin interrupt 28 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " PIQ27 ,Pin interrupt 27 request" "No pending,Pending"
|
|
eventfld.long 0x00 26. " PIQ26 ,Pin interrupt 26 request" "No pending,Pending"
|
|
eventfld.long 0x00 25. " PIQ25 ,Pin interrupt 25 request" "No pending,Pending"
|
|
eventfld.long 0x00 24. " PIQ24 ,Pin interrupt 24 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " PIQ23 ,Pin interrupt 23 request" "No pending,Pending"
|
|
eventfld.long 0x00 22. " PIQ22 ,Pin interrupt 22 request" "No pending,Pending"
|
|
eventfld.long 0x00 21. " PIQ21 ,Pin interrupt 21 request" "No pending,Pending"
|
|
eventfld.long 0x00 20. " PIQ20 ,Pin interrupt 20 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PIQ19 ,Pin interrupt 19 request" "No pending,Pending"
|
|
eventfld.long 0x00 18. " PIQ18 ,Pin interrupt 18 request" "No pending,Pending"
|
|
eventfld.long 0x00 17. " PIQ17 ,Pin interrupt 17 request" "No pending,Pending"
|
|
eventfld.long 0x00 16. " PIQ16 ,Pin interrupt 16 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " PIQ15 ,Pin interrupt 15 request" "No pending,Pending"
|
|
eventfld.long 0x00 14. " PIQ14 ,Pin interrupt 14 request" "No pending,Pending"
|
|
eventfld.long 0x00 13. " PIQ13 ,Pin interrupt 13 request" "No pending,Pending"
|
|
eventfld.long 0x00 12. " PIQ12 ,Pin interrupt 12 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " PIQ11 ,Pin interrupt 11 request" "No pending,Pending"
|
|
eventfld.long 0x00 10. " PIQ10 ,Pin interrupt 10 request" "No pending,Pending"
|
|
eventfld.long 0x00 9. " PIQ9 ,Pin interrupt 9 request" "No pending,Pending"
|
|
eventfld.long 0x00 8. " PIQ8 ,Pin interrupt 8 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PIQ7 ,Pin interrupt 7 request" "No pending,Pending"
|
|
eventfld.long 0x00 6. " PIQ6 ,Pin interrupt 6 request" "No pending,Pending"
|
|
eventfld.long 0x00 5. " PIQ5 ,Pin interrupt 5 request" "No pending,Pending"
|
|
eventfld.long 0x00 4. " PIQ4 ,Pin interrupt 4 request" "No pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PIQ3 ,Pin interrupt 3 request" "No pending,Pending"
|
|
eventfld.long 0x00 2. " PIQ2 ,Pin interrupt 2 request" "No pending,Pending"
|
|
eventfld.long 0x00 1. " PIQ1 ,Pin interrupt 1 request" "No pending,Pending"
|
|
eventfld.long 0x00 0. " PIQ0 ,Pin interrupt 0 request" "No pending,Pending"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PADS"
|
|
base ad:0x31004400
|
|
width 17.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PADS0_PCFG0,PADS 0 Peripheral PAD Configuration 0 Register"
|
|
bitfld.long 0x00 17. " EMACAUXIE ,PTP_AUXIN pins input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TWI0VSEL ,TWI0 voltage select" "3.3V,5V"
|
|
bitfld.long 0x00 9. " TWI1VSEL ,TWI1 voltage select" "3.3V,5V"
|
|
bitfld.long 0x00 8. " TWI2VSEL ,TWI2 voltage select" "3.3V,5V"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNT0DGSEL ,CNT0 down input select" "GPIO,Trigger"
|
|
bitfld.long 0x00 6. " CNT0UDSEL ,CNT0 up input select" "GPIO,Trigger"
|
|
bitfld.long 0x00 3.--4. " EMACPHYISEL ,Select PHY interface" "MII,RGMII,RMII,?..."
|
|
bitfld.long 0x00 2. " EMACRESET ,Reset enable for RGMII/RMII/MII" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " EMAC0 ,PTP clock source 0" "EMAC0_RMII CLK,SCLK,External clock,SCLK"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PADS0_PORTS_DS,PADS 0 Voltage Domain Control Register"
|
|
bitfld.long 0x00 0.--1. " HS_DS ,High speed drive strength" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PADS0_PORTA_PUE,PADS 0 PORT A Pull-Up Enable"
|
|
bitfld.long 0x00 15. " PUE[15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PADS0_PORTB_PUE,PADS 0 PORT B Pull-Up Enable"
|
|
bitfld.long 0x00 15. " PUE[15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PADS0_PORTC_PUE,PADS 0 PORT C Pull-Up Enable"
|
|
bitfld.long 0x00 15. " PUE[15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PADS0_PORTD_PUE,PADS 0 PORT D Pull-Up Enable"
|
|
bitfld.long 0x00 15. " PUE[15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PADS0_PORTE_PUE,PADS 0 PORT E Pull-Up Enable"
|
|
bitfld.long 0x00 15. " PUE[15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PADS0_PORTF_PUE,PADS 0 PORT F Pull-Up Enable"
|
|
bitfld.long 0x00 15. " PUE[15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PADS0_DAI_PUE,PADS 0 DAI Pull-Up Enable"
|
|
bitfld.long 0x00 19. " PUE[19] ,Pull-up 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pull-up 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pull-up 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pull-up 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Pull-up 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 enable" "Disabled,Enabled"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PADS0_PORTA_PUD,PADS 0 PORT A Pull-Up Disable"
|
|
bitfld.long 0x00 15. " PUD[15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PADS0_PORTB_PUD,PADS 0 PORT B Pull-Up Disable"
|
|
bitfld.long 0x00 15. " PUD[15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PADS0_PORTC_PUD,PADS 0 PORT C Pull-Up Disable"
|
|
bitfld.long 0x00 15. " PUD[15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "PADS0_PORTD_PUD,PADS 0 PORT D Pull-Up Disable"
|
|
bitfld.long 0x00 15. " PUD[15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "PADS0_PORTE_PUD,PADS 0 PORT E Pull-Up Disable"
|
|
bitfld.long 0x00 15. " PUD[15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PADS0_PORTF_PUD,PADS 0 PORT F Pull-Up Disable"
|
|
bitfld.long 0x00 15. " PUD[15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PADS0_DAI_PUD,PADS 0 DAI Pull-Up Disable"
|
|
bitfld.long 0x00 19. " PUD[19] ,Pull-up 19 disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pull-up 18 disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pull-up 17 disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pull-up 16 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Pull-up 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pull-up 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pull-up 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pull-up 12 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Pull-up 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pull-up 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pull-up 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pull-up 8 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Pull-up 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pull-up 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pull-up 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pull-up 4 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Pull-up 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pull-up 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pull-up 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pull-up 0 disable" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "LP (Link Port)"
|
|
tree "LP0"
|
|
base ad:0x30FFE000
|
|
width 16.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "LP0_CTL,LP0 Control Register"
|
|
bitfld.long 0x00 11. " ROVFMSK ,Receive FIFO overflow interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " RRQMSK ,Receive request interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " TRQMSK ,Transmit request interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TRAN ,Transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
line.long 0x04 "LP0_STAT,LP0 Status Register"
|
|
rbitfld.long 0x04 8. " LPBS ,Bus status" "Idle,Busy"
|
|
rbitfld.long 0x04 7. " LPACK ,Buffer pack status" "Done,In progress"
|
|
rbitfld.long 0x04 4.--6. " FFST ,FIFO status" "Both Empty,RX 1 word,RX 2 word,RX 3 word,TX 1 word/RX 4 word,,TX full,?..."
|
|
textline " "
|
|
eventfld.long 0x04 3. " ROVF ,Receive FIFO overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " LRRQ ,Receive request" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " LTRQ ,Transmit request" "No interrupt,Interrupt"
|
|
line.long 0x08 "LP0_DIV,LP0 Clock Divider Value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Divisor value"
|
|
hgroup.long 0x10++0x07
|
|
hide.long 0x00 "LP0_TX,LP0 Transmit Buffer"
|
|
in
|
|
hide.long 0x04 "LP0_RX,LP0 Receive Buffer"
|
|
in
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "LP0_TXIN_SHDW,LP0 Shadow Input Transmit Buffer"
|
|
line.long 0x04 "LP0_TXOUT_SHDW,LP0 Shadow Output Transmit Buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LP1"
|
|
base ad:0x30FFE100
|
|
width 16.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "LP1_CTL,LP1 Control Register"
|
|
bitfld.long 0x00 11. " ROVFMSK ,Receive FIFO overflow interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " RRQMSK ,Receive request interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " TRQMSK ,Transmit request interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TRAN ,Transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
line.long 0x04 "LP1_STAT,LP1 Status Register"
|
|
rbitfld.long 0x04 8. " LPBS ,Bus status" "Idle,Busy"
|
|
rbitfld.long 0x04 7. " LPACK ,Buffer pack status" "Done,In progress"
|
|
rbitfld.long 0x04 4.--6. " FFST ,FIFO status" "Both Empty,RX 1 word,RX 2 word,RX 3 word,TX 1 word/RX 4 word,,TX full,?..."
|
|
textline " "
|
|
eventfld.long 0x04 3. " ROVF ,Receive FIFO overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " LRRQ ,Receive request" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " LTRQ ,Transmit request" "No interrupt,Interrupt"
|
|
line.long 0x08 "LP1_DIV,LP1 Clock Divider Value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Divisor value"
|
|
hgroup.long 0x10++0x07
|
|
hide.long 0x00 "LP1_TX,LP1 Transmit Buffer"
|
|
in
|
|
hide.long 0x04 "LP1_RX,LP1 Receive Buffer"
|
|
in
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "LP1_TXIN_SHDW,LP1 Shadow Input Transmit Buffer"
|
|
line.long 0x04 "LP1_TXOUT_SHDW,LP1 Shadow Output Transmit Buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x3102E000
|
|
if (((per.l(ad:0x3102E000+0x04))&0x2003)==0x00)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x00)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2000)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2000)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x02)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x02)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2002)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2002)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x01)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x01)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2001)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2001)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x03)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x03)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102E000+0x04))&0x2003)==0x2003)&&(((per.l(ad:0x3102E000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 15.
|
|
if (((per.l(ad:0x3102E000+0x04))&0x02)==0x02)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI0_RXCTL,SPI0 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWCEN ,Receive word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTI ,Receive transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI0_TXCTL,SPI0 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " TWCEN ,Transmit word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TTI ,Transmit transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI0_RXCTL,SPI0 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI0_TXCTL,SPI0 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPI0_CLK,SPI0 Clock Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate"
|
|
line.long 0x04 "SPI0_DLY,SPI0 Delay Register"
|
|
bitfld.long 0x04 9. " LAGX ,Extended SPI clock lag control" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEADX ,Extended SPI clock lead control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STOP ,Transfer delay time in multiples of SPI clock period"
|
|
line.long 0x08 "SPI0_SLVSEL,SPI0 Slave Select Register"
|
|
bitfld.long 0x08 15. " SSEL7 ,Slave select 7 input" "Low,High"
|
|
bitfld.long 0x08 14. " SSEL6 ,Slave select 6 input" "Low,High"
|
|
bitfld.long 0x08 13. " SSEL5 ,Slave select 5 input" "Low,High"
|
|
bitfld.long 0x08 12. " SSEL4 ,Slave select 4 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SSEL3 ,Slave select 3 input" "Low,High"
|
|
bitfld.long 0x08 10. " SSEL2 ,Slave select 2 input" "Low,High"
|
|
bitfld.long 0x08 9. " SSEL1 ,Slave select 1 input" "Low,High"
|
|
bitfld.long 0x08 7. " SSE7 ,Slave select 7 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SSE6 ,Slave Select 6 Enable" "Low,High"
|
|
bitfld.long 0x08 5. " SSE5 ,Slave select 5 enable" "Low,High"
|
|
bitfld.long 0x08 4. " SSE4 ,Slave select 4 enable" "Low,High"
|
|
bitfld.long 0x08 3. " SSE3 ,Slave select 3 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SSE2 ,Slave select 2 enable" "Low,High"
|
|
bitfld.long 0x08 1. " SSE1 ,Slave select 1 enable" "Low,High"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "SPI0_RWC,SPI0 Received Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received word count"
|
|
line.long 0x04 "SPI0_RWCR,SPI0 Received Word Count Reload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Received word count reload"
|
|
line.long 0x08 "SPI0_TWC,SPI0 Transmitted Word Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Transmitted word count"
|
|
line.long 0x0C "SPI0_TWCR,SPI0 Transmitted Word Count Reload Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Transmitted word count reload"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI0_IMSK,SPI0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " TF ,Transmit finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " RF ,Receive finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " TS ,Transmit start" "Unmasked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RS ,Receive start" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MF ,Mode fault" "Unmasked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TC ,Transmit collision" "Unmasked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TUR ,Transmit under run" "Unmasked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ROR ,Receive overrun" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TUWM ,Transmit urgent watermark" "Unmasked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RUWM ,Receive urgent watermark" "Unmasked,Masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI0_STAT,SPI0 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
eventfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
eventfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
bitfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
bitfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " TFF ,SPI_TFIFO full" "Not full Tx FIFO,Full Tx FIFO"
|
|
bitfld.long 0x00 22. " RFE ,SPI_RFIFO empty" "RX FIFO Not empty,RX FIFO Empty"
|
|
bitfld.long 0x00 20. " FCS ,Flow control stall indication" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO status" "Full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO status" "Full TFIFO,25% empty RFIFO,50% empty RFIFO,75% empty RFIFO,Empty RFIFO,?..."
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
eventfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
eventfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
eventfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
eventfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
eventfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
eventfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
else
|
|
bitfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
bitfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
bitfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
bitfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPI0_ILAT,SPI0 Masked Interrupt Condition Register"
|
|
bitfld.long 0x00 11. " TF ,Transmit finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 10. " RF ,Receive finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 9. " TS ,Transmit start interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Receive start interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 7. " MF ,Mode fault interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Transmit under-run interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSPCM40"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI0_ILAT_CLR,SPI0 Masked Interrupt Clear Register"
|
|
eventfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI0_ILAT_CLR,SPI0 Masked Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
endif
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SPI0_RFIFO,SPI0 Receive FIFO Data Register"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI0_TFIFO,SPI0 Transmit FIFO Data Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI0_MMRDH,SPI0 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI0_MMTOP,SPI0 SPI Memory Top Address"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x3102F000
|
|
if (((per.l(ad:0x3102F000+0x04))&0x2003)==0x00)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x00)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2000)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2000)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x02)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x02)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2002)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2002)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x01)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x01)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2001)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2001)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x03)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x03)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x3102F000+0x04))&0x2003)==0x2003)&&(((per.l(ad:0x3102F000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 15.
|
|
if (((per.l(ad:0x3102F000+0x04))&0x02)==0x02)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI1_RXCTL,SPI1 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWCEN ,Receive word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTI ,Receive transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI1_TXCTL,SPI1 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " TWCEN ,Transmit word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TTI ,Transmit transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI1_RXCTL,SPI1 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI1_TXCTL,SPI1 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPI1_CLK,SPI1 Clock Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate"
|
|
line.long 0x04 "SPI1_DLY,SPI1 Delay Register"
|
|
bitfld.long 0x04 9. " LAGX ,Extended SPI clock lag control" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEADX ,Extended SPI clock lead control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STOP ,Transfer delay time in multiples of SPI clock period"
|
|
line.long 0x08 "SPI1_SLVSEL,SPI1 Slave Select Register"
|
|
bitfld.long 0x08 15. " SSEL7 ,Slave select 7 input" "Low,High"
|
|
bitfld.long 0x08 14. " SSEL6 ,Slave select 6 input" "Low,High"
|
|
bitfld.long 0x08 13. " SSEL5 ,Slave select 5 input" "Low,High"
|
|
bitfld.long 0x08 12. " SSEL4 ,Slave select 4 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SSEL3 ,Slave select 3 input" "Low,High"
|
|
bitfld.long 0x08 10. " SSEL2 ,Slave select 2 input" "Low,High"
|
|
bitfld.long 0x08 9. " SSEL1 ,Slave select 1 input" "Low,High"
|
|
bitfld.long 0x08 7. " SSE7 ,Slave select 7 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SSE6 ,Slave Select 6 Enable" "Low,High"
|
|
bitfld.long 0x08 5. " SSE5 ,Slave select 5 enable" "Low,High"
|
|
bitfld.long 0x08 4. " SSE4 ,Slave select 4 enable" "Low,High"
|
|
bitfld.long 0x08 3. " SSE3 ,Slave select 3 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SSE2 ,Slave select 2 enable" "Low,High"
|
|
bitfld.long 0x08 1. " SSE1 ,Slave select 1 enable" "Low,High"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "SPI1_RWC,SPI1 Received Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received word count"
|
|
line.long 0x04 "SPI1_RWCR,SPI1 Received Word Count Reload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Received word count reload"
|
|
line.long 0x08 "SPI1_TWC,SPI1 Transmitted Word Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Transmitted word count"
|
|
line.long 0x0C "SPI1_TWCR,SPI1 Transmitted Word Count Reload Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Transmitted word count reload"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI1_IMSK,SPI1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " TF ,Transmit finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " RF ,Receive finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " TS ,Transmit start" "Unmasked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RS ,Receive start" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MF ,Mode fault" "Unmasked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TC ,Transmit collision" "Unmasked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TUR ,Transmit under run" "Unmasked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ROR ,Receive overrun" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TUWM ,Transmit urgent watermark" "Unmasked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RUWM ,Receive urgent watermark" "Unmasked,Masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI1_STAT,SPI1 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
eventfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
eventfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
bitfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
bitfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " TFF ,SPI_TFIFO full" "Not full Tx FIFO,Full Tx FIFO"
|
|
bitfld.long 0x00 22. " RFE ,SPI_RFIFO empty" "RX FIFO Not empty,RX FIFO Empty"
|
|
bitfld.long 0x00 20. " FCS ,Flow control stall indication" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO status" "Full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO status" "Full TFIFO,25% empty RFIFO,50% empty RFIFO,75% empty RFIFO,Empty RFIFO,?..."
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
eventfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
eventfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
eventfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
eventfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
eventfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
eventfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
else
|
|
bitfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
bitfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
bitfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
bitfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPI1_ILAT,SPI1 Masked Interrupt Condition Register"
|
|
bitfld.long 0x00 11. " TF ,Transmit finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 10. " RF ,Receive finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 9. " TS ,Transmit start interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Receive start interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 7. " MF ,Mode fault interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Transmit under-run interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSPCM40"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI1_ILAT_CLR,SPI1 Masked Interrupt Clear Register"
|
|
eventfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI1_ILAT_CLR,SPI1 Masked Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
endif
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SPI1_RFIFO,SPI1 Receive FIFO Data Register"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI1_TFIFO,SPI1 Transmit FIFO Data Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI1_MMRDH,SPI1 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI1_MMTOP,SPI1 SPI Memory Top Address"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x31044000
|
|
if (((per.l(ad:0x31044000+0x04))&0x2003)==0x00)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x00)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2000)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2000)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x02)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x02)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2002)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2002)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x01)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x01)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2001)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2001)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x03)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x03)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x31044000+0x04))&0x2003)==0x2003)&&(((per.l(ad:0x31044000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 15.
|
|
if (((per.l(ad:0x31044000+0x04))&0x02)==0x02)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI2_RXCTL,SPI2 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWCEN ,Receive word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTI ,Receive transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI2_TXCTL,SPI2 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " TWCEN ,Transmit word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TTI ,Transmit transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI2_RXCTL,SPI2 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI2_TXCTL,SPI2 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPI2_CLK,SPI2 Clock Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate"
|
|
line.long 0x04 "SPI2_DLY,SPI2 Delay Register"
|
|
bitfld.long 0x04 9. " LAGX ,Extended SPI clock lag control" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEADX ,Extended SPI clock lead control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STOP ,Transfer delay time in multiples of SPI clock period"
|
|
line.long 0x08 "SPI2_SLVSEL,SPI2 Slave Select Register"
|
|
bitfld.long 0x08 15. " SSEL7 ,Slave select 7 input" "Low,High"
|
|
bitfld.long 0x08 14. " SSEL6 ,Slave select 6 input" "Low,High"
|
|
bitfld.long 0x08 13. " SSEL5 ,Slave select 5 input" "Low,High"
|
|
bitfld.long 0x08 12. " SSEL4 ,Slave select 4 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SSEL3 ,Slave select 3 input" "Low,High"
|
|
bitfld.long 0x08 10. " SSEL2 ,Slave select 2 input" "Low,High"
|
|
bitfld.long 0x08 9. " SSEL1 ,Slave select 1 input" "Low,High"
|
|
bitfld.long 0x08 7. " SSE7 ,Slave select 7 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SSE6 ,Slave Select 6 Enable" "Low,High"
|
|
bitfld.long 0x08 5. " SSE5 ,Slave select 5 enable" "Low,High"
|
|
bitfld.long 0x08 4. " SSE4 ,Slave select 4 enable" "Low,High"
|
|
bitfld.long 0x08 3. " SSE3 ,Slave select 3 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SSE2 ,Slave select 2 enable" "Low,High"
|
|
bitfld.long 0x08 1. " SSE1 ,Slave select 1 enable" "Low,High"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "SPI2_RWC,SPI2 Received Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received word count"
|
|
line.long 0x04 "SPI2_RWCR,SPI2 Received Word Count Reload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Received word count reload"
|
|
line.long 0x08 "SPI2_TWC,SPI2 Transmitted Word Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Transmitted word count"
|
|
line.long 0x0C "SPI2_TWCR,SPI2 Transmitted Word Count Reload Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Transmitted word count reload"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI2_IMSK,SPI2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " TF ,Transmit finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " RF ,Receive finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " TS ,Transmit start" "Unmasked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RS ,Receive start" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MF ,Mode fault" "Unmasked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TC ,Transmit collision" "Unmasked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TUR ,Transmit under run" "Unmasked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ROR ,Receive overrun" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TUWM ,Transmit urgent watermark" "Unmasked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RUWM ,Receive urgent watermark" "Unmasked,Masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI2_STAT,SPI2 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
eventfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
eventfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
bitfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
bitfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " TFF ,SPI_TFIFO full" "Not full Tx FIFO,Full Tx FIFO"
|
|
bitfld.long 0x00 22. " RFE ,SPI_RFIFO empty" "RX FIFO Not empty,RX FIFO Empty"
|
|
bitfld.long 0x00 20. " FCS ,Flow control stall indication" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO status" "Full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO status" "Full TFIFO,25% empty RFIFO,50% empty RFIFO,75% empty RFIFO,Empty RFIFO,?..."
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
eventfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
eventfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
eventfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
eventfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
eventfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
eventfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
else
|
|
bitfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
bitfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
bitfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
bitfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPI2_ILAT,SPI2 Masked Interrupt Condition Register"
|
|
bitfld.long 0x00 11. " TF ,Transmit finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 10. " RF ,Receive finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 9. " TS ,Transmit start interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Receive start interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 7. " MF ,Mode fault interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Transmit under-run interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSPCM40"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI2_ILAT_CLR,SPI2 Masked Interrupt Clear Register"
|
|
eventfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI2_ILAT_CLR,SPI2 Masked Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
endif
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SPI2_RFIFO,SPI2 Receive FIFO Data Register"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI2_TFIFO,SPI2 Transmit FIFO Data Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI2_MMRDH,SPI2 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI2_MMTOP,SPI2 SPI Memory Top Address"
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI2_MMRDH,SPI2 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI2_MMTOP,SPI2 SPI Memory Top Address"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x31003004
|
|
width 23.
|
|
group.long 0x0++0x0B
|
|
line.long 0x00 "UART0_CTL,UART0 Control Register"
|
|
bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1"
|
|
bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "2,4"
|
|
bitfld.long 0x00 28. " ACTS ,Automatic CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARTS ,Automatic RTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XOFF ,Transmitter off" "No,Yes"
|
|
bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "De-asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "Low CTS/RTS,High CTS/RTS"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SB ,Set Break" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STP ,Sticky Parity" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 14. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1"
|
|
bitfld.long 0x00 12. " STB ,Stop Bits" "1,2"
|
|
bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "UART,MDB,IrDA SIR,?..."
|
|
bitfld.long 0x00 1. " LOOP_EN ,Loop-back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable UART" "Disabled,Enabled"
|
|
line.long 0x04 "UART0_STAT,UART0 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "Less than 4,At least 4"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not clear,Clear"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "<,=>"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " RO ,Reception On-going" "Waiting,In progress"
|
|
bitfld.long 0x04 10. " ADDR ,Address Bit Status" "Low,High"
|
|
eventfld.long 0x04 9. " ASTKY ,Address Sticky" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 8. " TFI ,Transmission Finished Indicator" "Not finished,Finished"
|
|
rbitfld.long 0x04 7. " TEMT ,TSR and THR Empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 5. " THRE ,Transmit Hold Register Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 4. " BI ,Break Indicator" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " FE ,Framing Error" "No error,Error"
|
|
eventfld.long 0x04 2. " PE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " OE ,Overrun Error" "No error,Error"
|
|
rbitfld.long 0x04 0. " DR ,Data Ready" "No new data,New data"
|
|
line.long 0x08 "UART0_SCR,UART0 Scratch Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Stored 8-bit Data"
|
|
if (((per.l(ad:0x31003004))&0x30)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART0_CLK,UART0 Clock Rate Register"
|
|
rbitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART0_CLK,UART0 Clock Rate Register"
|
|
bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UART0_IMSK_set/clr,UART0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EAWI ,Enable Address Word Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ELSI ,Enable Line Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "Masked,Unmasked"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "UART0_RBR,UART0 Receive Buffer Register"
|
|
in
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART0_THR,UART0 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
else
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UART0_THR,UART0 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART0_TAIP,UART0 Transmit Address/Insert Pulse Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "UART0_TSR,UART0 Transmit Shift Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "UART0_RSR,UART0 Receive Shift Register"
|
|
in
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "UART0_TXCNT,UART0 Transmit Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
line.long 0x04 "UART0_RXCNT,UART0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x31003404
|
|
width 23.
|
|
group.long 0x0++0x0B
|
|
line.long 0x00 "UART1_CTL,UART1 Control Register"
|
|
bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1"
|
|
bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "2,4"
|
|
bitfld.long 0x00 28. " ACTS ,Automatic CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARTS ,Automatic RTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XOFF ,Transmitter off" "No,Yes"
|
|
bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "De-asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "Low CTS/RTS,High CTS/RTS"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SB ,Set Break" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STP ,Sticky Parity" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 14. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1"
|
|
bitfld.long 0x00 12. " STB ,Stop Bits" "1,2"
|
|
bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "UART,MDB,IrDA SIR,?..."
|
|
bitfld.long 0x00 1. " LOOP_EN ,Loop-back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable UART" "Disabled,Enabled"
|
|
line.long 0x04 "UART1_STAT,UART1 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "Less than 4,At least 4"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not clear,Clear"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "<,=>"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " RO ,Reception On-going" "Waiting,In progress"
|
|
bitfld.long 0x04 10. " ADDR ,Address Bit Status" "Low,High"
|
|
eventfld.long 0x04 9. " ASTKY ,Address Sticky" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 8. " TFI ,Transmission Finished Indicator" "Not finished,Finished"
|
|
rbitfld.long 0x04 7. " TEMT ,TSR and THR Empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 5. " THRE ,Transmit Hold Register Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 4. " BI ,Break Indicator" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " FE ,Framing Error" "No error,Error"
|
|
eventfld.long 0x04 2. " PE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " OE ,Overrun Error" "No error,Error"
|
|
rbitfld.long 0x04 0. " DR ,Data Ready" "No new data,New data"
|
|
line.long 0x08 "UART1_SCR,UART1 Scratch Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Stored 8-bit Data"
|
|
if (((per.l(ad:0x31003404))&0x30)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART1_CLK,UART1 Clock Rate Register"
|
|
rbitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART1_CLK,UART1 Clock Rate Register"
|
|
bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UART1_IMSK_set/clr,UART1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EAWI ,Enable Address Word Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ELSI ,Enable Line Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "Masked,Unmasked"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "UART1_RBR,UART1 Receive Buffer Register"
|
|
in
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART1_THR,UART1 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
else
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UART1_THR,UART1 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART1_TAIP,UART1 Transmit Address/Insert Pulse Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "UART1_TSR,UART1 Transmit Shift Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "UART1_RSR,UART1 Receive Shift Register"
|
|
in
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "UART1_TXCNT,UART1 Transmit Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
line.long 0x04 "UART1_RXCNT,UART1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x31003804
|
|
width 23.
|
|
group.long 0x0++0x0B
|
|
line.long 0x00 "UART2_CTL,UART2 Control Register"
|
|
bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1"
|
|
bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "2,4"
|
|
bitfld.long 0x00 28. " ACTS ,Automatic CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARTS ,Automatic RTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XOFF ,Transmitter off" "No,Yes"
|
|
bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "De-asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "Low CTS/RTS,High CTS/RTS"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SB ,Set Break" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STP ,Sticky Parity" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 14. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1"
|
|
bitfld.long 0x00 12. " STB ,Stop Bits" "1,2"
|
|
bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "UART,MDB,IrDA SIR,?..."
|
|
bitfld.long 0x00 1. " LOOP_EN ,Loop-back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable UART" "Disabled,Enabled"
|
|
line.long 0x04 "UART2_STAT,UART2 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "Less than 4,At least 4"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not clear,Clear"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "<,=>"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " RO ,Reception On-going" "Waiting,In progress"
|
|
bitfld.long 0x04 10. " ADDR ,Address Bit Status" "Low,High"
|
|
eventfld.long 0x04 9. " ASTKY ,Address Sticky" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 8. " TFI ,Transmission Finished Indicator" "Not finished,Finished"
|
|
rbitfld.long 0x04 7. " TEMT ,TSR and THR Empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 5. " THRE ,Transmit Hold Register Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 4. " BI ,Break Indicator" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " FE ,Framing Error" "No error,Error"
|
|
eventfld.long 0x04 2. " PE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " OE ,Overrun Error" "No error,Error"
|
|
rbitfld.long 0x04 0. " DR ,Data Ready" "No new data,New data"
|
|
line.long 0x08 "UART2_SCR,UART2 Scratch Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Stored 8-bit Data"
|
|
if (((per.l(ad:0x31003804))&0x30)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART2_CLK,UART2 Clock Rate Register"
|
|
rbitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART2_CLK,UART2 Clock Rate Register"
|
|
bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UART2_IMSK_set/clr,UART2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EAWI ,Enable Address Word Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ELSI ,Enable Line Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "Masked,Unmasked"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "UART2_RBR,UART2 Receive Buffer Register"
|
|
in
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART2_THR,UART2 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
else
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UART2_THR,UART2 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART2_TAIP,UART2 Transmit Address/Insert Pulse Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "UART2_TSR,UART2 Transmit Shift Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "UART2_RSR,UART2 Receive Shift Register"
|
|
in
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "UART2_TXCNT,UART2 Transmit Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
line.long 0x04 "UART2_RXCNT,UART2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "EPPI (Enhanced Parallel Peripheral Interface)"
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base ad:0x3102D000
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width 17.
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group.long 0x00++0x1F
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line.long 0x00 "EPPI0_STAT,EPPI0 Status Register"
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rbitfld.long 0x00 15. " FLD ,Current field received by EPPI" "Field 1,Field 2"
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eventfld.long 0x00 14. " ERRDET ,Preamble error detected" "No error,Error"
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eventfld.long 0x00 7. " PXPERR ,Pxp ready error" "No error,Error"
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eventfld.long 0x00 6. " ERRNCOR ,Preamble error not corrected" "No error,Uncorrected error"
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textline " "
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eventfld.long 0x00 5. " FTERRUNDR ,Frame track underflow" "No error,Error"
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eventfld.long 0x00 4. " FTERROVR ,Frame track overflow" "No error,Error"
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eventfld.long 0x00 3. " LTERRUNDR ,Line track underflow" "No error,Error"
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eventfld.long 0x00 2. " LTERROVR ,Line track overflow" "No error,Error"
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textline " "
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eventfld.long 0x00 1. " YFIFOERR ,Luma FIFO error" "No error,Error"
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eventfld.long 0x00 0. " CFIFOERR ,Chroma FIFO error" "No error,Error"
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line.long 0x04 "EPPI0_HCNT,EPPI0 Horizontal Transfer Count Register"
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hexmask.long.word 0x04 0.--15. 1. " VALUE ,Horizontal transfer count"
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line.long 0x08 "EPPI0_HDLY,EPPI0 Horizontal Delay Count Register"
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hexmask.long.word 0x08 0.--15. 1. " VALUE ,Horizontal delay count"
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line.long 0x0C "EPPI0_VCNT,EPPI0 Vertical Transfer Count Register"
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hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Vertical transfer count"
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line.long 0x10 "EPPI0_VDLY,EPPI0 Vertical Delay Count Register"
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hexmask.long.word 0x10 0.--15. 1. " VALUE ,Vertical delay count"
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line.long 0x14 "EPPI0_FRAME,EPPI0 Lines Per Frame Register"
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hexmask.long.word 0x14 0.--15. 1. " VALUE ,Lines per frame"
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line.long 0x18 "EPPI0_LINE,EPPI0 Samples Per Line Register"
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hexmask.long.word 0x18 0.--15. 1. " ,Samples per line"
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line.long 0x1C "EPPI0_CLKDIV,EPPI0 Clock Divide Register"
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hexmask.long.word 0x1C 0.--15. 1. " VALUE ,Internal clock divider"
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if (((per.l(ad:0x3102D000+0x20))&0x1000000)==0x00)
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group.long 0x20++0x03
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line.long 0x00 "EPPI0_CTL,EPPI0 Control Register"
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bitfld.long 0x00 31. " CLKGATEN ,Clock gating enable" "Disabled,Enabled"
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bitfld.long 0x00 30. " MUXSEL ,MUX select" "Normal,Multiplexed"
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bitfld.long 0x00 29. " DMAFINEN ,DMA finish enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 28. " DMACFG ,One or two DMA channels mode" "One channel,Two channels"
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bitfld.long 0x00 27. " RGBFMTEN ,RGB formatting enable" "Disabled,Enabled"
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bitfld.long 0x00 26. " SPLTWRD ,Split word" "Do not split,Split"
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textline " "
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textline " "
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bitfld.long 0x00 24. " SPLTEO ,Split even and odd data samples" "Do not split,Split"
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bitfld.long 0x00 23. " SWAPEN ,Swap enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 22. " PACKEN ,Pack/unpack enable" "Disabled,Enabled"
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bitfld.long 0x00 21. " SKIPEO ,Skip even or odd" "Skip odd,Skip even"
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bitfld.long 0x00 20. " SKIPEN ,Skip enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 19. " DMIRR ,Data mirroring" "Disabled,Enabled"
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bitfld.long 0x00 16.--18. " DLEN ,Data length" "8 bits,10 bits,12 bits,14 bits,16 bits,18 bits,20 bits,24 bits"
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bitfld.long 0x00 14.--15. " POLS ,Frame sync polarity" "FS1 and FS2 are active high,FS1 is active low. FS2 is active high,FS1 is active high. FS2 is active low,FS1 and FS2 are active low"
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textline " "
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bitfld.long 0x00 12.--13. " POLC ,Clock polarity" "Mode 0,Mode 1,Mode 2,Mode 3"
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bitfld.long 0x00 11. " SIGNEXT ,Sign extension" "Zero filled,Sign extended"
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bitfld.long 0x00 10. " IFSGEN ,Internal frame sync generation" "External,Internal"
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textline " "
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bitfld.long 0x00 9. " ICLKGEN ,Internal clock generation" "External,Internal"
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bitfld.long 0x00 8. " BLANKGEN ,King generation (ITU output mode)" "Disabled,Enabled"
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bitfld.long 0x00 7. " ITUTYPE ,ITU interlace or progressive" "Interlaced,Progressive"
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textline " "
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bitfld.long 0x00 6. " FLDSEL ,Field select/trigger" "Mode 0,Mode 1"
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bitfld.long 0x00 4.--5. " FSCFG ,Frame sync configuration" "Mode 0,Mode 1,Mode 2,Mode 3"
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bitfld.long 0x00 2.--3. " XFRTYPE ,Transfer type (operating mode)" "ITU656 Active Video Only,ITU656 Entire Field,ITU656 Vertical Blanking Only,Non-ITU656"
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textline " "
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bitfld.long 0x00 1. " DIR ,PPI direction" "Receive,Transmit"
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bitfld.long 0x00 0. " EN ,PPI enable" "Disabled,Enabled"
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else
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group.long 0x20++0x03
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line.long 0x00 "EPPI0_CTL,EPPI0 Control Register"
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bitfld.long 0x00 31. " CLKGATEN ,Clock gating enable" "Disabled,Enabled"
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bitfld.long 0x00 30. " MUXSEL ,MUX select" "Normal,Multiplexed"
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bitfld.long 0x00 29. " DMAFINEN ,DMA finish enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 28. " DMACFG ,One or two DMA channels mode" "One channel,Two channels"
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bitfld.long 0x00 27. " RGBFMTEN ,RGB formatting enable" "Disabled,Enabled"
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bitfld.long 0x00 26. " SPLTWRD ,Split word" "Do not split,Split"
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textline " "
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bitfld.long 0x00 25. " SUBSPLTODD ,Sub-Split odd samples" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 24. " SPLTEO ,Split even and odd data samples" "Do not split,Split"
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bitfld.long 0x00 23. " SWAPEN ,Swap enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 22. " PACKEN ,Pack/unpack enable" "Disabled,Enabled"
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bitfld.long 0x00 21. " SKIPEO ,Skip even or odd" "Skip odd,Skip even"
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bitfld.long 0x00 20. " SKIPEN ,Skip enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 19. " DMIRR ,Data mirroring" "Disabled,Enabled"
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bitfld.long 0x00 16.--18. " DLEN ,Data length" "8 bits,10 bits,12 bits,14 bits,16 bits,18 bits,20 bits,24 bits"
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bitfld.long 0x00 14.--15. " POLS ,Frame sync polarity" "FS1 and FS2 are active high,FS1 is active low. FS2 is active high,FS1 is active high. FS2 is active low,FS1 and FS2 are active low"
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textline " "
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bitfld.long 0x00 12.--13. " POLC ,Clock polarity" "Mode 0,Mode 1,Mode 2,Mode 3"
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bitfld.long 0x00 11. " SIGNEXT ,Sign extension" "Zero filled,Sign extended"
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bitfld.long 0x00 10. " IFSGEN ,Internal frame sync generation" "External,Internal"
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textline " "
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bitfld.long 0x00 9. " ICLKGEN ,Internal clock generation" "External,Internal"
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bitfld.long 0x00 8. " BLANKGEN ,King generation (ITU output mode)" "Disabled,Enabled"
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bitfld.long 0x00 7. " ITUTYPE ,ITU interlace or progressive" "Interlaced,Progressive"
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textline " "
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bitfld.long 0x00 6. " FLDSEL ,Field select/trigger" "Mode 0,Mode 1"
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bitfld.long 0x00 4.--5. " FSCFG ,Frame sync configuration" "Mode 0,Mode 1,Mode 2,Mode 3"
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bitfld.long 0x00 2.--3. " XFRTYPE ,Transfer type ( operating mode)" "ITU656 Active Video Only,ITU656 Entire Field,ITU656 Vertical Blanking Only,Non-ITU656"
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textline " "
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bitfld.long 0x00 1. " DIR ,PPI direction" "Receive,Transmit"
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bitfld.long 0x00 0. " EN ,PPI enable" "Disabled,Enabled"
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endif
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group.long 0x24++0x13
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line.long 0x00 "EPPI0_FS1_WLHB,EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register"
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line.long 0x04 "EPPI0_FS1_PASPL,EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register"
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line.long 0x08 "EPPI0_FS2_WLVB,EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register"
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hexmask.long.byte 0x08 24.--31. 1. " F2VBAD ,Field 2 vertical blanking after data"
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hexmask.long.byte 0x08 16.--23. 1. " F2VBBD ,Field 2 vertical blanking before data"
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textline " "
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hexmask.long.byte 0x08 8.--15. 1. " F1VBAD ,Field 1 vertical blanking after data"
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hexmask.long.byte 0x08 0.--7. 1. " F1VBBD ,Field 1 vertical blanking before data"
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line.long 0x0C "EPPI0_FS2_PALPF,EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register"
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hexmask.long.word 0x0C 16.--31. 1. " F2ACT ,Field 2 active"
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hexmask.long.word 0x0C 0.--15. 1. " F1ACT ,Field 1 active"
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line.long 0x10 "EPPI0_IMSK,EPPI0 Interrupt Mask Register"
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bitfld.long 0x10 7. " PXPERR ,PxP ready error interrupt mask" "Unmasked,Masked"
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bitfld.long 0x10 6. " ERRNCOR ,ITU preamble error not corrected interrupt mask" "Unmasked,Masked"
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bitfld.long 0x10 5. " FTERRUNDR ,Frame track underflow error interrupt mask" "Unmasked,Masked"
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textline " "
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bitfld.long 0x10 4. " FTERROVR ,Frame track overflow error interrupt mask" "Unmasked,Masked"
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bitfld.long 0x10 3. " LTERRUNDR ,Line track underflow error interrupt mask" "Unmasked,Masked"
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bitfld.long 0x10 2. " LTERROVR ,Line track overflow error interrupt mask" "Unmasked,Masked"
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textline " "
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bitfld.long 0x10 1. " YFIFOERR ,YFIFO underflow or overflow error interrupt mask" "Unmasked,Masked"
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bitfld.long 0x10 0. " CFIFOERR ,CFIFO underflow or overflow error interrupt mask" "Unmasked,Masked"
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group.long 0x3C++0x13
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line.long 0x00 "EPPI0_ODDCLIP,EPPI0 Clipping Register For ODD (chroma) Data"
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hexmask.long.word 0x00 16.--31. 1. " HIGHODD ,High odd clipping threshold (chroma data)"
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hexmask.long.word 0x00 0.--15. 1. " LOWODD ,Low odd clipping threshold (chroma data)"
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line.long 0x04 "EPPI0_EVENCLIP,EPPI0 Clipping Register For EVEN (luma) Data"
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hexmask.long.word 0x04 16.--31. 1. " HIGHEVEN ,High even clipping threshold (luma data)"
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hexmask.long.word 0x04 0.--15. 1. " LOWEVEN ,Low even clipping threshold (luma data)"
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line.long 0x08 "EPPI0_FS1_DLY,EPPI0 Frame Sync 1 Delay Value"
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line.long 0x0C "EPPI0_FS2_DLY,EPPI0 Frame Sync 2 Delay Value"
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line.long 0x10 "EPPI0_CTL2,EPPI0 Control Register 2"
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bitfld.long 0x10 1. " FS1FINEN ,HSYNC finish enable" "0,1"
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width 0x0B
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tree.end
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tree "TIMER (General-Purpose Timer)"
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base ad:0x31018004
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width 25.
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group.long 0x00++0x03
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line.long 0x00 "TIMER0_RUN_SET/CLR,TIMER0 Run Register"
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TMR07 ,Start/stop timer 7" "Stop,Start"
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setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TMR06 ,Start/stop timer 6" "Stop,Start"
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setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TMR05 ,Start/stop timer 5" "Stop,Start"
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setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TMR04 ,Start/stop timer 4" "Stop,Start"
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textline " "
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setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TMR03 ,Start/stop timer 3" "Stop,Start"
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setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TMR02 ,Start/stop timer 2" "Stop,Start"
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setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TMR01 ,Start/stop timer 1" "Stop,Start"
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TMR00 ,Start/stop timer 0" "Stop,Start"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER0_STOP_CFG_SET/CLR,TIMER0 Stop Configuration Register"
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TMR07 ,Stop mode select" "Graceful,Abrupt"
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setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TMR06 ,Stop mode select" "Graceful,Abrupt"
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setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TMR05 ,Stop mode select" "Graceful,Abrupt"
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setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TMR04 ,Stop mode select" "Graceful,Abrupt"
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textline " "
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setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TMR03 ,Stop mode select" "Graceful,Abrupt"
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setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TMR02 ,Stop mode select" "Graceful,Abrupt"
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setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TMR01 ,Stop mode select" "Graceful,Abrupt"
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TMR00 ,Stop mode select" "Graceful,Abrupt"
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group.long 0x18++0x17
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line.long 0x00 "TIMER0_DATA_IMSK,TIMER0 Data Interrupt Mask Register"
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bitfld.long 0x00 7. " TMR07 ,Data interrupt mask" "Unmasked,Masked"
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bitfld.long 0x00 6. " TMR06 ,Data interrupt mask" "Unmasked,Masked"
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bitfld.long 0x00 5. " TMR05 ,Data interrupt mask" "Unmasked,Masked"
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bitfld.long 0x00 4. " TMR04 ,Data interrupt mask" "Unmasked,Masked"
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textline " "
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bitfld.long 0x00 3. " TMR03 ,Data interrupt mask" "Unmasked,Masked"
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bitfld.long 0x00 2. " TMR02 ,Data interrupt mask" "Unmasked,Masked"
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bitfld.long 0x00 1. " TMR01 ,Data interrupt mask" "Unmasked,Masked"
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bitfld.long 0x00 0. " TMR00 ,Data interrupt mask" "Unmasked,Masked"
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line.long 0x04 "TIMER0_STAT_IMSK,TIMER0 Status Interrupt Mask Register"
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bitfld.long 0x04 7. " TMR07 ,Status interrupt mask" "Unmasked,Masked"
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bitfld.long 0x04 6. " TMR06 ,Status interrupt mask" "Unmasked,Masked"
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bitfld.long 0x04 5. " TMR05 ,Status interrupt mask" "Unmasked,Masked"
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bitfld.long 0x04 4. " TMR04 ,Status interrupt mask" "Unmasked,Masked"
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textline " "
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bitfld.long 0x04 3. " TMR03 ,Status interrupt mask" "Unmasked,Masked"
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bitfld.long 0x04 2. " TMR02 ,Status interrupt mask" "Unmasked,Masked"
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bitfld.long 0x04 1. " TMR01 ,Status interrupt mask" "Unmasked,Masked"
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bitfld.long 0x04 0. " TMR00 ,Status interrupt mask" "Unmasked,Masked"
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line.long 0x08 "TIMER0_TRG_MSK,TIMER0 Trigger Master Mask Register"
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bitfld.long 0x08 7. " TMR07 ,Trigger output mask" "Unmasked,Masked"
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bitfld.long 0x08 6. " TMR06 ,Trigger output mask" "Unmasked,Masked"
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bitfld.long 0x08 5. " TMR05 ,Trigger output mask" "Unmasked,Masked"
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bitfld.long 0x08 4. " TMR04 ,Trigger output mask" "Unmasked,Masked"
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textline " "
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bitfld.long 0x08 3. " TMR03 ,Trigger output mask" "Unmasked,Masked"
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bitfld.long 0x08 2. " TMR02 ,Trigger output mask" "Unmasked,Masked"
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bitfld.long 0x08 1. " TMR01 ,Trigger output mask" "Unmasked,Masked"
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bitfld.long 0x08 0. " TMR00 ,Trigger output mask" "Unmasked,Masked"
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line.long 0x0C "TIMER0_TRG_IE,TIMER0 Trigger Slave Enable Register"
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bitfld.long 0x0C 7. " TMR07 ,Trigger input enable" "Disabled,Enabled"
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bitfld.long 0x0C 6. " TMR06 ,Trigger input enable" "Disabled,Enabled"
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bitfld.long 0x0C 5. " TMR05 ,Trigger input enable" "Disabled,Enabled"
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bitfld.long 0x0C 4. " TMR04 ,Trigger input enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0C 3. " TMR03 ,Trigger input enable" "Disabled,Enabled"
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bitfld.long 0x0C 2. " TMR02 ,Trigger input enable" "Disabled,Enabled"
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bitfld.long 0x0C 1. " TMR01 ,Trigger input enable" "Disabled,Enabled"
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bitfld.long 0x0C 0. " TMR00 ,Trigger input enable" "Disabled,Enabled"
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line.long 0x10 "TIMER0_DATA_ILAT,TIMER0 Data Interrupt Latch Register"
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eventfld.long 0x10 7. " TMR07 ,Data interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x10 6. " TMR06 ,Data interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x10 5. " TMR05 ,Data interrupt latch" "No interrupt,Interrupt"
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eventfld.long 0x10 4. " TMR04 ,Data interrupt latch" "No interrupt,Interrupt"
|
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textline " "
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eventfld.long 0x10 3. " TMR03 ,Data interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x10 2. " TMR02 ,Data interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x10 1. " TMR01 ,Data interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x10 0. " TMR00 ,Data interrupt latch" "No interrupt,Interrupt"
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line.long 0x14 "TIMER0_STAT_ILAT,TIMER0 Status Interrupt Latch Register"
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eventfld.long 0x14 7. " TMR07 ,Status interrupt latch" "No interrupt,Interrupt"
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eventfld.long 0x14 6. " TMR06 ,Status interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x14 5. " TMR05 ,Status interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x14 4. " TMR04 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
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eventfld.long 0x14 3. " TMR03 ,Status interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x14 2. " TMR02 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 1. " TMR01 ,Status interrupt latch" "No interrupt,Interrupt"
|
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eventfld.long 0x14 0. " TMR00 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
|
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rgroup.long 0x30++0x03
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line.long 0x00 "TIMER0_ERR_TYPE,TIMER0 Error Type Status Register"
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bitfld.long 0x00 14.--15. " TERR7 ,Error type for timer 7" "No Error,Counter Overflow,PER,WID or DLY"
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bitfld.long 0x00 12.--13. " TERR6 ,Error type for timer 6" "No Error,Counter Overflow,PER,WID or DLY"
|
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bitfld.long 0x00 10.--11. " TERR5 ,Error type for timer 5" "No Error,Counter Overflow,PER,WID or DLY"
|
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bitfld.long 0x00 8.--9. " TERR4 ,Error type for timer 4" "No Error,Counter Overflow,PER,WID or DLY"
|
|
textline " "
|
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bitfld.long 0x00 6.--7. " TERR3 ,Error type for timer 3" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 4.--5. " TERR2 ,Error type for timer 2" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 2.--3. " TERR1 ,Error type for timer 1" "No Error,Counter Overflow,PER,WID or DLY"
|
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bitfld.long 0x00 0.--1. " TERR0 ,Error type for timer 0" "No Error,Counter Overflow,PER,WID or DLY"
|
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textline " "
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wgroup.long 0x34++0x0B
|
|
line.long 0x00 "TIMER0_BCAST_PER,TIMER0 Broadcast Period Register"
|
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line.long 0x04 "TIMER0_BCAST_WID,TIMER0 Broadcast Width Register"
|
|
line.long 0x08 "TIMER0_BCAST_DLY,TIMER0 Broadcast Delay Register"
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group.long 0x5C++0x03
|
|
line.long 0x00 "TIMER0_TMR0_CFG,TIMER0 Timer 0 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x5C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR0_CNT,TIMER0 Timer 0 Counter Register"
|
|
group.long (0x5C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR0_PER,TIMER0 Timer 0 Period Register"
|
|
line.long 0x04 "TIMER0_TMR0_WID,TIMER0 Timer 0 Width Register"
|
|
line.long 0x08 "TIMER0_TMR0_DLY,TIMER0 Timer 0 Delay Register"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TIMER0_TMR1_CFG,TIMER0 Timer 1 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x7C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR1_CNT,TIMER0 Timer 1 Counter Register"
|
|
group.long (0x7C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR1_PER,TIMER0 Timer 1 Period Register"
|
|
line.long 0x04 "TIMER0_TMR1_WID,TIMER0 Timer 1 Width Register"
|
|
line.long 0x08 "TIMER0_TMR1_DLY,TIMER0 Timer 1 Delay Register"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TIMER0_TMR2_CFG,TIMER0 Timer 2 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x9C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR2_CNT,TIMER0 Timer 2 Counter Register"
|
|
group.long (0x9C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR2_PER,TIMER0 Timer 2 Period Register"
|
|
line.long 0x04 "TIMER0_TMR2_WID,TIMER0 Timer 2 Width Register"
|
|
line.long 0x08 "TIMER0_TMR2_DLY,TIMER0 Timer 2 Delay Register"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TIMER0_TMR3_CFG,TIMER0 Timer 3 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xBC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR3_CNT,TIMER0 Timer 3 Counter Register"
|
|
group.long (0xBC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR3_PER,TIMER0 Timer 3 Period Register"
|
|
line.long 0x04 "TIMER0_TMR3_WID,TIMER0 Timer 3 Width Register"
|
|
line.long 0x08 "TIMER0_TMR3_DLY,TIMER0 Timer 3 Delay Register"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TIMER0_TMR4_CFG,TIMER0 Timer 4 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xDC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR4_CNT,TIMER0 Timer 4 Counter Register"
|
|
group.long (0xDC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR4_PER,TIMER0 Timer 4 Period Register"
|
|
line.long 0x04 "TIMER0_TMR4_WID,TIMER0 Timer 4 Width Register"
|
|
line.long 0x08 "TIMER0_TMR4_DLY,TIMER0 Timer 4 Delay Register"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TIMER0_TMR5_CFG,TIMER0 Timer 5 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xFC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR5_CNT,TIMER0 Timer 5 Counter Register"
|
|
group.long (0xFC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR5_PER,TIMER0 Timer 5 Period Register"
|
|
line.long 0x04 "TIMER0_TMR5_WID,TIMER0 Timer 5 Width Register"
|
|
line.long 0x08 "TIMER0_TMR5_DLY,TIMER0 Timer 5 Delay Register"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TIMER0_TMR6_CFG,TIMER0 Timer 6 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x11C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR6_CNT,TIMER0 Timer 6 Counter Register"
|
|
group.long (0x11C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR6_PER,TIMER0 Timer 6 Period Register"
|
|
line.long 0x04 "TIMER0_TMR6_WID,TIMER0 Timer 6 Width Register"
|
|
line.long 0x08 "TIMER0_TMR6_DLY,TIMER0 Timer 6 Delay Register"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TIMER0_TMR7_CFG,TIMER0 Timer 7 Configuration Register"
|
|
bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TGLTRIG ,Slave trigger toggle enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.long 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.long 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.long 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.long 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x13C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR7_CNT,TIMER0 Timer 7 Counter Register"
|
|
group.long (0x13C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR7_PER,TIMER0 Timer 7 Period Register"
|
|
line.long 0x04 "TIMER0_TMR7_WID,TIMER0 Timer 7 Width Register"
|
|
line.long 0x08 "TIMER0_TMR7_DLY,TIMER0 Timer 7 Delay Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "WDOG (Watchdog Timer)"
|
|
tree "WDOG0"
|
|
base ad:0x31008000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WDOG0_CTL,WDOG0 Control Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 16. " WDWE ,Watchdog window event" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 15. " WDRO ,Watch dog roll-over" "Not expired,Expired"
|
|
hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch dog enable"
|
|
if (((per.l(ad:0x31008000))&0xFF0)==0xAD0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDOG0_CNT,WDOG0 Count Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "WDOG0_CNT,WDOG0 Count Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "WDOG0_STAT,WDOG0 Watchdog Timer Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WDOG0_WIN,WDOG0 Watchdog Timer Window Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDOG1"
|
|
base ad:0x31008800
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WDOG1_CTL,WDOG1 Control Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 16. " WDWE ,Watchdog window event" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 15. " WDRO ,Watch dog roll-over" "Not expired,Expired"
|
|
hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch dog enable"
|
|
if (((per.l(ad:0x31008800))&0xFF0)==0xAD0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDOG1_CNT,WDOG1 Count Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "WDOG1_CNT,WDOG1 Count Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "WDOG1_STAT,WDOG1 Watchdog Timer Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WDOG1_WIN,WDOG1 Watchdog Timer Window Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDOG2"
|
|
base ad:0x31009000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WDOG2_CTL,WDOG2 Control Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 16. " WDWE ,Watchdog window event" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 15. " WDRO ,Watch dog roll-over" "Not expired,Expired"
|
|
hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch dog enable"
|
|
if (((per.l(ad:0x31009000))&0xFF0)==0xAD0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDOG2_CNT,WDOG2 Count Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "WDOG2_CNT,WDOG2 Count Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "WDOG2_STAT,WDOG2 Watchdog Timer Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WDOG2_WIN,WDOG2 Watchdog Timer Window Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CNT (General-Purpose Counter)"
|
|
base ad:0x3100B000
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CNT0_CFG,CNT0 Configuration Register"
|
|
bitfld.long 0x00 15. " INPDIS ,CUD and CDG pin input disable" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " BNDMODE ,Boundary register mode" "BND_COMP,BND_ZERO,BND_CAPT,BND_AEXT"
|
|
bitfld.long 0x00 11. " ZMZC ,CZM zeros counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CNTMODE ,Counter operating mode" "QUAD_ENC,BIN_ENC,UD_CNT,,DIR_CNT,DIR_TMR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIVMODE ,Divider mode" "Weighted,Non weighted"
|
|
bitfld.long 0x00 6. " CZMINV ,CZM pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 5. " CUDINV ,CUD pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 4. " CDGINV ,CDG pin polarity invert" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIVNTV ,Non-debounced inputs to divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DIVEN ,Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DEBEN ,Debounce enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT0_IMSK,CNT0 Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " DCHNG ,Direction change interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " DERR ,Direction error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MERR ,M value programming error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 11. " STP ,Stop detect interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CZMZ ,Counter zeroed by zero marker interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " CZME ,Zero marker error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " CZM ,CZM pin/pushbutton interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " CZERO ,CNT_CNTR counts to zero interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " COV15 ,Bit 15 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " COV31 ,Bit 31 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " MAXC ,Max count interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " MINC ,Min count interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DC ,Downcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " UC ,Upcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " IC ,Illegal Gray/binary code interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "CNT0_STAT,CNT0 Status Register"
|
|
eventfld.long 0x08 14. " DCHNG ,Direction change interrupt enable" "0,1"
|
|
eventfld.long 0x08 13. " DERR ,Direction error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " MERR ,M value programming error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 11. " STP ,Stop detect interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CZMZ ,Counter zeroed by zero marker interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " CZME ,Zero marker error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " CZM ,CZM pin/pushbutton interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " CZERO ,CNT_CNTR counts to zero interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 6. " COV15 ,Bit 15 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " COV31 ,Bit 31 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " MAXC ,Max count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " MINC ,Min count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 2. " DC ,Down count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " UC ,Up count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " IC ,Illegal Gray/binary code interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "CNT0_CMD,CNT0 Command Register"
|
|
bitfld.long 0x0C 12. " W1ZMONCE ,Write 1 zero marker clear once enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " W1LMAXMIN ,Write 1 MAX copy from MIN" "No effect,Copy"
|
|
bitfld.long 0x0C 9. " W1LMAXCNT ,Write 1 MAX capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 8. " W1LMAXZERO ,Write 1 MAX to zero" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " W1LMINMAX ,Write 1 MIN copy from MAX" "No effect,Copy"
|
|
bitfld.long 0x0C 5. " W1LMINCNT ,Write 1 MIN capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 4. " W1LMINZERO ,Write 1 MIN to zero" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " W1LCNTMAX ,Write 1 CNTR load from MAX" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " W1LCNTMIN ,Write 1 CNTR load from MIN" "No effect,Load"
|
|
bitfld.long 0x0C 0. " W1LCNTZERO ,Write 1 CNTR to zero" "No effect,Clear"
|
|
line.long 0x10 "CNT0_DEBNCE,CNT0 Debounce Register"
|
|
bitfld.long 0x10 0.--4. " DPRESCALE ,Debounce prescale" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,?..."
|
|
line.long 0x14 "CNT0_CNTR,CNT0 Counter Register"
|
|
line.long 0x18 "CNT0_MAX,CNT0 Maximum Count Register"
|
|
line.long 0x1C "CNT0_MIN,CNT0 Minimum Count Register"
|
|
line.long 0x20 "CNT0_MDIV,CNT0 M Value For Divider"
|
|
hexmask.long.word 0x20 0.--15. 1. " MDIV ,M value for divider"
|
|
line.long 0x24 "CNT0_NDIV,CNT0 N Value For Divider"
|
|
hexmask.long.word 0x24 0.--15. 1. " NDIV ,N value for divider"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACM (ADC Control Module)"
|
|
base ad:0x31020000
|
|
width 15.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "ACM_CTL,ACM Control Register"
|
|
bitfld.long 0x00 15. " EPS ,External peripheral select" "Half SPORT A,Half SPORT B"
|
|
bitfld.long 0x00 14. " OTSEL ,Order trigger select" "TMR0,TMR1"
|
|
bitfld.long 0x00 13. " AOREN ,Automatic order reset enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ORST ,Order register reset" "No effect,Reset"
|
|
bitfld.long 0x00 11. " CLKMOD ,ADC clock mode" "Continuous,Gated"
|
|
bitfld.long 0x00 10. " CLKPOL ,Clock polarity" "Falling Edge,Rising Edge"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSPOL ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 8. " TRGPOL1 ,Trigger polarity TMR1" "Rising Edge,Falling Edge"
|
|
bitfld.long 0x00 7. " TRGPOL0 ,Trigger polarity TMR0" "Rising Edge,Falling Edge"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TRGSEL1 ,Trigger select TMR1" "Trigger 0,Trigger 1,Trigger 2,Trigger 3"
|
|
bitfld.long 0x00 3.--4. " TRGSEL0 ,Trigger select TMR0" "Trigger 0,Trigger 1,Trigger 2,Trigger 3"
|
|
bitfld.long 0x00 2. " TMR1EN ,TMR1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TMR0EN ,TMR0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,ACM enable" "Disabled,Enabled"
|
|
line.long 0x04 "ACM_TC0,ACM Timing Configuration 0 Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " SC ,Setup cycle"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CKDIV ,Clock divisor"
|
|
line.long 0x08 "ACM_TC1,ACM Timing Configuration 1 Register"
|
|
bitfld.long 0x08 12.--15. " ZC ,Zero cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " HC ,Hold cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CSW ,Chip select width"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ACM_STAT,ACM Status Register"
|
|
bitfld.long 0x00 4.--7. " CEVNT ,Current event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " ECOM1 ,Event completion 1" "No status,Complete"
|
|
bitfld.long 0x00 2. " ECOM0 ,Event completion 0" "No status,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMISS ,Event(s) missed" "No Missed Event(s),Missed Event(s)"
|
|
bitfld.long 0x00 0. " BSY ,Busy" "Idle,Busy"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "ACM_EVSTAT,ACM Event Complete Status Register"
|
|
eventfld.long 0x00 17. " ECOM1S ,Event complete 1 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 16. " ECOM0S ,Event complete 0 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 15. " EV15 ,Event 15 status" "No conversion,Conversion done"
|
|
textline " "
|
|
eventfld.long 0x00 14. " EV14 ,Event 14 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 13. " EV13 ,Event 13 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 12. " EV12 ,Event 12 status" "No conversion,Conversion done"
|
|
textline " "
|
|
eventfld.long 0x00 11. " EV11 ,Event 11 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 10. " EV10 ,Event 10 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 9. " EV9 ,Event 9 status" "No conversion,Conversion done"
|
|
textline " "
|
|
eventfld.long 0x00 8. " EV8 ,Event 8 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 7. " EV7 ,Event 7 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 6. " EV6 ,Event 6 status" "No conversion,Conversion done"
|
|
textline " "
|
|
eventfld.long 0x00 5. " EV5 ,Event 5 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 4. " EV4 ,Event 4 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 3. " EV3 ,Event 3 status" "No conversion,Conversion done"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EV2 ,Event 2 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 1. " EV1 ,Event 1 status" "No conversion,Conversion done"
|
|
eventfld.long 0x00 0. " EV0 ,Event 0 status" "No conversion,Conversion done"
|
|
line.long 0x04 "ACM_EVMSK,ACM Event Complete Interrupt Mask Register"
|
|
bitfld.long 0x04 17. " IECOM1 ,Event complete 1 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 16. " IECOM0 ,Event complete 0 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 15. " EV15 ,Event 15 interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x04 14. " EV14 ,Event 14 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 13. " EV13 ,Event 13 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 12. " EV12 ,Event 12 interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EV11 ,Event 11 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 10. " EV10 ,Event 10 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 9. " EV9 ,Event 9 interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EV8 ,Event 8 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 7. " EV7 ,Event 7 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 6. " EV6 ,Event 6 interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EV5 ,Event 5 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 4. " EV4 ,Event 4 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 3. " EV3 ,Event 3 interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EV2 ,Event 2 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 1. " EV1 ,Event 1 interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x04 0. " EV0 ,Event 0 interrupt enable" "Mask,Unmask"
|
|
line.long 0x08 "ACM_MEVSTAT,ACM Missed Event Status Register"
|
|
eventfld.long 0x08 15. " EV15 ,Event 15 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 14. " EV14 ,Event 14 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 13. " EV13 ,Event 13 missed" "Not missed,Missed"
|
|
textline " "
|
|
eventfld.long 0x08 12. " EV12 ,Event 12 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 11. " EV11 ,Event 11 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 10. " EV10 ,Event 10 missed" "Not missed,Missed"
|
|
textline " "
|
|
eventfld.long 0x08 9. " EV9 ,Event 9 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 8. " EV8 ,Event 8 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 7. " EV7 ,Event 7 missed" "Not missed,Missed"
|
|
textline " "
|
|
eventfld.long 0x08 6. " EV6 ,Event 6 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 5. " EV5 ,Event 5 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 4. " EV4 ,Event 4 missed" "Not missed,Missed"
|
|
textline " "
|
|
eventfld.long 0x08 3. " EV3 ,Event 3 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 2. " EV2 ,Event 2 missed" "Not missed,Missed"
|
|
eventfld.long 0x08 1. " EV1 ,Event 1 missed" "Not missed,Missed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " EV0 ,Event 0 missed" "Not missed,Missed"
|
|
line.long 0x0C "ACM_MEVMSK,ACM Missed Event Interrupt Mask Register"
|
|
bitfld.long 0x0C 15. " EV15 ,Event 15 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 14. " EV14 ,Event 14 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 13. " EV13 ,Event 13 missed interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " EV12 ,Event 12 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 11. " EV11 ,Event 11 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 10. " EV10 ,Event 10 missed interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " EV9 ,Event 9 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 8. " EV8 ,Event 8 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 7. " EV7 ,Event 7 missed interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " EV6 ,Event 6 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 5. " EV5 ,Event 5 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 4. " EV4 ,Event 4 missed interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " EV3 ,Event 3 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 2. " EV2 ,Event 2 missed interrupt enable" "Mask,Unmask"
|
|
bitfld.long 0x0C 1. " EV1 ,Event 1 missed interrupt enable" "Mask,Unmask"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " EV0 ,Event 0 missed interrupt enable" "Mask,Unmask"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ACM_EVCTL0,ACM Event 0 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACM_EVCTL1,ACM Event 1 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ACM_EVCTL2,ACM Event 2 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ACM_EVCTL3,ACM Event 3 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ACM_EVCTL4,ACM Event 4 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ACM_EVCTL5,ACM Event 5 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ACM_EVCTL6,ACM Event 6 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ACM_EVCTL7,ACM Event 7 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACM_EVCTL8,ACM Event 8 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ACM_EVCTL9,ACM Event 9 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ACM_EVCTL10,ACM Event 10 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ACM_EVCTL11,ACM Event 11 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ACM_EVCTL12,ACM Event 12 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ACM_EVCTL13,ACM Event 13 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ACM_EVCTL14,ACM Event 14 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ACM_EVCTL15,ACM Event 15 Control Register"
|
|
bitfld.long 0x00 1.--5. " EPF ,Event parameter field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ENAEV ,Enable event" "Disabled,Enabled"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ACM_EVTIME0,ACM Event 0 Time Register"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ACM_EVTIME1,ACM Event 1 Time Register"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ACM_EVTIME2,ACM Event 2 Time Register"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ACM_EVTIME3,ACM Event 3 Time Register"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "ACM_EVTIME4,ACM Event 4 Time Register"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "ACM_EVTIME5,ACM Event 5 Time Register"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "ACM_EVTIME6,ACM Event 6 Time Register"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "ACM_EVTIME7,ACM Event 7 Time Register"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "ACM_EVTIME8,ACM Event 8 Time Register"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "ACM_EVTIME9,ACM Event 9 Time Register"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "ACM_EVTIME10,ACM Event 10 Time Register"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ACM_EVTIME11,ACM Event 11 Time Register"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "ACM_EVTIME12,ACM Event 12 Time Register"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ACM_EVTIME13,ACM Event 13 Time Register"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "ACM_EVTIME14,ACM Event 14 Time Register"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "ACM_EVTIME15,ACM Event 15 Time Register"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "ACM_EVORD0,ACM Event 0 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "ACM_EVORD1,ACM Event 1 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "ACM_EVORD2,ACM Event 2 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "ACM_EVORD3,ACM Event 3 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "ACM_EVORD4,ACM Event 4 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ACM_EVORD5,ACM Event 5 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "ACM_EVORD6,ACM Event 6 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "ACM_EVORD7,ACM Event 7 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "ACM_EVORD8,ACM Event 8 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "ACM_EVORD9,ACM Event 9 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "ACM_EVORD10,ACM Event 10 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "ACM_EVORD11,ACM Event 11 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "ACM_EVORD12,ACM Event 12 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "ACM_EVORD13,ACM Event 13 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "ACM_EVORD14,ACM Event 14 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "ACM_EVORD15,ACM Event 15 Order Register"
|
|
bitfld.long 0x00 17. " EVSTAT ,Event status" "0,1"
|
|
bitfld.long 0x00 16. " MEVSTAT ,Missed event status" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ORD ,Order of event completion"
|
|
rgroup.long 0xE8++0x07
|
|
line.long 0x00 "ACM_TMR0,ACM Timer 0 Register"
|
|
line.long 0x04 "ACM_TMR1,ACM Timer 1 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN0"
|
|
base ad:0x31000200
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CAN0_MC1,CAN0 Mailbox Configuration 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 enable/disable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CAN0_MD1,CAN0 Mailbox Direction 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit/receive" "Transmit,Receive"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CAN0_TRS1_SET/CLR,CAN0 Transmission Request Set/Clear 1 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB15 ,Mailbox 15 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB14 ,Mailbox 14 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB13 ,Mailbox 13 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB12 ,Mailbox 12 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB11 ,Mailbox 11 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB10 ,Mailbox 10 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB09 ,Mailbox 9 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB08 ,Mailbox 8 transmit request" "Not requested,Requested"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CAN0_TA1,CAN0 Transmission Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit acknowledge" "Failure,Success"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "CAN0_AA1,CAN0 Abort Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CAN0_RMP1,CAN0 Receive Message Pending 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 message pending" "Not pending,Pending"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CAN0_RML1,CAN0 Receive Message Lost 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 message lost" "Not lost,Lost"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CAN0_MBTIF1,CAN0 Mailbox Transmit Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CAN0_MBRIF1,CAN0 Mailbox Receive Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CAN0_MBIM1,CAN0 Mailbox Interrupt Mask 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CAN0_RFH1,CAN0 Remote Frame Handling 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CAN0_OPSS1,CAN0 Overwrite Protection/Single Shot Transmission 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 overwrite protection enable" "Disabled,Enabled"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CAN0_MC2,CAN0 Mailbox Configuration 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 enable/disable" "Disabled,Enabled"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CAN0_MD2,CAN0 Mailbox Direction 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit/receive" "Transmit,Receive"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CAN0_TRS2_SET/CLR,CAN0 Transmission Request Set/Clear 2 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB31 ,Mailbox 31 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB30 ,Mailbox 30 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB29 ,Mailbox 29 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB28 ,Mailbox 28 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB27 ,Mailbox 27 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB26 ,Mailbox 26 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB25 ,Mailbox 25 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB24 ,Mailbox 24 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x00 7. 0x04 7. " MB23 ,Mailbox 23 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x04 6. " MB22 ,Mailbox 22 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x04 5. " MB21 ,Mailbox 21 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 4. 0x00 4. 0x04 4. " MB20 ,Mailbox 20 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 3. 0x00 3. 0x04 3. " MB19 ,Mailbox 19 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 2. 0x00 2. 0x04 2. " MB18 ,Mailbox 18 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x04 1. " MB17 ,Mailbox 17 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 0. 0x00 0. 0x04 0. " MB16 ,Mailbox 16 transmit request" "Not requested,Requested"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CAN0_TA2,CAN0 Transmission Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit acknowledge" "Failure,Success"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CAN0_AA2,CAN0 Abort Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "CAN0_RMP2,CAN0 Receive Message Pending 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 message pending" "Not pending,Pending"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "CAN0_RML2,CAN0 Receive Message Lost 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 message lost" "Not lost,Lost"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CAN0_MBTIF2,CAN0 Mailbox Transmit Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "CAN0_MBRIF2,CAN0 Mailbox Receive Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "CAN0_MBIM2,CAN0 Mailbox Interrupt Mask 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "CAN0_RFH2,CAN0 Remote Frame Handling 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "CAN0_OPSS2,CAN0 Overwrite Protection/Single Shot Transmission 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "CAN0_CLK,CAN0 Clock Register"
|
|
hexmask.word 0x00 0.--9. 1. " BRP ,Bit rate prescaler"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "CAN0_TIMING,CAN0 Timing Register"
|
|
bitfld.word 0x00 8.--9. " SJW ,Synchronization jump width" "1,2,3,4"
|
|
bitfld.word 0x00 7. " SAM ,Sampling" "Normal sampling,Over sampling"
|
|
bitfld.word 0x00 4.--6. " TSEG2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " TSEG1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "CAN0_DBG,CAN0 Debug Register"
|
|
bitfld.word 0x00 15. " CDE ,CAN debug mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MRB ,Mode read back" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MAA ,Mode auto acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DIL ,Disable internal loop" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DTO ,Disable tx output pin" "No,Yes"
|
|
bitfld.word 0x00 1. " DRI ,Disable receive input pin" "No,Yes"
|
|
bitfld.word 0x00 0. " DEC ,Disable transmit and receive error counters" "No,Yes"
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "CAN0_STAT,CAN0 Status Register"
|
|
bitfld.word 0x00 15. " REC ,Receive mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " TRM ,Transmit mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--12. " MBPTR ,Mailbox pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CCA ,CAN configuration mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CSA ,CAN suspend mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EBO ,CAN error bus off mode (TXECNT)" "Below 256,Above bus off limit"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EP ,CAN error passive mode (TXECNT and/or RXECNT)" "Below 128,Above EP level"
|
|
bitfld.word 0x00 1. " WR ,CAN receive warning flag" "Below limit,At limit"
|
|
bitfld.word 0x00 0. " WT ,CAN transmit warning flag" "Below limit,At limit"
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "CAN0_CEC,CAN0 Error Counter Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TXECNT ,Transmit error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXECNT ,Receive error counter"
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "CAN0_GIS,CAN0 Global CAN Interrupt Status Register"
|
|
eventfld.word 0x00 10. " ADIS ,Access denied interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 8. " UCEIS ,Universal counter exceeded interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RMLIS ,Receive message lost interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 6. " AAIS ,Abort acknowledge interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 5. " UIAIS ,Unimplemented address interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " WUIS ,Wake up interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 3. " BOIS ,Bus off interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " EPIS ,Error passive interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 1. " EWRIS ,Error warning receive interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 0. " EWTIS ,Error warning transmit interrupt status" "No interrupt,Interrupt"
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "CAN0_GIM,CAN0 Global CAN Interrupt Mask Register"
|
|
bitfld.word 0x00 10. " ADIM ,Access denied interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 8. " UCEIM ,Universal counter exceeded interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RMLIM ,Receive message lost interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 6. " AAIM ,Abort acknowledge interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIM ,Unimplemented address interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " WUIM ,Wake up interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 3. " BOIM ,Bus off interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " EPIM ,Error passive interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIM ,Error warning receive interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 0. " EWTIM ,Error warning transmit interrupt mask" "Masked,Unmasked"
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "CAN0_GIF,CAN0 Global CAN Interrupt Flag Register"
|
|
bitfld.word 0x00 10. " ADIF ,Access denied interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 8. " UCEIF ,Universal counter exceeded interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 7. " RMLIF ,Receive message lost interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 6. " AAIF ,Abort acknowledge interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIF ,Unimplemented address interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 4. " WUIF ,Wake up interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 3. " BOIF ,Bus off interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 2. " EPIF ,Error passive interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIF ,Error warning receive interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 0. " EWTIF ,Error warning transmit interrupt flag" "Not latched,Latched"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "CAN0_CTL,CAN0 Master Control Register"
|
|
bitfld.word 0x00 7. " CCR ,CAN configuration mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " CSR ,CAN suspend mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " SMR ,Sleep mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " WBA ,Wake up on CAN bus activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABO ,Auto bus on" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DNM ,Device net mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SRS ,Software reset" "No effect,Reset"
|
|
group.word 0xA4++0x01
|
|
line.word 0x00 "CAN0_INT,CAN0 Interrupt Pending Register"
|
|
rbitfld.word 0x00 7. " CANRX ,Serial input from transceiver" "Dominant,Recessive"
|
|
rbitfld.word 0x00 6. " CANTX ,Serial input to transceiver" "Dominant,Recessive"
|
|
bitfld.word 0x00 3. " SMACK ,Sleep mode acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " GIRQ ,Global CAN interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 1. " MBTIRQ ,Mailbox transmit interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 0. " MBRIRQ ,Mailbox receive interrupt output" "No flag set,One or more flag set"
|
|
group.word 0xAC++0x01
|
|
line.word 0x00 "CAN0_MBTD,CAN0 Temporary Mailbox Disable Register"
|
|
bitfld.word 0x00 7. " TDR ,Temporary disable request" "No,Yes"
|
|
rbitfld.word 0x00 6. " TDA ,Temporary disable acknowledge" "No,Yes"
|
|
bitfld.word 0x00 0.--4. " TDPTR ,Temporary disable pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "CAN0_EWR,CAN0 Error Counter Warning Level Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " EWLTEC ,Transmit error warning limit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EWLREC ,Receive error warning limit"
|
|
group.word 0xB4++0x01
|
|
line.word 0x00 "CAN0_ESR,CAN0 Error Status Register"
|
|
eventfld.word 0x00 7. " FER ,Form error" "No error,Error"
|
|
eventfld.word 0x00 6. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.word 0x00 5. " SAO ,Stuck at dominant" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 4. " CRCE ,CRC error" "No error,Error"
|
|
eventfld.word 0x00 3. " SER ,Stuff bit error" "No error,Error"
|
|
eventfld.word 0x00 2. " ACKE ,Acknowledge error" "No error,Error"
|
|
group.word 0xC4++0x01
|
|
line.word 0x00 "CAN0_UCCNT,CAN0 Universal Counter Register"
|
|
group.word 0xC8++0x01
|
|
line.word 0x00 "CAN0_UCRC,CAN0 Universal Counter Reload/Capture Register"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x02)
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN0_UCCNF,CAN0 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Reload"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
else
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN0_UCCNF,CAN0 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Clear"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
endif
|
|
textline " "
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "CAN0_AM00L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x100+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM00H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "CAN0_AM01L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x108+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM01H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAN0_AM02L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x110+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM02H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "CAN0_AM03L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x118+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM03H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "CAN0_AM04L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x120+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM04H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "CAN0_AM05L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x128+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM05H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "CAN0_AM06L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x130+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM06H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "CAN0_AM07L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x138+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM07H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x140++0x01
|
|
line.word 0x00 "CAN0_AM08L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x140+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM08H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "CAN0_AM09L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x148+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM09H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x150++0x01
|
|
line.word 0x00 "CAN0_AM10L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x150+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM10H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x158++0x01
|
|
line.word 0x00 "CAN0_AM11L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x158+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM11H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x160++0x01
|
|
line.word 0x00 "CAN0_AM12L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x160+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM12H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x168++0x01
|
|
line.word 0x00 "CAN0_AM13L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x168+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM13H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x170++0x01
|
|
line.word 0x00 "CAN0_AM14L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x170+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM14H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x178++0x01
|
|
line.word 0x00 "CAN0_AM15L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x178+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM15H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "CAN0_AM16L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x180+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM16H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x188++0x01
|
|
line.word 0x00 "CAN0_AM17L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x188+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM17H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x190++0x01
|
|
line.word 0x00 "CAN0_AM18L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x190+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM18H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x198++0x01
|
|
line.word 0x00 "CAN0_AM19L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x198+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM19H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A0++0x01
|
|
line.word 0x00 "CAN0_AM20L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM20H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A8++0x01
|
|
line.word 0x00 "CAN0_AM21L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1A8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM21H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B0++0x01
|
|
line.word 0x00 "CAN0_AM22L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1B0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM22H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B8++0x01
|
|
line.word 0x00 "CAN0_AM23L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1B8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM23H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C0++0x01
|
|
line.word 0x00 "CAN0_AM24L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM24H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C8++0x01
|
|
line.word 0x00 "CAN0_AM25L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1C8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM25H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "CAN0_AM26L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1D0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM26H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D8++0x01
|
|
line.word 0x00 "CAN0_AM27L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1D8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM27H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E0++0x01
|
|
line.word 0x00 "CAN0_AM28L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM28H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "CAN0_AM29L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1E8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM29H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F0++0x01
|
|
line.word 0x00 "CAN0_AM30L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1F0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM30H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F8++0x01
|
|
line.word 0x00 "CAN0_AM31L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1F8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM31H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x200+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x200+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x200+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x200+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB00_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x200+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB00_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x200+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB00_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x200+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB00_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x200+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB00_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x220++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x220+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x220+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x220+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x220+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB01_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x220+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB01_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x220+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB01_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x220+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB01_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x220+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB01_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x240++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x240+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x240+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x240+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x240+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB02_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x240+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB02_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x240+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB02_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x240+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB02_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x240+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB02_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x260++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x260+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x260+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x260+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x260+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB03_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x260+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB03_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x260+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB03_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x260+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB03_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x260+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB03_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x280++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x280+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x280+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x280+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x280+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB04_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x280+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB04_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x280+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB04_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x280+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB04_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x280+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB04_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2A0++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB05_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x2A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB05_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB05_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB05_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x2A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB05_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2C0++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB06_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x2C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB06_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB06_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB06_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x2C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB06_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2E0++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB07_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x2E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB07_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB07_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB07_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x2E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB07_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x300++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x300+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x300+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x300+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x300+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB08_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x300+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB08_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x300+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB08_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x300+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB08_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x300+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB08_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x320++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x320+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x320+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x320+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x320+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB09_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x320+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB09_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x320+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB09_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x320+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB09_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x320+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB09_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x340++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x340+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x340+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x340+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x340+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB10_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x340+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB10_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x340+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB10_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x340+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB10_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x340+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB10_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x360++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x360+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x360+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x360+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x360+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB11_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x360+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB11_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x360+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB11_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x360+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB11_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x360+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB11_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x380++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x380+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x380+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x380+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x380+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB12_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x380+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB12_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x380+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB12_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x380+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB12_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x380+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB12_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3A0++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB13_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x3A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB13_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB13_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB13_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x3A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB13_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3C0++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB14_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x3C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB14_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB14_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB14_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x3C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB14_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3E0++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB15_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x3E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB15_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB15_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB15_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x3E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB15_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x400++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x400+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x400+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x400+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x400+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB16_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x400+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB16_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x400+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB16_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x400+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB16_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x400+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB16_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x420++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x420+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x420+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x420+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x420+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB17_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x420+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB17_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x420+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB17_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x420+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB17_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x420+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB17_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x440++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x440+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x440+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x440+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x440+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB18_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x440+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB18_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x440+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB18_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x440+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB18_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x440+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB18_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x460++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x460+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x460+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x460+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x460+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB19_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x460+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB19_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x460+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB19_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x460+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB19_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x460+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB19_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x480++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x480+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x480+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x480+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x480+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB20_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x480+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB20_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x480+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB20_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x480+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB20_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x480+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB20_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4A0++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB21_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x4A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB21_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB21_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB21_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x4A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB21_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4C0++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB22_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x4C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB22_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB22_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB22_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x4C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB22_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4E0++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB23_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x4E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB23_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB23_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB23_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x4E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB23_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x500++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x500+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x500+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x500+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x500+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB24_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x500+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB24_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x500+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB24_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x500+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB24_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x500+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB24_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x520++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x520+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x520+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x520+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x520+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB25_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x520+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB25_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x520+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB25_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x520+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB25_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x520+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB25_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x540++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x540+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x540+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x540+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x540+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB26_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x540+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB26_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x540+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB26_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x540+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB26_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x540+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB26_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x560++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x560+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x560+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x560+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x560+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB27_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x560+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB27_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x560+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB27_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x560+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB27_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x560+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB27_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x580++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x580+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x580+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x580+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x580+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB28_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x580+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB28_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x580+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB28_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x580+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB28_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x580+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB28_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5A0++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB29_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x5A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB29_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB29_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB29_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x5A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB29_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5C0++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB30_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x5C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB30_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB30_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB30_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x5C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB30_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5E0++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB31_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000200+0xCC))&0x0F)==0x01)
|
|
group.word (0x5E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB31_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB31_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB31_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x5E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB31_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x31000A00
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CAN1_MC1,CAN1 Mailbox Configuration 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 enable/disable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CAN1_MD1,CAN1 Mailbox Direction 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit/receive" "Transmit,Receive"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CAN1_TRS1_SET/CLR,CAN1 Transmission Request Set/Clear 1 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB15 ,Mailbox 15 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB14 ,Mailbox 14 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB13 ,Mailbox 13 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB12 ,Mailbox 12 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB11 ,Mailbox 11 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB10 ,Mailbox 10 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB09 ,Mailbox 9 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB08 ,Mailbox 8 transmit request" "Not requested,Requested"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CAN1_TA1,CAN1 Transmission Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit acknowledge" "Failure,Success"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "CAN1_AA1,CAN1 Abort Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CAN1_RMP1,CAN1 Receive Message Pending 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 message pending" "Not pending,Pending"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CAN1_RML1,CAN1 Receive Message Lost 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 message lost" "Not lost,Lost"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CAN1_MBTIF1,CAN1 Mailbox Transmit Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CAN1_MBRIF1,CAN1 Mailbox Receive Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CAN1_MBIM1,CAN1 Mailbox Interrupt Mask 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CAN1_RFH1,CAN1 Remote Frame Handling 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CAN1_OPSS1,CAN1 Overwrite Protection/Single Shot Transmission 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 overwrite protection enable" "Disabled,Enabled"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CAN1_MC2,CAN1 Mailbox Configuration 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 enable/disable" "Disabled,Enabled"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CAN1_MD2,CAN1 Mailbox Direction 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit/receive" "Transmit,Receive"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CAN1_TRS2_SET/CLR,CAN1 Transmission Request Set/Clear 2 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB31 ,Mailbox 31 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB30 ,Mailbox 30 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB29 ,Mailbox 29 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB28 ,Mailbox 28 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB27 ,Mailbox 27 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB26 ,Mailbox 26 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB25 ,Mailbox 25 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB24 ,Mailbox 24 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x00 7. 0x04 7. " MB23 ,Mailbox 23 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x04 6. " MB22 ,Mailbox 22 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x04 5. " MB21 ,Mailbox 21 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 4. 0x00 4. 0x04 4. " MB20 ,Mailbox 20 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 3. 0x00 3. 0x04 3. " MB19 ,Mailbox 19 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 2. 0x00 2. 0x04 2. " MB18 ,Mailbox 18 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x04 1. " MB17 ,Mailbox 17 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 0. 0x00 0. 0x04 0. " MB16 ,Mailbox 16 transmit request" "Not requested,Requested"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CAN1_TA2,CAN1 Transmission Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit acknowledge" "Failure,Success"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CAN1_AA2,CAN1 Abort Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "CAN1_RMP2,CAN1 Receive Message Pending 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 message pending" "Not pending,Pending"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "CAN1_RML2,CAN1 Receive Message Lost 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 message lost" "Not lost,Lost"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CAN1_MBTIF2,CAN1 Mailbox Transmit Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "CAN1_MBRIF2,CAN1 Mailbox Receive Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "CAN1_MBIM2,CAN1 Mailbox Interrupt Mask 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "CAN1_RFH2,CAN1 Remote Frame Handling 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "CAN1_OPSS2,CAN1 Overwrite Protection/Single Shot Transmission 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "CAN1_CLK,CAN1 Clock Register"
|
|
hexmask.word 0x00 0.--9. 1. " BRP ,Bit rate prescaler"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "CAN1_TIMING,CAN1 Timing Register"
|
|
bitfld.word 0x00 8.--9. " SJW ,Synchronization jump width" "1,2,3,4"
|
|
bitfld.word 0x00 7. " SAM ,Sampling" "Normal sampling,Over sampling"
|
|
bitfld.word 0x00 4.--6. " TSEG2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " TSEG1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "CAN1_DBG,CAN1 Debug Register"
|
|
bitfld.word 0x00 15. " CDE ,CAN debug mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MRB ,Mode read back" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MAA ,Mode auto acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DIL ,Disable internal loop" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DTO ,Disable tx output pin" "No,Yes"
|
|
bitfld.word 0x00 1. " DRI ,Disable receive input pin" "No,Yes"
|
|
bitfld.word 0x00 0. " DEC ,Disable transmit and receive error counters" "No,Yes"
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "CAN1_STAT,CAN1 Status Register"
|
|
bitfld.word 0x00 15. " REC ,Receive mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " TRM ,Transmit mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--12. " MBPTR ,Mailbox pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CCA ,CAN configuration mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CSA ,CAN suspend mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EBO ,CAN error bus off mode (TXECNT)" "Below 256,Above bus off limit"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EP ,CAN error passive mode (TXECNT and/or RXECNT)" "Below 128,Above EP level"
|
|
bitfld.word 0x00 1. " WR ,CAN receive warning flag" "Below limit,At limit"
|
|
bitfld.word 0x00 0. " WT ,CAN transmit warning flag" "Below limit,At limit"
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "CAN1_CEC,CAN1 Error Counter Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TXECNT ,Transmit error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXECNT ,Receive error counter"
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "CAN1_GIS,CAN1 Global CAN Interrupt Status Register"
|
|
eventfld.word 0x00 10. " ADIS ,Access denied interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 8. " UCEIS ,Universal counter exceeded interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RMLIS ,Receive message lost interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 6. " AAIS ,Abort acknowledge interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 5. " UIAIS ,Unimplemented address interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " WUIS ,Wake up interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 3. " BOIS ,Bus off interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " EPIS ,Error passive interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 1. " EWRIS ,Error warning receive interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 0. " EWTIS ,Error warning transmit interrupt status" "No interrupt,Interrupt"
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "CAN1_GIM,CAN1 Global CAN Interrupt Mask Register"
|
|
bitfld.word 0x00 10. " ADIM ,Access denied interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 8. " UCEIM ,Universal counter exceeded interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RMLIM ,Receive message lost interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 6. " AAIM ,Abort acknowledge interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIM ,Unimplemented address interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " WUIM ,Wake up interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 3. " BOIM ,Bus off interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " EPIM ,Error passive interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIM ,Error warning receive interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 0. " EWTIM ,Error warning transmit interrupt mask" "Masked,Unmasked"
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "CAN1_GIF,CAN1 Global CAN Interrupt Flag Register"
|
|
bitfld.word 0x00 10. " ADIF ,Access denied interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 8. " UCEIF ,Universal counter exceeded interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 7. " RMLIF ,Receive message lost interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 6. " AAIF ,Abort acknowledge interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIF ,Unimplemented address interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 4. " WUIF ,Wake up interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 3. " BOIF ,Bus off interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 2. " EPIF ,Error passive interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIF ,Error warning receive interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 0. " EWTIF ,Error warning transmit interrupt flag" "Not latched,Latched"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "CAN1_CTL,CAN1 Master Control Register"
|
|
bitfld.word 0x00 7. " CCR ,CAN configuration mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " CSR ,CAN suspend mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " SMR ,Sleep mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " WBA ,Wake up on CAN bus activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABO ,Auto bus on" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DNM ,Device net mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SRS ,Software reset" "No effect,Reset"
|
|
group.word 0xA4++0x01
|
|
line.word 0x00 "CAN1_INT,CAN1 Interrupt Pending Register"
|
|
rbitfld.word 0x00 7. " CANRX ,Serial input from transceiver" "Dominant,Recessive"
|
|
rbitfld.word 0x00 6. " CANTX ,Serial input to transceiver" "Dominant,Recessive"
|
|
bitfld.word 0x00 3. " SMACK ,Sleep mode acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " GIRQ ,Global CAN interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 1. " MBTIRQ ,Mailbox transmit interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 0. " MBRIRQ ,Mailbox receive interrupt output" "No flag set,One or more flag set"
|
|
group.word 0xAC++0x01
|
|
line.word 0x00 "CAN1_MBTD,CAN1 Temporary Mailbox Disable Register"
|
|
bitfld.word 0x00 7. " TDR ,Temporary disable request" "No,Yes"
|
|
rbitfld.word 0x00 6. " TDA ,Temporary disable acknowledge" "No,Yes"
|
|
bitfld.word 0x00 0.--4. " TDPTR ,Temporary disable pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "CAN1_EWR,CAN1 Error Counter Warning Level Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " EWLTEC ,Transmit error warning limit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EWLREC ,Receive error warning limit"
|
|
group.word 0xB4++0x01
|
|
line.word 0x00 "CAN1_ESR,CAN1 Error Status Register"
|
|
eventfld.word 0x00 7. " FER ,Form error" "No error,Error"
|
|
eventfld.word 0x00 6. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.word 0x00 5. " SAO ,Stuck at dominant" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 4. " CRCE ,CRC error" "No error,Error"
|
|
eventfld.word 0x00 3. " SER ,Stuff bit error" "No error,Error"
|
|
eventfld.word 0x00 2. " ACKE ,Acknowledge error" "No error,Error"
|
|
group.word 0xC4++0x01
|
|
line.word 0x00 "CAN1_UCCNT,CAN1 Universal Counter Register"
|
|
group.word 0xC8++0x01
|
|
line.word 0x00 "CAN1_UCRC,CAN1 Universal Counter Reload/Capture Register"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x02)
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN1_UCCNF,CAN1 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Reload"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
else
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN1_UCCNF,CAN1 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Clear"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
endif
|
|
textline " "
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "CAN1_AM00L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x100+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM00H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "CAN1_AM01L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x108+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM01H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAN1_AM02L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x110+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM02H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "CAN1_AM03L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x118+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM03H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "CAN1_AM04L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x120+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM04H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "CAN1_AM05L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x128+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM05H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "CAN1_AM06L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x130+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM06H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "CAN1_AM07L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x138+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM07H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x140++0x01
|
|
line.word 0x00 "CAN1_AM08L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x140+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM08H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "CAN1_AM09L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x148+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM09H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x150++0x01
|
|
line.word 0x00 "CAN1_AM10L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x150+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM10H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x158++0x01
|
|
line.word 0x00 "CAN1_AM11L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x158+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM11H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x160++0x01
|
|
line.word 0x00 "CAN1_AM12L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x160+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM12H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x168++0x01
|
|
line.word 0x00 "CAN1_AM13L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x168+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM13H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x170++0x01
|
|
line.word 0x00 "CAN1_AM14L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x170+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM14H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x178++0x01
|
|
line.word 0x00 "CAN1_AM15L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x178+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM15H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "CAN1_AM16L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x180+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM16H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x188++0x01
|
|
line.word 0x00 "CAN1_AM17L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x188+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM17H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x190++0x01
|
|
line.word 0x00 "CAN1_AM18L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x190+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM18H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x198++0x01
|
|
line.word 0x00 "CAN1_AM19L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x198+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM19H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A0++0x01
|
|
line.word 0x00 "CAN1_AM20L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM20H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A8++0x01
|
|
line.word 0x00 "CAN1_AM21L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1A8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM21H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B0++0x01
|
|
line.word 0x00 "CAN1_AM22L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1B0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM22H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B8++0x01
|
|
line.word 0x00 "CAN1_AM23L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1B8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM23H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C0++0x01
|
|
line.word 0x00 "CAN1_AM24L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM24H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C8++0x01
|
|
line.word 0x00 "CAN1_AM25L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1C8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM25H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "CAN1_AM26L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1D0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM26H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D8++0x01
|
|
line.word 0x00 "CAN1_AM27L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1D8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM27H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E0++0x01
|
|
line.word 0x00 "CAN1_AM28L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM28H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "CAN1_AM29L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1E8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM29H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F0++0x01
|
|
line.word 0x00 "CAN1_AM30L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1F0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM30H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F8++0x01
|
|
line.word 0x00 "CAN1_AM31L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1F8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM31H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x200+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x200+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x200+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x200+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB00_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x200+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB00_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x200+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB00_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x200+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB00_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x200+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB00_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x220++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x220+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x220+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x220+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x220+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB01_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x220+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB01_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x220+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB01_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x220+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB01_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x220+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB01_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x240++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x240+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x240+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x240+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x240+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB02_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x240+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB02_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x240+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB02_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x240+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB02_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x240+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB02_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x260++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x260+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x260+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x260+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x260+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB03_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x260+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB03_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x260+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB03_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x260+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB03_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x260+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB03_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x280++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x280+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x280+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x280+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x280+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB04_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x280+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB04_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x280+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB04_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x280+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB04_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x280+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB04_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2A0++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB05_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x2A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB05_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB05_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB05_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x2A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB05_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2C0++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB06_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x2C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB06_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB06_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB06_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x2C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB06_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2E0++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB07_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x2E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB07_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB07_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB07_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x2E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB07_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x300++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x300+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x300+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x300+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x300+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB08_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x300+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB08_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x300+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB08_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x300+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB08_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x300+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB08_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x320++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x320+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x320+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x320+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x320+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB09_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x320+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB09_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x320+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB09_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x320+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB09_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x320+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB09_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x340++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x340+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x340+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x340+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x340+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB10_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x340+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB10_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x340+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB10_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x340+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB10_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x340+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB10_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x360++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x360+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x360+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x360+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x360+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB11_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x360+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB11_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x360+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB11_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x360+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB11_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x360+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB11_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x380++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x380+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x380+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x380+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x380+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB12_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x380+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB12_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x380+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB12_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x380+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB12_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x380+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB12_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3A0++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB13_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x3A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB13_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB13_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB13_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x3A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB13_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3C0++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB14_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x3C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB14_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB14_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB14_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x3C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB14_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3E0++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB15_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x3E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB15_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB15_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB15_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x3E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB15_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x400++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x400+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x400+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x400+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x400+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB16_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x400+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB16_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x400+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB16_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x400+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB16_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x400+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB16_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x420++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x420+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x420+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x420+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x420+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB17_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x420+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB17_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x420+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB17_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x420+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB17_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x420+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB17_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x440++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x440+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x440+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x440+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x440+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB18_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x440+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB18_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x440+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB18_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x440+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB18_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x440+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB18_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x460++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x460+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x460+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x460+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x460+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB19_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x460+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB19_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x460+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB19_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x460+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB19_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x460+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB19_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x480++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x480+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x480+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x480+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x480+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB20_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x480+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB20_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x480+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB20_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x480+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB20_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x480+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB20_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4A0++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB21_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x4A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB21_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB21_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB21_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x4A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB21_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4C0++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB22_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x4C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB22_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB22_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB22_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x4C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB22_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4E0++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB23_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x4E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB23_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB23_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB23_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x4E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB23_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x500++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x500+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x500+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x500+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x500+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB24_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x500+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB24_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x500+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB24_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x500+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB24_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x500+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB24_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x520++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x520+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x520+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x520+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x520+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB25_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x520+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB25_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x520+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB25_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x520+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB25_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x520+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB25_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x540++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x540+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x540+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x540+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x540+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB26_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x540+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB26_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x540+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB26_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x540+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB26_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x540+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB26_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x560++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x560+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x560+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x560+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x560+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB27_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x560+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB27_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x560+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB27_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x560+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB27_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x560+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB27_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x580++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x580+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x580+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x580+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x580+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB28_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x580+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB28_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x580+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB28_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x580+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB28_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x580+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB28_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5A0++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB29_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x5A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB29_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB29_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB29_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x5A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB29_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5C0++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB30_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x5C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB30_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB30_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB30_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x5C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB30_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5E0++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB31_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x31000A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x5E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB31_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB31_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB31_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x5E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB31_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "MSI (Mobile Storage Interface)"
|
|
base ad:0x31010000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MSI0_CTL,MSI0 Control Register"
|
|
bitfld.long 0x00 25. " INTDMAC ,Use internal DMA controller to perform transfers" "Host,DMA"
|
|
sif !cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 10. " AUTOSTOP ,Send auto stop CCSD" "0,1"
|
|
bitfld.long 0x00 9. " CCSD ,Send Auto Stop CCSD" "Clear bit if MSI does not reset the bit,Send internally generated STOP command"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDABORT ,Abort read data" "No change,Reset"
|
|
bitfld.long 0x00 7. " IRQRESP ,Send IRQ response" "No change,Send"
|
|
bitfld.long 0x00 6. " RDWAIT ,Read wait" "Cleared,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTEN ,Global interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DMARST ,DMA reset" "No change,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FIFORST ,Fifo reset" "No change,Reset"
|
|
bitfld.long 0x00 0. " CTLRST ,Controller reset" "No change,Reset"
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MSI0_CLKDIV,MSI0 Clock Divider Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV0 ,Divider 0"
|
|
group.long 0x10++0x1F
|
|
line.long 0x00 "MSI0_CLKEN,MSI0 Clock Enable Register"
|
|
bitfld.long 0x00 16. " LP0 ,Clock low power mode for card 0" "Normal,Low-power"
|
|
bitfld.long 0x00 0. " EN0 ,MSI clock enable for card 0" "Disabled,Enabled"
|
|
line.long 0x04 "MSI0_TMOUT,MSI0 Timeout Register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " DATA ,Data timeout"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RESPONSE ,Response timeout"
|
|
line.long 0x08 "MSI0_CTYPE,MSI0 Card Type Register"
|
|
bitfld.long 0x08 16. " WIDBYTE0 ,Width Byte 0 (Enables 8-bit mode for card 0)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " WIDNIB0 ,Width Nibble 0 (Enables 4-bit mode for card 0)" "Disabled,Enabled"
|
|
line.long 0x0C "MSI0_BLKSIZ,MSI0 Block Size Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Block size (configures data block size in bytes)"
|
|
line.long 0x10 "MSI0_BYTCNT,MSI0 Byte Count Register"
|
|
line.long 0x14 "MSI0_IMSK,MSI0 Interrupt Mask Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDIOMSK0 ,SDIO interrupt mask for SDIO device 0"
|
|
bitfld.long 0x14 15. " EBE ,End-bit error (read)/write no CRC" "Masked,Enabled"
|
|
bitfld.long 0x14 14. " ACD ,Auto command done" "Masked,Enabled"
|
|
bitfld.long 0x14 13. " SBEBCI ,Start bit error(sbe)/busy complete interrupt (BCI)" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " HLE ,Hardware locked write error" "Masked,Enabled"
|
|
bitfld.long 0x14 11. " FRUN ,FIFO underrun/overrun error" "Masked,Enabled"
|
|
bitfld.long 0x14 10. " HTO ,Data starvation by host timeout" "Masked,Enabled"
|
|
bitfld.long 0x14 9. " DRTO ,Data read timeout" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " RTO ,Response timeout" "Masked,Enabled"
|
|
bitfld.long 0x14 7. " DCRC ,Data CRC error" "Masked,Enabled"
|
|
bitfld.long 0x14 6. " RCRC ,Response CRC error" "Masked,Enabled"
|
|
bitfld.long 0x14 5. " RXDR ,Receive FIFO data request" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " TXDR ,Transmit FIFO data request" "Masked,Enabled"
|
|
bitfld.long 0x14 3. " DTO ,Data transfer over" "Masked,Enabled"
|
|
bitfld.long 0x14 2. " CMDDONE ,Command done" "Masked,Enabled"
|
|
bitfld.long 0x14 1. " RE ,Response error" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CD ,Card detect" "Masked,Enabled"
|
|
line.long 0x18 "MSI0_CMDARG,MSI0 Command Argument Register"
|
|
line.long 0x1C "MSI0_CMD,MSI0 Command Register"
|
|
bitfld.long 0x1C 31. " STARTCMD ,Start command" "No command,Command issued"
|
|
bitfld.long 0x1C 29. " USEHOLDREG ,Use hold reg (CMD and DATA are sent to card through or bypassing the HOLD Register)" "Bypass HOLD,Use HOLD"
|
|
bitfld.long 0x1C 27. " BOOTMODE ,Boot mode" "Mandatory,Alternate"
|
|
textline " "
|
|
bitfld.long 0x1C 26. " BOOTDIS ,Disable boot (Do NOT set BOOTDIS and BOOTEN together)" "No action,Terminate boot"
|
|
bitfld.long 0x1C 25. " XPECTBOOTACK ,Expect boot ack" "No ACK expected,ACK expected"
|
|
bitfld.long 0x1C 24. " BOOTEN ,Enable boot (Do NOT set BOOTDIS and BOOTEN together)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " UCLKREGS ,Update clock registers only (Do not send commands)" "Normal sequence,Update clk only"
|
|
bitfld.long 0x1C 16.--20. " CARDNUM ,Card number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1C 15. " SENDINIT ,Send initialization" "Do not send,Send init seq"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " STPABORTCMD ,Stop or Abort command (intended to stop current data transfer) in progress" "No Stop/Abort,Stop/Abort cmd"
|
|
bitfld.long 0x1C 13. " WTPRIVDATA ,Wait for previous data transfer completion before sending command" "Send at once,Wait for prv data"
|
|
bitfld.long 0x1C 12. " SENDASTOP ,Send auto stop (Send stop command at the end of data transfer)" "No stop cmd,Send stop cmd"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " XFRMODE ,Transfer mode (Block/Stream data transfer command)" "Block,Stream"
|
|
bitfld.long 0x1C 10. " RDWR ,Read from or write to card" "Read,Write"
|
|
bitfld.long 0x1C 9. " DXPECT ,Data expected" "Not expected,Expected"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " CHKRESPCRC ,Check response CRC" "Do not check,Check response"
|
|
bitfld.long 0x1C 7. " RLEN ,Response length expected from card" "Short,Long"
|
|
bitfld.long 0x1C 6. " RXPECT ,Response expect" "Not expected,Expected"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--5. " INDX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "MSI0_RESP0,MSI0 Response Register 0"
|
|
line.long 0x04 "MSI0_RESP1,MSI0 Response Register 1"
|
|
line.long 0x08 "MSI0_RESP2,MSI0 Response Register 2"
|
|
line.long 0x0C "MSI0_RESP3,MSI0 Response Register 3"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MSI0_MSKISTAT,MSI0 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 16. " SDIOINT0 ,SDIO interrupt for device 0" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " EBE ,End-bit error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " ACD ,Auto command done" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " SBEBCI ,Start bit error (sbe)/busy complete interrupt (BCI)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HLE ,Hardware locked write error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " FRUN ,FIFO underrun/overrun error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " HTO ,Data starvation by host timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " DRTO ,Data read timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RTO ,Response timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " DCRC ,Data CRC error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " RCRC ,Response CRC error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " RXDR ,Receive FIFO data request" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXDR ,Transmit FIFO data request" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " DTO ,Data transfer over" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CMDDONE ,Command done" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " RE ,Response error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CD ,Card detect" "Not occurred,Occurred"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MSI0_ISTAT,MSI0 Raw Interrupt Status Register"
|
|
eventfld.long 0x00 16. " SDIOINT0 ,SDIO interrupt for device 0" "No error,Error"
|
|
eventfld.long 0x00 15. " EBE ,End-bit error" "No error,Error"
|
|
eventfld.long 0x00 14. " ACD ,Auto command done" "No error,Error"
|
|
eventfld.long 0x00 13. " SBEBCI ,Start bit error busy complete interrupt" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 12. " HLE ,Hardware locked write error" "No error,Error"
|
|
eventfld.long 0x00 11. " FRUN ,FIFO underrun/overrun error" "No error,Error"
|
|
eventfld.long 0x00 10. " HTO ,Host timeout" "No error,Error"
|
|
eventfld.long 0x00 9. " DRTO ,Data read timeout" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RTO ,Response timeout" "No error,Error"
|
|
eventfld.long 0x00 7. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x00 6. " RCRC ,Response CRC error" "No error,Error"
|
|
eventfld.long 0x00 5. " RXDR ,Receive FIFO data request" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " TXDR ,Transmit FIFO data request" "No error,Error"
|
|
eventfld.long 0x00 3. " DTO ,Data transfer over" "No error,Error"
|
|
eventfld.long 0x00 2. " CMDDONE ,Command done" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RE ,Response error" "No error,Error"
|
|
eventfld.long 0x00 0. " CD ,Card detect" "No error,Error"
|
|
textline " "
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MSI0_STAT,MSI0 Status Register"
|
|
bitfld.long 0x00 31. " DMAREQ ,DMA request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " DMAACK ,DMA acknowledge" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
hexmask.long.word 0x00 17.--29. 1. " FIFOCNT ,FIFO count"
|
|
bitfld.long 0x00 11.--16. " RSPINDX ,Response index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10. " DMCBUSY ,Data state machine busy" "DMC idle,DMC busy"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DBUSY ,Data busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " D33STAT ,Data 3 status (Card presence)" "Not present,Present"
|
|
bitfld.long 0x00 4.--7. " CMDFSM ,Command FSM states" "Idle,Send init sequence,Tx cmd start bit,Tx cmd tx bit,Tx cmd index + arg,Tx cmd CRC7,Tx cmd end bit,Rx resp start bit,Rx resp IRQ response,Rx resp tx bit,Rx resp cmd idx,Rx resp data,Rx resp CRC7,Rx resp end bit,Cmd path wait NCC,CMD-to-response turnaround"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " FIFOEMPTY ,FIFO empty" "Not empty,empty"
|
|
bitfld.long 0x00 1. " FIFOTXWM ,FIFO tx watermark" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFORXWM ,FIFO rx watermark" "Not reached,Reached"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MSI0_FIFOTH,MSI0 FIFO Threshold Watermark Register"
|
|
bitfld.long 0x00 28.--30. " DMAMSZ ,DMA multiple transaction size" "1 transfer,4 transfers,8 transfers,16 transfers,32 transfers,64 transfers,128 transfers,256 transfers"
|
|
hexmask.long.word 0x00 16.--27. 1. " RXWM ,RX watermark"
|
|
hexmask.long.word 0x00 0.--11. 1. " TXWM ,TX watermark"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MSI0_CDETECT,MSI0 Card Detect Register"
|
|
bitfld.long 0x00 0. " CD0 ,Card detect for card 0" "Not detected,Detected"
|
|
group.long 0x5C++0x0B
|
|
line.long 0x00 "MSI0_TCBCNT,MSI0 Transferred CIU Card Byte Count Register"
|
|
line.long 0x04 "MSI0_TBBCNT,MSI0 Transferred Host To BIU-FIFO Byte Count Register"
|
|
line.long 0x08 "MSI0_DEBNCE,MSI0 Debounce Count Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " VALUE ,Debounce count"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "MSI0_BUSMODE,MSI0 Bus Mode Register"
|
|
bitfld.long 0x00 8.--10. " PBL ,Programmable burst length" "1 transfer,4 transfers,8 transfers,16 transfers,32 transfers,64 transfers,128 transfers,256 transfers"
|
|
bitfld.long 0x00 7. " DE ,IDMAC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB ,Fixed burst" "Not Fixed,Fixed"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "MSI0_PLDMND,MSI0 Poll Demand Register"
|
|
line.long 0x08 "MSI0_DBADDR,MSI0 Descriptor List Base Address Register"
|
|
if (((per.l(ad:0x31010000+0x8C))&0x04)==0x04)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "MSI0_IDSTS,MSI0 Internal DMA Status Register"
|
|
rbitfld.long 0x00 13.--16. " FSM ,DMAC finite state machine present state" "DMA Idle,DMA suspend,DESC_RD,DESC_CHK,DMA_RD_REQ_WAIT,DMA_WR_REQ_WAIT,DMA_RD,DMA_WR,DESC_CLOSE,?..."
|
|
rbitfld.long 0x00 10.--12. " EB ,Error bits (Type of error that caused a bus error)" ",Host Abort received during transmission,Host abort received during reception,?..."
|
|
textline " "
|
|
eventfld.long 0x00 9. " AIS ,Abnormal interrupt summary ('Fatal Bus' OR 'DU bit' Interrupt)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " NIS ,Normal interrupt summary (Transmit or Receive Interrupt)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " CES ,Card error summary" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " DU ,Descriptor unavailable interrupt" "No error,Error"
|
|
eventfld.long 0x00 2. " FBE ,Fatal bus error interrupt" "No error,Error"
|
|
eventfld.long 0x00 1. " RI ,Receive interrupt (data reception is finished for a descriptor)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt (data transmission is finished for a descriptor)" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "MSI0_IDSTS,MSI0 Internal DMA Status Register"
|
|
rbitfld.long 0x00 13.--16. " FSM ,DMAC finite state machine present state" "DMA Idle,DMA suspend,DESC_RD,DESC_CHK,DMA_RD_REQ_WAIT,DMA_WR_REQ_WAIT,DMA_RD,DMA_WR,DESC_CLOSE,?..."
|
|
textline " "
|
|
eventfld.long 0x00 9. " AIS ,Abnormal interrupt summary ('Fatal Bus' OR 'DU bit' Interrupt)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " NIS ,Normal interrupt summary (Transmit or Receive Interrupt)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " CES ,Card error summary" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " DU ,Descriptor unavailable interrupt" "No error,Error"
|
|
eventfld.long 0x00 2. " FBE ,Fatal bus error interrupt" "No error,Error"
|
|
eventfld.long 0x00 1. " RI ,Receive interrupt (data reception is finished for a descriptor)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt (data transmission is finished for a descriptor)" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "MSI0_IDINTEN,MSI0 Internal DMA Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " AI ,Abnormal interrupt summary" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " NI ,Normal interrupt summary" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CES ,Card error summary" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DU ,Descriptor unavailable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FBE ,Fatal bus error" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RI ,Receive interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TI ,Transmit interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "MSI0_DSCADDR,MSI0 Current Host Descriptor Address Register"
|
|
line.long 0x08 "MSI0_BUFADDR,MSI0 Current Buffer Descriptor Address Register"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MSI0_CDTHRCTL,MSI0 Card Threshold Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " RDTHR ,Card read threshold size"
|
|
bitfld.long 0x00 1. " BSYCLRIEN ,Busy clear interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RDTHREN ,Card read threshold enable" "Disabled,Enabled"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MSI0_ENSHIFT,MSI0 Enable Phase Shift Register"
|
|
bitfld.long 0x00 0.--1. " CD0 ,Enable shift for card 0" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "USB (Universal Serial Bus)"
|
|
tree "USB0"
|
|
base ad:0x310C1000
|
|
width 18.
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "USB0_FADDR,USB0 Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,Function address value"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "USB0_POWER,USB0 Power And Device Control Register"
|
|
bitfld.byte 0x00 7. " ISOUPDT ,ISO update enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SOFTCONN ,Soft connect/disconnect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " HSEN ,High speed mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " HSMODE ,High speed mode" "Full speed,High speed"
|
|
rbitfld.byte 0x00 3. " RESET ,Reset USB" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SUSPEND ,Suspend mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SUSEN ,SUSPENDM output enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "USB0_FADDR,USB0 Function Address Register"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "USB0_POWER,USB0 Power And Device Control Register"
|
|
bitfld.byte 0x00 5. " HSEN ,High speed mode enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4. " HSMODE ,High speed mode" "Full speed,High speed"
|
|
bitfld.byte 0x00 3. " RESET ,Reset USB" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RESUME ,Resume mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SUSPEND ,Suspend mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SUSEN ,SUSPENDM output enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "USB0_INTRTX,USB0 Transmit Interrupt Register"
|
|
in
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "USB0_INTRRX,USB0 Receive Interrupt Register"
|
|
in
|
|
group.word 0x06++0x03
|
|
line.word 0x00 "USB0_INTRTXE,USB0 Transmit Interrupt Enable Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11. " EP11 ,End point 11 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " EP10 ,End point 10 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " EP9 ,End point 9 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " EP8 ,End point 8 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " EP7 ,End point 7 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " EP6 ,End point 6 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EP5 ,End point 5 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " EP4 ,End point 4 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " EP3 ,End point 3 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " EP2 ,End point 2 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EP1 ,End point 1 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EP0 ,End point 0 TX interrupt enable" "Disabled,Enabled"
|
|
line.word 0x02 "USB0_INTRRXE,USB0 Receive Interrupt Enable Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x02 11. " EP11 ,End point 11 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " EP10 ,End point 10 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 9. " EP9 ,End point 9 RX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 8. " EP8 ,End point 8 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " EP7 ,End point 7 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " EP6 ,End point 6 RX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 5. " EP5 ,End point 5 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " EP4 ,End point 4 RX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 3. " EP3 ,End point 3 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " EP2 ,End point 2 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " EP1 ,End point 1 RX interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x0A++0x00
|
|
hide.byte 0x00 "USB0_IRQ,USB0 Common Interrupts Register"
|
|
in
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "USB0_IEN,USB0 Common Interrupts Enable Register"
|
|
bitfld.byte 0x00 7. " VBUSERR ,VBUS threshold indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SESSREQ ,Session request indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DISCON ,Disconnect indicator interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CON ,Connection indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SOF ,Start-of-frame indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RSTBABBLE ,Reset/babble indicator interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RESUME ,Resume indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SUSPEND ,Suspend indicator interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "USB0_FRAME,USB0 Frame Number Register"
|
|
hexmask.word 0x00 0.--10. 1. " VALUE ,Frame number value"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "USB0_INDEX,USB0 Index Register"
|
|
bitfld.byte 0x00 0.--3. " EP ,Endpoint index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "USB0_TESTMODE,USB0 Testmode Register"
|
|
bitfld.byte 0x00 6. " FIFOACCESS ,FIFO access" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.byte 0x00 3. " TESTPACKET ,Test_packet mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TESTK ,Test_k mode" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 2. " TESTK ,Test_k mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 1. " TESTJ ,Test_j mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TESTSE0NAK ,Test SE0 NAK" "Disabled,Enabled"
|
|
width 26.
|
|
tree "EPI Registers"
|
|
group.word 0x10++0x01 "Endpoint 0"
|
|
line.word 0x00 "USB0_EPI0_TXMAXP,USB0 EP0 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.w(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0I_CSR0_H,USB0 EP0 Configuration And Status (host) Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11. " DISPING ,Disable ping" "No,Yes"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " NAKTO ,NAK timeout" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status packet" "No request,Request"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "No request,Request"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TOERR ,Timeout error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,Setup packet" "No request,Request"
|
|
bitfld.word 0x00 2. " RXSTALL ,RX stall" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0I_CSR0_P,USB0 EP0 Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 7. " SSETUPEND ,Service setup end" "No effect,Clear SETUPEND"
|
|
bitfld.word 0x00 6. " SPKTRDY ,Service RX packet ready" "No effect,Clear RXPKTRDY"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send stall" "No effect,Send"
|
|
rbitfld.word 0x00 4. " SETUPEND ,Setup end" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,Sent stall" "0,1"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x10+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI0_RXMAXP,USB0 EP0 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x10+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI0_RXCSR_H,USB0 EP0 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x10+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI0_RXCSR_P,USB0 EP0 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x10+0x08)++0x01
|
|
line.word 0x00 "USB0_EP0I_CNT0,USB0 EP0 Number Of Received Bytes Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RXCNT ,RX byte count value"
|
|
group.byte (0x10+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP0I_TYPE0,USB0 EP0 Connection Type Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
group.byte (0x10+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP0I_NAKLIMIT0,USB0 EP0 NAK Limit Register"
|
|
bitfld.byte 0x00 0.--4. " VALUE ,Endpoint 0 timeout value (in frames)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x10+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x10+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
endif
|
|
group.byte (0x10+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI0_RXINTERVAL,USB0 EP0 Receive Polling Interval Register"
|
|
group.byte (0x10+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP0I_CFGDATA0,USB0 EP0 Configuration Information Register"
|
|
rbitfld.byte 0x00 7. " MPRX ,Multi-Packet aggregate for RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " MPTX ,Multi-Packet split for TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " BIGEND ,Big endian data" "Little endian,Big endian"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " HBRX ,High bandwidth RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " HBTX ,High bandwidth TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " DYNFIFO ,Dynamic FIFO size enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SOFTCON ,Soft connect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " UTMIWID ,UTMI data width" "8 bit,16 bit"
|
|
group.word 0x20++0x01 "Endpoint 1"
|
|
line.word 0x00 "USB0_EPI1_TXMAXP,USB0 EP1 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x20+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI1_TXCSR_H,USB0 EP1 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x20+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI1_TXCSR_P,USB0 EP1 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x20+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXMAXP,USB0 EP1 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x20+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXCSR_H,USB0 EP1 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x20+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXCSR_P,USB0 EP1 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x20+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXCNT,USB0 EP1 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x20+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x20+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
endif
|
|
group.byte (0x20+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI1_TXINTERVAL,USB0 EP1 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x20+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x20+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
endif
|
|
group.byte (0x20+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI1_RXINTERVAL,USB0 EP1 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x20+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP1 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x30++0x01 "Endpoint 2"
|
|
line.word 0x00 "USB0_EPI2_TXMAXP,USB0 EP2 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x30+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI2_TXCSR_H,USB0 EP2 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x30+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI2_TXCSR_P,USB0 EP2 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x30+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXMAXP,USB0 EP2 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x30+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXCSR_H,USB0 EP2 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x30+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXCSR_P,USB0 EP2 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x30+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXCNT,USB0 EP2 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x30+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x30+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
endif
|
|
group.byte (0x30+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI2_TXINTERVAL,USB0 EP2 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x30+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x30+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
endif
|
|
group.byte (0x30+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI2_RXINTERVAL,USB0 EP2 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x30+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP2 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x40++0x01 "Endpoint 3"
|
|
line.word 0x00 "USB0_EPI3_TXMAXP,USB0 EP3 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI3_TXCSR_H,USB0 EP3 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI3_TXCSR_P,USB0 EP3 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x40+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXMAXP,USB0 EP3 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x40+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXCSR_H,USB0 EP3 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x40+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXCSR_P,USB0 EP3 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x40+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXCNT,USB0 EP3 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x40+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x40+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
endif
|
|
group.byte (0x40+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI3_TXINTERVAL,USB0 EP3 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x40+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x40+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
endif
|
|
group.byte (0x40+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI3_RXINTERVAL,USB0 EP3 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x40+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP3 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x50++0x01 "Endpoint 4"
|
|
line.word 0x00 "USB0_EPI4_TXMAXP,USB0 EP4 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x50+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI4_TXCSR_H,USB0 EP4 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x50+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI4_TXCSR_P,USB0 EP4 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x50+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI4_RXMAXP,USB0 EP4 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x50+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI4_RXCSR_H,USB0 EP4 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x50+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI4_RXCSR_P,USB0 EP4 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x50+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI4_RXCNT,USB0 EP4 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x50+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI4_TXTYPE,USB0 EP4 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x50+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI4_TXTYPE,USB0 EP4 Transmit Type Register"
|
|
endif
|
|
group.byte (0x50+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI4_TXINTERVAL,USB0 EP4 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x50+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI4_RXTYPE,USB0 EP4 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x50+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI4_RXTYPE,USB0 EP4 Receive Type Register"
|
|
endif
|
|
group.byte (0x50+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI4_RXINTERVAL,USB0 EP4 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x50+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP4 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x60++0x01 "Endpoint 5"
|
|
line.word 0x00 "USB0_EPI5_TXMAXP,USB0 EP5 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x60+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI5_TXCSR_H,USB0 EP5 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x60+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI5_TXCSR_P,USB0 EP5 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x60+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI5_RXMAXP,USB0 EP5 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x60+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI5_RXCSR_H,USB0 EP5 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x60+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI5_RXCSR_P,USB0 EP5 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x60+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI5_RXCNT,USB0 EP5 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x60+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI5_TXTYPE,USB0 EP5 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x60+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI5_TXTYPE,USB0 EP5 Transmit Type Register"
|
|
endif
|
|
group.byte (0x60+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI5_TXINTERVAL,USB0 EP5 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x60+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI5_RXTYPE,USB0 EP5 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x60+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI5_RXTYPE,USB0 EP5 Receive Type Register"
|
|
endif
|
|
group.byte (0x60+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI5_RXINTERVAL,USB0 EP5 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x60+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP5 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x70++0x01 "Endpoint 6"
|
|
line.word 0x00 "USB0_EPI6_TXMAXP,USB0 EP6 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x70+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI6_TXCSR_H,USB0 EP6 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x70+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI6_TXCSR_P,USB0 EP6 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x70+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI6_RXMAXP,USB0 EP6 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x70+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI6_RXCSR_H,USB0 EP6 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x70+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI6_RXCSR_P,USB0 EP6 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x70+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI6_RXCNT,USB0 EP6 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x70+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI6_TXTYPE,USB0 EP6 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x70+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI6_TXTYPE,USB0 EP6 Transmit Type Register"
|
|
endif
|
|
group.byte (0x70+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI6_TXINTERVAL,USB0 EP6 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x70+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI6_RXTYPE,USB0 EP6 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x70+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI6_RXTYPE,USB0 EP6 Receive Type Register"
|
|
endif
|
|
group.byte (0x70+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI6_RXINTERVAL,USB0 EP6 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x70+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP6 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x80++0x01 "Endpoint 7"
|
|
line.word 0x00 "USB0_EPI7_TXMAXP,USB0 EP7 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x80+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI7_TXCSR_H,USB0 EP7 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x80+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI7_TXCSR_P,USB0 EP7 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x80+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI7_RXMAXP,USB0 EP7 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x80+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI7_RXCSR_H,USB0 EP7 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x80+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI7_RXCSR_P,USB0 EP7 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x80+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI7_RXCNT,USB0 EP7 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x80+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI7_TXTYPE,USB0 EP7 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x80+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI7_TXTYPE,USB0 EP7 Transmit Type Register"
|
|
endif
|
|
group.byte (0x80+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI7_TXINTERVAL,USB0 EP7 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x80+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI7_RXTYPE,USB0 EP7 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x80+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI7_RXTYPE,USB0 EP7 Receive Type Register"
|
|
endif
|
|
group.byte (0x80+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI7_RXINTERVAL,USB0 EP7 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x80+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP7 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x90++0x01 "Endpoint 8"
|
|
line.word 0x00 "USB0_EPI8_TXMAXP,USB0 EP8 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x90+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI8_TXCSR_H,USB0 EP8 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x90+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI8_TXCSR_P,USB0 EP8 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x90+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI8_RXMAXP,USB0 EP8 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x90+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI8_RXCSR_H,USB0 EP8 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x90+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI8_RXCSR_P,USB0 EP8 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x90+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI8_RXCNT,USB0 EP8 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x90+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI8_TXTYPE,USB0 EP8 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x90+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI8_TXTYPE,USB0 EP8 Transmit Type Register"
|
|
endif
|
|
group.byte (0x90+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI8_TXINTERVAL,USB0 EP8 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x90+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI8_RXTYPE,USB0 EP8 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x90+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI8_RXTYPE,USB0 EP8 Receive Type Register"
|
|
endif
|
|
group.byte (0x90+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI8_RXINTERVAL,USB0 EP8 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x90+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP8 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0xA0++0x01 "Endpoint 9"
|
|
line.word 0x00 "USB0_EPI9_TXMAXP,USB0 EP9 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0xA0+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI9_TXCSR_H,USB0 EP9 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0xA0+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI9_TXCSR_P,USB0 EP9 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0xA0+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI9_RXMAXP,USB0 EP9 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0xA0+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI9_RXCSR_H,USB0 EP9 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0xA0+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI9_RXCSR_P,USB0 EP9 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0xA0+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI9_RXCNT,USB0 EP9 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0xA0+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI9_TXTYPE,USB0 EP9 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0xA0+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI9_TXTYPE,USB0 EP9 Transmit Type Register"
|
|
endif
|
|
group.byte (0xA0+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI9_TXINTERVAL,USB0 EP9 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0xA0+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI9_RXTYPE,USB0 EP9 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0xA0+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI9_RXTYPE,USB0 EP9 Receive Type Register"
|
|
endif
|
|
group.byte (0xA0+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI9_RXINTERVAL,USB0 EP9 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0xA0+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP9 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0xB0++0x01 "Endpoint 10"
|
|
line.word 0x00 "USB0_EPI10_TXMAXP,USB0 EP10 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0xB0+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI10_TXCSR_H,USB0 EP10 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0xB0+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI10_TXCSR_P,USB0 EP10 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0xB0+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI10_RXMAXP,USB0 EP10 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0xB0+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI10_RXCSR_H,USB0 EP10 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0xB0+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI10_RXCSR_P,USB0 EP10 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0xB0+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI10_RXCNT,USB0 EP10 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0xB0+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI10_TXTYPE,USB0 EP10 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0xB0+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI10_TXTYPE,USB0 EP10 Transmit Type Register"
|
|
endif
|
|
group.byte (0xB0+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI10_TXINTERVAL,USB0 EP10 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0xB0+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI10_RXTYPE,USB0 EP10 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0xB0+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI10_RXTYPE,USB0 EP10 Receive Type Register"
|
|
endif
|
|
group.byte (0xB0+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI10_RXINTERVAL,USB0 EP10 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0xB0+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP10 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0xC0++0x01 "Endpoint 11"
|
|
line.word 0x00 "USB0_EPI11_TXMAXP,USB0 EP11 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0xC0+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI11_TXCSR_H,USB0 EP11 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0xC0+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI11_TXCSR_P,USB0 EP11 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0xC0+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI11_RXMAXP,USB0 EP11 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0xC0+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI11_RXCSR_H,USB0 EP11 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0xC0+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI11_RXCSR_P,USB0 EP11 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0xC0+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI11_RXCNT,USB0 EP11 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0xC0+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI11_TXTYPE,USB0 EP11 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0xC0+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI11_TXTYPE,USB0 EP11 Transmit Type Register"
|
|
endif
|
|
group.byte (0xC0+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI11_TXINTERVAL,USB0 EP11 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0xC0+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI11_RXTYPE,USB0 EP11 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0xC0+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI11_RXTYPE,USB0 EP11 Receive Type Register"
|
|
endif
|
|
group.byte (0xC0+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI11_RXINTERVAL,USB0 EP11 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0xC0+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP11 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "FIFO Registers"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
tree.end
|
|
width 20.
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "USB0_DEV_CTL,USB0 Device Control Register"
|
|
rbitfld.byte 0x00 7. " BDEVICE ,A or B devices indicator" "A device,B device"
|
|
rbitfld.byte 0x00 6. " FSDEV ,Full or High-Speed indicator" "Not detected,Detected"
|
|
rbitfld.byte 0x00 5. " LSDEV ,Low-Speed indicator" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 3.--4. " VBUS ,VBUS level indicator" "<sessionend,Sessionend-avalid,Avalid-vbusvalid,>vbusvalid"
|
|
rbitfld.byte 0x00 2. " HOSTMODE ,Host mode indicator" "Peripheral,Host"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host negotiation request" "Completed,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session indicator" "Not detected,Detected"
|
|
else
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "USB0_DEV_CTL,USB0 Device Control Register"
|
|
rbitfld.byte 0x00 7. " BDEVICE ,A or B devices indicator" "A device,B device"
|
|
rbitfld.byte 0x00 3.--4. " VBUS ,VBUS level indicator" "<sessionend,Sessionend-avalid,Avalid-vbusvalid,>vbusvalid"
|
|
rbitfld.byte 0x00 2. " HOSTMODE ,Host mode indicator" "Peripheral,Host"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host negotiation request" "Completed,Requested"
|
|
bitfld.byte 0x00 0. " SESSION ,Session indicator" "Not detected,Detected"
|
|
endif
|
|
sif !cpuis("ADSPCM40*")
|
|
if (((per.b(ad:0x310C1000+0x62))&0x10)==0x00)
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "USB0_TXFIFOSZ,USB0 Transmit FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
else
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "USB0_TXFIFOSZ,USB0 Transmit FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "16,32,64,128,256,512,1024,2048,4096,8192,?..."
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x63))&0x10)==0x00)
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "USB0_RXFIFOSZ,USB0 Receive FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
else
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "USB0_RXFIFOSZ,USB0 Receive FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "16,32,64,128,256,512,1024,2048,4096,8192,?..."
|
|
endif
|
|
group.word 0x64++0x03
|
|
line.word 0x00 "USB0_TXFIFOADDR,USB0 Transmit FIFO Address Register"
|
|
hexmask.word 0x00 0.--12. 1. " VALUE ,TX FIFO start address"
|
|
line.word 0x02 "USB0_RXFIFOADDR,USB0 Receive FIFO Address Register"
|
|
hexmask.word 0x02 0.--12. 1. " VALUE ,RX FIFO start address"
|
|
endif
|
|
rgroup.byte 0x78++0x01
|
|
line.byte 0x00 "USB0_EPINFO,USB0 Endpoint Information Register"
|
|
bitfld.byte 0x00 4.--7. " RXEP ,RX endpoints" ",1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.byte 0x00 0.--3. " TXEP ,TX endpoints" ",1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.byte 0x01 "USB0_RAMINFO,USB0 RAM Information Register"
|
|
bitfld.byte 0x01 4.--7. " DMACHANS ,DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " RAMBITS ,RAM address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x7A++0x01
|
|
line.byte 0x00 "USB0_LINKINFO,USB0 Link Information Register"
|
|
bitfld.byte 0x00 4.--7. " WTCON ,Wait for connect/disconnect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " WTID ,Wait from ID Pull-up" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "USB0_VPLEN,USB0 VBUS Pulse Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "USB0_HS_EOF1,USB0 High-Speed EOF 1 Register"
|
|
endif
|
|
group.byte 0x7A++0x02
|
|
line.byte 0x00 "USB0_FS_EOF1,USB0 Full-Speed EOF 1 Register"
|
|
line.byte 0x01 "USB0_LS_EOF1,USB0 Low-Speed EOF 1 Register"
|
|
line.byte 0x02 "USB0_SOFT_RST,USB0 Software Reset Register"
|
|
bitfld.byte 0x02 1. " RSTX ,Reset USB XCLK domain" "No effect,Reset"
|
|
bitfld.byte 0x02 0. " RST ,Reset USB CLK domain" "No effect,Reset"
|
|
width 25.
|
|
tree "MP Registers"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "USB0_MP0_TXFUNCADDR,USB0 MP0 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x80+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP0_TXHUBADDR,USB0 MP0 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP0_TXHUBPORT,USB0 MP0 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x80++0x00
|
|
hide.byte 0x00 "USB0_MP0_TXFUNCADDR,USB0 MP0 Transmit Function Address Register"
|
|
hgroup.byte (0x80+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP0_TXHUBADDR,USB0 MP0 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP0_TXHUBPORT,USB0 MP0 Transmit Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "USB0_MP1_TXFUNCADDR,USB0 MP1 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x88+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP1_TXHUBADDR,USB0 MP1 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP1_TXHUBPORT,USB0 MP1 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0x88+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP1_RXFUNCADDR,USB0 MP1 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0x88+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP1_RXHUBADDR,USB0 MP1 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP1_RXHUBPORT,USB0 MP1 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x88++0x00
|
|
hide.byte 0x00 "USB0_MP1_TXFUNCADDR,USB0 MP1 Transmit Function Address Register"
|
|
hgroup.byte (0x88+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP1_TXHUBADDR,USB0 MP1 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP1_TXHUBPORT,USB0 MP1 Transmit Hub Port Register"
|
|
hgroup.byte (0x88+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP1_RXFUNCADDR,USB0 MP1 Receive Function Address Register"
|
|
hgroup.byte (0x88+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP1_RXHUBADDR,USB0 MP1 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP1_RXHUBPORT,USB0 MP1 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "USB0_MP2_TXFUNCADDR,USB0 MP2 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x90+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP2_TXHUBADDR,USB0 MP2 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP2_TXHUBPORT,USB0 MP2 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0x90+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP2_RXFUNCADDR,USB0 MP2 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0x90+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP2_RXHUBADDR,USB0 MP2 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP2_RXHUBPORT,USB0 MP2 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x90++0x00
|
|
hide.byte 0x00 "USB0_MP2_TXFUNCADDR,USB0 MP2 Transmit Function Address Register"
|
|
hgroup.byte (0x90+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP2_TXHUBADDR,USB0 MP2 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP2_TXHUBPORT,USB0 MP2 Transmit Hub Port Register"
|
|
hgroup.byte (0x90+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP2_RXFUNCADDR,USB0 MP2 Receive Function Address Register"
|
|
hgroup.byte (0x90+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP2_RXHUBADDR,USB0 MP2 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP2_RXHUBPORT,USB0 MP2 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "USB0_MP3_TXFUNCADDR,USB0 MP3 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x98+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP3_TXHUBADDR,USB0 MP3 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP3_TXHUBPORT,USB0 MP3 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0x98+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP3_RXFUNCADDR,USB0 MP3 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0x98+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP3_RXHUBADDR,USB0 MP3 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP3_RXHUBPORT,USB0 MP3 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x98++0x00
|
|
hide.byte 0x00 "USB0_MP3_TXFUNCADDR,USB0 MP3 Transmit Function Address Register"
|
|
hgroup.byte (0x98+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP3_TXHUBADDR,USB0 MP3 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP3_TXHUBPORT,USB0 MP3 Transmit Hub Port Register"
|
|
hgroup.byte (0x98+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP3_RXFUNCADDR,USB0 MP3 Receive Function Address Register"
|
|
hgroup.byte (0x98+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP3_RXHUBADDR,USB0 MP3 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP3_RXHUBPORT,USB0 MP3 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "USB0_MP4_TXFUNCADDR,USB0 MP4 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xA0+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP4_TXHUBADDR,USB0 MP4 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP4_TXHUBPORT,USB0 MP4 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xA0+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP4_RXFUNCADDR,USB0 MP4 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xA0+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP4_RXHUBADDR,USB0 MP4 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP4_RXHUBPORT,USB0 MP4 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xA0++0x00
|
|
hide.byte 0x00 "USB0_MP4_TXFUNCADDR,USB0 MP4 Transmit Function Address Register"
|
|
hgroup.byte (0xA0+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP4_TXHUBADDR,USB0 MP4 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP4_TXHUBPORT,USB0 MP4 Transmit Hub Port Register"
|
|
hgroup.byte (0xA0+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP4_RXFUNCADDR,USB0 MP4 Receive Function Address Register"
|
|
hgroup.byte (0xA0+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP4_RXHUBADDR,USB0 MP4 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP4_RXHUBPORT,USB0 MP4 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "USB0_MP5_TXFUNCADDR,USB0 MP5 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xA8+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP5_TXHUBADDR,USB0 MP5 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP5_TXHUBPORT,USB0 MP5 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xA8+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP5_RXFUNCADDR,USB0 MP5 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xA8+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP5_RXHUBADDR,USB0 MP5 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP5_RXHUBPORT,USB0 MP5 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xA8++0x00
|
|
hide.byte 0x00 "USB0_MP5_TXFUNCADDR,USB0 MP5 Transmit Function Address Register"
|
|
hgroup.byte (0xA8+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP5_TXHUBADDR,USB0 MP5 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP5_TXHUBPORT,USB0 MP5 Transmit Hub Port Register"
|
|
hgroup.byte (0xA8+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP5_RXFUNCADDR,USB0 MP5 Receive Function Address Register"
|
|
hgroup.byte (0xA8+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP5_RXHUBADDR,USB0 MP5 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP5_RXHUBPORT,USB0 MP5 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "USB0_MP6_TXFUNCADDR,USB0 MP6 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xB0+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP6_TXHUBADDR,USB0 MP6 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP6_TXHUBPORT,USB0 MP6 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xB0+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP6_RXFUNCADDR,USB0 MP6 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xB0+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP6_RXHUBADDR,USB0 MP6 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP6_RXHUBPORT,USB0 MP6 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xB0++0x00
|
|
hide.byte 0x00 "USB0_MP6_TXFUNCADDR,USB0 MP6 Transmit Function Address Register"
|
|
hgroup.byte (0xB0+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP6_TXHUBADDR,USB0 MP6 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP6_TXHUBPORT,USB0 MP6 Transmit Hub Port Register"
|
|
hgroup.byte (0xB0+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP6_RXFUNCADDR,USB0 MP6 Receive Function Address Register"
|
|
hgroup.byte (0xB0+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP6_RXHUBADDR,USB0 MP6 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP6_RXHUBPORT,USB0 MP6 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xB8++0x00
|
|
line.byte 0x00 "USB0_MP7_TXFUNCADDR,USB0 MP7 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xB8+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP7_TXHUBADDR,USB0 MP7 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP7_TXHUBPORT,USB0 MP7 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xB8+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP7_RXFUNCADDR,USB0 MP7 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xB8+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP7_RXHUBADDR,USB0 MP7 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP7_RXHUBPORT,USB0 MP7 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xB8++0x00
|
|
hide.byte 0x00 "USB0_MP7_TXFUNCADDR,USB0 MP7 Transmit Function Address Register"
|
|
hgroup.byte (0xB8+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP7_TXHUBADDR,USB0 MP7 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP7_TXHUBPORT,USB0 MP7 Transmit Hub Port Register"
|
|
hgroup.byte (0xB8+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP7_RXFUNCADDR,USB0 MP7 Receive Function Address Register"
|
|
hgroup.byte (0xB8+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP7_RXHUBADDR,USB0 MP7 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP7_RXHUBPORT,USB0 MP7 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "USB0_MP8_TXFUNCADDR,USB0 MP8 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xC0+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP8_TXHUBADDR,USB0 MP8 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP8_TXHUBPORT,USB0 MP8 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xC0+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP8_RXFUNCADDR,USB0 MP8 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xC0+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP8_RXHUBADDR,USB0 MP8 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP8_RXHUBPORT,USB0 MP8 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xC0++0x00
|
|
hide.byte 0x00 "USB0_MP8_TXFUNCADDR,USB0 MP8 Transmit Function Address Register"
|
|
hgroup.byte (0xC0+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP8_TXHUBADDR,USB0 MP8 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP8_TXHUBPORT,USB0 MP8 Transmit Hub Port Register"
|
|
hgroup.byte (0xC0+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP8_RXFUNCADDR,USB0 MP8 Receive Function Address Register"
|
|
hgroup.byte (0xC0+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP8_RXHUBADDR,USB0 MP8 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP8_RXHUBPORT,USB0 MP8 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "USB0_MP9_TXFUNCADDR,USB0 MP9 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xC8+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP9_TXHUBADDR,USB0 MP9 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP9_TXHUBPORT,USB0 MP9 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xC8+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP9_RXFUNCADDR,USB0 MP9 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xC8+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP9_RXHUBADDR,USB0 MP9 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP9_RXHUBPORT,USB0 MP9 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xC8++0x00
|
|
hide.byte 0x00 "USB0_MP9_TXFUNCADDR,USB0 MP9 Transmit Function Address Register"
|
|
hgroup.byte (0xC8+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP9_TXHUBADDR,USB0 MP9 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP9_TXHUBPORT,USB0 MP9 Transmit Hub Port Register"
|
|
hgroup.byte (0xC8+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP9_RXFUNCADDR,USB0 MP9 Receive Function Address Register"
|
|
hgroup.byte (0xC8+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP9_RXHUBADDR,USB0 MP9 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP9_RXHUBPORT,USB0 MP9 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "USB0_MP10_TXFUNCADDR,USB0 MP10 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xD0+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP10_TXHUBADDR,USB0 MP10 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP10_TXHUBPORT,USB0 MP10 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xD0+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP10_RXFUNCADDR,USB0 MP10 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xD0+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP10_RXHUBADDR,USB0 MP10 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP10_RXHUBPORT,USB0 MP10 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xD0++0x00
|
|
hide.byte 0x00 "USB0_MP10_TXFUNCADDR,USB0 MP10 Transmit Function Address Register"
|
|
hgroup.byte (0xD0+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP10_TXHUBADDR,USB0 MP10 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP10_TXHUBPORT,USB0 MP10 Transmit Hub Port Register"
|
|
hgroup.byte (0xD0+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP10_RXFUNCADDR,USB0 MP10 Receive Function Address Register"
|
|
hgroup.byte (0xD0+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP10_RXHUBADDR,USB0 MP10 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP10_RXHUBPORT,USB0 MP10 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "USB0_MP11_TXFUNCADDR,USB0 MP11 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0xD8+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP11_TXHUBADDR,USB0 MP11 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP11_TXHUBPORT,USB0 MP11 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0xD8+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP11_RXFUNCADDR,USB0 MP11 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0xD8+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP11_RXHUBADDR,USB0 MP11 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP11_RXHUBPORT,USB0 MP11 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0xD8++0x00
|
|
hide.byte 0x00 "USB0_MP11_TXFUNCADDR,USB0 MP11 Transmit Function Address Register"
|
|
hgroup.byte (0xD8+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP11_TXHUBADDR,USB0 MP11 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP11_TXHUBPORT,USB0 MP11 Transmit Hub Port Register"
|
|
hgroup.byte (0xD8+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP11_RXFUNCADDR,USB0 MP11 Receive Function Address Register"
|
|
hgroup.byte (0xD8+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP11_RXHUBADDR,USB0 MP11 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP11_RXHUBPORT,USB0 MP11 Receive Hub Port Register"
|
|
endif
|
|
tree.end
|
|
width 25.
|
|
tree "Endpoints Registers"
|
|
group.word 0x100++0x01 "Endpoint 0"
|
|
line.word 0x00 "USB0_EP0_TXMAXP,USB0 EP0 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0_CSR0_H,USB0 EP0 Configuration And Status (host) Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11. " DISPING ,Disable ping" "No,Yes"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " NAKTO ,NAK timeout" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status packet" "No request,Request"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "No request,Request"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TOERR ,Timeout error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,Setup packet" "No request,Request"
|
|
bitfld.word 0x00 2. " RXSTALL ,RX stall" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0_CSR0_P,USB0 EP0 Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 7. " SSETUPEND ,Service setup end" "No effect,Clear SETUPEND"
|
|
bitfld.word 0x00 6. " SPKTRDY ,Service RX packet ready" "No effect,Clear RXPKTRDY"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send stall" "No effect,Send"
|
|
rbitfld.word 0x00 4. " SETUPEND ,Setup end" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,Sent stall" "0,1"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x100+0x04)++0x01
|
|
line.word 0x00 "USB0_EP0_RXMAXP,USB0 EP0 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x100+0x06)++0x01
|
|
line.word 0x00 "USB0_EP0_RXCSR_H,USB0 EP0 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x100+0x06)++0x01
|
|
line.word 0x00 "USB0_EP0_RXCSR_P,USB0 EP0 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x100+0x08)++0x01
|
|
line.word 0x00 "USB0_EP0_CNT0,USB0 EP0 Number Of Received Bytes Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RXCNT ,RX byte count value"
|
|
group.byte (0x100+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP0_TYPE0,USB0 EP0 Connection Type Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
group.byte (0x100+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP0_NAKLIMIT0,USB0 EP0 NAK Limit Register"
|
|
bitfld.byte 0x00 0.--4. " VALUE ,Endpoint 0 timeout value (in frames)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x100+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x100+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
endif
|
|
group.byte (0x100+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP0_RXINTERVAL,USB0 EP0 Receive Polling Interval Register"
|
|
group.byte (0x100+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP0_CFGDATA0,USB0 EP0 Configuration Information Register"
|
|
rbitfld.byte 0x00 7. " MPRX ,Multi-Packet aggregate for RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " MPTX ,Multi-Packet split for TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " BIGEND ,Big endian data" "Little endian,Big endian"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " HBRX ,High bandwidth RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " HBTX ,High bandwidth TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " DYNFIFO ,Dynamic FIFO size enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SOFTCON ,Soft connect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " UTMIWID ,UTMI data width" "8 bit,16 bit"
|
|
group.word 0x110++0x01 "Endpoint 1"
|
|
line.word 0x00 "USB0_EP1_TXMAXP,USB0 EP1 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "USB0_EP1_TXCSR_H,USB0 EP1 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "USB0_EP1_TXCSR_P,USB0 EP1 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x110+0x04)++0x01
|
|
line.word 0x00 "USB0_EP1_RXMAXP,USB0 EP1 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x110+0x06)++0x01
|
|
line.word 0x00 "USB0_EP1_RXCSR_H,USB0 EP1 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x110+0x06)++0x01
|
|
line.word 0x00 "USB0_EP1_RXCSR_P,USB0 EP1 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x110+0x08)++0x01
|
|
line.word 0x00 "USB0_EP1_RXCNT,USB0 EP1 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x110+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x110+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
endif
|
|
group.byte (0x110+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP1_TXINTERVAL,USB0 EP1 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x110+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x110+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
endif
|
|
group.byte (0x110+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP1_RXINTERVAL,USB0 EP1 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x110+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP1_FIFOSZ,USB0 EP1 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x120++0x01 "Endpoint 2"
|
|
line.word 0x00 "USB0_EP2_TXMAXP,USB0 EP2 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "USB0_EP2_TXCSR_H,USB0 EP2 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "USB0_EP2_TXCSR_P,USB0 EP2 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x120+0x04)++0x01
|
|
line.word 0x00 "USB0_EP2_RXMAXP,USB0 EP2 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x120+0x06)++0x01
|
|
line.word 0x00 "USB0_EP2_RXCSR_H,USB0 EP2 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x120+0x06)++0x01
|
|
line.word 0x00 "USB0_EP2_RXCSR_P,USB0 EP2 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x120+0x08)++0x01
|
|
line.word 0x00 "USB0_EP2_RXCNT,USB0 EP2 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x120+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x120+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
endif
|
|
group.byte (0x120+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP2_TXINTERVAL,USB0 EP2 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x120+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x120+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
endif
|
|
group.byte (0x120+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP2_RXINTERVAL,USB0 EP2 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x120+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP2_FIFOSZ,USB0 EP2 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x130++0x01 "Endpoint 3"
|
|
line.word 0x00 "USB0_EP3_TXMAXP,USB0 EP3 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "USB0_EP3_TXCSR_H,USB0 EP3 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "USB0_EP3_TXCSR_P,USB0 EP3 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x130+0x04)++0x01
|
|
line.word 0x00 "USB0_EP3_RXMAXP,USB0 EP3 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x130+0x06)++0x01
|
|
line.word 0x00 "USB0_EP3_RXCSR_H,USB0 EP3 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x130+0x06)++0x01
|
|
line.word 0x00 "USB0_EP3_RXCSR_P,USB0 EP3 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x130+0x08)++0x01
|
|
line.word 0x00 "USB0_EP3_RXCNT,USB0 EP3 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x130+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x130+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
endif
|
|
group.byte (0x130+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP3_TXINTERVAL,USB0 EP3 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x130+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x130+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
endif
|
|
group.byte (0x130+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP3_RXINTERVAL,USB0 EP3 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x130+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP3_FIFOSZ,USB0 EP3 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x140++0x01 "Endpoint 4"
|
|
line.word 0x00 "USB0_EP4_TXMAXP,USB0 EP4 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x140+0x02)++0x01
|
|
line.word 0x00 "USB0_EP4_TXCSR_H,USB0 EP4 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x140+0x02)++0x01
|
|
line.word 0x00 "USB0_EP4_TXCSR_P,USB0 EP4 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x140+0x04)++0x01
|
|
line.word 0x00 "USB0_EP4_RXMAXP,USB0 EP4 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x140+0x06)++0x01
|
|
line.word 0x00 "USB0_EP4_RXCSR_H,USB0 EP4 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x140+0x06)++0x01
|
|
line.word 0x00 "USB0_EP4_RXCSR_P,USB0 EP4 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x140+0x08)++0x01
|
|
line.word 0x00 "USB0_EP4_RXCNT,USB0 EP4 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x140+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP4_TXTYPE,USB0 EP4 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x140+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP4_TXTYPE,USB0 EP4 Transmit Type Register"
|
|
endif
|
|
group.byte (0x140+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP4_TXINTERVAL,USB0 EP4 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x140+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP4_RXTYPE,USB0 EP4 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x140+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP4_RXTYPE,USB0 EP4 Receive Type Register"
|
|
endif
|
|
group.byte (0x140+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP4_RXINTERVAL,USB0 EP4 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x140+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP4_FIFOSZ,USB0 EP4 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x150++0x01 "Endpoint 5"
|
|
line.word 0x00 "USB0_EP5_TXMAXP,USB0 EP5 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x150+0x02)++0x01
|
|
line.word 0x00 "USB0_EP5_TXCSR_H,USB0 EP5 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x150+0x02)++0x01
|
|
line.word 0x00 "USB0_EP5_TXCSR_P,USB0 EP5 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x150+0x04)++0x01
|
|
line.word 0x00 "USB0_EP5_RXMAXP,USB0 EP5 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x150+0x06)++0x01
|
|
line.word 0x00 "USB0_EP5_RXCSR_H,USB0 EP5 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x150+0x06)++0x01
|
|
line.word 0x00 "USB0_EP5_RXCSR_P,USB0 EP5 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x150+0x08)++0x01
|
|
line.word 0x00 "USB0_EP5_RXCNT,USB0 EP5 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x150+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP5_TXTYPE,USB0 EP5 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x150+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP5_TXTYPE,USB0 EP5 Transmit Type Register"
|
|
endif
|
|
group.byte (0x150+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP5_TXINTERVAL,USB0 EP5 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x150+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP5_RXTYPE,USB0 EP5 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x150+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP5_RXTYPE,USB0 EP5 Receive Type Register"
|
|
endif
|
|
group.byte (0x150+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP5_RXINTERVAL,USB0 EP5 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x150+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP5_FIFOSZ,USB0 EP5 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x160++0x01 "Endpoint 6"
|
|
line.word 0x00 "USB0_EP6_TXMAXP,USB0 EP6 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x160+0x02)++0x01
|
|
line.word 0x00 "USB0_EP6_TXCSR_H,USB0 EP6 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x160+0x02)++0x01
|
|
line.word 0x00 "USB0_EP6_TXCSR_P,USB0 EP6 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x160+0x04)++0x01
|
|
line.word 0x00 "USB0_EP6_RXMAXP,USB0 EP6 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x160+0x06)++0x01
|
|
line.word 0x00 "USB0_EP6_RXCSR_H,USB0 EP6 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x160+0x06)++0x01
|
|
line.word 0x00 "USB0_EP6_RXCSR_P,USB0 EP6 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x160+0x08)++0x01
|
|
line.word 0x00 "USB0_EP6_RXCNT,USB0 EP6 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x160+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP6_TXTYPE,USB0 EP6 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x160+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP6_TXTYPE,USB0 EP6 Transmit Type Register"
|
|
endif
|
|
group.byte (0x160+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP6_TXINTERVAL,USB0 EP6 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x160+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP6_RXTYPE,USB0 EP6 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x160+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP6_RXTYPE,USB0 EP6 Receive Type Register"
|
|
endif
|
|
group.byte (0x160+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP6_RXINTERVAL,USB0 EP6 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x160+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP6_FIFOSZ,USB0 EP6 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x170++0x01 "Endpoint 7"
|
|
line.word 0x00 "USB0_EP7_TXMAXP,USB0 EP7 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x170+0x02)++0x01
|
|
line.word 0x00 "USB0_EP7_TXCSR_H,USB0 EP7 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x170+0x02)++0x01
|
|
line.word 0x00 "USB0_EP7_TXCSR_P,USB0 EP7 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x170+0x04)++0x01
|
|
line.word 0x00 "USB0_EP7_RXMAXP,USB0 EP7 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x170+0x06)++0x01
|
|
line.word 0x00 "USB0_EP7_RXCSR_H,USB0 EP7 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x170+0x06)++0x01
|
|
line.word 0x00 "USB0_EP7_RXCSR_P,USB0 EP7 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x170+0x08)++0x01
|
|
line.word 0x00 "USB0_EP7_RXCNT,USB0 EP7 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x170+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP7_TXTYPE,USB0 EP7 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x170+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP7_TXTYPE,USB0 EP7 Transmit Type Register"
|
|
endif
|
|
group.byte (0x170+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP7_TXINTERVAL,USB0 EP7 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x170+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP7_RXTYPE,USB0 EP7 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x170+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP7_RXTYPE,USB0 EP7 Receive Type Register"
|
|
endif
|
|
group.byte (0x170+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP7_RXINTERVAL,USB0 EP7 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x170+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP7_FIFOSZ,USB0 EP7 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x180++0x01 "Endpoint 8"
|
|
line.word 0x00 "USB0_EP8_TXMAXP,USB0 EP8 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x180+0x02)++0x01
|
|
line.word 0x00 "USB0_EP8_TXCSR_H,USB0 EP8 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x180+0x02)++0x01
|
|
line.word 0x00 "USB0_EP8_TXCSR_P,USB0 EP8 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x180+0x04)++0x01
|
|
line.word 0x00 "USB0_EP8_RXMAXP,USB0 EP8 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x180+0x06)++0x01
|
|
line.word 0x00 "USB0_EP8_RXCSR_H,USB0 EP8 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x180+0x06)++0x01
|
|
line.word 0x00 "USB0_EP8_RXCSR_P,USB0 EP8 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x180+0x08)++0x01
|
|
line.word 0x00 "USB0_EP8_RXCNT,USB0 EP8 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x180+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP8_TXTYPE,USB0 EP8 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x180+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP8_TXTYPE,USB0 EP8 Transmit Type Register"
|
|
endif
|
|
group.byte (0x180+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP8_TXINTERVAL,USB0 EP8 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x180+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP8_RXTYPE,USB0 EP8 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x180+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP8_RXTYPE,USB0 EP8 Receive Type Register"
|
|
endif
|
|
group.byte (0x180+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP8_RXINTERVAL,USB0 EP8 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x180+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP8_FIFOSZ,USB0 EP8 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x190++0x01 "Endpoint 9"
|
|
line.word 0x00 "USB0_EP9_TXMAXP,USB0 EP9 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x190+0x02)++0x01
|
|
line.word 0x00 "USB0_EP9_TXCSR_H,USB0 EP9 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x190+0x02)++0x01
|
|
line.word 0x00 "USB0_EP9_TXCSR_P,USB0 EP9 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x190+0x04)++0x01
|
|
line.word 0x00 "USB0_EP9_RXMAXP,USB0 EP9 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x190+0x06)++0x01
|
|
line.word 0x00 "USB0_EP9_RXCSR_H,USB0 EP9 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x190+0x06)++0x01
|
|
line.word 0x00 "USB0_EP9_RXCSR_P,USB0 EP9 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x190+0x08)++0x01
|
|
line.word 0x00 "USB0_EP9_RXCNT,USB0 EP9 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x190+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP9_TXTYPE,USB0 EP9 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x190+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP9_TXTYPE,USB0 EP9 Transmit Type Register"
|
|
endif
|
|
group.byte (0x190+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP9_TXINTERVAL,USB0 EP9 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x190+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP9_RXTYPE,USB0 EP9 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x190+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP9_RXTYPE,USB0 EP9 Receive Type Register"
|
|
endif
|
|
group.byte (0x190+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP9_RXINTERVAL,USB0 EP9 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x190+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP9_FIFOSZ,USB0 EP9 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x1A0++0x01 "Endpoint 10"
|
|
line.word 0x00 "USB0_EP10_TXMAXP,USB0 EP10 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x1A0+0x02)++0x01
|
|
line.word 0x00 "USB0_EP10_TXCSR_H,USB0 EP10 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x1A0+0x02)++0x01
|
|
line.word 0x00 "USB0_EP10_TXCSR_P,USB0 EP10 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x1A0+0x04)++0x01
|
|
line.word 0x00 "USB0_EP10_RXMAXP,USB0 EP10 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x1A0+0x06)++0x01
|
|
line.word 0x00 "USB0_EP10_RXCSR_H,USB0 EP10 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x1A0+0x06)++0x01
|
|
line.word 0x00 "USB0_EP10_RXCSR_P,USB0 EP10 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x1A0+0x08)++0x01
|
|
line.word 0x00 "USB0_EP10_RXCNT,USB0 EP10 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x1A0+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP10_TXTYPE,USB0 EP10 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x1A0+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP10_TXTYPE,USB0 EP10 Transmit Type Register"
|
|
endif
|
|
group.byte (0x1A0+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP10_TXINTERVAL,USB0 EP10 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x1A0+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP10_RXTYPE,USB0 EP10 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x1A0+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP10_RXTYPE,USB0 EP10 Receive Type Register"
|
|
endif
|
|
group.byte (0x1A0+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP10_RXINTERVAL,USB0 EP10 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x1A0+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP10_FIFOSZ,USB0 EP10 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x1B0++0x01 "Endpoint 11"
|
|
line.word 0x00 "USB0_EP11_TXMAXP,USB0 EP11 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x1B0+0x02)++0x01
|
|
line.word 0x00 "USB0_EP11_TXCSR_H,USB0 EP11 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x1B0+0x02)++0x01
|
|
line.word 0x00 "USB0_EP11_TXCSR_P,USB0 EP11 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x1B0+0x04)++0x01
|
|
line.word 0x00 "USB0_EP11_RXMAXP,USB0 EP11 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.word (0x1B0+0x06)++0x01
|
|
line.word 0x00 "USB0_EP11_RXCSR_H,USB0 EP11 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x1B0+0x06)++0x01
|
|
line.word 0x00 "USB0_EP11_RXCSR_P,USB0 EP11 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x1B0+0x08)++0x01
|
|
line.word 0x00 "USB0_EP11_RXCNT,USB0 EP11 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x1B0+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP11_TXTYPE,USB0 EP11 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x1B0+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP11_TXTYPE,USB0 EP11 Transmit Type Register"
|
|
endif
|
|
group.byte (0x1B0+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP11_TXINTERVAL,USB0 EP11 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x310C1000+0x60))&0x04)==0x04)
|
|
group.byte (0x1B0+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP11_RXTYPE,USB0 EP11 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x1B0+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP11_RXTYPE,USB0 EP11 Receive Type Register"
|
|
endif
|
|
group.byte (0x1B0+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP11_RXINTERVAL,USB0 EP11 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x1B0+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP11_FIFOSZ,USB0 EP11 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
width 20.
|
|
tree "DMA Registers"
|
|
hgroup.byte 0x200++0x00
|
|
hide.byte 0x00 "USB0_DMA_IRQ,USB0 DMA Interrupt Register"
|
|
in
|
|
group.word 0x204++0x01 "Channel 0"
|
|
line.word 0x00 "USB0_DMA0_CTL,USB0 DMA Channel 0 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x204+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA0_ADDR,USB0 DMA Channel 0 Address Register"
|
|
line.long 0x04 "USB0_DMA0_CNT,USB0 DMA Channel 0 Count Register"
|
|
group.word 0x214++0x01 "Channel 1"
|
|
line.word 0x00 "USB0_DMA1_CTL,USB0 DMA Channel 1 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x214+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA1_ADDR,USB0 DMA Channel 1 Address Register"
|
|
line.long 0x04 "USB0_DMA1_CNT,USB0 DMA Channel 1 Count Register"
|
|
group.word 0x224++0x01 "Channel 2"
|
|
line.word 0x00 "USB0_DMA2_CTL,USB0 DMA Channel 2 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x224+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA2_ADDR,USB0 DMA Channel 2 Address Register"
|
|
line.long 0x04 "USB0_DMA2_CNT,USB0 DMA Channel 2 Count Register"
|
|
group.word 0x234++0x01 "Channel 3"
|
|
line.word 0x00 "USB0_DMA3_CTL,USB0 DMA Channel 3 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x234+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA3_ADDR,USB0 DMA Channel 3 Address Register"
|
|
line.long 0x04 "USB0_DMA3_CNT,USB0 DMA Channel 3 Count Register"
|
|
group.word 0x244++0x01 "Channel 4"
|
|
line.word 0x00 "USB0_DMA4_CTL,USB0 DMA Channel 4 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x244+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA4_ADDR,USB0 DMA Channel 4 Address Register"
|
|
line.long 0x04 "USB0_DMA4_CNT,USB0 DMA Channel 4 Count Register"
|
|
group.word 0x254++0x01 "Channel 5"
|
|
line.word 0x00 "USB0_DMA5_CTL,USB0 DMA Channel 5 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x254+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA5_ADDR,USB0 DMA Channel 5 Address Register"
|
|
line.long 0x04 "USB0_DMA5_CNT,USB0 DMA Channel 5 Count Register"
|
|
group.word 0x264++0x01 "Channel 6"
|
|
line.word 0x00 "USB0_DMA6_CTL,USB0 DMA Channel 6 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x264+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA6_ADDR,USB0 DMA Channel 6 Address Register"
|
|
line.long 0x04 "USB0_DMA6_CNT,USB0 DMA Channel 6 Count Register"
|
|
group.word 0x274++0x01 "Channel 7"
|
|
line.word 0x00 "USB0_DMA7_CTL,USB0 DMA Channel 7 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x274+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA7_ADDR,USB0 DMA Channel 7 Address Register"
|
|
line.long 0x04 "USB0_DMA7_CNT,USB0 DMA Channel 7 Count Register"
|
|
tree.end
|
|
width 20.
|
|
tree "Endpoint Request Packet Count Registers"
|
|
group.word 0x300++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT0,USB0 EP0 Request Packet Count Register"
|
|
group.word 0x304++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT1,USB0 EP1 Request Packet Count Register"
|
|
group.word 0x308++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT2,USB0 EP2 Request Packet Count Register"
|
|
group.word 0x30C++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT3,USB0 EP3 Request Packet Count Register"
|
|
group.word 0x310++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT4,USB0 EP4 Request Packet Count Register"
|
|
group.word 0x314++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT5,USB0 EP5 Request Packet Count Register"
|
|
group.word 0x318++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT6,USB0 EP6 Request Packet Count Register"
|
|
group.word 0x31C++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT7,USB0 EP7 Request Packet Count Register"
|
|
group.word 0x320++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT8,USB0 EP8 Request Packet Count Register"
|
|
group.word 0x324++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT9,USB0 EP9 Request Packet Count Register"
|
|
group.word 0x328++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT10,USB0 EP10 Request Packet Count Register"
|
|
tree.end
|
|
width 22.
|
|
sif cpuis("ADSPCM40*")
|
|
group.word 0x340++0x03
|
|
line.word 0x00 "USB0_RXDPKTBUFDIS,USB0 RX Double Packet Buffer Disable for Endpoints"
|
|
bitfld.word 0x00 3. " EP3 ,Disable RX Double Buffer of Endpoint 3" "Enabled,Disabled"
|
|
bitfld.word 0x00 2. " EP2 ,Disable RX Double Buffer of Endpoint 2" "Enabled,Disabled"
|
|
bitfld.word 0x00 1. " EP1 ,Disable RX Double Buffer of Endpoint 1" "Enabled,Disabled"
|
|
line.word 0x02 "USB0_TXDPKTBUFDIS,USB0 TX Double Packet Buffer Disable for Endpoints"
|
|
bitfld.word 0x02 3. " EP3 ,Disable TX Double Buffer of Endpoint 3" "Enabled,Disabled"
|
|
bitfld.word 0x02 2. " EP2 ,Disable TX Double Buffer of Endpoint 2" "Enabled,Disabled"
|
|
bitfld.word 0x02 1. " EP1 ,Disable TX Double Buffer of Endpoint 1" "Enabled,Disabled"
|
|
else
|
|
group.word 0x344++0x05
|
|
line.word 0x00 "USB0_CT_UCH,USB0 Chirp Timeout Register"
|
|
hexmask.word 0x00 0.--14. 1. " VALUE ,Chirp timeout value"
|
|
line.word 0x02 "USB0_CT_HHSRTN,USB0 Host High Speed Return To Normal Register"
|
|
hexmask.word 0x02 0.--14. 1. " VALUE ,Host high speed return to normal value"
|
|
line.word 0x04 "USB0_CT_HSBT,USB0 High Speed Timeout Register"
|
|
bitfld.word 0x04 0.--3. " VALUE ,HS timeout adder" "736 bit time,800 bit time,864 bit time,?..."
|
|
endif
|
|
group.word 0x360++0x01
|
|
line.word 0x00 "USB0_LPM_ATTR,USB0 LPM Attribute Register"
|
|
bitfld.word 0x00 12.--15. " EP ,Endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.word 0x00 8. " RMTWAK ,Remote wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4.--7. " HIRD ,Host initiated resume duration" "50 us,125 us,200 us,275 us,350 us,425 us,500 us,575 us,650 us,725 us,800 us,875 us,950 us,1025 us,1100 us,1175 us"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " LINKSTATE ,Link state" ",Sleep state,?..."
|
|
group.byte 0x362++0x01
|
|
line.byte 0x00 "USB0_LPM_CTL,USB0 LPM Control Register"
|
|
bitfld.byte 0x00 4. " NAK ,LPM NAK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " EN ,LPM enable" "Disabled,Disabled,Enabled extended transactions,Enabled LPM and extended transactions"
|
|
bitfld.byte 0x00 1. " RESUME ,LPM resume (remote wakeup)" "No effect,Resume"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TX ,LPM transmit" "Disabled,Enabled"
|
|
line.byte 0x01 "USB0_LPM_IEN,USB0 LPM Interrupt Enable Register"
|
|
bitfld.byte 0x01 5. " LPMERR ,LPM error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " LPMRES ,LPM resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " LPMNC ,LPM NYET control interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " LPMACK ,LPM ACK interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " LPMNY ,LPM NYET interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " LPMST ,LPM STALL interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x364++0x00
|
|
hide.byte 0x00 "USB0_LPM_IRQ,USB0 LPM Interrupt Status Register"
|
|
in
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "USB0_LPM_FADDR,USB0 LPM Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,Function address value"
|
|
group.byte 0x380++0x00
|
|
line.byte 0x00 "USB0_VBUS_CTL,USB0 VBUS Control Register"
|
|
rbitfld.byte 0x00 4. " DRV ,VBUS drive" "Low,High"
|
|
eventfld.byte 0x00 3. " DRVINT ,VBUS drive interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " DRVIEN ,VBUS drive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DRVOD ,VBUS drive open drain" "No open drain,Open drain"
|
|
bitfld.byte 0x00 0. " INVDRV ,VBUS invert drive" "Not inverted,Inverted"
|
|
sif !cpuis("ADSPCM40*")
|
|
if ((((per.b(ad:0x310C1000+0x60))&0x80)==0x80)&&(((per.b(ad:0x310C1000+0x381))&0x01)==0x01))
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
bitfld.byte 0x00 4. " DEDCHG ,Dedicated charging port" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CONDET ,Connected detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
elif ((((per.b(ad:0x310C1000+0x60))&0x80)==0x80)&&(((per.b(ad:0x310C1000+0x381))&0x01)==0x00))
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
bitfld.byte 0x00 4. " DEDCHG ,Dedicated charging port" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
elif ((((per.b(ad:0x310C1000+0x60))&0x80)==0x00)&&(((per.b(ad:0x310C1000+0x381))&0x01)==0x01))
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 1. " CONDET ,Connected detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif !cpuis("ADSP-SC57?")
|
|
group.byte 0x382++0x00
|
|
line.byte 0x00 "USB0_IDCTL,USB0 ID Control"
|
|
bitfld.byte 0x00 1. " IDVAL ,ID value" "0,1"
|
|
bitfld.byte 0x00 0. " IDSEL ,ID select" "0,1"
|
|
endif
|
|
sif cpuis("ADSPCM40*")
|
|
group.byte 0x39C++0x00
|
|
line.byte 0x00 "USB0_PHY_CTL,USB0 PHY Control Register"
|
|
bitfld.byte 0x00 1. " SUSPEND ,Suspend power" "Normal operation,Enabled"
|
|
bitfld.byte 0x00 0. " PHYMAN ,PHY management" "From controller,From PHY_CTL"
|
|
rgroup.word 0x3A0++0x01
|
|
line.word 0x00 "USB0_PHY_STAT,USB0 PHY Status Register"
|
|
bitfld.word 0x00 7. " VBUSVALID ,Vbus Voltage Valid" "Vbus < 4.4V,Vbus >4.75V"
|
|
bitfld.word 0x00 5. " AVALID ,Vbus Voltage A Device Valid" "Vbus < 0.8V,Vbus > 2V"
|
|
bitfld.word 0x00 4. " VBUSLO ,Vbus Voltage Session End" "Vbus > 0.8V,Vbus < 0.2V"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CID ,ID Input State" "0,1"
|
|
else
|
|
group.byte 0x394++0x00
|
|
line.byte 0x00 "USB0_PHY_CTL,USB0 PHY Control Register"
|
|
bitfld.byte 0x00 7. " EN ,PHY enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("ADSP-SC57?")
|
|
bitfld.byte 0x00 4. " DIS ,Disable PHY" "Yes,No"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 1. " RESTORE ,Restore from hibernate" "Not restore,Restore"
|
|
bitfld.byte 0x00 0. " HIBER ,Hibernate" "Disabled,Enabled"
|
|
group.word 0x398++0x01
|
|
line.word 0x00 "USB0_PLL_OSC,USB0 PLL And Oscillator Control Register"
|
|
rbitfld.word 0x00 14. " PLLSTABLE ,PLL stable" "Unstable,Stable"
|
|
bitfld.word 0x00 7. " PLLMSEL ,PLL multiplier select" "Not used,Used"
|
|
bitfld.word 0x00 1.--6. " PLLM ,PLL multiplier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DIVCLKIN ,Divide CLKIN" "Not divided,Divided by 2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "MLB (Media Local Bus)"
|
|
base ad:0x3109D000
|
|
width 12.
|
|
if (((per.l(ad:0x3109D000+0x00))&0x20)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MLB0_CTL0,MLB0 Medialb Control 0 Register"
|
|
bitfld.long 0x00 15.--17. " FCNT ,Frames per Sub-buffer" "1 frame,2 frames,4 frames,8 frames,16 frames,32 frames,64 frames,?..."
|
|
bitfld.long 0x00 14. " CTLRETRY ,Control TX packet retry" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASYRETRY ,Asynchronous TX packet retry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " LKSTAT ,Lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PEN ,6-pin interface enable" "3-pin,6-pin"
|
|
bitfld.long 0x00 2.--4. " CLK ,Clock speed select" "256 x fs,512 x fs,1024 x fs,?..."
|
|
bitfld.long 0x00 0. " EN ,Medialb enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MLB0_CTL0,MLB0 Medialb Control 0 Register"
|
|
bitfld.long 0x00 15.--17. " FCNT ,Frames per Sub-buffer" "1 frame,2 frames,4 frames,8 frames,16 frames,32 frames,64 frames,?..."
|
|
bitfld.long 0x00 14. " CTLRETRY ,Control TX packet retry" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASYRETRY ,Asynchronous TX packet retry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " LKSTAT ,Lock status" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PEN ,6-pin interface enable" "3-pin,6-pin"
|
|
bitfld.long 0x00 2.--4. " CLK ,Clock speed select" ",,,2048 x fs,3072 x fs,4096 x fs,6144 x fs,8192 x fs"
|
|
bitfld.long 0x00 0. " EN ,Medialb enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MLB0_PCTL0,MLB0 Medialb 6-pin Control 0 Register"
|
|
bitfld.long 0x00 1. " CMRES ,Medialb 6-pin common mode resistor enable (No longer used)" "0,1"
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MLB0_MS0,MLB0 Channel Status 0 Register"
|
|
bitfld.long 0x00 31. " MCS[31] ,Medialb channel status - channel 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,Medialb channel status - channel 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,Medialb channel status - channel 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,Medialb channel status - channel 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Medialb channel status - channel 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,Medialb channel status - channel 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [25] ,Medialb channel status - channel 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,Medialb channel status - channel 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Medialb channel status - channel 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,Medialb channel status - channel 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,Medialb channel status - channel 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,Medialb channel status - channel 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Medialb channel status - channel 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,Medialb channel status - channel 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,Medialb channel status - channel 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,Medialb channel status - channel 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Medialb channel status - channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,Medialb channel status - channel 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Medialb channel status - channel 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Medialb channel status - channel 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Medialb channel status - channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,Medialb channel status - channel 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,Medialb channel status - channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Medialb channel status - channel 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Medialb channel status - channel 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Medialb channel status - channel 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Medialb channel status - channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Medialb channel status - channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Medialb channel status - channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Medialb channel status - channel 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,Medialb channel status - channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Medialb channel status - channel 0" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MLB0_MS1,MLB0 Channel Status 1 Register"
|
|
bitfld.long 0x00 31. " MCS[63] ,Medialb channel status - channel 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [62] ,Medialb channel status - channel 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [61] ,Medialb channel status - channel 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [60] ,Medialb channel status - channel 60" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Medialb channel status - channel 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [58] ,Medialb channel status - channel 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [57] ,Medialb channel status - channel 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,Medialb channel status - channel 56" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Medialb channel status - channel 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [54] ,Medialb channel status - channel 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [53] ,Medialb channel status - channel 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [52] ,Medialb channel status - channel 52" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Medialb channel status - channel 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [50] ,Medialb channel status - channel 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [49] ,Medialb channel status - channel 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [48] ,Medialb channel status - channel 48" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,Medialb channel status - channel 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [46] ,Medialb channel status - channel 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [45] ,Medialb channel status - channel 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [44] ,Medialb channel status - channel 44" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Medialb channel status - channel 43" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [42] ,Medialb channel status - channel 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [41] ,Medialb channel status - channel 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [40] ,Medialb channel status - channel 40" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Medialb channel status - channel 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [38] ,Medialb channel status - channel 38" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [37] ,Medialb channel status - channel 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [36] ,Medialb channel status - channel 36" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Medialb channel status - channel 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [34] ,Medialb channel status - channel 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [33] ,Medialb channel status - channel 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [32] ,Medialb channel status - channel 32" "No interrupt,Interrupt"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MLB0_MSS,MLB0 System Status Register"
|
|
bitfld.long 0x00 5. " SERVREQ ,Service request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SWSYSCMD ,Software system command detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " CSSYSCMD ,Channel scan system command detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ULKSYSCMD ,Network unlock system command detected" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " LKSYSCMD ,Network lock system command detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " RSTSYSCMD ,Reset system command detected" "Not detected,Detected"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "MLB0_MSD,MLB0 System Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SD3 ,System data byte 3 (Msb)"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SD2 ,System data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SD1 ,System data byte 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SD0 ,System data byte 0 (Lsb)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MLB0_MIEN,MLB0 Interrupt Enable Register"
|
|
bitfld.long 0x00 29. " CTXBREAK ,Control transmit break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CTXPE ,Control transmit protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CTXDONE ,Control transmit packet done enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CRXBREAK ,Control receive break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CRXPE ,Control receive protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CRXDONE ,Control receive packet done enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ATXBREAK ,Asynchronous transmit break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ATXPE ,Asynchronous transmit protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ATXDONE ,Asynchronous transmit done enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ARXBREAK ,Asynchronous receive break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ARXPE ,Asynchronous receive protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ARXDONE ,Asynchronous receive packet done enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SYNCPE ,Synchronous protocol error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ISOCBUFO ,Isochronous receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ISOCPE ,Isochronous receive protocol error enable" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MLB0_GCTL,MLB0 MLB Global Control Register"
|
|
bitfld.long 0x00 2. " CLKOUTSEL ,CLKOUT select" "MLB 3-pin clk,MLB 6-pin clk"
|
|
bitfld.long 0x00 1. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MLB0_CTL1,MLB0 Control 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NDA ,Node device address"
|
|
eventfld.long 0x00 7. " CLKM ,Lock missing status" "Not missing,Missing"
|
|
eventfld.long 0x00 6. " LOCK ,Lock error status" "No error,Error"
|
|
tree "Host Bus Interface"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MLB0_HCTL,MLB0 HBI Control Register"
|
|
bitfld.long 0x00 15. " EN ,HBI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RST1 ,AGU1 software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RST0 ,AGU0 software reset" "No reset,Reset"
|
|
textline " "
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "MLB0_HCMR0,MLB0 HBI Channel Mask 0 Register"
|
|
bitfld.long 0x00 31. " CHM[31] ,Bitwise channel HBI interrupt mask - channel 31" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " [30] ,Bitwise channel HBI interrupt mask - channel 30" "Masked,Unmasked"
|
|
bitfld.long 0x00 29. " [29] ,Bitwise channel HBI interrupt mask - channel 29" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " [28] ,Bitwise channel HBI interrupt mask - channel 28" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Bitwise channel HBI interrupt mask - channel 27" "Masked,Unmasked"
|
|
bitfld.long 0x00 26. " [26] ,Bitwise channel HBI interrupt mask - channel 26" "Masked,Unmasked"
|
|
bitfld.long 0x00 25. " [25] ,Bitwise channel HBI interrupt mask - channel 25" "Masked,Unmasked"
|
|
bitfld.long 0x00 24. " [24] ,Bitwise channel HBI interrupt mask - channel 24" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Bitwise channel HBI interrupt mask - channel 23" "Masked,Unmasked"
|
|
bitfld.long 0x00 22. " [22] ,Bitwise channel HBI interrupt mask - channel 22" "Masked,Unmasked"
|
|
bitfld.long 0x00 21. " [21] ,Bitwise channel HBI interrupt mask - channel 21" "Masked,Unmasked"
|
|
bitfld.long 0x00 20. " [20] ,Bitwise channel HBI interrupt mask - channel 20" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Bitwise channel HBI interrupt mask - channel 19" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " [18] ,Bitwise channel HBI interrupt mask - channel 18" "Masked,Unmasked"
|
|
bitfld.long 0x00 17. " [17] ,Bitwise channel HBI interrupt mask - channel 17" "Masked,Unmasked"
|
|
bitfld.long 0x00 16. " [16] ,Bitwise channel HBI interrupt mask - channel 16" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Bitwise channel HBI interrupt mask - channel 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " [14] ,Bitwise channel HBI interrupt mask - channel 14" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " [13] ,Bitwise channel HBI interrupt mask - channel 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " [12] ,Bitwise channel HBI interrupt mask - channel 12" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Bitwise channel HBI interrupt mask - channel 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " [10] ,Bitwise channel HBI interrupt mask - channel 10" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " [9] ,Bitwise channel HBI interrupt mask - channel 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " [8] ,Bitwise channel HBI interrupt mask - channel 8" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Bitwise channel HBI interrupt mask - channel 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " [6] ,Bitwise channel HBI interrupt mask - channel 6" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " [5] ,Bitwise channel HBI interrupt mask - channel 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " [4] ,Bitwise channel HBI interrupt mask - channel 4" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Bitwise channel HBI interrupt mask - channel 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " [2] ,Bitwise channel HBI interrupt mask - channel 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " [1] ,Bitwise channel HBI interrupt mask - channel 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " [0] ,Bitwise channel HBI interrupt mask - channel 0" "Masked,Unmasked"
|
|
line.long 0x04 "MLB0_HCMR1,MLB0 HBI Channel Mask 1 Register"
|
|
bitfld.long 0x04 31. " CHM[63] ,Bitwise channel HBI interrupt mask - channel 63" "Masked,Unmasked"
|
|
bitfld.long 0x04 30. " [62] ,Bitwise channel HBI interrupt mask - channel 62" "Masked,Unmasked"
|
|
bitfld.long 0x04 29. " [61] ,Bitwise channel HBI interrupt mask - channel 61" "Masked,Unmasked"
|
|
bitfld.long 0x04 28. " [60] ,Bitwise channel HBI interrupt mask - channel 60" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Bitwise channel HBI interrupt mask - channel 59" "Masked,Unmasked"
|
|
bitfld.long 0x04 26. " [58] ,Bitwise channel HBI interrupt mask - channel 58" "Masked,Unmasked"
|
|
bitfld.long 0x04 25. " [57] ,Bitwise channel HBI interrupt mask - channel 57" "Masked,Unmasked"
|
|
bitfld.long 0x04 24. " [56] ,Bitwise channel HBI interrupt mask - channel 56" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Bitwise channel HBI interrupt mask - channel 55" "Masked,Unmasked"
|
|
bitfld.long 0x04 22. " [54] ,Bitwise channel HBI interrupt mask - channel 54" "Masked,Unmasked"
|
|
bitfld.long 0x04 21. " [53] ,Bitwise channel HBI interrupt mask - channel 53" "Masked,Unmasked"
|
|
bitfld.long 0x04 20. " [52] ,Bitwise channel HBI interrupt mask - channel 52" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Bitwise channel HBI interrupt mask - channel 51" "Masked,Unmasked"
|
|
bitfld.long 0x04 18. " [50] ,Bitwise channel HBI interrupt mask - channel 50" "Masked,Unmasked"
|
|
bitfld.long 0x04 17. " [49] ,Bitwise channel HBI interrupt mask - channel 49" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " [48] ,Bitwise channel HBI interrupt mask - channel 48" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Bitwise channel HBI interrupt mask - channel 47" "Masked,Unmasked"
|
|
bitfld.long 0x04 14. " [46] ,Bitwise channel HBI interrupt mask - channel 46" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " [45] ,Bitwise channel HBI interrupt mask - channel 45" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " [44] ,Bitwise channel HBI interrupt mask - channel 44" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Bitwise channel HBI interrupt mask - channel 43" "Masked,Unmasked"
|
|
bitfld.long 0x04 10. " [42] ,Bitwise channel HBI interrupt mask - channel 42" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " [41] ,Bitwise channel HBI interrupt mask - channel 41" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " [40] ,Bitwise channel HBI interrupt mask - channel 40" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Bitwise channel HBI interrupt mask - channel 39" "Masked,Unmasked"
|
|
bitfld.long 0x04 6. " [38] ,Bitwise channel HBI interrupt mask - channel 38" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " [37] ,Bitwise channel HBI interrupt mask - channel 37" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " [36] ,Bitwise channel HBI interrupt mask - channel 36" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Bitwise channel HBI interrupt mask - channel 35" "Masked,Unmasked"
|
|
bitfld.long 0x04 2. " [34] ,Bitwise channel HBI interrupt mask - channel 34" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " [33] ,Bitwise channel HBI interrupt mask - channel 33" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " [32] ,Bitwise channel HBI interrupt mask - channel 32" "Masked,Unmasked"
|
|
line.long 0x08 "MLB0_HCER0,MLB0 HBI Channel Error 0 Register"
|
|
bitfld.long 0x08 31. " CERR[31] ,Bitwise channel error - channel 31" "No error,Error"
|
|
bitfld.long 0x08 30. " [30] ,Bitwise channel error - channel 30" "No error,Error"
|
|
bitfld.long 0x08 29. " [29] ,Bitwise channel error - channel 29" "No error,Error"
|
|
bitfld.long 0x08 28. " [28] ,Bitwise channel error - channel 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Bitwise channel error - channel 27" "No error,Error"
|
|
bitfld.long 0x08 26. " [26] ,Bitwise channel error - channel 26" "No error,Error"
|
|
bitfld.long 0x08 25. " [25] ,Bitwise channel error - channel 25" "No error,Error"
|
|
bitfld.long 0x08 24. " [24] ,Bitwise channel error - channel 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Bitwise channel error - channel 23" "No error,Error"
|
|
bitfld.long 0x08 22. " [22] ,Bitwise channel error - channel 22" "No error,Error"
|
|
bitfld.long 0x08 21. " [21] ,Bitwise channel error - channel 21" "No error,Error"
|
|
bitfld.long 0x08 20. " [20] ,Bitwise channel error - channel 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Bitwise channel error - channel 19" "No error,Error"
|
|
bitfld.long 0x08 18. " [18] ,Bitwise channel error - channel 18" "No error,Error"
|
|
bitfld.long 0x08 17. " [17] ,Bitwise channel error - channel 17" "No error,Error"
|
|
bitfld.long 0x08 16. " [16] ,Bitwise channel error - channel 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Bitwise channel error - channel 15" "No error,Error"
|
|
bitfld.long 0x08 14. " [14] ,Bitwise channel error - channel 14" "No error,Error"
|
|
bitfld.long 0x08 13. " [13] ,Bitwise channel error - channel 13" "No error,Error"
|
|
bitfld.long 0x08 12. " [12] ,Bitwise channel error - channel 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Bitwise channel error - channel 11" "No error,Error"
|
|
bitfld.long 0x08 10. " [10] ,Bitwise channel error - channel 10" "No error,Error"
|
|
bitfld.long 0x08 9. " [9] ,Bitwise channel error - channel 9" "No error,Error"
|
|
bitfld.long 0x08 8. " [8] ,Bitwise channel error - channel 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Bitwise channel error - channel 7" "No error,Error"
|
|
bitfld.long 0x08 6. " [6] ,Bitwise channel error - channel 6" "No error,Error"
|
|
bitfld.long 0x08 5. " [5] ,Bitwise channel error - channel 5" "No error,Error"
|
|
bitfld.long 0x08 4. " [4] ,Bitwise channel error - channel 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Bitwise channel error - channel 3" "No error,Error"
|
|
bitfld.long 0x08 2. " [2] ,Bitwise channel error - channel 2" "No error,Error"
|
|
bitfld.long 0x08 1. " [1] ,Bitwise channel error - channel 1" "No error,Error"
|
|
bitfld.long 0x08 0. " [0] ,Bitwise channel error - channel 0" "No error,Error"
|
|
line.long 0x0C "MLB0_HCER1,MLB0 HBI Channel Error 1 Register"
|
|
bitfld.long 0x0C 31. " CERR[63] ,Bitwise channel error - channel 63" "No error,Error"
|
|
bitfld.long 0x0C 30. " [62] ,Bitwise channel error - channel 62" "No error,Error"
|
|
bitfld.long 0x0C 29. " [61] ,Bitwise channel error - channel 61" "No error,Error"
|
|
bitfld.long 0x0C 28. " [60] ,Bitwise channel error - channel 60" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [59] ,Bitwise channel error - channel 59" "No error,Error"
|
|
bitfld.long 0x0C 26. " [58] ,Bitwise channel error - channel 58" "No error,Error"
|
|
bitfld.long 0x0C 25. " [57] ,Bitwise channel error - channel 57" "No error,Error"
|
|
bitfld.long 0x0C 24. " [56] ,Bitwise channel error - channel 56" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [55] ,Bitwise channel error - channel 55" "No error,Error"
|
|
bitfld.long 0x0C 22. " [54] ,Bitwise channel error - channel 54" "No error,Error"
|
|
bitfld.long 0x0C 21. " [53] ,Bitwise channel error - channel 53" "No error,Error"
|
|
bitfld.long 0x0C 20. " [52] ,Bitwise channel error - channel 52" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [51] ,Bitwise channel error - channel 51" "No error,Error"
|
|
bitfld.long 0x0C 18. " [50] ,Bitwise channel error - channel 50" "No error,Error"
|
|
bitfld.long 0x0C 17. " [49] ,Bitwise channel error - channel 49" "No error,Error"
|
|
bitfld.long 0x0C 16. " [48] ,Bitwise channel error - channel 48" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [47] ,Bitwise channel error - channel 47" "No error,Error"
|
|
bitfld.long 0x0C 14. " [46] ,Bitwise channel error - channel 46" "No error,Error"
|
|
bitfld.long 0x0C 13. " [45] ,Bitwise channel error - channel 45" "No error,Error"
|
|
bitfld.long 0x0C 12. " [44] ,Bitwise channel error - channel 44" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [43] ,Bitwise channel error - channel 43" "No error,Error"
|
|
bitfld.long 0x0C 10. " [42] ,Bitwise channel error - channel 42" "No error,Error"
|
|
bitfld.long 0x0C 9. " [41] ,Bitwise channel error - channel 41" "No error,Error"
|
|
bitfld.long 0x0C 8. " [40] ,Bitwise channel error - channel 40" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [39] ,Bitwise channel error - channel 39" "No error,Error"
|
|
bitfld.long 0x0C 6. " [38] ,Bitwise channel error - channel 38" "No error,Error"
|
|
bitfld.long 0x0C 5. " [37] ,Bitwise channel error - channel 37" "No error,Error"
|
|
bitfld.long 0x0C 4. " [36] ,Bitwise channel error - channel 36" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [35] ,Bitwise channel error - channel 35" "No error,Error"
|
|
bitfld.long 0x0C 2. " [34] ,Bitwise channel error - channel 34" "No error,Error"
|
|
bitfld.long 0x0C 1. " [33] ,Bitwise channel error - channel 33" "No error,Error"
|
|
bitfld.long 0x0C 0. " [32] ,Bitwise channel error - channel 32" "No error,Error"
|
|
rgroup.long 0x98++0x07
|
|
line.long 0x00 "MLB0_HCBR0,MLB0 HBI Channel Busy 0 Register"
|
|
bitfld.long 0x00 31. " CHB[31] ,Bitwise channel busy bit - channel 31" "Idle,Busy"
|
|
bitfld.long 0x00 30. " [30] ,Bitwise channel busy bit - channel 30" "Idle,Busy"
|
|
bitfld.long 0x00 29. " [29] ,Bitwise channel busy bit - channel 29" "Idle,Busy"
|
|
bitfld.long 0x00 28. " [28] ,Bitwise channel busy bit - channel 28" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Bitwise channel busy bit - channel 27" "Idle,Busy"
|
|
bitfld.long 0x00 26. " [26] ,Bitwise channel busy bit - channel 26" "Idle,Busy"
|
|
bitfld.long 0x00 25. " [25] ,Bitwise channel busy bit - channel 25" "Idle,Busy"
|
|
bitfld.long 0x00 24. " [24] ,Bitwise channel busy bit - channel 24" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Bitwise channel busy bit - channel 23" "Idle,Busy"
|
|
bitfld.long 0x00 22. " [22] ,Bitwise channel busy bit - channel 22" "Idle,Busy"
|
|
bitfld.long 0x00 21. " [21] ,Bitwise channel busy bit - channel 21" "Idle,Busy"
|
|
bitfld.long 0x00 20. " [20] ,Bitwise channel busy bit - channel 20" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Bitwise channel busy bit - channel 19" "Idle,Busy"
|
|
bitfld.long 0x00 18. " [18] ,Bitwise channel busy bit - channel 18" "Idle,Busy"
|
|
bitfld.long 0x00 17. " [17] ,Bitwise channel busy bit - channel 17" "Idle,Busy"
|
|
bitfld.long 0x00 16. " [16] ,Bitwise channel busy bit - channel 16" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Bitwise channel busy bit - channel 15" "Idle,Busy"
|
|
bitfld.long 0x00 14. " [14] ,Bitwise channel busy bit - channel 14" "Idle,Busy"
|
|
bitfld.long 0x00 13. " [13] ,Bitwise channel busy bit - channel 13" "Idle,Busy"
|
|
bitfld.long 0x00 12. " [12] ,Bitwise channel busy bit - channel 12" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Bitwise channel busy bit - channel 11" "Idle,Busy"
|
|
bitfld.long 0x00 10. " [10] ,Bitwise channel busy bit - channel 10" "Idle,Busy"
|
|
bitfld.long 0x00 9. " [9] ,Bitwise channel busy bit - channel 9" "Idle,Busy"
|
|
bitfld.long 0x00 8. " [8] ,Bitwise channel busy bit - channel 8" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Bitwise channel busy bit - channel 7" "Idle,Busy"
|
|
bitfld.long 0x00 6. " [6] ,Bitwise channel busy bit - channel 6" "Idle,Busy"
|
|
bitfld.long 0x00 5. " [5] ,Bitwise channel busy bit - channel 5" "Idle,Busy"
|
|
bitfld.long 0x00 4. " [4] ,Bitwise channel busy bit - channel 4" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Bitwise channel busy bit - channel 3" "Idle,Busy"
|
|
bitfld.long 0x00 2. " [2] ,Bitwise channel busy bit - channel 2" "Idle,Busy"
|
|
bitfld.long 0x00 1. " [1] ,Bitwise channel busy bit - channel 1" "Idle,Busy"
|
|
bitfld.long 0x00 0. " [0] ,Bitwise channel busy bit - channel 0" "Idle,Busy"
|
|
line.long 0x04 "MLB0_HCBR1,MLB0 HBI Channel Busy 1 Register"
|
|
bitfld.long 0x04 31. " CHB[63] ,Bitwise channel busy bit - channel 63" "Idle,Busy"
|
|
bitfld.long 0x04 30. " [62] ,Bitwise channel busy bit - channel 62" "Idle,Busy"
|
|
bitfld.long 0x04 29. " [61] ,Bitwise channel busy bit - channel 61" "Idle,Busy"
|
|
bitfld.long 0x04 28. " [60] ,Bitwise channel busy bit - channel 60" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Bitwise channel busy bit - channel 59" "Idle,Busy"
|
|
bitfld.long 0x04 26. " [58] ,Bitwise channel busy bit - channel 58" "Idle,Busy"
|
|
bitfld.long 0x04 25. " [57] ,Bitwise channel busy bit - channel 57" "Idle,Busy"
|
|
bitfld.long 0x04 24. " [56] ,Bitwise channel busy bit - channel 56" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Bitwise channel busy bit - channel 55" "Idle,Busy"
|
|
bitfld.long 0x04 22. " [54] ,Bitwise channel busy bit - channel 54" "Idle,Busy"
|
|
bitfld.long 0x04 21. " [53] ,Bitwise channel busy bit - channel 53" "Idle,Busy"
|
|
bitfld.long 0x04 20. " [52] ,Bitwise channel busy bit - channel 52" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Bitwise channel busy bit - channel 51" "Idle,Busy"
|
|
bitfld.long 0x04 18. " [50] ,Bitwise channel busy bit - channel 50" "Idle,Busy"
|
|
bitfld.long 0x04 17. " [49] ,Bitwise channel busy bit - channel 49" "Idle,Busy"
|
|
bitfld.long 0x04 16. " [48] ,Bitwise channel busy bit - channel 48" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Bitwise channel busy bit - channel 47" "Idle,Busy"
|
|
bitfld.long 0x04 14. " [46] ,Bitwise channel busy bit - channel 46" "Idle,Busy"
|
|
bitfld.long 0x04 13. " 45] ,Bitwise channel busy bit - channel 45" "Idle,Busy"
|
|
bitfld.long 0x04 12. " [44] ,Bitwise channel busy bit - channel 44" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Bitwise channel busy bit - channel 43" "Idle,Busy"
|
|
bitfld.long 0x04 10. " [42] ,Bitwise channel busy bit - channel 42" "Idle,Busy"
|
|
bitfld.long 0x04 9. " [41] ,Bitwise channel busy bit - channel 41" "Idle,Busy"
|
|
bitfld.long 0x04 8. " [40] ,Bitwise channel busy bit - channel 40" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Bitwise channel busy bit - channel 39" "Idle,Busy"
|
|
bitfld.long 0x04 6. " [38] ,Bitwise channel busy bit - channel 38" "Idle,Busy"
|
|
bitfld.long 0x04 5. " [37] ,Bitwise channel busy bit - channel 37" "Idle,Busy"
|
|
bitfld.long 0x04 4. " [36] ,Bitwise channel busy bit - channel 36" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Bitwise channel busy bit - channel 35" "Idle,Busy"
|
|
bitfld.long 0x04 2. " [34] ,Bitwise channel busy bit - channel 34" "Idle,Busy"
|
|
bitfld.long 0x04 1. " [33] ,Bitwise channel busy bit - channel 33" "Idle,Busy"
|
|
bitfld.long 0x04 0. " [32] ,Bitwise channel busy bit - channel 32" "Idle,Busy"
|
|
tree.end
|
|
width 12.
|
|
tree "Memory Interface"
|
|
group.long 0xC0++0x0F
|
|
line.long 0x00 "MLB0_MDAT0,MLB0 Memory Interface Control Data 0 Register"
|
|
line.long 0x04 "MLB0_MDAT1,MLB0 Memory Interface Control Data 1 Register"
|
|
line.long 0x08 "MLB0_MDAT2,MLB0 Memory Interface Control Data 2 Register"
|
|
line.long 0x0C "MLB0_MDAT3,MLB0 Memory Interface Control Data 3 Register"
|
|
group.long 0xD0++0x0F
|
|
line.long 0x00 "MLB0_MDWE0,MLB0 Memory Interface Control Data Write Enable 0 Register"
|
|
bitfld.long 0x00 31. " MSK[31] ,Write enable for CTR data - bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Write enable for CTR data - bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Write enable for CTR data - bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Write enable for CTR data - bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Write enable for CTR data - bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Write enable for CTR data - bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Write enable for CTR data - bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Write enable for CTR data - bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Write enable for CTR data - bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Write enable for CTR data - bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Write enable for CTR data - bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Write enable for CTR data - bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Write enable for CTR data - bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Write enable for CTR data - bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Write enable for CTR data - bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Write enable for CTR data - bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Write enable for CTR data - bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Write enable for CTR data - bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Write enable for CTR data - bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Write enable for CTR data - bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Write enable for CTR data - bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Write enable for CTR data - bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Write enable for CTR data - bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Write enable for CTR data - bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Write enable for CTR data - bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Write enable for CTR data - bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Write enable for CTR data - bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Write enable for CTR data - bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Write enable for CTR data - bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Write enable for CTR data - bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Write enable for CTR data - bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Write enable for CTR data - bit 0" "Disabled,Enabled"
|
|
line.long 0x04 "MLB0_MDWE1,MLB0 Memory Interface Control Data Write Enable 1 Register"
|
|
bitfld.long 0x04 31. " MSK[63] ,Write enable for CTR data - bit 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Write enable for CTR data - bit 62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Write enable for CTR data - bit 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Write enable for CTR data - bit 60" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Write enable for CTR data - bit 59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Write enable for CTR data - bit 58" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Write enable for CTR data - bit 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Write enable for CTR data - bit 56" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Write enable for CTR data - bit 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Write enable for CTR data - bit 54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Write enable for CTR data - bit 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Write enable for CTR data - bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Write enable for CTR data - bit 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Write enable for CTR data - bit 50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Write enable for CTR data - bit 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Write enable for CTR data - bit 48" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Write enable for CTR data - bit 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Write enable for CTR data - bit 46" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Write enable for CTR data - bit 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Write enable for CTR data - bit 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Write enable for CTR data - bit 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Write enable for CTR data - bit 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Write enable for CTR data - bit 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Write enable for CTR data - bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Write enable for CTR data - bit 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Write enable for CTR data - bit 38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Write enable for CTR data - bit 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Write enable for CTR data - bit 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Write enable for CTR data - bit 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Write enable for CTR data - bit 34" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Write enable for CTR data - bit 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Write enable for CTR data - bit 32" "Disabled,Enabled"
|
|
line.long 0x08 "MLB0_MDWE2,MLB0 Memory Interface Control Data Write Enable 2 Register"
|
|
bitfld.long 0x08 31. " MSK[95] ,Write enable for CTR data - bit 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Write enable for CTR data - bit 94" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Write enable for CTR data - bit 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Write enable for CTR data - bit 92" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Write enable for CTR data - bit 91" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Write enable for CTR data - bit 90" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Write enable for CTR data - bit 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Write enable for CTR data - bit 88" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Write enable for CTR data - bit 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Write enable for CTR data - bit 86" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Write enable for CTR data - bit 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Write enable for CTR data - bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Write enable for CTR data - bit 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Write enable for CTR data - bit 82" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Write enable for CTR data - bit 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Write enable for CTR data - bit 80" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Write enable for CTR data - bit 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Write enable for CTR data - bit 78" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Write enable for CTR data - bit 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Write enable for CTR data - bit 76" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Write enable for CTR data - bit 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Write enable for CTR data - bit 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Write enable for CTR data - bit 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Write enable for CTR data - bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Write enable for CTR data - bit 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Write enable for CTR data - bit 70" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Write enable for CTR data - bit 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Write enable for CTR data - bit 68" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Write enable for CTR data - bit 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Write enable for CTR data - bit 66" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Write enable for CTR data - bit 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Write enable for CTR data - bit 64" "Disabled,Enabled"
|
|
line.long 0x0C "MLB0_MDWE3,MLB064 Memory Interface Control Data Writ64e Enable 3 Register"
|
|
bitfld.long 0x0C 31. " MSK[127] ,Write enable for CTR data - bit 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Write enable for CTR data - bit 126" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Write enable for CTR data - bit 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Write enable for CTR data - bit 124" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Write enable for CTR data - bit 123" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Write enable for CTR data - bit 122" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Write enable for CTR data - bit 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Write enable for CTR data - bit 120" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Write enable for CTR data - bit 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Write enable for CTR data - bit 118" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Write enable for CTR data - bit 117" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Write enable for CTR data - bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Write enable for CTR data - bit 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Write enable for CTR data - bit 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Write enable for CTR data - bit 113" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Write enable for CTR data - bit 112" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Write enable for CTR data - bit 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Write enable for CTR data - bit 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Write enable for CTR data - bit 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Write enable for CTR data - bit 108" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Write enable for CTR data - bit 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Write enable for CTR data - bit 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Write enable for CTR data - bit 105" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Write enable for CTR data - bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Write enable for CTR data - bit 103" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [102] ,Write enable for CTR data - bit 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,Write enable for CTR data - bit 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Write enable for CTR data - bit 100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Write enable for CTR data - bit 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Write enable for CTR data - bit 98" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Write enable for CTR data - bit 97" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Write enable for CTR data - bit 96" "Disabled,Enabled"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "MLB0_MCTL,MLB0 Memory Interface Control Register"
|
|
bitfld.long 0x00 0. " XCMP ,Transfer complete (Write 0 to clear)" "Not completed,Completed"
|
|
line.long 0x04 "MLB0_MADR,MLB0 Memory Interface Address Register"
|
|
bitfld.long 0x04 31. " WNR ,Write-not-read" "Read,Write"
|
|
bitfld.long 0x04 30. " TB ,Target bit (Channel table RAM / data buffer RAM)" "CTR,DBR"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ADDRH ,Address higher bits"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADDRL ,Address lower bits"
|
|
tree.end
|
|
tree "Peripheral Interface"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "MLB0_ACTL,MLB0 Bus Control"
|
|
bitfld.long 0x00 4. " MPB ,Packet buffering mode" "Single-packet,Multiple-packet"
|
|
bitfld.long 0x00 2. " DMAMODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 1. " SMX ,Interrupt multiplex (Enable ACSR[0/1] interrupts generation on MLB_INT[0] only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SCE ,Software clear enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x3D0++0x1F
|
|
line.long 0x00 "MLB0_ACSR0,MLB0 Peripheral Channel Status 0"
|
|
eventfld.long 0x00 31. " CHS[31] ,Bitwise channel status - channel 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Bitwise channel status - channel 30" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Bitwise channel status - channel 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Bitwise channel status - channel 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Bitwise channel status - channel 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Bitwise channel status - channel 26" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Bitwise channel status - channel 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Bitwise channel status - channel 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Bitwise channel status - channel 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Bitwise channel status - channel 22" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Bitwise channel status - channel 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Bitwise channel status - channel 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Bitwise channel status - channel 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Bitwise channel status - channel 18" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Bitwise channel status - channel 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Bitwise channel status - channel 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Bitwise channel status - channel 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Bitwise channel status - channel 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Bitwise channel status - channel 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Bitwise channel status - channel 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Bitwise channel status - channel 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Bitwise channel status - channel 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Bitwise channel status - channel 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Bitwise channel status - channel 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Bitwise channel status - channel 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Bitwise channel status - channel 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Bitwise channel status - channel 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Bitwise channel status - channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Bitwise channel status - channel 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Bitwise channel status - channel 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Bitwise channel status - channel 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Bitwise channel status - channel 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "MLB0_ACSR1,MLB0 Peripheral Channel Status 1"
|
|
eventfld.long 0x04 31. " CHS[63] ,Bitwise channel status - channel 63" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 30. " [62] ,Bitwise channel status - channel 62" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " [61] ,Bitwise channel status - channel 61" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 28. " [60] ,Bitwise channel status - channel 60" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 27. " [59] ,Bitwise channel status - channel 59" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 26. " [58] ,Bitwise channel status - channel 58" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 25. " [57] ,Bitwise channel status - channel 57" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " [56] ,Bitwise channel status - channel 56" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 23. " [55] ,Bitwise channel status - channel 55" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 22. " [54] ,Bitwise channel status - channel 54" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 21. " [53] ,Bitwise channel status - channel 53" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 20. " [52] ,Bitwise channel status - channel 52" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 19. " [51] ,Bitwise channel status - channel 51" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 18. " [50] ,Bitwise channel status - channel 50" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " [49] ,Bitwise channel status - channel 49" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 16. " [48] ,Bitwise channel status - channel 48" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 15. " [47] ,Bitwise channel status - channel 47" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " [46] ,Bitwise channel status - channel 46" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 13. " [45] ,Bitwise channel status - channel 45" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " [44] ,Bitwise channel status - channel 44" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 11. " [43] ,Bitwise channel status - channel 43" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " [42] ,Bitwise channel status - channel 42" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " [41] ,Bitwise channel status - channel 41" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " [40] ,Bitwise channel status - channel 40" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 7. " [39] ,Bitwise channel status - channel 39" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " [38] ,Bitwise channel status - channel 38" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " [37] ,Bitwise channel status - channel 37" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " [36] ,Bitwise channel status - channel 36" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 3. " [35] ,Bitwise channel status - channel 35" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " [34] ,Bitwise channel status - channel 34" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " [33] ,Bitwise channel status - channel 33" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " [32] ,Bitwise channel status - channel 32" "No interrupt,Interrupt"
|
|
line.long 0x08 "MLB0_ACMR0,MLB0 Peripheral Channel Mask 0"
|
|
bitfld.long 0x08 31. " CHM[31] ,Bitwise channel interrupt mask - channel 31" "Masked,Unmasked"
|
|
bitfld.long 0x08 30. " [30] ,Bitwise channel interrupt mask - channel 30" "Masked,Unmasked"
|
|
bitfld.long 0x08 29. " [29] ,Bitwise channel interrupt mask - channel 29" "Masked,Unmasked"
|
|
bitfld.long 0x08 28. " [28] ,Bitwise channel interrupt mask - channel 28" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Bitwise channel interrupt mask - channel 27" "Masked,Unmasked"
|
|
bitfld.long 0x08 26. " [26] ,Bitwise channel interrupt mask - channel 26" "Masked,Unmasked"
|
|
bitfld.long 0x08 25. " [25] ,Bitwise channel interrupt mask - channel 25" "Masked,Unmasked"
|
|
bitfld.long 0x08 24. " [24] ,Bitwise channel interrupt mask - channel 24" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Bitwise channel interrupt mask - channel 23" "Masked,Unmasked"
|
|
bitfld.long 0x08 22. " [22] ,Bitwise channel interrupt mask - channel 22" "Masked,Unmasked"
|
|
bitfld.long 0x08 21. " [21] ,Bitwise channel interrupt mask - channel 21" "Masked,Unmasked"
|
|
bitfld.long 0x08 20. " [20] ,Bitwise channel interrupt mask - channel 20" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Bitwise channel interrupt mask - channel 19" "Masked,Unmasked"
|
|
bitfld.long 0x08 18. " [18] ,Bitwise channel interrupt mask - channel 18" "Masked,Unmasked"
|
|
bitfld.long 0x08 17. " [17] ,Bitwise channel interrupt mask - channel 17" "Masked,Unmasked"
|
|
bitfld.long 0x08 16. " [16] ,Bitwise channel interrupt mask - channel 16" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Bitwise channel interrupt mask - channel 15" "Masked,Unmasked"
|
|
bitfld.long 0x08 14. " [14] ,Bitwise channel interrupt mask - channel 14" "Masked,Unmasked"
|
|
bitfld.long 0x08 13. " [13] ,Bitwise channel interrupt mask - channel 13" "Masked,Unmasked"
|
|
bitfld.long 0x08 12. " [12] ,Bitwise channel interrupt mask - channel 12" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Bitwise channel interrupt mask - channel 11" "Masked,Unmasked"
|
|
bitfld.long 0x08 10. " [10] ,Bitwise channel interrupt mask - channel 10" "Masked,Unmasked"
|
|
bitfld.long 0x08 9. " [9] ,Bitwise channel interrupt mask - channel 9" "Masked,Unmasked"
|
|
bitfld.long 0x08 8. " [8] ,Bitwise channel interrupt mask - channel 8" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Bitwise channel interrupt mask - channel 7" "Masked,Unmasked"
|
|
bitfld.long 0x08 6. " [6] ,Bitwise channel interrupt mask - channel 6" "Masked,Unmasked"
|
|
bitfld.long 0x08 5. " [5] ,Bitwise channel interrupt mask - channel 5" "Masked,Unmasked"
|
|
bitfld.long 0x08 4. " [4] ,Bitwise channel interrupt mask - channel 4" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Bitwise channel interrupt mask - channel 3" "Masked,Unmasked"
|
|
bitfld.long 0x08 2. " [2] ,Bitwise channel interrupt mask - channel 2" "Masked,Unmasked"
|
|
bitfld.long 0x08 1. " [1] ,Bitwise channel interrupt mask - channel 1" "Masked,Unmasked"
|
|
bitfld.long 0x08 0. " [0] ,Bitwise channel interrupt mask - channel 0" "Masked,Unmasked"
|
|
line.long 0x0C "MLB0_ACMR1,MLB0 Peripheral Channel Mask 1"
|
|
bitfld.long 0x0C 31. " CHM[63] ,Bitwise channel interrupt mask - channel 63" "Masked,Unmasked"
|
|
bitfld.long 0x0C 30. " [62] ,Bitwise channel interrupt mask - channel 62" "Masked,Unmasked"
|
|
bitfld.long 0x0C 29. " [61] ,Bitwise channel interrupt mask - channel 61" "Masked,Unmasked"
|
|
bitfld.long 0x0C 28. " [60] ,Bitwise channel interrupt mask - channel 60" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [59] ,Bitwise channel interrupt mask - channel 59" "Masked,Unmasked"
|
|
bitfld.long 0x0C 26. " [58] ,Bitwise channel interrupt mask - channel 58" "Masked,Unmasked"
|
|
bitfld.long 0x0C 25. " [57] ,Bitwise channel interrupt mask - channel 57" "Masked,Unmasked"
|
|
bitfld.long 0x0C 24. " [56] ,Bitwise channel interrupt mask - channel 56" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [55] ,Bitwise channel interrupt mask - channel 55" "Masked,Unmasked"
|
|
bitfld.long 0x0C 22. " [54] ,Bitwise channel interrupt mask - channel 54" "Masked,Unmasked"
|
|
bitfld.long 0x0C 21. " [53] ,Bitwise channel interrupt mask - channel 53" "Masked,Unmasked"
|
|
bitfld.long 0x0C 20. " [52] ,Bitwise channel interrupt mask - channel 52" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [51] ,Bitwise channel interrupt mask - channel 51" "Masked,Unmasked"
|
|
bitfld.long 0x0C 18. " [50] ,Bitwise channel interrupt mask - channel 50" "Masked,Unmasked"
|
|
bitfld.long 0x0C 17. " [49] ,Bitwise channel interrupt mask - channel 49" "Masked,Unmasked"
|
|
bitfld.long 0x0C 16. " [48] ,Bitwise channel interrupt mask - channel 48" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [47] ,Bitwise channel interrupt mask - channel 47" "Masked,Unmasked"
|
|
bitfld.long 0x0C 14. " [46] ,Bitwise channel interrupt mask - channel 46" "Masked,Unmasked"
|
|
bitfld.long 0x0C 13. " [45] ,Bitwise channel interrupt mask - channel 45" "Masked,Unmasked"
|
|
bitfld.long 0x0C 12. " [44] ,Bitwise channel interrupt mask - channel 44" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [43] ,Bitwise channel interrupt mask - channel 43" "Masked,Unmasked"
|
|
bitfld.long 0x0C 10. " [42] ,Bitwise channel interrupt mask - channel 42" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " [41] ,Bitwise channel interrupt mask - channel 41" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " [40] ,Bitwise channel interrupt mask - channel 40" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [39] ,Bitwise channel interrupt mask - channel 39" "Masked,Unmasked"
|
|
bitfld.long 0x0C 6. " [38] ,Bitwise channel interrupt mask - channel 38" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " [37] ,Bitwise channel interrupt mask - channel 37" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " [36] ,Bitwise channel interrupt mask - channel 36" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [35] ,Bitwise channel interrupt mask - channel 35" "Masked,Unmasked"
|
|
bitfld.long 0x0C 2. " [34] ,Bitwise channel interrupt mask - channel 34" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " [33] ,Bitwise channel interrupt mask - channel 33" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " [32] ,Bitwise channel interrupt mask - channel 32" "Masked,Unmasked"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TWI (Two-Wire Interface)"
|
|
tree "TWI0"
|
|
base ad:0x31001400
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TWI0_CLKDIV,TWI0 SCL Clock Divider Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL clock high periods"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL clock low periods"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TWI0_CTL,TWI0 Control Register"
|
|
bitfld.word 0x00 9. " SCCB ,SCCB compatibility" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " EN ,Enable module" "Disabled,Enabled"
|
|
hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK prescale value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TWI0_SLVCTL,TWI0 Slave Mode Control Register"
|
|
bitfld.word 0x00 4. " GEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " NAK ,Not acknowledge" "ACK,NAK"
|
|
bitfld.word 0x00 2. " TDVAL ,Transmit data valid for slave" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,Enable slave mode" "Disabled,Enabled"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "TWI0_SLVSTAT,TWI0 Slave Mode Status Register"
|
|
bitfld.word 0x00 1. " GCALL ,General call" "Not general,General"
|
|
bitfld.word 0x00 0. " DIR ,Transfer direction for slave" "Receive,Transmit"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TWI0_SLVADDR,TWI0 Slave Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave mode address"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TWI0_MSTRCTL,TWI0 Master Mode Control Registers"
|
|
bitfld.word 0x00 15. " SCLOVR ,Serial clock override" "No override,Override"
|
|
bitfld.word 0x00 14. " SDAOVR ,Serial data override" "No override,Override"
|
|
hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data transfer count"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RSTART ,Repeat start" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STOP ,Issue stop condition" "Normal,Issue"
|
|
bitfld.word 0x00 3. " FAST ,Fast mode" "Standard,Fast"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DIR ,Transfer direction for master" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " EN ,Enable master mode" "Disabled,Enabled"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TWI0_MSTRSTAT,TWI0 Master Mode Status Register"
|
|
rbitfld.word 0x00 8. " BUSBUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.word 0x00 7. " SCLSEN ,Serial clock sense" "Inactive One,Actice Zero"
|
|
rbitfld.word 0x00 6. " SDASEN ,Serial data sense" "Inactive One,Actice 0Zero"
|
|
textline " "
|
|
eventfld.word 0x00 5. " BUFWRERR ,Buffer write error" "No error,Error"
|
|
eventfld.word 0x00 4. " BUFRDERR ,Buffer read error" "No error,Error"
|
|
eventfld.word 0x00 3. " DNAK ,Data not acknowledged" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ANAK ,Address not acknowledged" "Not occurred,Occurred"
|
|
eventfld.word 0x00 1. " LOSTARB ,Lost arbitration" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " MPROG ,Master transfer in progress" "Idle,In progress"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TWI0_MSTRADDR,TWI0 Master Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master mode address"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TWI0_ISTAT,TWI0 Interrupt Status Register"
|
|
eventfld.word 0x00 15. " SCLI ,Serial clock interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 14. " SDAI ,Serial data interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RXSERV ,Rx FIFO service" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 6. " TXSERV ,Tx FIFO service" "Low,High"
|
|
eventfld.word 0x00 5. " MERR ,Master transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " MCOMP ,Master transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 3. " SOVF ,Slave overflow" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " SERR ,Slave transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " SCOMP ,Slave transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 0. " SINIT ,Slave transfer initiated" "No interrupt,Interrupt"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TWI0_IMSK,TWI0 Interrupt Mask Register"
|
|
bitfld.word 0x00 15. " SCLI ,Serial clock interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 14. " SDAI ,Serial data interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RXSERV ,Rx FIFO service interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TXSERV ,Tx FIFO service interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 5. " MERR ,Master transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " MCOMP ,Master transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SOVF ,Slave overflow interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " SERR ,Slave transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 1. " SCOMP ,Slave transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SINIT ,Slave transfer initiated interrupt mask" "Masked,Unmasked"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TWI0_FIFOCTL,TWI0 FIFO Control Register"
|
|
bitfld.word 0x00 3. " RXILEN ,Rx buffer interrupt Llngth" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 2. " TXILEN ,Tx buffer interrupt length" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 1. " RXFLUSH ,Rx buffer flush" "Normal,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXFLUSH ,Tx buffer flush" "Normal,Flushed"
|
|
hgroup.word 0x2C++0x01
|
|
hide.word 0x00 "TWI0_FIFOSTAT,TWI0 FIFO Status Register"
|
|
in
|
|
wgroup.word 0x80++0x01
|
|
line.word 0x00 "TWI0_TXDATA8,TWI0 Tx Data Single-Byte Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value"
|
|
wgroup.word 0x84++0x01
|
|
line.word 0x00 "TWI0_TXDATA16,TWI0 Tx Data Double-Byte Register"
|
|
hgroup.word 0x88++0x01
|
|
hide.word 0x00 "TWI0_RXDATA8,TWI0 Rx Data Single-Byte Register"
|
|
in
|
|
hgroup.word 0x8C++0x01
|
|
hide.word 0x00 "TWI0_RXDATA16,TWI0 Rx Data Double-Byte Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "TWI1"
|
|
base ad:0x31001500
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TWI1_CLKDIV,TWI1 SCL Clock Divider Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL clock high periods"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL clock low periods"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TWI1_CTL,TWI1 Control Register"
|
|
bitfld.word 0x00 9. " SCCB ,SCCB compatibility" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " EN ,Enable module" "Disabled,Enabled"
|
|
hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK prescale value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TWI1_SLVCTL,TWI1 Slave Mode Control Register"
|
|
bitfld.word 0x00 4. " GEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " NAK ,Not acknowledge" "ACK,NAK"
|
|
bitfld.word 0x00 2. " TDVAL ,Transmit data valid for slave" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,Enable slave mode" "Disabled,Enabled"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "TWI1_SLVSTAT,TWI1 Slave Mode Status Register"
|
|
bitfld.word 0x00 1. " GCALL ,General call" "Not general,General"
|
|
bitfld.word 0x00 0. " DIR ,Transfer direction for slave" "Receive,Transmit"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TWI1_SLVADDR,TWI1 Slave Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave mode address"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TWI1_MSTRCTL,TWI1 Master Mode Control Registers"
|
|
bitfld.word 0x00 15. " SCLOVR ,Serial clock override" "No override,Override"
|
|
bitfld.word 0x00 14. " SDAOVR ,Serial data override" "No override,Override"
|
|
hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data transfer count"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RSTART ,Repeat start" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STOP ,Issue stop condition" "Normal,Issue"
|
|
bitfld.word 0x00 3. " FAST ,Fast mode" "Standard,Fast"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DIR ,Transfer direction for master" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " EN ,Enable master mode" "Disabled,Enabled"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TWI1_MSTRSTAT,TWI1 Master Mode Status Register"
|
|
rbitfld.word 0x00 8. " BUSBUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.word 0x00 7. " SCLSEN ,Serial clock sense" "Inactive One,Actice Zero"
|
|
rbitfld.word 0x00 6. " SDASEN ,Serial data sense" "Inactive One,Actice 0Zero"
|
|
textline " "
|
|
eventfld.word 0x00 5. " BUFWRERR ,Buffer write error" "No error,Error"
|
|
eventfld.word 0x00 4. " BUFRDERR ,Buffer read error" "No error,Error"
|
|
eventfld.word 0x00 3. " DNAK ,Data not acknowledged" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ANAK ,Address not acknowledged" "Not occurred,Occurred"
|
|
eventfld.word 0x00 1. " LOSTARB ,Lost arbitration" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " MPROG ,Master transfer in progress" "Idle,In progress"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TWI1_MSTRADDR,TWI1 Master Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master mode address"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TWI1_ISTAT,TWI1 Interrupt Status Register"
|
|
eventfld.word 0x00 15. " SCLI ,Serial clock interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 14. " SDAI ,Serial data interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RXSERV ,Rx FIFO service" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 6. " TXSERV ,Tx FIFO service" "Low,High"
|
|
eventfld.word 0x00 5. " MERR ,Master transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " MCOMP ,Master transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 3. " SOVF ,Slave overflow" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " SERR ,Slave transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " SCOMP ,Slave transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 0. " SINIT ,Slave transfer initiated" "No interrupt,Interrupt"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TWI1_IMSK,TWI1 Interrupt Mask Register"
|
|
bitfld.word 0x00 15. " SCLI ,Serial clock interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 14. " SDAI ,Serial data interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RXSERV ,Rx FIFO service interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TXSERV ,Tx FIFO service interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 5. " MERR ,Master transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " MCOMP ,Master transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SOVF ,Slave overflow interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " SERR ,Slave transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 1. " SCOMP ,Slave transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SINIT ,Slave transfer initiated interrupt mask" "Masked,Unmasked"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TWI1_FIFOCTL,TWI1 FIFO Control Register"
|
|
bitfld.word 0x00 3. " RXILEN ,Rx buffer interrupt Llngth" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 2. " TXILEN ,Tx buffer interrupt length" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 1. " RXFLUSH ,Rx buffer flush" "Normal,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXFLUSH ,Tx buffer flush" "Normal,Flushed"
|
|
hgroup.word 0x2C++0x01
|
|
hide.word 0x00 "TWI1_FIFOSTAT,TWI1 FIFO Status Register"
|
|
in
|
|
wgroup.word 0x80++0x01
|
|
line.word 0x00 "TWI1_TXDATA8,TWI1 Tx Data Single-Byte Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value"
|
|
wgroup.word 0x84++0x01
|
|
line.word 0x00 "TWI1_TXDATA16,TWI1 Tx Data Double-Byte Register"
|
|
hgroup.word 0x88++0x01
|
|
hide.word 0x00 "TWI1_RXDATA8,TWI1 Rx Data Single-Byte Register"
|
|
in
|
|
hgroup.word 0x8C++0x01
|
|
hide.word 0x00 "TWI1_RXDATA16,TWI1 Rx Data Double-Byte Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "TWI2"
|
|
base ad:0x31001600
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TWI2_CLKDIV,TWI2 SCL Clock Divider Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL clock high periods"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL clock low periods"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TWI2_CTL,TWI2 Control Register"
|
|
bitfld.word 0x00 9. " SCCB ,SCCB compatibility" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " EN ,Enable module" "Disabled,Enabled"
|
|
hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK prescale value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TWI2_SLVCTL,TWI2 Slave Mode Control Register"
|
|
bitfld.word 0x00 4. " GEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " NAK ,Not acknowledge" "ACK,NAK"
|
|
bitfld.word 0x00 2. " TDVAL ,Transmit data valid for slave" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,Enable slave mode" "Disabled,Enabled"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "TWI2_SLVSTAT,TWI2 Slave Mode Status Register"
|
|
bitfld.word 0x00 1. " GCALL ,General call" "Not general,General"
|
|
bitfld.word 0x00 0. " DIR ,Transfer direction for slave" "Receive,Transmit"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TWI2_SLVADDR,TWI2 Slave Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave mode address"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TWI2_MSTRCTL,TWI2 Master Mode Control Registers"
|
|
bitfld.word 0x00 15. " SCLOVR ,Serial clock override" "No override,Override"
|
|
bitfld.word 0x00 14. " SDAOVR ,Serial data override" "No override,Override"
|
|
hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data transfer count"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RSTART ,Repeat start" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STOP ,Issue stop condition" "Normal,Issue"
|
|
bitfld.word 0x00 3. " FAST ,Fast mode" "Standard,Fast"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DIR ,Transfer direction for master" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " EN ,Enable master mode" "Disabled,Enabled"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TWI2_MSTRSTAT,TWI2 Master Mode Status Register"
|
|
rbitfld.word 0x00 8. " BUSBUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.word 0x00 7. " SCLSEN ,Serial clock sense" "Inactive One,Actice Zero"
|
|
rbitfld.word 0x00 6. " SDASEN ,Serial data sense" "Inactive One,Actice 0Zero"
|
|
textline " "
|
|
eventfld.word 0x00 5. " BUFWRERR ,Buffer write error" "No error,Error"
|
|
eventfld.word 0x00 4. " BUFRDERR ,Buffer read error" "No error,Error"
|
|
eventfld.word 0x00 3. " DNAK ,Data not acknowledged" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ANAK ,Address not acknowledged" "Not occurred,Occurred"
|
|
eventfld.word 0x00 1. " LOSTARB ,Lost arbitration" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " MPROG ,Master transfer in progress" "Idle,In progress"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TWI2_MSTRADDR,TWI2 Master Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master mode address"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TWI2_ISTAT,TWI2 Interrupt Status Register"
|
|
eventfld.word 0x00 15. " SCLI ,Serial clock interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 14. " SDAI ,Serial data interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RXSERV ,Rx FIFO service" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 6. " TXSERV ,Tx FIFO service" "Low,High"
|
|
eventfld.word 0x00 5. " MERR ,Master transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " MCOMP ,Master transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 3. " SOVF ,Slave overflow" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " SERR ,Slave transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " SCOMP ,Slave transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 0. " SINIT ,Slave transfer initiated" "No interrupt,Interrupt"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TWI2_IMSK,TWI2 Interrupt Mask Register"
|
|
bitfld.word 0x00 15. " SCLI ,Serial clock interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 14. " SDAI ,Serial data interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RXSERV ,Rx FIFO service interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TXSERV ,Tx FIFO service interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 5. " MERR ,Master transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " MCOMP ,Master transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SOVF ,Slave overflow interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " SERR ,Slave transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 1. " SCOMP ,Slave transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SINIT ,Slave transfer initiated interrupt mask" "Masked,Unmasked"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TWI2_FIFOCTL,TWI2 FIFO Control Register"
|
|
bitfld.word 0x00 3. " RXILEN ,Rx buffer interrupt Llngth" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 2. " TXILEN ,Tx buffer interrupt length" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 1. " RXFLUSH ,Rx buffer flush" "Normal,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXFLUSH ,Tx buffer flush" "Normal,Flushed"
|
|
hgroup.word 0x2C++0x01
|
|
hide.word 0x00 "TWI2_FIFOSTAT,TWI2 FIFO Status Register"
|
|
in
|
|
wgroup.word 0x80++0x01
|
|
line.word 0x00 "TWI2_TXDATA8,TWI2 Tx Data Single-Byte Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value"
|
|
wgroup.word 0x84++0x01
|
|
line.word 0x00 "TWI2_TXDATA16,TWI2 Tx Data Double-Byte Register"
|
|
hgroup.word 0x88++0x01
|
|
hide.word 0x00 "TWI2_RXDATA8,TWI2 Rx Data Single-Byte Register"
|
|
in
|
|
hgroup.word 0x8C++0x01
|
|
hide.word 0x00 "TWI2_RXDATA16,TWI2 Rx Data Double-Byte Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "EMAC (Ethernet Media Access Controller)"
|
|
base ad:0x3100C000
|
|
width 29.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EMAC0_MACCFG,EMAC0 MAC Configuration Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 28.--30. " SARC ,Source address insertion or replacement control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 27. " TWOKPE ,Support for 2K packets" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 25. " CST ,CRC stripping" "Disabled,Enabled"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 24. " TC ,Transmit configuration in RGMII" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " WD ,Watch dog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JB ,Jabber disable" "No,Yes"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " BE ,Frame burst enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " JE ,Jumbo frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " IFG ,Inter-Frame gap" "96-bit,88-bit,80-bit,72-bit,64-bit,56-bit,48-bit,40-bit"
|
|
bitfld.long 0x00 16. " DCRS ,Disable carrier sense" "No,Yes"
|
|
textline " "
|
|
sif cpuis("ADSP-SC57?")
|
|
textline " "
|
|
rbitfld.long 0x00 15. " PS ,Port Select" "1000 Mbps,10/100 Mbps"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " FES ,Speed of operation" "10 Mbps,100 Mbps"
|
|
bitfld.long 0x00 13. " DO ,Disable receive own" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "No loopback,Loopback"
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex"
|
|
bitfld.long 0x00 10. " IPC ,IP checksum" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR ,Disable retry" "No,Yes"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " LUD ,Link up or down" "Down,Up"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACS ,Automatic pad/crc stripping" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " BL ,Back off limit-min(attempts, BL)" "10,8,4,1"
|
|
bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRELEN ,Preamble length for transmit frames" "0,1,2,3"
|
|
endif
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "EMAC0_MACFRMFILT,EMAC0 MAC Rx Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all frames" "Disabled,Enabled"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " DNTU ,Drop non-TCP/UDP over IP frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " IPFE ,Layer 3 and layer 4 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VTFE ,VAN tag filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Hash,Hash or perfect"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 9. " SAF ,Source address filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "None,All but PAUSE,All,Address filtered"
|
|
bitfld.long 0x00 5. " DBF ,Disable broadcast frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PM ,Pass all multicast frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HMC ,Hash multicast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HUC ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PR ,Promiscuous mode" "Disabled,Enabled"
|
|
line.long 0x04 "EMAC0_HASHTBL_HI,EMAC0 Hash Table High Register"
|
|
line.long 0x08 "EMAC0_HASHTBL_LO,EMAC0 Hash Table Low Register"
|
|
line.long 0x0C "EMAC0_SMI_ADDR,EMAC0 SMI Address Register"
|
|
bitfld.long 0x0C 11.--15. " PA ,Physical layer address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--10. " SMIR ,SMI register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 2.--5. " CR ,Clock range" "SCLK/42,SCLK/62,SCLK/16,SCLK/26,,,,,SCLK/4,SCLK/6,SCLK/8,SCLK/10,SCLK/12,SCLK/14,SCLK/16,SCLK/18"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SMIW ,SMI write" "Read,Write"
|
|
bitfld.long 0x0C 0. " SMIB ,SMI busy" "Not busy,Busy"
|
|
line.long 0x10 "EMAC0_SMI_DATA,EMAC0 SMI Data Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " SMID ,SMI data"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "EMAC0_FLOWCTL,EMAC0 Flow Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " DZPQ ,Disable Zero-Quanta pause" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UP ,Unicast pause frame detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFE ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE ,Transmit flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCBBPA ,Initiate pause control frame" "No action,Initiated"
|
|
line.long 0x04 "EMAC0_VLANTAG,EMAC0 VLAN Tag Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x04 19. " VTHM ,VLAN tag hash table match enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ESVL ,Enable S-VLAN" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " VTIM ,VLAN tag inverse match enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 16. " ETV ,Enable tag VLAN comparison" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " VL ,VLAN tag id receive frames"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "EMAC0_DBG,EMAC0 Debug Register"
|
|
bitfld.long 0x00 25. " TXFIFOFULL ,Tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 24. " TXFIFONE ,Tx FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 22. " TXFIFOACT ,Tx FIFO active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TXFIFOCTLST ,Tx FIFO controller state" "Idle,Read,Waiting for TxStatus,Writing TxStatus"
|
|
bitfld.long 0x00 19. " TXPAUSE ,Tx paused" "Not paused,Paused"
|
|
bitfld.long 0x00 17.--18. " TXFRCTL ,Tx frame controller state" "Idle,Wait,Pause,Transmit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMTEA ,MM tx engine active" "Not active,Active"
|
|
bitfld.long 0x00 8.--9. " RXFIFOST ,Rx FIFO state" "Empty,Below FCT,Above FCT,Full"
|
|
bitfld.long 0x00 5.--6. " RXFIFOCTLST ,Rx FIFO controller state" "Idle,Read data,Read status,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXFIFOACT ,Rx FIFO active" "Not active,Active"
|
|
bitfld.long 0x00 2. " SFIFOST[1] ,Small FIFO write state" "Not active,Active"
|
|
bitfld.long 0x00 1. " [0] ,Small FIFO read state" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MMREA ,MM Rx engine active" "Not active,Active"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "EMAC0_LPI_CTLSTAT,EMAC0 Low Power Idle Control And Status Register"
|
|
in
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMAC0_LPI_TMRSCTL,EMAC0 Low Power Idle Timeout Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " LST ,Link status timer"
|
|
hexmask.long.word 0x00 0.--15. 1. " TWT ,Timer wait time"
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMAC0_ISTAT,EMAC0 Interrupt Status Register"
|
|
bitfld.long 0x00 10. " LPIIS ,LPI interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " TS ,Time stamp interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " MMCRC ,MMC receive checksum offload interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MMCTX ,MMC transmit interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " MMCRX ,MMC receive interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " MMC ,MMC interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RGMIIIS ,RGMII or SMII interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMAC0_IMSK,EMAC0 Interrupt Mask Register"
|
|
bitfld.long 0x00 10. " LPIIM ,LPI interrupt mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 9. " TS ,Time stamp interrupt mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " RGMIIIM ,RGMII or SMII interrupt mask" "Unmasked,Masked"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "EMAC0_ADDR0_HI,EMAC0 MAC Address 0 High Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDR ,Address"
|
|
line.long 0x04 "EMAC0_ADDR0_LO,EMAC0 MAC Address 0 Low Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "EMAC0_ADDR1_HI,EMAC0 MAC Address 1 High Register"
|
|
bitfld.long 0x00 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SA ,Source address compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MBC[5] ,Mask byte 5 control" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [4] ,Mask byte 4 control" "Unmasked,Masked"
|
|
bitfld.long 0x00 27. " [3] ,Mask byte 3 control" "Unmasked,Masked"
|
|
bitfld.long 0x00 26. " [2] ,Mask byte 2 control" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [1] ,Mask byte 1 control" "Unmasked,Masked"
|
|
bitfld.long 0x00 24. " [0] ,Mask byte 0 control" "Unmasked,Masked"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRHI ,Mac address"
|
|
line.long 0x04 "EMAC0_ADDR1_LO,EMAC0 MAC Address 1 Low Register"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "EMAC0_GIGE_CTLSTAT,EMAC0 RGMII Control And Status Register"
|
|
bitfld.long 0x00 3. " LNKSTS ,Link status" "Down,Up"
|
|
bitfld.long 0x00 1.--2. " LNKSPEED ,Link speed" "10Mbps,100Mbps,1000Mbps,"
|
|
bitfld.long 0x00 0. " LNKMOD ,Link mode" "Half duplex,Full duplex"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "EMAC0_WDOG_TIMOUT,EMAC0 Watchdog Timeout Register"
|
|
bitfld.long 0x00 16. " PWE ,Programmable watchdog enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " WTO ,Watchdog timeout"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "EMAC0_MMC_CTL,EMAC0 MMC Control Register"
|
|
bitfld.long 0x00 5. " FULLPSET ,Full preset" "Half,Full"
|
|
bitfld.long 0x00 4. " CNTRPSET ,Counter reset/preset" "No action,Reset"
|
|
bitfld.long 0x00 3. " CNTRFRZ ,Counter freeze" "No freeze,Freeze"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RDRST ,Read reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " NOROLL ,Disable rollover" "No,Yes"
|
|
bitfld.long 0x00 0. " RST ,Reset" "No action,Reset"
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "EMAC0_MMC_RXINT,EMAC0 MMC Rx Interrupt Register"
|
|
in
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "EMAC0_MMC_TXINT,EMAC0 MMC Tx Interrupt Register"
|
|
in
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "EMAC0_MMC_RXIMSK,EMAC0 MMC Rx Interrupt Mask Register"
|
|
sif (cpuis("ADSPCM40*")||cpuis("ADSP-SC57?"))
|
|
bitfld.long 0x00 25. " CTLFIM ,Rx control frame counter interrupt mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 24. " RCVERRFIM ,Rx error frame counter interrupt mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " WATCHERR ,Rx watch dog error count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VLANFRGB ,Rx VLAN frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 21. " FIFOOV ,Rx FIFO overflow count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 20. " PAUSEFRM ,Rx pause frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OUTRANGE ,Rx out of range type count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 18. " LENERR ,Rx length error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 17. " UCASTG ,Rx unicast frames (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " R1024TOMAX ,Rx 1024-to-max octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 15. " R512TO1023 ,Rx 512-to-1023 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 14. " R256TO511 ,Rx 255-to-511 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " R128TO255 ,Rx 128-to-255 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 12. " R65TO127 ,Rx 65-to-127 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 11. " R64 ,Rx 64 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSIZEG ,Rx oversize (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 9. " USIZEG ,Rx undersize (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 8. " JABERR ,Rx jabber error count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RUNTERR ,Rx runt error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 6. " ALIGNERR ,Rx alignment error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 5. " CRCERR ,Rx CRC error count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MCASTG ,Rx multicast frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " BCASTG ,Rx broadcast frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 2. " OCTCNTG ,Rx octet count (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCTCNTGB ,Rx octet count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " FRCNTGB ,Rx frame count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
line.long 0x04 "EMAC0_MMC_TXIMSK,EMAC0 MMC TX Interrupt Mask Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x04 25. " OSZGFIM ,Tx oversize good frame count interrupt mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24. " VLANFRG ,Tx VLAN frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 23. " PAUSEFRM ,Tx pause frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXCESSDEF ,Tx excess deferred count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 21. " FRCNTG ,Tx frame count (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 20. " OCTCNTG ,Tx octet count (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CARRERR ,Tx carrier error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 18. " EXCESSCOL ,Tx exess collision count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 17. " LATECOL ,Tx late collision count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DEFERRED ,Tx deferred count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 15. " MULTCOLG ,Tx multiple collisions (good) count mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 14. " SNGCOLG ,Tx single collision (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " UNDERR ,Tx underflow error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 12. " BCASTGB ,Tx broadcast frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 11. " MCASTGB ,Tx multicast frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " UCASTGB ,Tx unicast frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 9. " T1024TOMAX ,Tx 1024-to-max octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 8. " T512TO1023 ,Tx 512-to-1023 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " T256TO511 ,Tx 256-to-511 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 6. " T128TO255 ,Tx 128-to-255 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 5. " T65TO127 ,Tx 65-to-127 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " T64 ,Tx 64 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 3. " MCASTG ,Tx multicast frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 2. " BCASTG ,Tx broadcast frames (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FRCNTGB ,Tx frame count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 0. " OCTCNTGB ,Tx octet count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
rgroup.long 0x114++0x67
|
|
line.long 0x00 "EMAC0_TXOCTCNT_GB,EMAC0 Tx OCT Count (good/bad) Register"
|
|
line.long 0x04 "EMAC0_TXFRMCNT_GB,EMAC0 Tx Frame Count (good/bad) Register"
|
|
line.long 0x08 "EMAC0_TXBCASTFRM_G,EMAC0 Tx Broadcast Frames (good) Register"
|
|
line.long 0x0C "EMAC0_TXMCASTFRM_G,EMAC0 Tx Multicast Frames (good) Register"
|
|
line.long 0x10 "EMAC0_TX64_GB,EMAC0 Tx 64-Byte Frames (good/bad) Register"
|
|
line.long 0x14 "EMAC0_TX65TO127_GB,EMAC0 Tx 65- To 127-Byte Frames (good/bad) Register"
|
|
line.long 0x18 "EMAC0_TX128TO255_GB,EMAC0 Tx 128- To 255-Byte Frames (good/bad) Register"
|
|
line.long 0x1C "EMAC0_TX256TO511_GB,EMAC0 Tx 256- To 511-Byte Frames (good/bad) Register"
|
|
line.long 0x20 "EMAC0_TX512TO1023_GB,EMAC0 Tx 512- To 1023-Byte Frames (good/bad) Register"
|
|
line.long 0x24 "EMAC0_TX1024TOMAX_GB,EMAC0 Tx 1024- To Max-Byte Frames (good/bad) Register"
|
|
line.long 0x28 "EMAC0_TXUCASTFRM_GB,EMAC0 Tx Unicast Frames (good/bad) Register"
|
|
line.long 0x2C "EMAC0_TXMCASTFRM_GB,EMAC0 Tx Multicast Frames (good/bad) Register"
|
|
line.long 0x30 "EMAC0_TXBCASTFRM_GB,EMAC0 Tx Broadcast Frames (good/bad) Register"
|
|
line.long 0x34 "EMAC0_TXUNDR_ERR,EMAC0 Tx Underflow Error Register"
|
|
line.long 0x38 "EMAC0_TXSNGCOL_G,EMAC0 Tx Single Collision (good) Register"
|
|
line.long 0x3C "EMAC0_TXMULTCOL_G,EMAC0 Tx Multiple Collision (good) Register"
|
|
line.long 0x40 "EMAC0_TXDEFERRED,EMAC0 Tx Deferred Register"
|
|
line.long 0x44 "EMAC0_TXLATECOL,EMAC0 Tx Late Collision Register"
|
|
line.long 0x48 "EMAC0_TXEXCESSCOL,EMAC0 Tx Excess Collision Register"
|
|
line.long 0x4C "EMAC0_TXCARR_ERR,EMAC0 Tx Carrier Error Register"
|
|
line.long 0x50 "EMAC0_TXOCTCNT_G,EMAC0 Tx Octet Count (good) Register"
|
|
line.long 0x54 "EMAC0_TXFRMCNT_G,EMAC0 Tx Frame Count (good) Register"
|
|
line.long 0x58 "EMAC0_TXEXCESSDEF,EMAC0 Tx Excess Deferral Register"
|
|
line.long 0x5C "EMAC0_TXPAUSEFRM,EMAC0 Tx Pause Frame Register"
|
|
line.long 0x60 "EMAC0_TXVLANFRM_G,EMAC0 Tx VLAN Frames (good) Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "EMAC0_TXOVRSIZE_G,EMAC0 Number Of Tx Frames (good) Greater Than Maxsize"
|
|
endif
|
|
rgroup.long 0x180++0x67
|
|
line.long 0x00 "EMAC0_RXFRMCNT_GB,EMAC0 Rx Frame Count (good/bad) Register"
|
|
line.long 0x04 "EMAC0_RXOCTCNT_GB,EMAC0 Rx Octet Count (good/bad) Register"
|
|
line.long 0x08 "EMAC0_RXOCTCNT_G,EMAC0 Rx Octet Count (good) Register"
|
|
line.long 0x0C "EMAC0_RXBCASTFRM_G,EMAC0 Rx Broadcast Frames (good) Register"
|
|
line.long 0x10 "EMAC0_RXMCASTFRM_G,EMAC0 Rx Multicast Frames (good) Register"
|
|
line.long 0x14 "EMAC0_RXCRC_ERR,EMAC0 Rx CRC Error Register"
|
|
line.long 0x18 "EMAC0_RXALIGN_ERR,EMAC0 Rx Alignment Error Register"
|
|
line.long 0x1C "EMAC0_RXRUNT_ERR,EMAC0 Rx Runt Error Register"
|
|
line.long 0x20 "EMAC0_RXJAB_ERR,EMAC0 Rx Jab Error Register"
|
|
line.long 0x24 "EMAC0_RXUSIZE_G,EMAC0 Rx Undersize (good) Register"
|
|
line.long 0x28 "EMAC0_RXOSIZE_G,EMAC0 Rx Oversize (good) Register"
|
|
line.long 0x2C "EMAC0_RX64_GB,EMAC0 Rx 64-Byte Frames (good/bad) Register"
|
|
line.long 0x30 "EMAC0_RX65TO127_GB,EMAC0 Rx 65- To 127-Byte Frames (good/bad) Register"
|
|
line.long 0x34 "EMAC0_RX128TO255_GB,EMAC0 Rx 128- To 255-Byte Frames (good/bad) Register"
|
|
line.long 0x38 "EMAC0_RX256TO511_GB,EMAC0 Rx 256- To 511-Byte Frames (good/bad) Register"
|
|
line.long 0x3C "EMAC0_RX512TO1023_GB,EMAC0 Rx 512- To 1023-Byte Frames (good/bad) Register"
|
|
line.long 0x40 "EMAC0_RX1024TOMAX_GB,EMAC0 Rx 1024- To Max-Byte Frames (good/bad) Register"
|
|
line.long 0x44 "EMAC0_RXUCASTFRM_G,EMAC0 Rx Unicast Frames (good) Register"
|
|
line.long 0x48 "EMAC0_RXLEN_ERR,EMAC0 Rx Length Error Register"
|
|
line.long 0x4C "EMAC0_RXOORTYPE,EMAC0 Rx Out Of Range Type Register"
|
|
line.long 0x50 "EMAC0_RXPAUSEFRM,EMAC0 Rx Pause Frames Register"
|
|
line.long 0x54 "EMAC0_RXFIFO_OVF,EMAC0 Rx FIFO Overflow Register"
|
|
line.long 0x58 "EMAC0_RXVLANFRM_GB,EMAC0 Rx VLAN Frames (good/bad) Register"
|
|
line.long 0x5C "EMAC0_RXWDOG_ERR,EMAC0 Rx Watch Dog Error Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
rgroup.long 0x1E0++0x07
|
|
line.long 0x00 "EMAC0_RXRCV_ERR,EMAC0 Rx Error Frames Received Register"
|
|
line.long 0x04 "EMAC0_RXCTLFRM_G,EMAC0 Rx Good Control Frames Register"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "EMAC0_IPC_RXIMSK,EMAC0 MMC IPC Rx Interrupt Mask Register"
|
|
bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (good) octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 27. " TCPERROCT ,Rx TCP error octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (good) octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 25. " UDPERROCT ,Rx UDP error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (good) octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " V6NOPAYOCT ,Rx ipv6 no payload octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 22. " V6HDERROCT ,Rx ipv6 header error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 21. " V6GOCT ,Rx ipv6 (good) octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " V4UDSBLOCT ,Rx ipv4 UDS disable octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 19. " V4FRAGOCT ,Rx ipv4 fragmented octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 18. " V4NOPAYOCT ,Rx ipv4 no payload octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " V4HDERROCT ,Rx ipv4 header error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 16. " V4GOCT ,Rx ipv4 (good) octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP error frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (good) frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP error frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (good) frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UDPERRFRM ,Rx UDP error frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (good) frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 7. " V6NOPAYFRM ,Rx ipv6 no payload frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " V6HDERRFRM ,Rx ipv6 header error frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 5. " V6GFRM ,Rx ipv6 (good) frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 4. " V4UDSBLFRM ,Rx ipv4 UDS disable frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " V4FRAGFRM ,Rx ipv4 fragmented frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 2. " V4NOPAYFRM ,Rx ipv4 no payload frame count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " V4HDERRFRM ,Rx ipv4 header error frame count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " V4GFRM ,Rx ipv4 (good) frames count half/full mask" "Unmasked,Masked"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "EMAC0_IPC_RXINT,EMAC0 MMC IPC Rx Interrupt Register"
|
|
bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " TCPERROCT ,Rx TCP error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " UDPERROCT ,Rx UDP error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " V6NOPAYOCT ,Rx ipv6 no payload octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " V6HDERROCT ,Rx ipv6 header error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " V6GOCT ,Rx ipv6 (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " V4UDSBLOCT ,Rx ipv4 UDS disable octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " V4FRAGOCT ,Rx ipv4 fragmented octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " V4NOPAYOCT ,Rx ipv4 no payload octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " V4HDERROCT ,Rx ipv4 header error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " V4GOCT ,Rx ipv4 (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UDPERRFRM ,Rx IDP error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " V6NOPAYFRM ,Rx ipv6 no payload frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " V6HDERRFRM ,Rx ipv6 header error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " V6GFRM ,Rx ipv6 (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " V4UDSBLFRM ,Rx ipv4 UDS disable frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " V4FRAGFRM ,Rx ipv4 fragmented frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " V4NOPAYFRM ,Rx ipv4 no payload frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " V4HDERRFRM ,Rx ipv4 header error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " V4GFRM ,Rx ipv4 (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0x210++0x37
|
|
line.long 0x00 "EMAC0_RXIPV4_GD_FRM,EMAC0 Rx Ipv4 Datagrams (good) Register"
|
|
line.long 0x04 "EMAC0_RXIPV4_HDR_ERR_FRM,EMAC0 Rx Ipv4 Datagrams Header Errors Register"
|
|
line.long 0x08 "EMAC0_RXIPV4_NOPAY_FRM,EMAC0 Rx Ipv4 Datagrams No Payload Frame Register"
|
|
line.long 0x0C "EMAC0_RXIPV4_FRAG_FRM,EMAC0 Rx Ipv4 Datagrams Fragmented Frames Register"
|
|
line.long 0x10 "EMAC0_RXIPV4_UDSBL_FRM,EMAC0 Rx Ipv4 UDP Disabled Frames Register"
|
|
line.long 0x14 "EMAC0_RXIPV6_GD_FRM,EMAC0 Rx Ipv6 Datagrams Good Frames Register"
|
|
line.long 0x18 "EMAC0_RXIPV6_HDR_ERR_FRM,EMAC0 Rx Ipv6 Datagrams Header Error Frames Register"
|
|
line.long 0x1C "EMAC0_RXIPV6_NOPAY_FRM,EMAC0 Rx Ipv6 Datagrams No Payload Frames Register"
|
|
line.long 0x20 "EMAC0_RXUDP_GD_FRM,EMAC0 Rx UDP Good Frames Register"
|
|
line.long 0x24 "EMAC0_RXUDP_ERR_FRM,EMAC0 Rx UDP Error Frames Register"
|
|
line.long 0x28 "EMAC0_RXTCP_GD_FRM,EMAC0 Rx TCP Good Frames Register"
|
|
line.long 0x2C "EMAC0_RXTCP_ERR_FRM,EMAC0 Rx TCP Error Frames Register"
|
|
line.long 0x30 "EMAC0_RXICMP_GD_FRM,EMAC0 Rx ICMP Good Frames Register"
|
|
line.long 0x34 "EMAC0_RXICMP_ERR_FRM,EMAC0 Rx ICMP Error Frames Register"
|
|
rgroup.long 0x250++0x37
|
|
line.long 0x00 "EMAC0_RXIPV4_GD_OCT,EMAC0 Rx Ipv4 Datagrams Good Octets Register"
|
|
line.long 0x04 "EMAC0_RXIPV4_HDR_ERR_OCT,EMAC0 Rx Ipv4 Datagrams Header Errors Register"
|
|
line.long 0x08 "EMAC0_RXIPV4_NOPAY_OCT,EMAC0 Rx Ipv4 Datagrams No Payload Octets Register"
|
|
line.long 0x0C "EMAC0_RXIPV4_FRAG_OCT,EMAC0 Rx Ipv4 Datagrams Fragmented Octets Register"
|
|
line.long 0x10 "EMAC0_RXIPV4_UDSBL_OCT,EMAC0 Rx Ipv4 UDP Disabled Octets Register"
|
|
line.long 0x14 "EMAC0_RXIPV6_GD_OCT,EMAC0 Rx Ipv6 Good Octets Register"
|
|
line.long 0x18 "EMAC0_RXIPV6_HDR_ERR_OCT,EMAC0 Rx Ipv6 Header Errors Register"
|
|
line.long 0x1C "EMAC0_RXIPV6_NOPAY_OCT,EMAC0 Rx Ipv6 No Payload Octets Register"
|
|
line.long 0x20 "EMAC0_RXUDP_GD_OCT,EMAC0 Rx UDP Good Octets Register"
|
|
line.long 0x24 "EMAC0_RXUDP_ERR_OCT,EMAC0 Rx UDP Error Octets Register"
|
|
line.long 0x28 "EMAC0_RXTCP_GD_OCT,EMAC0 Rx TCP Good Octets Register"
|
|
line.long 0x2C "EMAC0_RXTCP_ERR_OCT,EMAC0 Rx TCP Error Octets Register"
|
|
line.long 0x30 "EMAC0_RXICMP_GD_OCT,EMAC0 Rx ICMP Good Octets Register"
|
|
line.long 0x34 "EMAC0_RXICMP_ERR_OCT,EMAC0 Rx ICMP Error Octets Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "EMAC0_L3L4_CTL,EMAC0 Layer3 And Layer4 Control Register"
|
|
bitfld.long 0x00 21. " L4DPIM ,Layer 4 destination port inverse matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " L4DPM ,Layer 4 destination port matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " L4SPIM ,Layer 4 source port inverse matching" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " L4SPM ,Layer 4 source port matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L4PEN ,Layer 4 filtering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--15. " L3HDBM ,Layer 3 destination address bits mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " L3HSBM ,Layer 3 source address bits mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " L3DAIM ,Layer 3 destination address inverse matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " L3DAM ,Layer 3 destination address matching" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " L3SAIM ,Layer 3 source address inverse matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " L3SAM ,Layer 3 source address matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " L3PEN ,Layer 3 enabled" "Disabled,Enabled"
|
|
line.long 0x04 "EMAC0_L4_ADDR,EMAC0 Layer 4 Address Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " L4DP ,Layer 4 destination port"
|
|
hexmask.long.word 0x04 0.--15. 1. " L4SP ,Layer 4 source port"
|
|
group.long 0x410++0x0F
|
|
line.long 0x00 "EMAC0_L3_ADDR0,EMAC0 Layer 3 Address0 Register"
|
|
line.long 0x04 "EMAC0_L3_ADDR1,EMAC0 Layer 3 Address1 Register"
|
|
line.long 0x08 "EMAC0_L3_ADDR2,EMAC0 Layer 3 Address2 Register"
|
|
line.long 0x0C "EMAC0_L3_ADDR3,EMAC0 Layer 3 Address3 Register"
|
|
group.long 0x584++0x07
|
|
line.long 0x00 "EMAC0_VLAN_INCL,EMAC0 VLAN Tag Inclusion Or Replacement Register"
|
|
bitfld.long 0x00 19. " CSVL ,C-VLAN or S-VLAN" "C-VLAN,S-VLAN"
|
|
bitfld.long 0x00 18. " VLP ,VLAN priority control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " VLC ,VLAN tag control in transmit frames" "No operation,Deletion,Insertion,Replacement"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " VLT ,VLAN tag for transmit frames"
|
|
line.long 0x04 "EMAC0_VLAN_HSHTBL,EMAC0 VLAN Hash Table Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VLHT ,VLAN hash table"
|
|
endif
|
|
group.long 0x700++0x07
|
|
line.long 0x00 "EMAC0_TM_CTL,EMAC0 Time Stamp Control Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 28. " ATSEN3 ,Auxiliary snapshot 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ATSEN2 ,Auxiliary snapshot 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ATSEN1 ,Auxiliary snapshot 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATSEN0 ,Auxiliary snapshot 0 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 24. " ATSFC ,Auxiliary time stamp FIFO clear" "No clear,Clear"
|
|
bitfld.long 0x00 18. " TSENMACADDR ,Time stamp enable MAC address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SNAPTYPSEL ,Snapshot type select" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TSMSTRENA ,Time stamp master (frames) enable" "Slave,Master"
|
|
bitfld.long 0x00 14. " TSEVNTENA ,Time stamp event (PTP frames) enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TSIPV4ENA ,Time stamp IPV4 (PTP frames) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSIPV6ENA ,Time stamp IPV6 (PTP frames) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSIPENA ,Time stamp IP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TSVER2ENA ,Time stamp VER2 (snooping) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TSCTRLSSR ,Time stamp control nanosecond rollover" "0x7FFFFFFF,0x3B9AC9FF"
|
|
bitfld.long 0x00 8. " TSENALL ,Time stamp enable all (frames)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSADDREG ,Time stamp addend register update" "No effect,Update"
|
|
bitfld.long 0x00 4. " TSTRIG ,Time stamp (target time) trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSUPDT ,Time stamp (system time) update" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TSINIT ,Time stamp (system time) initialize" "No effect,Initialize"
|
|
bitfld.long 0x00 1. " TSCFUPDT ,Time stamp (system time) fine/coarse update" "Coarse,Fine"
|
|
bitfld.long 0x00 0. " TSENA ,Time stamp (PTP) enable" "Disabled,Enabled"
|
|
line.long 0x04 "EMAC0_TM_SUBSEC,EMAC0 Time Stamp Sub Second Increment Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SSINC ,Sub-Second increment value"
|
|
rgroup.long 0x708++0x07
|
|
line.long 0x00 "EMAC0_TM_SEC,EMAC0 Time Stamp Low Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_NSEC,EMAC0 Time Stamp Nanoseconds Register"
|
|
hexmask.long 0x04 0.--30. 1. " TSSS ,Time stamp nanoseconds"
|
|
group.long 0x710++0x17
|
|
line.long 0x00 "EMAC0_TM_SECUPDT,EMAC0 Time Stamp Seconds Update Register"
|
|
line.long 0x04 "EMAC0_TM_NSECUPDT,EMAC0 Time Stamp Nanoseconds Update Register"
|
|
bitfld.long 0x04 31. " ADDSUB ,Add or subtract the time" "Add,Subtract"
|
|
hexmask.long 0x04 0.--30. 1. " TSSS ,Time stamp sub second initialize/increment"
|
|
line.long 0x08 "EMAC0_TM_ADDEND,EMAC0 Time Stamp Addend Register"
|
|
line.long 0x0C "EMAC0_TM_PPS0TGTM,EMAC0 Time Stamp Target Time Seconds Register"
|
|
line.long 0x10 "EMAC0_TM_PPS0NTGTM,EMAC0 Time Stamp Target Time Nanoseconds Register"
|
|
bitfld.long 0x10 31. " TSTRBUSY ,Target time register busy" "Not busy,Busy"
|
|
hexmask.long 0x10 0.--30. 1. " TSTR ,Target time nano seconds"
|
|
line.long 0x14 "EMAC0_TM_HISEC,EMAC0 Time Stamp High Second Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " TSHWR ,Time stamp higher word seconds register"
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "EMAC0_TM_STMPSTAT,EMAC0 Time Stamp Status Register"
|
|
in
|
|
group.long 0x72C++0x0B
|
|
line.long 0x00 "EMAC0_TM_PPSCTL,EMAC0 PPS Control Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 29.--30. " TRGTMODSEL3 ,Target time register mode for PPS3" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
bitfld.long 0x00 24.--26. " PPSCMD3 ,Flexible PPS3 output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--22. " TRGTMODSEL2 ,Target time register mode for PPS2" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PPSCMD2 ,Flexible PPS2 output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--14. " TRGTMODSEL1 ,Target time register mode for PPS1" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
bitfld.long 0x00 8.--10. " PPSCMD1 ,Flexible PPS1 output control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TRGTMODSEL0 ,Target time register mode" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
bitfld.long 0x00 4. " PPSEN ,Enable the flexible PPS output mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PPSCTL0 ,PPS frequency control (command,BR,DR)" "No command,START Single/2kHz/1kHz,START Pulse/4kHz/2kHz,Cancel START/8kHz/4kHz,STOP Pulse Time/16kHz/8kHz,STOP Pulse Now,Cancel STOP Pulse,?..."
|
|
line.long 0x04 "EMAC0_TM_AUXSTMP_NSEC,EMAC0 Time Stamp Auxiliary TS Nano Seconds Register"
|
|
line.long 0x08 "EMAC0_TM_AUXSTMP_SEC,EMAC0 Time Stamp Auxiliary TM Seconds Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x738++0x03
|
|
line.long 0x00 "EMAC0_MAC_AVCTL,EMAC0 AV MAC Control Register"
|
|
bitfld.long 0x00 24.--25. " PTPCH ,Channel for queuing the PTP packets" "0,1,2,?..."
|
|
bitfld.long 0x00 21.--22. " AVCH ,Channel for queuing AV control packets" "0,1,2,?..."
|
|
bitfld.long 0x00 20. " AVCD ,AV channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VQE ,VLAN tagged non-AV packets queuing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " AVP ,AV priority for queuing" "Lowest,1,2,3,4,5,6,Highest"
|
|
hexmask.long.word 0x00 0.--15. 1. " AVT ,AV ether type value"
|
|
endif
|
|
group.long 0x760++0x07
|
|
line.long 0x00 "EMAC0_TM_PPS0INTVL,EMAC0 Time Stamp PPS Interval Register"
|
|
line.long 0x04 "EMAC0_TM_PPS0WIDTH,EMAC0 PPS Width Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x780++0x0F
|
|
line.long 0x00 "EMAC0_TM_PPS1TGTM,EMAC0 PPS 1 Target Time Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_PPS1NTGTM,EMAC0 PPS 1 Target Time Nanoseconds Register"
|
|
bitfld.long 0x04 31. " TSTRBUSY ,Target time register" "Not busy,Busy"
|
|
hexmask.long 0x04 0.--30. 1. " TSTR ,Target time low register"
|
|
line.long 0x08 "EMAC0_TM_PPS1INTVL,EMAC0 PPS 1 Interval Register"
|
|
line.long 0x0C "EMAC0_TM_PPS1WIDTH,EMAC0 PPS 1 Width Register"
|
|
group.long 0x7A0++0x0F
|
|
line.long 0x00 "EMAC0_TM_PPS2TGTM,EMAC0 PPS 2 Target Time Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_PPS2NTGTM,EMAC0 PPS 2 Target Time Nanoseconds Register"
|
|
bitfld.long 0x04 31. " TSTRBUSY ,Target time register" "Not busy,Busy"
|
|
hexmask.long 0x04 0.--30. 1. " TSTR ,Target time low register"
|
|
line.long 0x08 "EMAC0_TM_PPS2INTVL,EMAC0 PPS 2 Interval Register"
|
|
line.long 0x0C "EMAC0_TM_PPS2WIDTH,EMAC0 PPS 2 Width Register"
|
|
group.long 0x7C0++0x0F
|
|
line.long 0x00 "EMAC0_TM_PPS3TGTM,EMAC0 PPS 3 Target Time Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_PPS3NTGTM,EMAC0 PPS 3 Target Time Nanoseconds Register"
|
|
bitfld.long 0x04 31. " TSTRBUSY ,Target time register" "Not busy,Busy"
|
|
hexmask.long 0x04 0.--30. 1. " TSTR ,Target time low register"
|
|
line.long 0x08 "EMAC0_TM_PPS3INTVL,EMAC0 PPS 3 Interval Register"
|
|
line.long 0x0C "EMAC0_TM_PPS3WIDTH,EMAC0 PPS 3 Width Register"
|
|
endif
|
|
group.long 0x1000++0x0B
|
|
line.long 0x00 "EMAC0_DMA0_BUSMODE,EMAC0 DMA Bus Mode Register"
|
|
bitfld.long 0x00 25. " AAL ,Address aligned bursts" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PBL8 ,PBL * 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RPBL ,Receive programmable burst length" ",1,2,,4,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "EMAC0_DMA0_TXPOLL,EMAC0 DMA Tx Poll Demand Register"
|
|
line.long 0x08 "EMAC0_DMA0_RXPOLL,EMAC0 DMA Rx Poll Demand Register"
|
|
if (((per.l(ad:0x3100C000+0x1018))&0x2)==0x0)
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "EMAC0_DMA0_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "EMAC0_DMA0_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
endif
|
|
if (((per.l(ad:0x3100C000+0x1018))&0x2000)==0x0)
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "EMAC0_DMA0_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "EMAC0_DMA0_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
endif
|
|
group.long 0x1014++0x03
|
|
line.long 0x00 "EMAC0_DMA0_STAT,EMAC0 DMA Status Register"
|
|
rbitfld.long 0x00 30. " GLPII ,GMAC LPI interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " TTI ,Time stamp trigger interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 27. " MCI ,MAC MMC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " GLI ,Line interface interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 23.--25. " EB ,Error bits" "Data buffer/write/RxDMA,Data buffer/write/TxDMA,Data buffer/read/RxDMA,Data buffer/read/TxDMA,Descriptor/write/RxDMA,Descriptor/write/TxDMA,Descriptor/read/RxDMA,Descriptor/read/TxDMA"
|
|
rbitfld.long 0x00 20.--22. " TS ,Tx process state" "Stopped,Fetching,Waiting,Reading data,TIME_STAMP write,,Suspended,Closing descriptor"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " RS ,Rx process state" "Stopped,Fetching,,Waiting,Suspended,Closing descriptor,TIME_STAMP write,Packed data transfer"
|
|
eventfld.long 0x00 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " AIS ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RWT ,Receive watchdog timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 8. " RPS ,Receive process stopped" "Not stopped,Stopped"
|
|
eventfld.long 0x00 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " UNF ,Transmit buffer underflow" "No underflow,Underflow"
|
|
eventfld.long 0x00 4. " OVF ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TJT ,Transmit jabber timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
eventfld.long 0x00 1. " TPS ,Transmit process stopped" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
group.long 0x1018++0x07
|
|
line.long 0x00 "EMAC0_DMA0_OPMODE,EMAC0 DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DT ,Disable dropping TCP/IP errors" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No flush,Flush"
|
|
bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FUF ,Forward undersized good frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DGF ,Drop gaint frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
line.long 0x04 "EMAC0_DMA0_IEN,EMAC0 DMA Interrupt Enable Register"
|
|
bitfld.long 0x04 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FBE ,Fatal bus error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RSE ,Receive stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " UNE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OVE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1020++0x03
|
|
hide.long 0x00 "EMAC0_DMA0_MISS_FRM,EMAC0 DMA Missed Frame Register"
|
|
in
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "EMAC0_DMA0_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timer count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "EMAC0_DMA0_BMMODE,EMAC0 DMA SCB Bus Mode Register"
|
|
bitfld.long 0x00 31. " ENLPI ,Enable low power interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " WROSRLMT ,SCB maximum write outstanding request" "1,2,3,4,?..."
|
|
bitfld.long 0x00 16.--18. " RDOSRLMT ,SCB maximum read outstanding request" "1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " ONEKBBE ,1K boundary crossing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " AAL ,Address aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BLEN16 ,SCB burst length 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BLEN8 ,SCB burst length 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BLEN4 ,SCB burst length 4" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " UNDEF ,SCB undefined burst length" "Fixed,Any"
|
|
rgroup.long 0x102C++0x03
|
|
line.long 0x00 "EMAC0_DMA0_BMSTAT,EMAC0 DMA SCB Status Register"
|
|
bitfld.long 0x00 1. " BUSRD ,Bus (SCB master) read active" "Not active,Active"
|
|
bitfld.long 0x00 0. " BUSWR ,Bus (SCB master) write active" "Not active,Active"
|
|
rgroup.long 0x1048++0x0F
|
|
line.long 0x00 "EMAC0_DMA0_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register"
|
|
line.long 0x04 "EMAC0_DMA0_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register"
|
|
line.long 0x08 "EMAC0_DMA0_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register"
|
|
line.long 0x0C "EMAC0_DMA0_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x1100++0x0B
|
|
line.long 0x00 "EMAC0_DMA1_BUSMODE,EMAC0 DMA Bus Mode Register"
|
|
bitfld.long 0x00 25. " AAL ,Address aligned bursts" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PBL8 ,PBL * 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RPBL ,Receive programmable burst length" ",1,2,,4,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EMAC0_DMA1_TXPOLL,EMAC0 DMA Tx Poll Demand Register"
|
|
line.long 0x08 "EMAC0_DMA1_RXPOLL,EMAC0 DMA Rx Poll Demand Register"
|
|
if (((per.l(ad:0x3100C000+0x1118))&0x2)==0x00)
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA1_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA1_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
endif
|
|
if (((per.l(ad:0x3100C000+0x1118))&0x2000)==0x00)
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA1_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA1_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
endif
|
|
group.long 0x1114++0x0B
|
|
line.long 0x00 "EMAC0_DMA1_STAT,EMAC0 DMA Status Register"
|
|
rbitfld.long 0x00 30. " GTMSI ,MAC TMS interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " TTI ,Time stamp trigger interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 27. " MCI ,MAC MMC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " GLI ,Line interface interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 23.--25. " EB ,Error bits" "Data buffer/write/RxDMA,Data buffer/write/TxDMA,Data buffer/read/RxDMA,Data buffer/read/TxDMA,Descriptor/write/RxDMA,Descriptor/write/TxDMA,Descriptor/read/RxDMA,Descriptor/read/TxDMA"
|
|
rbitfld.long 0x00 20.--22. " TS ,Tx process state" "Stopped,Fetching,Waiting,Reading data,TIME_STAMP write,,Suspended,Closing descriptor"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " RS ,Rx process state" "Stopped,Fetching,,Waiting,Suspended,Closing descriptor,TIME_STAMP write,Packed data transfer"
|
|
eventfld.long 0x00 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " AIS ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RWT ,Receive watchdog timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 8. " RPS ,Receive process stopped" "Not stopped,Stopped"
|
|
eventfld.long 0x00 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " UNF ,Transmit buffer underflow" "No underflow,Underflow"
|
|
eventfld.long 0x00 4. " OVF ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TJT ,Transmit jabber timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
eventfld.long 0x00 1. " TPS ,Transmit process stopped" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "EMAC0_DMA1_OPMODE,EMAC0 DMA Operation Mode Register"
|
|
bitfld.long 0x04 26. " DT ,Disable dropping TCP/IP errors" "No,Yes"
|
|
bitfld.long 0x04 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TSF ,Transmit store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " FTF ,Flush transmit FIFO" "No flush,Flush"
|
|
bitfld.long 0x04 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x04 7. " FEF ,Forward error frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FUF ,Forward undersized good frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DGF ,Drop gaint frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x04 2. " OSF ,Operate on second frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
line.long 0x08 "EMAC0_DMA1_IEN,EMAC0 DMA Interrupt Enable Register"
|
|
bitfld.long 0x08 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " FBE ,Fatal bus error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " RSE ,Receive stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UNE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OVE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1120++0x03
|
|
hide.long 0x00 "EMAC0_DMA1_MISS_FRM,EMAC0 DMA Missed Frame Register"
|
|
in
|
|
group.long 0x1124++0x03
|
|
line.long 0x00 "EMAC0_DMA1_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timer count"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "EMAC0_DMA1_CHSFCS,EMAC0 Channel 1 Control Bits For Slot Function Register"
|
|
rbitfld.long 0x00 16.--19. " RSN ,Reference slot number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " ASC ,Advance slot check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ESC ,Enable slot comparison" "Disabled,Enabled"
|
|
rgroup.long 0x1148++0x0F
|
|
line.long 0x00 "EMAC0_DMA1_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register"
|
|
line.long 0x04 "EMAC0_DMA1_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register"
|
|
line.long 0x08 "EMAC0_DMA1_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register"
|
|
line.long 0x0C "EMAC0_DMA1_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "EMAC0_DMA1_CHCBSCTL,EMAC0 Channel 1 Credit Shaping Control Register"
|
|
bitfld.long 0x00 17. " ABPSSIE ,Average bits per slot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SLC ,Slot count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " CC ,Credit control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CBSD ,Credit based shaper disable" "No,Yes"
|
|
hgroup.long 0x1164++0x03
|
|
hide.long 0x00 "EMAC0_DMA1_CHCBSSTAT,EMAC0 Channel 1 Average Traffic Transmitted Register"
|
|
in
|
|
group.long 0x1168++0x0F
|
|
line.long 0x00 "EMAC0_DMA1_CHISC,EMAC0 Channel 1 Idle Slope Credit Value Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ISC ,Idle slope credit"
|
|
line.long 0x04 "EMAC0_DMA1_CHSSC,EMAC0 Channel 1 Send Slope Credit Value Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " SSC ,Send slope credit"
|
|
line.long 0x08 "EMAC0_DMA1_CHHIC,EMAC0 Channel 1 High Credit Value Register"
|
|
hexmask.long 0x08 0.--28. 1. " HC ,High credit"
|
|
line.long 0x0C "EMAC0_DMA1_CHLOC,EMAC0 Channel 1 Low Credit Value Register"
|
|
hexmask.long 0x0C 0.--28. 1. " LC ,Low credit"
|
|
group.long 0x1200++0x0B
|
|
line.long 0x00 "EMAC0_DMA2_BUSMODE,EMAC0 DMA Bus Mode Register"
|
|
bitfld.long 0x00 25. " AAL ,Address aligned bursts" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PBL8 ,PBL * 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RPBL ,Receive programmable burst length" ",1,2,,4,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "EMAC0_DMA2_TXPOLL,EMAC0 DMA Tx Poll Demand Register"
|
|
line.long 0x08 "EMAC0_DMA2_RXPOLL,EMAC0 DMA Rx Poll Demand Register"
|
|
if (((per.l(ad:0x3100C000+0x1218))&0x2)==0x00)
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA2_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA2_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
endif
|
|
if (((per.l(ad:0x3100C000+0x1218))&0x2000)==0x00)
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA2_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA2_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
endif
|
|
group.long 0x1214++0x0B
|
|
line.long 0x00 "EMAC0_DMA2_STAT,EMAC0 DMA Status Register"
|
|
rbitfld.long 0x00 30. " GTMSI ,MAC TMS interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " TTI ,Time stamp trigger interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 27. " MCI ,MAC MMC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " GLI ,Line interface interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 23.--25. " EB ,Error bits" "Data buffer/write/RxDMA,Data buffer/write/TxDMA,Data buffer/read/RxDMA,Data buffer/read/TxDMA,Descriptor/write/RxDMA,Descriptor/write/TxDMA,Descriptor/read/RxDMA,Descriptor/read/TxDMA"
|
|
rbitfld.long 0x00 20.--22. " TS ,Tx process state" "Stopped,Fetching,Waiting,Reading data,TIME_STAMP write,,Suspended,Closing descriptor"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " RS ,Rx process state" "Stopped,Fetching,,Waiting,Suspended,Closing descriptor,TIME_STAMP write,Packed data transfer"
|
|
eventfld.long 0x00 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " AIS ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RWT ,Receive watchdog timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 8. " RPS ,Receive process stopped" "Not stopped,Stopped"
|
|
eventfld.long 0x00 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " UNF ,Transmit buffer underflow" "No underflow,Underflow"
|
|
eventfld.long 0x00 4. " OVF ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TJT ,Transmit jabber timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
eventfld.long 0x00 1. " TPS ,Transmit process stopped" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "EMAC0_DMA2_OPMODE,EMAC0 DMA Operation Mode Register"
|
|
bitfld.long 0x04 26. " DT ,Disable dropping TCP/IP errors" "No,Yes"
|
|
bitfld.long 0x04 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TSF ,Transmit store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " FTF ,Flush transmit FIFO" "No flush,Flush"
|
|
bitfld.long 0x04 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x04 7. " FEF ,Forward error frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FUF ,Forward undersized good frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DGF ,Drop gaint frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x04 2. " OSF ,Operate on second frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
line.long 0x08 "EMAC0_DMA2_IEN,EMAC0 DMA Interrupt Enable Register"
|
|
bitfld.long 0x08 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " FBE ,Fatal bus error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " RSE ,Receive stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UNE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OVE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1220++0x03
|
|
hide.long 0x00 "EMAC0_DMA2_MISS_FRM,EMAC0 DMA Missed Frame Register"
|
|
in
|
|
group.long 0x1224++0x03
|
|
line.long 0x00 "EMAC0_DMA2_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timer count"
|
|
group.long 0x1230++0x03
|
|
line.long 0x00 "EMAC0_DMA2_CHSFCS,EMAC0 Channel 2 Control Bits For Slot Function Register"
|
|
rbitfld.long 0x00 16.--19. " RSN ,Reference slot number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " ASC ,Advance slot check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ESC ,Enable slot comparison" "Disabled,Enabled"
|
|
rgroup.long 0x1248++0x0F
|
|
line.long 0x00 "EMAC0_DMA2_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register"
|
|
line.long 0x04 "EMAC0_DMA2_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register"
|
|
line.long 0x08 "EMAC0_DMA2_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register"
|
|
line.long 0x0C "EMAC0_DMA2_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register"
|
|
group.long 0x1260++0x03
|
|
line.long 0x00 "EMAC0_DMA2_CHCBSCTL,EMAC0 Channel 2 Credit Shaping Control Register"
|
|
bitfld.long 0x00 17. " ABPSSIE ,Average bits per slot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SLC ,Slot count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " CC ,Credit control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CBSD ,Credit based shaper disable" "No,Yes"
|
|
hgroup.long 0x1264++0x03
|
|
hide.long 0x00 "EMAC0_DMA2_CHCBSSTAT,EMAC0 Channel 2 Avg Traffic Transmitted Status Register"
|
|
in
|
|
group.long 0x1268++0x0F
|
|
line.long 0x00 "EMAC0_DMA2_CHISC,EMAC0 Channel 2 Idle Slope Credit Value Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ISC ,Idle slope credit"
|
|
line.long 0x04 "EMAC0_DMA2_CHSSC,EMAC0 Channel 2 Send Slope Credit Value Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " SSC ,Send slope credit"
|
|
line.long 0x08 "EMAC0_DMA2_CHHIC,EMAC0 Channel 2 High Credit Value Register"
|
|
hexmask.long 0x08 0.--28. 1. " HC ,High credit"
|
|
line.long 0x0C "EMAC0_DMA2_CHLOC,EMAC0 Channel 2 Low Credit Value Register"
|
|
hexmask.long 0x0C 0.--28. 1. " LC ,Low credit"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAI (Digital Audio Interface)"
|
|
base ad:0x310C90C0
|
|
width 15.
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DAI0_CLK0,DAI0 Clock Routing Control Register $2"
|
|
bitfld.long 0x00 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x00 20.--24. " IN4 ,Input clock 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x00 15.--19. " IN3 ,Input clock 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x00 10.--14. " IN2 ,Input clock 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x00 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x00 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
line.long 0x04 "DAI0_CLK1,DAI0 Clock Routing Control Register 1"
|
|
bitfld.long 0x04 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x04 20.--24. " IN4 ,Input clock 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x04 15.--19. " IN3 ,Input clock 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x04 10.--14. " IN2 ,Input clock 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x04 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x04 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
line.long 0x08 "DAI0_CLK2,DAI0 Clock Routing Control Register 2"
|
|
bitfld.long 0x08 10.--14. " IN2 ,Input clock 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x08 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x08 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
line.long 0x0C "DAI0_CLK3,DAI0 Clock Routing Control Register 3"
|
|
bitfld.long 0x0C 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
line.long 0x10 "DAI0_CLK4,DAI0 Clock Routing Control Register 4"
|
|
bitfld.long 0x10 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x10 20.--24. " IN4 ,Input clock 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
|
|
bitfld.long 0x10 15.--19. " IN3 ,Input clock 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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|
bitfld.long 0x10 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x14 "DAI0_CLK5,DAI0 Clock Routing Control Register 5"
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bitfld.long 0x14 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x14 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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elif cpuis("ADSP-SC57?")
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group.long 0x00++0x17
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line.long 0x00 "DAI0_CLK0,DAI0 Clock Routing Control Register $2"
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bitfld.long 0x00 25.--29. " IN5 ,Input clock 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 20.--24. " IN4 ,Input clock 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 15.--19. " IN3 ,Input clock 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 10.--14. " IN2 ,Input clock 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 5.--9. " IN1 ,Input clock 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 0.--4. " IN0 ,Input clock 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x04 "DAI0_CLK1,DAI0 Clock Routing Control Register 1"
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bitfld.long 0x04 25.--29. " IN5 ,Input clock 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 20.--24. " IN4 ,Input clock 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 15.--19. " IN3 ,Input clock 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 10.--14. " IN2 ,Input clock 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 5.--9. " IN1 ,Input clock 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 0.--4. " IN0 ,Input clock 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x08 "DAI0_CLK2,DAI0 Clock Routing Control Register 2"
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bitfld.long 0x08 10.--14. " IN2 ,Input clock 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x08 5.--9. " IN1 ,Input clock 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x08 0.--4. " IN0 ,Input clock 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x0C "DAI0_CLK3,DAI0 Clock Routing Control Register 3"
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bitfld.long 0x0C 25.--29. " IN5 ,Input clock 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x10 "DAI0_CLK4,DAI0 Clock Routing Control Register 4"
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bitfld.long 0x10 25.--29. " IN5 ,Input clock 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 20.--24. " IN4 ,Input clock 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 15.--19. " IN3 ,Input clock 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 5.--9. " IN1 ,Input clock 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 0.--4. " IN0 ,Input clock 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x14 "DAI0_CLK5,DAI0 Clock Routing Control Register 5"
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bitfld.long 0x14 5.--9. " IN1 ,Input clock 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x14 0.--4. " IN0 ,Input clock 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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else
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group.long 0x00++0x17
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line.long 0x00 "DAI0_CLK0,DAI0 Clock Routing Control Register $2"
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bitfld.long 0x00 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 20.--24. " IN4 ,Input clock 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 15.--19. " IN3 ,Input clock 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 10.--14. " IN2 ,Input clock 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x00 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x04 "DAI0_CLK1,DAI0 Clock Routing Control Register 1"
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bitfld.long 0x04 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 20.--24. " IN4 ,Input clock 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 15.--19. " IN3 ,Input clock 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 10.--14. " IN2 ,Input clock 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x04 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x08 "DAI0_CLK2,DAI0 Clock Routing Control Register 2"
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bitfld.long 0x08 10.--14. " IN2 ,Input clock 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x08 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x08 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x0C "DAI0_CLK3,DAI0 Clock Routing Control Register 3"
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bitfld.long 0x0C 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x10 "DAI0_CLK4,DAI0 Clock Routing Control Register 4"
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bitfld.long 0x10 25.--29. " IN5 ,Input clock 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 20.--24. " IN4 ,Input clock 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 15.--19. " IN3 ,Input clock 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x10 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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line.long 0x14 "DAI0_CLK5,DAI0 Clock Routing Control Register 5"
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bitfld.long 0x14 5.--9. " IN1 ,Input clock 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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bitfld.long 0x14 0.--4. " IN0 ,Input clock 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_ACLK,SPT0_BCLK,SPT1_ACLK,SPT1_BCLK,SPT2_ACLK,SPT2_BCLK,SPDIF0_RX_CLK,SPDIF0_RX_TDMCLK,PCG0_CLKA,PCG0_CLKB,LOW,HIGH"
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endif
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textline " "
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sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))
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group.long 0x40++0x1B
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line.long 0x00 "DAI0_DAT0,DAI0 Serial Data Routing Control Register 0"
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bitfld.long 0x00 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x04 "DAI0_DAT1,DAI0 Serial Data Routing Control Register 1"
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bitfld.long 0x04 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x08 "DAI0_DAT2,DAI0 Serial Data Routing Control Register 2"
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bitfld.long 0x08 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x0C "DAI0_DAT3,DAI0 Serial Data Routing Control Register 3"
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bitfld.long 0x0C 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x10 "DAI0_DAT4,DAI0 Serial Data Routing Control Register 4"
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bitfld.long 0x10 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x14 "DAI0_DAT5,DAI0 Serial Data Routing Control Register 5"
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bitfld.long 0x14 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x18 "DAI0_DAT6,DAI0 Serial Data Routing Control Register 6"
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bitfld.long 0x18 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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elif cpuis("ADSP-SC57?")
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group.long 0x40++0x1B
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line.long 0x00 "DAI0_DAT0,DAI0 Serial Data Routing Control Register 0"
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bitfld.long 0x00 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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line.long 0x04 "DAI0_DAT1,DAI0 Serial Data Routing Control Register 1"
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bitfld.long 0x04 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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line.long 0x08 "DAI0_DAT2,DAI0 Serial Data Routing Control Register 2"
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bitfld.long 0x08 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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line.long 0x0C "DAI0_DAT3,DAI0 Serial Data Routing Control Register 3"
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bitfld.long 0x0C 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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line.long 0x10 "DAI0_DAT4,DAI0 Serial Data Routing Control Register 4"
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bitfld.long 0x10 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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line.long 0x14 "DAI0_DAT5,DAI0 Serial Data Routing Control Register 5"
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bitfld.long 0x14 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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line.long 0x18 "DAI0_DAT6,DAI0 Serial Data Routing Control Register 6"
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bitfld.long 0x18 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,,,,,,,,,,,,,,LOW,HIGH"
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else
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group.long 0x40++0x1B
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line.long 0x00 "DAI0_DAT0,DAI0 Serial Data Routing Control Register 0"
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bitfld.long 0x00 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x00 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x04 "DAI0_DAT1,DAI0 Serial Data Routing Control Register 1"
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bitfld.long 0x04 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x04 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x08 "DAI0_DAT2,DAI0 Serial Data Routing Control Register 2"
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bitfld.long 0x08 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x08 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x0C "DAI0_DAT3,DAI0 Serial Data Routing Control Register 3"
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bitfld.long 0x0C 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x0C 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x10 "DAI0_DAT4,DAI0 Serial Data Routing Control Register 4"
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bitfld.long 0x10 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x14 "DAI0_DAT5,DAI0 Serial Data Routing Control Register 5"
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bitfld.long 0x14 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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line.long 0x18 "DAI0_DAT6,DAI0 Serial Data Routing Control Register 6"
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bitfld.long 0x18 24.--29. " IN4 ,Input data 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 18.--23. " IN3 ,Input data 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 12.--17. " IN2 ,Input data 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 6.--11. " IN1 ,Input data 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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bitfld.long 0x18 0.--5. " IN0 ,Input data 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AD0,SPT0_AD1,SPT0_BD0,SPT0_BD1,SPT1_AD0,SPT1_AD1,SPT1_BD0,SPT1_BD1,SPT2_AD0,SPT2_AD1,SPT2_BD0,SPT2_BD1,SRC0_DATP,SRC1_DATP,SRC2_DATP,SRC3_DATP,SRC0_TDM_IP,SRC1_TDM_IP,SRC2_TDM_IP,SRC3_TDM_IP,SPDIF0_RX_DAT,,,,SPT3_AD0,SPT3_AD1,SPT3_BD0,SPT3_BD1,SPDIF0_TX,SRC3_CRS_DAT_OP,SRC3_CRS_TDM_IP,,,,,,,,,,,,LOW,HIGH"
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endif
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textline " "
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sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))
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group.long 0x80++0x0B
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line.long 0x00 "DAI0_FS0,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x00 25.--29. " IN5 ,Input frame sync 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 20.--24. " IN4 ,Input frame sync 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 15.--19. " IN3 ,Input frame sync 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 10.--14. " IN2 ,Input frame sync 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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line.long 0x04 "DAI0_FS1,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x04 25.--29. " IN5 ,Input frame sync 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 20.--24. " IN4 ,Input frame sync 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 15.--19. " IN3 ,Input frame sync 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 10.--14. " IN2 ,Input frame sync 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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line.long 0x08 "DAI0_FS2,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x08 10.--14. " IN2 ,Input frame sync 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x08 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x08 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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group.long 0x90++0x03
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line.long 0x00 "DAI0_FS4,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x00 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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elif cpuis("ADSP-SC57?")
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group.long 0x80++0x0B
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line.long 0x00 "DAI0_FS0,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x00 25.--29. " IN5 ,Input frame sync 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 20.--24. " IN4 ,Input frame sync 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 15.--19. " IN3 ,Input frame sync 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 10.--14. " IN2 ,Input frame sync 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 5.--9. " IN1 ,Input frame sync 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 0.--4. " IN0 ,Input frame sync 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
line.long 0x04 "DAI0_FS1,DAI0 Frame Sync Routing Control Register"
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|
bitfld.long 0x04 25.--29. " IN5 ,Input frame sync 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 20.--24. " IN4 ,Input frame sync 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 15.--19. " IN3 ,Input frame sync 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 10.--14. " IN2 ,Input frame sync 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 5.--9. " IN1 ,Input frame sync 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 0.--4. " IN0 ,Input frame sync 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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line.long 0x08 "DAI0_FS2,DAI0 Frame Sync Routing Control Register"
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|
bitfld.long 0x08 10.--14. " IN2 ,Input frame sync 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x08 5.--9. " IN1 ,Input frame sync 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x08 0.--4. " IN0 ,Input frame sync 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
group.long 0x90++0x03
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|
line.long 0x00 "DAI0_FS4,DAI0 Frame Sync Routing Control Register"
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|
bitfld.long 0x00 5.--9. " IN1 ,Input frame sync 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 0.--4. " IN0 ,Input frame sync 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
else
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group.long 0x80++0x0B
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|
line.long 0x00 "DAI0_FS0,DAI0 Frame Sync Routing Control Register"
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|
bitfld.long 0x00 25.--29. " IN5 ,Input frame sync 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 20.--24. " IN4 ,Input frame sync 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 15.--19. " IN3 ,Input frame sync 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 10.--14. " IN2 ,Input frame sync 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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line.long 0x04 "DAI0_FS1,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x04 25.--29. " IN5 ,Input frame sync 5" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 20.--24. " IN4 ,Input frame sync 4" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 15.--19. " IN3 ,Input frame sync 3" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 10.--14. " IN2 ,Input frame sync 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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line.long 0x08 "DAI0_FS2,DAI0 Frame Sync Routing Control Register"
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bitfld.long 0x08 10.--14. " IN2 ,Input frame sync 2" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x08 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x08 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
group.long 0x90++0x03
|
|
line.long 0x00 "DAI0_FS4,DAI0 Frame Sync Routing Control Register"
|
|
bitfld.long 0x00 5.--9. " IN1 ,Input frame sync 1" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 0.--4. " IN0 ,Input frame sync 0" "DAI0_CRS_PB03,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_FS,,PCG0_FSA,PCG0_FSB,LOW,HIGH"
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|
endif
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|
textline " "
|
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group.long 0xC0++0x0B
|
|
line.long 0x00 "DAI0_PIN0,DAI0 Pin Buffer Assignment Register 0"
|
|
hexmask.long.byte 0x00 21.--27. 1. " PB04 ,Pin buffer 4 input"
|
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hexmask.long.byte 0x00 14.--20. 1. " PB03 ,Pin buffer 3 input"
|
|
hexmask.long.byte 0x00 7.--13. 1. " PB02 ,Pin buffer 2 input"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PB01 ,Pin buffer 1 input"
|
|
line.long 0x04 "DAI0_PIN1,DAI0 Pin Buffer Assignment Register 1"
|
|
hexmask.long.byte 0x04 21.--27. 1. " PB08 ,Pin buffer 8 input"
|
|
hexmask.long.byte 0x04 14.--20. 1. " PB07 ,Pin buffer 7 input"
|
|
hexmask.long.byte 0x04 7.--13. 1. " PB06 ,Pin buffer 6 input"
|
|
hexmask.long.byte 0x04 0.--6. 1. " PB05 ,Pin buffer 5 input"
|
|
line.long 0x08 "DAI0_PIN2,DAI0 Pin Buffer Assignment Register 2"
|
|
hexmask.long.byte 0x08 21.--27. 1. " PB12 ,Pin buffer 12 input"
|
|
hexmask.long.byte 0x08 14.--20. 1. " PB11 ,Pin buffer 11 input"
|
|
hexmask.long.byte 0x08 7.--13. 1. " PB10 ,Pin buffer 10 input"
|
|
hexmask.long.byte 0x08 0.--6. 1. " PB09 ,Pin buffer 9 input"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))||cpuis("ADSP-SC57?")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DAI0_PIN3,DAI0 Pin Buffer Assignment Register 3"
|
|
hexmask.long.byte 0x00 21.--27. 1. " PB16 ,Pin buffer 16 input"
|
|
hexmask.long.byte 0x00 14.--20. 1. " PB15 ,Pin buffer 15 input"
|
|
hexmask.long.byte 0x00 7.--13. 1. " PB14 ,Pin buffer 14 input"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PB13 ,Pin buffer 13 input"
|
|
endif
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DAI0_PIN4,DAI0 Pin Buffer Assignment Register 4"
|
|
bitfld.long 0x00 29. " INV20 ,Pin buffer 20 invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 28. " INV19 ,Pin buffer 19 invert" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))||cpuis("ADSP-SC57?")
|
|
hexmask.long.byte 0x00 21.--27. 1. " PB20 ,Pin buffer 20 input"
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|
hexmask.long.byte 0x00 14.--20. 1. " PB19 ,Pin buffer 19 input"
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|
hexmask.long.byte 0x00 7.--13. 1. " PB18 ,Pin buffer 18 input"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PB17 ,Pin buffer 17 input"
|
|
else
|
|
hexmask.long.byte 0x00 21.--27. 1. " PB20 ,Pin buffer 20 input"
|
|
hexmask.long.byte 0x00 14.--20. 1. " PB19 ,Pin buffer 19 input"
|
|
endif
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))||cpuis("ADSP-SC57?")
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "DAI0_MISC0,DAI0 Miscellaneous Control Register 0"
|
|
bitfld.long 0x00 31. " INV11 ,Invert 11" "Not inverted,Inverted"
|
|
bitfld.long 0x00 30. " INV10 ,Invert 10" "Not inverted,Inverted"
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|
bitfld.long 0x00 25.--29. " IN11 ,Input 11" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
bitfld.long 0x00 20.--24. " IN10 ,Input 10" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
textline " "
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bitfld.long 0x00 15.--19. " IN9 ,Input 9" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 10.--14. " IN8 ,Input 8" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 5.--9. " IN7 ,Input 7" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x00 0.--4. " IN6 ,Input 6" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
line.long 0x04 "DAI0_MISC1,DAI0 Miscellaneous Control Register 1"
|
|
bitfld.long 0x04 25.--29. " IN5 ,Input 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 20.--24. " IN4 ,Input 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 15.--19. " IN3 ,Input 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
textline " "
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|
bitfld.long 0x04 10.--14. " IN2 ,Input 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
bitfld.long 0x04 5.--9. " IN1 ,Input 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 0.--4. " IN0 ,Input 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,DAI0_PB13,DAI0_PB14,DAI0_PB15,DAI0_PB16,DAI0_PB17,DAI0_PB18,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
else
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "DAI0_MISC0,DAI0 Miscellaneous Control Register 0"
|
|
bitfld.long 0x00 31. " INV11 ,Invert 11" "Not inverted,Inverted"
|
|
bitfld.long 0x00 30. " INV10 ,Invert 10" "Not inverted,Inverted"
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|
bitfld.long 0x00 25.--29. " IN11 ,Input 11" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 20.--24. " IN10 ,Input 10" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
textline " "
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|
bitfld.long 0x00 15.--19. " IN9 ,Input 9" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 10.--14. " IN8 ,Input 8" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 5.--9. " IN7 ,Input 7" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x00 0.--4. " IN6 ,Input 6" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
line.long 0x04 "DAI0_MISC1,DAI0 Miscellaneous Control Register 1"
|
|
bitfld.long 0x04 25.--29. " IN5 ,Input 5" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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|
bitfld.long 0x04 20.--24. " IN4 ,Input 4" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
bitfld.long 0x04 15.--19. " IN3 ,Input 3" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " IN2 ,Input 2" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 5.--9. " IN1 ,Input 1" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
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bitfld.long 0x04 0.--4. " IN0 ,Input 0" "DAI0_PB01,DAI0_PB02,DAI0_PB03,DAI0_PB04,DAI0_PB05,DAI0_PB06,DAI0_PB07,DAI0_PB08,DAI0_PB09,DAI0_PB10,DAI0_PB11,DAI0_PB12,,,,,,,DAI0_PB19,DAI0_PB20,SPT0_AFS,SPT0_BFS,SPT1_AFS,SPT1_BFS,SPT2_AFS,SPT2_BFS,SPDIF0_TX_BLKSTART,PCG0_FSA,PCG0_CLKB,PCG0_FSB,LOW,HIGH"
|
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endif
|
|
textline " "
|
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group.long 0x120++0x0F
|
|
line.long 0x00 "DAI0_PBEN0,DAI0 Pin Buffer Enable Register 0"
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bitfld.long 0x00 24.--29. " PB05 ,Pin buffer enable 5" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x00 18.--23. " PB04 ,Pin buffer enable 4" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x00 12.--17. " PB03 ,Pin buffer enable 3" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x00 6.--11. " PB02 ,Pin buffer enable 2" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x00 0.--5. " PB01 ,Pin buffer enable 1" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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line.long 0x04 "DAI0_PBEN1,DAI0 Pin Buffer Enable Register 1"
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bitfld.long 0x04 24.--29. " PB10 ,Pin buffer enable 10" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x04 18.--23. " PB09 ,Pin buffer enable 9" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x04 12.--17. " PB08 ,Pin buffer enable 8" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x04 6.--11. " PB07 ,Pin buffer enable 7" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x04 0.--5. " PB06 ,Pin buffer enable 6" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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line.long 0x08 "DAI0_PBEN2,DAI0 Pin Buffer Enable Register 2"
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sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))||cpuis("ADSP-SC57?")
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bitfld.long 0x08 24.--29. " PB15 ,Pin buffer enable 15" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x08 18.--23. " PB14 ,Pin buffer enable 14" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x08 12.--17. " PB13 ,Pin buffer enable 13" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x08 6.--11. " PB12 ,Pin buffer enable 12" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x08 0.--5. " PB11 ,Pin buffer enable 11" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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else
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bitfld.long 0x08 6.--11. " PB12 ,Pin buffer enable 12" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x08 0.--5. " PB11 ,Pin buffer enable 11" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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endif
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line.long 0x0C "DAI0_PBEN3,DAI0 Pin Buffer Enable Register 3"
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sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))||cpuis("ADSP-SC57?")
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bitfld.long 0x0C 24.--29. " PB20 ,Pin buffer enable 20" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x0C 18.--23. " PB19 ,Pin buffer enable 19" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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bitfld.long 0x0C 12.--17. " PB18 ,Pin buffer enable 18" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
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|
bitfld.long 0x0C 6.--11. " PB17 ,Pin buffer enable 17" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
|
|
bitfld.long 0x0C 0.--5. " PB16 ,Pin buffer enable 16" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
|
|
else
|
|
bitfld.long 0x0C 24.--29. " PB20 ,Pin buffer enable 20" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
|
|
bitfld.long 0x0C 18.--23. " PB19 ,Pin buffer enable 19" "LOW,HIGH,DAI0_MISCA0,DAI0_MISCA1,DAI0_MISCA2,DAI0_MISCA3,DAI0_MISCA4,DAI0_MISCA5,SPT0_ACLK_PBEN,SPT0_AFS_PBEN,SPT0_AD0_PBEN,SPT0_AD1_PBEN,SPT0_BCLK_PBEN,SPT0_BFS_PBEN,SPT0_BD0_PBEN,SPT0_BD1_PBEN,SPT1_ACLK_PBEN,SPT1_AFS_PBEN,SPT1_AD0_PBEN,SPT1_AD1_PBEN,SPT1_BCLK_PBEN,SPT1_BFS_PBEN,SPT1_BD0_PBEN,SPT1_BD1_PBEN,SPT2_ACLK_PBEN,SPT2_AFS_PBEN,SPT2_AD0_PBEN,SPT2_AD1_PBEN,SPT2_BCLK_PBEN,SPT2_BFS_PBEN,SPT2_BD0_PBEN,SPT2_BD1_PBEN,SPT3_ACLK_PBEN,SPT3_AFS_PBEN,SPT3_AD0_PBEN,SPT3_AD1_PBEN,SPT3_BCLK_PBEN,SPT3_BFS_PBEN,SPT3_BD0_PBEN,SPT3_BD1_PBEN,SPT0_ATDV_PBEN,SPT0_BTDV_PBEN,SPT1_ATDV_PBEN,SPT1_BTDV_PBEN,SPT2_ATDV_PBEN,SPT2_BTDV_PBEN,SPT3_ATDV_PBEN,SPT3_BTDV_PBEN,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "DAI0_IMSK_FE,DAI0 Falling-Edge Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous interrupt 9" "Masked,Unmasked"
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|
bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous interrupt 8" "Masked,Unmasked"
|
|
bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous interrupt 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous interrupt 6" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous interrupt 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous interrupt 4" "Masked,Unmasked"
|
|
bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous interrupt 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous interrupt 2" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous interrupt 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous interrupt 0" "Masked,Unmasked"
|
|
bitfld.long 0x00 21. " SRC3MUTE ,SRC3 mute" "Masked,Unmasked"
|
|
bitfld.long 0x00 20. " SRC2MUTE ,SRC2 mute" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SRC1MUTE ,SRC1 mute" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " SRC0MUTE ,SRC0 mute" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " RXNONAUDIO ,Receive non audio" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive loss of lock" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " RXLOCK ,Receive lock" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " RXVALID ,Receive valid" "Masked,Unmasked"
|
|
line.long 0x04 "DAI0_IMSK_RE,DAI0 Rising-Edge Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " MISCINT9 ,Miscellaneous interrupt 9" "Masked,Unmasked"
|
|
bitfld.long 0x04 30. " MISCINT8 ,Miscellaneous interrupt 8" "Masked,Unmasked"
|
|
bitfld.long 0x04 29. " MISCINT7 ,Miscellaneous interrupt 7" "Masked,Unmasked"
|
|
bitfld.long 0x04 28. " MISCINT6 ,Miscellaneous interrupt 6" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MISCINT5 ,Miscellaneous interrupt 5" "Masked,Unmasked"
|
|
bitfld.long 0x04 26. " MISCINT4 ,Miscellaneous interrupt 4" "Masked,Unmasked"
|
|
bitfld.long 0x04 25. " MISCINT3 ,Miscellaneous interrupt 3" "Masked,Unmasked"
|
|
bitfld.long 0x04 24. " MISCINT2 ,Miscellaneous interrupt 2" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MISCINT1 ,Miscellaneous interrupt 1" "Masked,Unmasked"
|
|
bitfld.long 0x04 22. " MISCINT0 ,Miscellaneous interrupt 0" "Masked,Unmasked"
|
|
bitfld.long 0x04 21. " SRC3MUTE ,SRC3 mute" "Masked,Unmasked"
|
|
bitfld.long 0x04 20. " SRC2MUTE ,SRC2 mute" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SRC1MUTE ,SRC1 mute" "Masked,Unmasked"
|
|
bitfld.long 0x04 18. " SRC0MUTE ,SRC0 mute" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " RXNONAUDIO ,Receive non audio" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " RXLOSSOFLOCK ,Receive loss of lock" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " RXLOCK ,Receive lock" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " RXVALID ,Receive valid" "Masked,Unmasked"
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|
group.long 0x150++0x03
|
|
line.long 0x00 "DAI0_IMSK_PRI,DAI0 Core Interrupt Priority Assignment Register"
|
|
bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous interrupt 9" "IRQL,IRQH"
|
|
bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous interrupt 8" "IRQL,IRQH"
|
|
bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous interrupt 7" "IRQL,IRQH"
|
|
bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous interrupt 6" "IRQL,IRQH"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous interrupt 5" "IRQL,IRQH"
|
|
bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous interrupt 4" "IRQL,IRQH"
|
|
bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous interrupt 3" "IRQL,IRQH"
|
|
bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous interrupt 2" "IRQL,IRQH"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous interrupt 1" "IRQL,IRQH"
|
|
bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous interrupt 0" "IRQL,IRQH"
|
|
bitfld.long 0x00 21. " SRC3MUTE ,SRC3 mute" "IRQL,IRQH"
|
|
bitfld.long 0x00 20. " SRC2MUTE ,SRC2 mute" "IRQL,IRQH"
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textline " "
|
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bitfld.long 0x00 19. " SRC1MUTE ,SRC1 mute" "IRQL,IRQH"
|
|
bitfld.long 0x00 18. " SRC0MUTE ,SRC0 mute" "IRQL,IRQH"
|
|
bitfld.long 0x00 4. " RXNONAUDIO ,Receiver Non-Audio" "IRQL,IRQH"
|
|
textline " "
|
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bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive loss of lock" "IRQL,IRQH"
|
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bitfld.long 0x00 1. " RXLOCK ,Receive lock" "IRQL,IRQH"
|
|
bitfld.long 0x00 0. " RXVALID ,Receive valid" "IRQL,IRQH"
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hgroup.long 0x160++0x07
|
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hide.long 0x00 "DAI0_IRPTL_H,DAI0 High Priority Interrupt Latch Register"
|
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in
|
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hide.long 0x04 "DAI0_IRPTL_L,DAI0 Low Priority Interrupt Latch Register"
|
|
in
|
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rgroup.long 0x170++0x07
|
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line.long 0x00 "DAI0_IRPTL_HS,DAI0 Shadow High Priority Interrupt Latch Register"
|
|
bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous interrupt 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous interrupt 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous interrupt 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous interrupt 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous interrupt 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous interrupt 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous interrupt 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous interrupt 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " SRC3MUTE ,SRC3 mute" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " SRC2MUTE ,SRC2 mute" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SRC1MUTE ,SRC1 mute" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " SRC0MUTE ,SRC0 mute" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXNONAUDIO ,Receive non audio" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive loss of lock" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RXLOCK ,Receive lock" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXSTATCNG ,Receive valid" "No interrupt,Interrupt"
|
|
line.long 0x04 "DAI0_IRPTL_LS,DAI0 Shadow Low Priority Interrupt Latch Register"
|
|
bitfld.long 0x04 31. " MISCINT9 ,Miscellaneous interrupt 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " MISCINT8 ,Miscellaneous interrupt 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " MISCINT7 ,Miscellaneous interrupt 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " MISCINT6 ,Miscellaneous interrupt 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MISCINT5 ,Miscellaneous interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " MISCINT4 ,Miscellaneous interrupt 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " MISCINT3 ,Miscellaneous interrupt 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " MISCINT2 ,Miscellaneous interrupt 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MISCINT1 ,Miscellaneous interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " MISCINT0 ,Miscellaneous interrupt 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " SRC3MUTE ,SRC3 mute" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " SRC2MUTE ,SRC2 mute" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SRC1MUTE ,SRC1 mute" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " SRC0MUTE ,SRC0 mute" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXNONAUDIO ,CRC receive error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " RXLOSSOFLOCK ,Receive emphasis loss of lock" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RXLOCK ,Receive error lock" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXVALID ,Receive status change" "No interrupt,Interrupt"
|
|
textline " "
|
|
rgroup.long 0x224++0x03
|
|
line.long 0x00 "DAI0_PIN_STAT,DAI0 Pin Status Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589"))||cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 19. " PB20 ,Pin buffer 20 status" "Low,High"
|
|
bitfld.long 0x00 18. " PB19 ,Pin buffer 19 status" "Low,High"
|
|
bitfld.long 0x00 17. " PB18 ,Pin buffer 18 status" "Low,High"
|
|
bitfld.long 0x00 16. " PB17 ,Pin buffer 17 status" "Low,High"
|
|
bitfld.long 0x00 15. " PB16 ,Pin buffer 16 status" "Low,High"
|
|
bitfld.long 0x00 14. " PB15 ,Pin buffer 15 status" "Low,High"
|
|
bitfld.long 0x00 13. " PB14 ,Pin buffer 14 status" "Low,High"
|
|
bitfld.long 0x00 12. " PB13 ,Pin buffer 13 status" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " PB20 ,Pin buffer 20 status" "Low,High"
|
|
bitfld.long 0x00 18. " PB19 ,Pin buffer 19 status" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " PB12 ,Pin buffer 12 status" "Low,High"
|
|
bitfld.long 0x00 10. " PB11 ,Pin buffer 11 status" "Low,High"
|
|
bitfld.long 0x00 9. " PB10 ,Pin buffer 10 status" "Low,High"
|
|
bitfld.long 0x00 8. " PB09 ,Pin buffer 09 status" "Low,High"
|
|
bitfld.long 0x00 7. " PB08 ,Pin buffer 08 status" "Low,High"
|
|
bitfld.long 0x00 6. " PB07 ,Pin buffer 07 status" "Low,High"
|
|
bitfld.long 0x00 5. " PB06 ,Pin buffer 06 status" "Low,High"
|
|
bitfld.long 0x00 4. " PB05 ,Pin buffer 05 status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PB04 ,Pin buffer 04 status" "Low,High"
|
|
bitfld.long 0x00 2. " PB03 ,Pin buffer 03 status" "Low,High"
|
|
bitfld.long 0x00 1. " PB02 ,Pin buffer 02 status" "Low,High"
|
|
bitfld.long 0x00 0. " PB01 ,Pin buffer 01 status" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPORT (Serial Port)"
|
|
tree "SPORT0"
|
|
base ad:0x31002000
|
|
width 20.
|
|
if ((((per.l(ad:0x31002000+0x0))&0x6800)==0x800)&&(((per.l(ad:0x31002000+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002000+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x31002000+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002000+0x0))&0x4800)==0x00)&&(((per.l(ad:0x31002000+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002000+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT0_DIV_A,SPORT0 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT0_MCTL_A,SPORT0 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT0_CS0_A,SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT0_CS1_A,SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT0_CS2_A,SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT0_CS3_A,SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT0_ERR_A,SPORT0 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT0_MSTAT_A,SPORT0 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT0_CTL2_A,SPORT0 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT0_TXPRI_A,SPORT0 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT0_RXPRI_A,SPORT0 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT0_TXSEC_A,SPORT0 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT0_RXSEC_A,SPORT0 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
if ((((per.l(ad:0x31002000+0x80))&0x6800)==0x800)&&(((per.l(ad:0x31002000+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002000+0x80))&0x6800)==0x2800)&&(((per.l(ad:0x31002000+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002000+0x80))&0x4800)==0x00)&&(((per.l(ad:0x31002000+0x80+0x08))&0x01)==0x01))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002000+0x80))&0x204800)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "SPORT0_DIV_B,SPORT0 Half SPORT 'B' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT0_MCTL_B,SPORT0 Half SPORT 'B' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "SPORT0_CS0_B,SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT0_CS1_B,SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT0_CS2_B,SPORT0 Half SPORT 'B' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT0_CS3_B,SPORT0 Half SPORT 'B' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x80+0x20)++0x03
|
|
line.long 0x00 "SPORT0_ERR_B,SPORT0 Half SPORT 'B' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x80+0x24)++0x03
|
|
line.long 0x00 "SPORT0_MSTAT_B,SPORT0 Half SPORT 'B' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x80+0x28)++0x03
|
|
line.long 0x00 "SPORT0_CTL2_B,SPORT0 Half SPORT 'B' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x80+0x40)++0x03
|
|
line.long 0x00 "SPORT0_TXPRI_B,SPORT0 Half SPORT 'B' Tx Buffer (primary) Register"
|
|
hgroup.long (0x80+0x44)++0x03
|
|
hide.long 0x00 "SPORT0_RXPRI_B,SPORT0 Half SPORT 'B' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x80+0x48)++0x03
|
|
line.long 0x00 "SPORT0_TXSEC_B,SPORT0 Half SPORT 'B' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x80+0x4C)++0x03
|
|
hide.long 0x00 "SPORT0_RXSEC_B,SPORT0 Half SPORT 'B' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPORT1"
|
|
base ad:0x31002100
|
|
width 20.
|
|
if ((((per.l(ad:0x31002100+0x0))&0x6800)==0x800)&&(((per.l(ad:0x31002100+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002100+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x31002100+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002100+0x0))&0x4800)==0x00)&&(((per.l(ad:0x31002100+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002100+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT1_DIV_A,SPORT1 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT1_MCTL_A,SPORT1 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT1_CS0_A,SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT1_CS1_A,SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT1_CS2_A,SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT1_CS3_A,SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT1_ERR_A,SPORT1 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT1_MSTAT_A,SPORT1 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT1_CTL2_A,SPORT1 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT1_TXPRI_A,SPORT1 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT1_RXPRI_A,SPORT1 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT1_TXSEC_A,SPORT1 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT1_RXSEC_A,SPORT1 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
if ((((per.l(ad:0x31002100+0x80))&0x6800)==0x800)&&(((per.l(ad:0x31002100+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002100+0x80))&0x6800)==0x2800)&&(((per.l(ad:0x31002100+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002100+0x80))&0x4800)==0x00)&&(((per.l(ad:0x31002100+0x80+0x08))&0x01)==0x01))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002100+0x80))&0x204800)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "SPORT1_DIV_B,SPORT1 Half SPORT 'B' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT1_MCTL_B,SPORT1 Half SPORT 'B' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "SPORT1_CS0_B,SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT1_CS1_B,SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT1_CS2_B,SPORT1 Half SPORT 'B' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT1_CS3_B,SPORT1 Half SPORT 'B' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x80+0x20)++0x03
|
|
line.long 0x00 "SPORT1_ERR_B,SPORT1 Half SPORT 'B' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x80+0x24)++0x03
|
|
line.long 0x00 "SPORT1_MSTAT_B,SPORT1 Half SPORT 'B' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x80+0x28)++0x03
|
|
line.long 0x00 "SPORT1_CTL2_B,SPORT1 Half SPORT 'B' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x80+0x40)++0x03
|
|
line.long 0x00 "SPORT1_TXPRI_B,SPORT1 Half SPORT 'B' Tx Buffer (primary) Register"
|
|
hgroup.long (0x80+0x44)++0x03
|
|
hide.long 0x00 "SPORT1_RXPRI_B,SPORT1 Half SPORT 'B' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x80+0x48)++0x03
|
|
line.long 0x00 "SPORT1_TXSEC_B,SPORT1 Half SPORT 'B' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x80+0x4C)++0x03
|
|
hide.long 0x00 "SPORT1_RXSEC_B,SPORT1 Half SPORT 'B' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPORT2"
|
|
base ad:0x31002200
|
|
width 20.
|
|
if ((((per.l(ad:0x31002200+0x0))&0x6800)==0x800)&&(((per.l(ad:0x31002200+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT2_CTL_A,SPORT2 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002200+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x31002200+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT2_CTL_A,SPORT2 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002200+0x0))&0x4800)==0x00)&&(((per.l(ad:0x31002200+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT2_CTL_A,SPORT2 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002200+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT2_CTL_A,SPORT2 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT2_CTL_A,SPORT2 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT2_DIV_A,SPORT2 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT2_MCTL_A,SPORT2 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT2_CS0_A,SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT2_CS1_A,SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT2_CS2_A,SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT2_CS3_A,SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT2_ERR_A,SPORT2 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT2_MSTAT_A,SPORT2 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT2_CTL2_A,SPORT2 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT2_TXPRI_A,SPORT2 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT2_RXPRI_A,SPORT2 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT2_TXSEC_A,SPORT2 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT2_RXSEC_A,SPORT2 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
if ((((per.l(ad:0x31002200+0x80))&0x6800)==0x800)&&(((per.l(ad:0x31002200+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT2_CTL_B,SPORT2 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002200+0x80))&0x6800)==0x2800)&&(((per.l(ad:0x31002200+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT2_CTL_B,SPORT2 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002200+0x80))&0x4800)==0x00)&&(((per.l(ad:0x31002200+0x80+0x08))&0x01)==0x01))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT2_CTL_B,SPORT2 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002200+0x80))&0x204800)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT2_CTL_B,SPORT2 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT2_CTL_B,SPORT2 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "SPORT2_DIV_B,SPORT2 Half SPORT 'B' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT2_MCTL_B,SPORT2 Half SPORT 'B' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "SPORT2_CS0_B,SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT2_CS1_B,SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT2_CS2_B,SPORT2 Half SPORT 'B' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT2_CS3_B,SPORT2 Half SPORT 'B' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x80+0x20)++0x03
|
|
line.long 0x00 "SPORT2_ERR_B,SPORT2 Half SPORT 'B' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x80+0x24)++0x03
|
|
line.long 0x00 "SPORT2_MSTAT_B,SPORT2 Half SPORT 'B' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x80+0x28)++0x03
|
|
line.long 0x00 "SPORT2_CTL2_B,SPORT2 Half SPORT 'B' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x80+0x40)++0x03
|
|
line.long 0x00 "SPORT2_TXPRI_B,SPORT2 Half SPORT 'B' Tx Buffer (primary) Register"
|
|
hgroup.long (0x80+0x44)++0x03
|
|
hide.long 0x00 "SPORT2_RXPRI_B,SPORT2 Half SPORT 'B' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x80+0x48)++0x03
|
|
line.long 0x00 "SPORT2_TXSEC_B,SPORT2 Half SPORT 'B' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x80+0x4C)++0x03
|
|
hide.long 0x00 "SPORT2_RXSEC_B,SPORT2 Half SPORT 'B' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPORT3"
|
|
base ad:0x31002300
|
|
width 20.
|
|
if ((((per.l(ad:0x31002300+0x0))&0x6800)==0x800)&&(((per.l(ad:0x31002300+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT3_CTL_A,SPORT3 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002300+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x31002300+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT3_CTL_A,SPORT3 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002300+0x0))&0x4800)==0x00)&&(((per.l(ad:0x31002300+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT3_CTL_A,SPORT3 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002300+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT3_CTL_A,SPORT3 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT3_CTL_A,SPORT3 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT3_DIV_A,SPORT3 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT3_MCTL_A,SPORT3 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT3_CS0_A,SPORT3 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT3_CS1_A,SPORT3 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT3_CS2_A,SPORT3 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT3_CS3_A,SPORT3 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT3_ERR_A,SPORT3 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT3_MSTAT_A,SPORT3 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT3_CTL2_A,SPORT3 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT3_TXPRI_A,SPORT3 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT3_RXPRI_A,SPORT3 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT3_TXSEC_A,SPORT3 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT3_RXSEC_A,SPORT3 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
if ((((per.l(ad:0x31002300+0x80))&0x6800)==0x800)&&(((per.l(ad:0x31002300+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT3_CTL_B,SPORT3 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002300+0x80))&0x6800)==0x2800)&&(((per.l(ad:0x31002300+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT3_CTL_B,SPORT3 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x31002300+0x80))&0x4800)==0x00)&&(((per.l(ad:0x31002300+0x80+0x08))&0x01)==0x01))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT3_CTL_B,SPORT3 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x31002300+0x80))&0x204800)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT3_CTL_B,SPORT3 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT3_CTL_B,SPORT3 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "SPORT3_DIV_B,SPORT3 Half SPORT 'B' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT3_MCTL_B,SPORT3 Half SPORT 'B' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "SPORT3_CS0_B,SPORT3 Half SPORT 'B' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT3_CS1_B,SPORT3 Half SPORT 'B' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT3_CS2_B,SPORT3 Half SPORT 'B' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT3_CS3_B,SPORT3 Half SPORT 'B' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x80+0x20)++0x03
|
|
line.long 0x00 "SPORT3_ERR_B,SPORT3 Half SPORT 'B' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x80+0x24)++0x03
|
|
line.long 0x00 "SPORT3_MSTAT_B,SPORT3 Half SPORT 'B' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x80+0x28)++0x03
|
|
line.long 0x00 "SPORT3_CTL2_B,SPORT3 Half SPORT 'B' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x80+0x40)++0x03
|
|
line.long 0x00 "SPORT3_TXPRI_B,SPORT3 Half SPORT 'B' Tx Buffer (primary) Register"
|
|
hgroup.long (0x80+0x44)++0x03
|
|
hide.long 0x00 "SPORT3_RXPRI_B,SPORT3 Half SPORT 'B' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x80+0x48)++0x03
|
|
line.long 0x00 "SPORT3_TXSEC_B,SPORT3 Half SPORT 'B' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x80+0x4C)++0x03
|
|
hide.long 0x00 "SPORT3_RXSEC_B,SPORT3 Half SPORT 'B' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PCG (Precision Clock Generators)"
|
|
base ad:0x310C9300
|
|
width 12.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "PCG_CTLA0,PCG Precision Clock A Control 0"
|
|
bitfld.long 0x00 31. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FSEN ,Frame sync enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for frame sync high"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame sync divider"
|
|
line.long 0x04 "PCG_CTLA1,PCG Precision Clock A Control 1"
|
|
sif cpuis("ADSP-SC57?")
|
|
bitfld.long 0x04 31. " CLKSRC ,Clock source" "CLKIN0,PCG_EXT_DAI0"
|
|
bitfld.long 0x04 30. " FSSRC ,Frame sync source" "CLKIN0,PCG_EXT_DAI0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 31. " CLKSRC ,Clock source" "CLKIN,PCG_EXT_I"
|
|
bitfld.long 0x04 30. " FSSRC ,Frame sync source" "CLKIN,PCG_EXTX_I"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x04 20.--29. 1. " FSPHASELO ,Phase for frame sync low"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x08 "PCG_CTLB0,PCG Precision Clock B Control 0"
|
|
bitfld.long 0x08 31. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " FSEN ,Frame sync enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 20.--29. 1. " FSPHASEHI ,Phase for frame sync high"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " FSDIV ,Frame sync divider"
|
|
line.long 0x0C "PCG_CTLB1,PCG Precision Clock B Control 1"
|
|
sif cpuis("ADSP-SC57?")
|
|
bitfld.long 0x0C 31. " CLKSRC ,Clock source" "CLKIN0,PCG_EXT_DAI0"
|
|
bitfld.long 0x0C 30. " FSSRC ,Frame sync source" "CLKIN0,PCG_EXT_DAI0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 31. " CLKSRC ,Clock source" "CLKIN,PCG_EXT_I"
|
|
bitfld.long 0x0C 30. " FSSRC ,Frame sync source" "CLKIN,PCG_EXTX_I"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x0C 20.--29. 1. " FSPHASELO ,Phase for frame sync low"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " CLKDIV ,Clock divisor"
|
|
if ((((per.l(ad:0x310C9300))&0xFFFFF)==(0x00||0x01))&&(((per.l(ad:0x310C9300+0x08))&0xFFFFF)==(0x00||0x01)))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCG_PW1,PCG Precision Clock Pulse Width Control 1"
|
|
bitfld.long 0x00 17. " INVFSB ,Active low frame sync select for frame in bypass PCG B" "Low,High"
|
|
bitfld.long 0x00 16. " STROBEB ,One shot frame sync bypass mode PCG B" "Low,High"
|
|
bitfld.long 0x00 1. " INVFSA ,Active low frame sync select for frame sync in bypass mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STROBEA ,One shot frame sync PCG A" "Low,High"
|
|
elif ((((per.l(ad:0x310C9300))&0xFFFFF)==(0x00||0x01))&&(((per.l(ad:0x310C9300+0x08))&0xFFFFF)!=(0x00||0x01)))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCG_PW1,PCG Precision Clock Pulse Width Control 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSB ,Pulse width for frame sync PCG B"
|
|
bitfld.long 0x00 1. " INVFSA ,Active low frame sync select for frame sync in bypass mode" "Low,High"
|
|
bitfld.long 0x00 0. " STROBEA ,One shot frame sync PCG A" "Low,High"
|
|
elif ((((per.l(ad:0x310C9300))&0xFFFFF)!=(0x00||0x01))&&(((per.l(ad:0x310C9300+0x08))&0xFFFFF)==(0x00||0x01)))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCG_PW1,PCG Precision Clock Pulse Width Control 1"
|
|
bitfld.long 0x00 17. " INVFSB ,Active low frame sync select for frame in bypass PCG B" "Low,High"
|
|
bitfld.long 0x00 16. " STROBEB ,One shot frame sync bypass mode PCG B" "Low,High"
|
|
hexmask.long.word 0x00 0.--15. 1. " FSA ,Pulse width for frame sync PCG A"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCG_PW1,PCG Precision Clock Pulse Width Control 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSB ,Pulse width for frame sync PCG B"
|
|
hexmask.long.word 0x00 0.--15. 1. " FSA ,Pulse width for frame sync PCG A"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCG_SYNC1,PCG Precision Clock Frame Sync Synchronization 1"
|
|
sif cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 21. " FSB_CLKINSEL ,CLKIN source for FSB" "CLKIN0,CLKIN1"
|
|
bitfld.long 0x00 20. " CLKB_CLKINSEL ,CLKIN source for CLKB" "CLKIN0,CLKIN1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " FSBSRC ,Frame sync B source" "FSBSOURCE,PLL"
|
|
bitfld.long 0x00 18. " CLKBSRC ,Clock B source" "CLKBSOURCE,PLL"
|
|
bitfld.long 0x00 17. " CLKB ,Clock B enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FSB ,Frame sync B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSA_CLKINSEL ,CLKIN source for FSA" "CLKIN0,CLKIN1"
|
|
bitfld.long 0x00 4. " CLKA_CLKINSEL ,CLKIN source for CLKA" "CLKIN0,CLKIN1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FSASRC ,Frame sync source" "FSASOURCE,PLL"
|
|
bitfld.long 0x00 2. " CLKASRC ,Clock A source" "CLKASOURCE,PLL"
|
|
bitfld.long 0x00 1. " CLKA ,Clock A enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSA ,Frame sync A enable" "Disabled,Enabled"
|
|
sif !cpuis("ADSP-SC57?")
|
|
group.long 0x2000++0x0F
|
|
line.long 0x00 "PCG_CTLC0,PCG Precision Clock C Control 0"
|
|
bitfld.long 0x00 31. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FSEN ,Frame sync enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for frame sync high"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame sync divider"
|
|
line.long 0x04 "PCG_CTLC1,PCG Precision Clock C Control 1"
|
|
bitfld.long 0x04 31. " CLKSRC ,Clock source" "CLKIN,PCG_EXT_I"
|
|
bitfld.long 0x04 30. " FSSRC ,Frame sync source" "CLKIN,PCG_EXTX_I"
|
|
hexmask.long.word 0x04 20.--29. 1. " FSPHASELO ,Phase for frame sync low"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x08 "PCG_CTLD0,PCG Precision Clock D Control 0"
|
|
bitfld.long 0x08 31. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " FSEN ,Frame sync enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 20.--29. 1. " FSPHASEHI ,Phase for frame sync high"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " FSDIV ,Frame sync divider"
|
|
line.long 0x0C "PCG_CTLD1,PCG Precision Clock D Control 1"
|
|
bitfld.long 0x0C 31. " CLKSRC ,Clock source" "CLKIN,PCG_EXT_I"
|
|
bitfld.long 0x0C 30. " FSSRC ,Frame sync source" "CLKIN,PCG_EXTX_I"
|
|
hexmask.long.word 0x0C 20.--29. 1. " FSPHASELO ,Phase for frame sync low"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " CLKDIV ,Clock divisor"
|
|
if ((((per.l(ad:0x310C9300+0x2000))&0xFFFFF)==(0x00||0x01))&&(((per.l(ad:0x310C9300+0x2008))&0xFFFFF)==(0x00||0x01)))
|
|
group.long 0x2010++0x03
|
|
line.long 0x00 "PCG_PW2,PCG Precision Clock Pulse Width Control 2"
|
|
bitfld.long 0x00 17. " INVFSD ,Active low frame sync select for frame sync in bypass mode" "Low,High"
|
|
bitfld.long 0x00 16. " STROBED ,One shot frame sync PCG D" "Low,High"
|
|
bitfld.long 0x00 1. " INVFSC ,Active low frame sync select for frame sync in bypass mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STROBEC ,One shot frame sync PCG C" "Low,High"
|
|
elif ((((per.l(ad:0x310C9300+0x2000))&0xFFFFF)==(0x00||0x01))&&(((per.l(ad:0x310C9300+0x2008))&0xFFFFF)!=(0x00||0x01)))
|
|
group.long 0x2010++0x03
|
|
line.long 0x00 "PCG_PW2,PCG Precision Clock Pulse Width Control 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSD ,Pulse width for frame sync PCG D"
|
|
bitfld.long 0x00 1. " INVFSC ,Active low frame sync select for frame sync in bypass mode" "Low,High"
|
|
bitfld.long 0x00 0. " STROBEC ,One shot frame sync PCG C" "Low,High"
|
|
elif ((((per.l(ad:0x310C9300+0x2000))&0xFFFFF)!=(0x00||0x01))&&(((per.l(ad:0x310C9300+0x2008))&0xFFFFF)==(0x00||0x01)))
|
|
group.long 0x2010++0x03
|
|
line.long 0x00 "PCG_PW2,PCG Precision Clock Pulse Width Control 2"
|
|
bitfld.long 0x00 17. " INVFSD ,Active low frame sync select for frame sync in bypass mode" "Low,High"
|
|
bitfld.long 0x00 16. " STROBED ,One shot frame sync PCG D" "Low,High"
|
|
hexmask.long.word 0x00 0.--15. 1. " FSC ,Pulse width for frame sync PCG C"
|
|
else
|
|
group.long 0x2010++0x03
|
|
line.long 0x00 "PCG_PW2,PCG Precision Clock Pulse Width Control 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSD ,Pulse width for frame sync PCG D"
|
|
hexmask.long.word 0x00 0.--15. 1. " FSC ,Pulse width for frame sync PCG C"
|
|
endif
|
|
group.long 0x2014++0x03
|
|
line.long 0x00 "PCG_SYNC2,PCG Precision Clock Frame Sync Synchronization 2"
|
|
bitfld.long 0x00 19. " FSDSRC ,Frame sync D source" "FSDSOURCE,PLL"
|
|
bitfld.long 0x00 18. " CLKDSRC ,Clock D source" "CLKDSOURCE,PLL"
|
|
bitfld.long 0x00 17. " CLKD ,Clock D enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FSD ,Frame sync D enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSCSRC ,Frame sync source" "FSCSOURCE,PLL"
|
|
bitfld.long 0x00 2. " CLKCSRC ,Clock C source" "CLKCSOURCE,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKC ,Clock C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSC ,Frame sync C enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ASRC (Asynchronous Sample Rate Converter)"
|
|
base ad:0x310C9240
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "ASRC0_CTL01,ASRC0 Control Register For ASRC 0 And 1"
|
|
bitfld.long 0x00 31. " EN1 ,Enable SRC 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MPHASE1 ,Matched-phase mode 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " LENOUT1 ,Length output 1" "24 bits,20 bits,18 bits,16 bits"
|
|
bitfld.long 0x00 26.--27. " SMODEOUT1 ,Serial mode output 1" "Left-justified,I2S,TDM,Right-justified"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DITHER1 ,Dither enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SOFTMUTE1 ,Soft mute 1" "Unmute,Mute"
|
|
bitfld.long 0x00 22.--23. " DEEMPHASIS1 ,De-emphasize audio 1" "No de-emphasis,32 khz,44.1 khz,48 khz"
|
|
bitfld.long 0x00 21. " BYP1 ,Bypass 1" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMODEIN1 ,Serial mode input 1" "Left-justified,I2S,TDM,24-bit right-justified,20-bit right-justified,18-bit right-justified,16-bit right-justified,?..."
|
|
bitfld.long 0x00 17. " AUTOMUTE1 ,Auto hard mute 1" "Unmute,Mute"
|
|
bitfld.long 0x00 16. " HARDMUTE1 ,Hard mute 1" "Unmute,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN0 ,Enable SRC 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MPHASE0 ,Matched-phase mode 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " LENOUT0 ,Length output 0" "24 bits,20 bits,18 bits,16 bits"
|
|
bitfld.long 0x00 10.--11. " SMODEOUT0 ,Serial mode output 0" "Left-justified,I2S,TDM,Right-justified"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DITHER0 ,Dither enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFTMUTE0 ,Soft mute 0" "Unmute,Mute"
|
|
bitfld.long 0x00 6.--7. " DEEMPHASIS0 ,De-emphasize audio 0" "No de-emphasis,32 khz,44.1 khz,48 khz"
|
|
bitfld.long 0x00 5. " BYP0 ,Bypass 0" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " SMODEIN0 ,Serial mode input 0" "Left-justified,I2S,TDM,24-bit right-justified,20-bit right-justified,18-bit right-justified,16-bit right-justified,?..."
|
|
bitfld.long 0x00 1. " AUTOMUTE0 ,Auto hard mute 0" "Unmute,Mute"
|
|
bitfld.long 0x00 0. " HARDMUTE0 ,Hard mute 0" "Unmute,Mute"
|
|
line.long 0x04 "ASRC0_CTL23,ASRC0 Control Register For ASRC 2 And 3"
|
|
bitfld.long 0x04 31. " EN3 ,Enable SRC 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " MPHASE3 ,Matched-phase mode 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 28.--29. " LENOUT3 ,Length output 3" "24 bits,20 bits,18 bits,16 bits"
|
|
bitfld.long 0x04 26.--27. " SMODEOUT3 ,Serial mode output 3" "Left-justified,I2S,TDM,Right-justified"
|
|
textline " "
|
|
bitfld.long 0x04 25. " DITHER3 ,Dither enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " SOFTMUTE3 ,Soft mute 3" "Unmute,Mute"
|
|
bitfld.long 0x04 22.--23. " DEEMPHASIS3 ,De-emphasize audio 3" "No de-emphasis,32 khz,44.1 khz,48 khz"
|
|
bitfld.long 0x04 21. " BYP3 ,Bypass 3" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " SMODEIN3 ,Serial mode input 3" "Left-justified,I2S,TDM,24-bit right-justified,20-bit right-justified,18-bit right-justified,16-bit right-justified,?..."
|
|
bitfld.long 0x04 17. " AUTOMUTE3 ,Auto hard mute 3" "Unmute,Mute"
|
|
bitfld.long 0x04 16. " HARDMUTE3 ,Hard mute 3" "Unmute,Mute"
|
|
textline " "
|
|
bitfld.long 0x04 15. " EN2 ,Enable SRC 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " MPHASE2 ,Matched-phase mode 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " LENOUT2 ,Length output 2" "24 bits,20 bits,18 bits,16 bits"
|
|
bitfld.long 0x04 10.--11. " SMODEOUT2 ,Serial mode output 2" "Left-justified,I2S,TDM,Right-justified"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DITHER2 ,Dither enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " SOFTMUTE2 ,Soft mute 2" "Unmute,Mute"
|
|
bitfld.long 0x04 6.--7. " DEEMPHASIS2 ,De-emphasize audio 2" "No de-emphasis,32 khz,44.1 khz,48 khz"
|
|
bitfld.long 0x04 5. " BYP2 ,Bypass 2" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 2.--4. " SMODEIN2 ,Serial mode input 2" "Left-justified,I2S,TDM,24-bit right-justified,20-bit right-justified,18-bit right-justified,16-bit right-justified,?..."
|
|
bitfld.long 0x04 1. " AUTOMUTE2 ,Auto hard mute 2" "Unmute,Mute"
|
|
bitfld.long 0x04 0. " HARDMUTE2 ,Hard mute 2" "Unmute,Mute"
|
|
line.long 0x08 "ASRC0_MUTE,ASRC0 Mute Register"
|
|
bitfld.long 0x08 3. " MUTE3 ,Mute ASRC3" "0,1"
|
|
bitfld.long 0x08 2. " MUTE2 ,Mute ASRC2" "0,1"
|
|
bitfld.long 0x08 1. " MUTE1 ,Mute ASRC1" "0,1"
|
|
bitfld.long 0x08 0. " MUTE0 ,Mute ASRC0" "0,1"
|
|
textline " "
|
|
if (((per.l(ad:0x310C9240+0x20))&0x80008000)==0x00)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ASRC0_RAT01,ASRC0 Ratio Register For ASRC 0 And 1"
|
|
bitfld.long 0x00 31. " MUTEOUT1 ,Mute status for ASRC1" "Not completed,Completed"
|
|
hexmask.long.word 0x00 16.--30. 1. " RATIO1 ,Sampling ratio of frame syncs for ASRC1"
|
|
bitfld.long 0x00 15. " MUTEOUT0 ,Mute status for ASRC0" "Not completed,Completed"
|
|
hexmask.long.word 0x00 0.--14. 1. " RATIO0 ,Sampling ratio of frame syncs for ASRC0"
|
|
elif (((per.l(ad:0x310C9240+0x20))&0x80008000)==0x8000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ASRC0_RAT01,ASRC0 Ratio Register For ASRC 0 And 1"
|
|
bitfld.long 0x00 31. " MUTEOUT1 ,Mute status for ASRC1" "Not completed,Completed"
|
|
hexmask.long.word 0x00 16.--30. 1. " RATIO1 ,Sampling ratio of frame syncs for ASRC1"
|
|
bitfld.long 0x00 15. " MUTEOUT0 ,Mute status for ASRC0" "Not completed,Completed"
|
|
elif (((per.l(ad:0x310C9240+0x20))&0x80008000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ASRC0_RAT01,ASRC0 Ratio Register For ASRC 0 And 1"
|
|
bitfld.long 0x00 31. " MUTEOUT1 ,Mute status for ASRC1" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " MUTEOUT0 ,Mute status for ASRC0" "Not completed,Completed"
|
|
hexmask.long.word 0x00 0.--14. 1. " RATIO0 ,Sampling ratio of frame syncs for ASRC0"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ASRC0_RAT01,ASRC0 Ratio Register For ASRC 0 And 1"
|
|
bitfld.long 0x00 31. " MUTEOUT1 ,Mute status for ASRC1" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " MUTEOUT0 ,Mute status for ASRC0" "Not completed,Completed"
|
|
endif
|
|
if (((per.l(ad:0x310C9240+0x24))&0x80008000)==0x00)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ASRC0_RAT23,ASRC0 Ratio Register For ASRC 2 And 3"
|
|
bitfld.long 0x00 31. " MUTEOUT3 ,Mute status for ASRC3" "Not completed,Completed"
|
|
hexmask.long.word 0x00 16.--30. 1. " RATIO3 ,Sampling ratio of frame syncs for ASRC3"
|
|
bitfld.long 0x00 15. " MUTEOUT2 ,Mute status for ASRC2" "Not completed,Completed"
|
|
hexmask.long.word 0x00 0.--14. 1. " RATIO2 ,Sampling ratio of frame syncs for ASRC2"
|
|
elif (((per.l(ad:0x310C9240+0x24))&0x80008000)==0x8000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ASRC0_RAT23,ASRC0 Ratio Register For ASRC 2 And 3"
|
|
bitfld.long 0x00 31. " MUTEOUT3 ,Mute status for ASRC3" "Not completed,Completed"
|
|
hexmask.long.word 0x00 16.--30. 1. " RATIO3 ,Sampling ratio of frame syncs for ASRC3"
|
|
bitfld.long 0x00 15. " MUTEOUT2 ,Mute status for ASRC2" "Not completed,Completed"
|
|
elif (((per.l(ad:0x310C9240+0x24))&0x80008000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ASRC0_RAT23,ASRC0 Ratio Register For ASRC 2 And 3"
|
|
bitfld.long 0x00 31. " MUTEOUT3 ,Mute status for ASRC3" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " MUTEOUT2 ,Mute status for ASRC2" "Not completed,Completed"
|
|
hexmask.long.word 0x00 0.--14. 1. " RATIO2 ,Sampling ratio of frame syncs for ASRC2"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ASRC0_RAT23,ASRC0 Ratio Register For ASRC 2 And 3"
|
|
bitfld.long 0x00 31. " MUTEOUT3 ,Mute status for ASRC3" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " MUTEOUT2 ,Mute status for ASRC2" "Not completed,Completed"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "S/PDIF (Sony/Philips Digital Interface)"
|
|
base ad:0x310C9280
|
|
width 20.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPDIF0_RX_CTL,SPDIF0 Receive Control"
|
|
bitfld.long 0x00 4. " RST ,Reset SPDIF receiver" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RSTRTAUDIO ,Restart audio" "Manually,Automatically"
|
|
bitfld.long 0x00 2. " FASTLOCK ,Fast lock select" "Normal,Fast"
|
|
bitfld.long 0x00 1. " STRENGTH ,FS strength control" "Strong mode,Weak mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,SPDIF receiver enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPDIF0_RX_STAT,SPDIF0 Receive Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " COMPMODE ,Compression mode"
|
|
bitfld.long 0x00 12.--15. " WLCHANB ,Word length channel B" ",,16,,18,22,,,19,23,20,24,17,21,?..."
|
|
bitfld.long 0x00 8.--11. " WLCHANA ,Word length channel A" ",,16,,18,22,,,19,23,20,24,17,21,?..."
|
|
bitfld.long 0x00 4. " LOCKLOSS ,Loss of lock (sticky)" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LOCK ,Lock receiver" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " VALID ,Validity bit" "Linear,Non-linear"
|
|
bitfld.long 0x00 1. " COMPTYPE ,Compression type" "AC3,DTS"
|
|
bitfld.long 0x00 0. " AUDIOTYPE ,Audio type" "PCM,Compressed"
|
|
textline " "
|
|
rgroup.long 0x28++0x0F
|
|
line.long 0x00 "SPDIF0_RX_STAT0_A,SPDIF0 Receive Status A0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,CS byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,CS byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,CS byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,CS byte 0"
|
|
line.long 0x04 "SPDIF0_RX_STAT0_B,SPDIF0 Receive Status B0 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BYTE3 ,CS byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " BYTE2 ,CS byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BYTE1 ,CS byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BYTE0 ,CS byte 0"
|
|
line.long 0x08 "SPDIF0_RX_STAT1_A,SPDIF0 Receive Status A1 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BYTE4 ,CS byte 4"
|
|
line.long 0x0C "SPDIF0_RX_STAT1_B,SPDIF0 Receive Status B1 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BYTE4 ,CS byte 4"
|
|
textline " "
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPDIF0_TX_CTL,SPDIF0 Transmit Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE0B ,Channel status byte for subframe B"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE0A ,Channel status byte for subframe A"
|
|
bitfld.long 0x00 15. " EXTSYNC ,External sync enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " USRPEND ,User bits pending" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " BLKSTART ,Block start" "Not blocked,Blocked"
|
|
bitfld.long 0x00 11. " VALIDR ,Validity bit B" "Manually,Automatically"
|
|
bitfld.long 0x00 10. " VALIDL ,Validity bit A" "Manually,Automatically"
|
|
bitfld.long 0x00 9. " AUTO ,Automatically generate block start" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " SMODEIN ,Serial data input format" "Left-justified,I2S,,,Right-justified - 24 bits,Right-justified - 20 bits,Right-justified - 18 bits,Right-justified - 16 bits"
|
|
bitfld.long 0x00 5. " SCDFLR ,Select L/R Single-channel" "Left,Right"
|
|
bitfld.long 0x00 4. " SCDF ,Single-channel" "Two-channel,SCDF"
|
|
bitfld.long 0x00 2.--3. " FREQ ,Frequency multiplier" "256,384,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPDIF0_TX_STAT_A0,SPDIF0 Transmit Status A0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE4 ,Byte 4 sub frame A"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Byte 3 sub frame A"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE2 ,Byte 2 sub frame A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE1 ,Byte 1 sub frame A"
|
|
group.long 0xD0++0x13
|
|
line.long 0x00 "SPDIF0_TX_STAT_A1,SPDIF0 Transmit Status A1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE8 ,Byte 8 sub frame A"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE7 ,Byte 7 sub frame A"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE6 ,Byte 6 sub frame A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE5 ,Byte 5 sub frame A"
|
|
line.long 0x04 "SPDIF0_TX_STAT_A2,SPDIF0 Transmit Status A2 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BYTE12 ,Byte 12 sub frame A"
|
|
hexmask.long.byte 0x04 16.--23. 1. " BYTE11 ,Byte 11 sub frame A"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BYTE10 ,Byte 10 sub frame A"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BYTE9 ,Byte 9 sub frame A"
|
|
line.long 0x08 "SPDIF0_TX_STAT_A3,SPDIF0 Transmit Status A3 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " BYTE16 ,Byte 16 sub frame A"
|
|
hexmask.long.byte 0x08 16.--23. 1. " BYTE15 ,Byte 15 sub frame A"
|
|
hexmask.long.byte 0x08 8.--15. 1. " BYTE14 ,Byte 14 sub frame A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BYTE13 ,Byte 13 sub frame A"
|
|
line.long 0x0C "SPDIF0_TX_STAT_A4,SPDIF0 Transmit Status A4 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BYTE20 ,Byte 20 sub frame A"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " BYTE19 ,Byte 19 sub frame A"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " BYTE18 ,Byte 18 sub frame A"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BYTE17 ,Byte 17 sub frame A"
|
|
line.long 0x10 "SPDIF0_TX_STAT_A5,SPDIF0 Transmit Status A5 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " BYTE23 ,Byte 23 sub frame A"
|
|
hexmask.long.byte 0x10 8.--15. 1. " BYTE22 ,Byte 22 sub frame A"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BYTE21 ,Byte 21 sub frame A"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPDIF0_TX_STAT_B0,SPDIF0 Transmit Status B0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE4 ,Byte 4 sub frame B"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Byte 3 sub frame B"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE2 ,Byte 2 sub frame B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE1 ,Byte 1 sub frame B"
|
|
group.long 0xE8++0x13
|
|
line.long 0x00 "SPDIF0_TX_STAT_B1,SPDIF0 Transmit Status B1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE8 ,Byte 8 sub frame B"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE7 ,Byte 7 sub frame B"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE6 ,Byte 6 sub frame B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE5 ,Byte 5 sub frame B"
|
|
line.long 0x04 "SPDIF0_TX_STAT_B2,SPDIF0 Transmit Status B2 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BYTE12 ,Byte 12 sub frame B"
|
|
hexmask.long.byte 0x04 16.--23. 1. " BYTE11 ,Byte 11 sub frame B"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BYTE10 ,Byte 10 sub frame B"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BYTE9 ,Byte 9 sub frame B"
|
|
line.long 0x08 "SPDIF0_TX_STAT_B3,SPDIF0 Transmit Status B3 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " BYTE16 ,Byte 16 sub frame B"
|
|
hexmask.long.byte 0x08 16.--23. 1. " BYTE15 ,Byte 15 sub frame B"
|
|
hexmask.long.byte 0x08 8.--15. 1. " BYTE14 ,Byte 14 sub frame B"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BYTE13 ,Byte 13 sub frame B"
|
|
line.long 0x0C "SPDIF0_TX_STAT_B4,SPDIF0 Transmit Status B4 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BYTE20 ,Byte 20 sub frame B"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " BYTE19 ,Byte 19 sub frame B"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " BYTE18 ,Byte 18 sub frame B"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BYTE17 ,Byte 17 sub frame B"
|
|
line.long 0x10 "SPDIF0_TX_STAT_B5,SPDIF0 Transmit Status B5 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " BYTE23 ,Byte 23 sub frame B"
|
|
hexmask.long.byte 0x10 8.--15. 1. " BYTE22 ,Byte 22 sub frame B"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BYTE21 ,Byte 21 sub frame B"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "SPDIF0_TX_UBUFF_A0,SPDIF0 Transmit User Buffer A0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Byte 3 of subframe A user bit buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Byte 2 sub frame A"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Byte 1 sub frame A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Byte 0 sub frame A"
|
|
line.long 0x04 "SPDIF0_TX_UBUFF_A1,SPDIF0 Transmit User Buffer A1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BYTE7 ,Byte 7 sub frame A"
|
|
hexmask.long.byte 0x04 16.--23. 1. " BYTE6 ,Byte 6 sub frame A"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BYTE5 ,Byte 5 sub frame A"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BYTE4 ,Byte 4 sub frame A"
|
|
line.long 0x08 "SPDIF0_TX_UBUFF_A2,SPDIF0 Transmit User Buffer A2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " BYTE11 ,Byte 11 sub frame A"
|
|
hexmask.long.byte 0x08 16.--23. 1. " BYTE10 ,Byte 10 sub frame A"
|
|
hexmask.long.byte 0x08 8.--15. 1. " BYTE9 ,Byte 9 sub frame A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BYTE8 ,Byte 8 sub frame A"
|
|
line.long 0x0C "SPDIF0_TX_UBUFF_A3,SPDIF0 Transmit User Buffer A3 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BYTE15 ,Byte 15 sub frame A"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " BYTE14 ,Byte 14 sub frame A"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " BYTE13 ,Byte 13 sub frame A"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BYTE12 ,Byte 12 sub frame A"
|
|
line.long 0x10 "SPDIF0_TX_UBUFF_A4,SPDIF0 Transmit User Buffer A4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " BYTE19 ,Byte 19 sub frame A"
|
|
hexmask.long.byte 0x10 16.--23. 1. " BYTE18 ,Byte 18 sub frame A"
|
|
hexmask.long.byte 0x10 8.--15. 1. " BYTE17 ,Byte 17 sub frame A"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BYTE16 ,Byte 16 sub frame A"
|
|
line.long 0x14 "SPDIF0_TX_UBUFF_A5,SPDIF0 Transmit User Buffer A5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " BYTE23 ,Byte 23 sub frame A"
|
|
hexmask.long.byte 0x14 16.--23. 1. " BYTE22 ,Byte 22 sub frame A"
|
|
hexmask.long.byte 0x14 8.--15. 1. " BYTE21 ,Byte 21 sub frame A"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BYTE20 ,Byte 20 sub frame A"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "SPDIF0_TX_UBUFF_B0,SPDIF0 Transmit User Buffer B0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Byte 3 sub frame B"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Byte 2 sub frame B"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Byte 1 sub frame B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Byte 0 sub frame B"
|
|
line.long 0x04 "SPDIF0_TX_UBUFF_B1,SPDIF0 Transmit User Buffer B1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BYTE7 ,Byte 7 sub frame B"
|
|
hexmask.long.byte 0x04 16.--23. 1. " BYTE6 ,Byte 6 sub frame B"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BYTE5 ,Byte 5 sub frame B"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BYTE4 ,Byte 4 sub frame B"
|
|
line.long 0x08 "SPDIF0_TX_UBUFF_B2,SPDIF0 Transmit User Buffer B2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " BYTE11 ,Byte 11 sub frame B"
|
|
hexmask.long.byte 0x08 16.--23. 1. " BYTE10 ,Byte 10 sub frame B"
|
|
hexmask.long.byte 0x08 8.--15. 1. " BYTE9 ,Byte 9 sub frame B"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BYTE8 ,Byte 8 sub frame B"
|
|
line.long 0x0C "SPDIF0_TX_UBUFF_B3,SPDIF0 Transmit User Buffer B3 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BYTE15 ,Byte 15 sub frame B"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " BYTE14 ,Byte 14 sub frame B"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " BYTE13 ,Byte 13 sub frame B"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BYTE12 ,Byte 12 sub frame B"
|
|
line.long 0x10 "SPDIF0_TX_UBUFF_B4,SPDIF0 Transmit User Buffer B4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " BYTE19 ,Byte 19 sub frame B"
|
|
hexmask.long.byte 0x10 16.--23. 1. " BYTE18 ,Byte 18 sub frame B"
|
|
hexmask.long.byte 0x10 8.--15. 1. " BYTE17 ,Byte 17 sub frame B"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BYTE16 ,Byte 16 sub frame B"
|
|
line.long 0x14 "SPDIF0_TX_UBUFF_B5,SPDIF0 Transmit User Buffer B5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " BYTE23 ,Byte 23 sub frame B"
|
|
hexmask.long.byte 0x14 16.--23. 1. " BYTE22 ,Byte 22 sub frame B"
|
|
hexmask.long.byte 0x14 8.--15. 1. " BYTE21 ,Byte 21 sub frame B"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BYTE20 ,Byte 20 sub frame B"
|
|
textline " "
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "SPDIF0_TX_USRUPDT,SPDIF0 User Bit Update Register"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
tree "DMA0"
|
|
base ad:0x31022000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA0_CFG,DMA0 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA0_CFG,DMA0 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA0_CFG,DMA0 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA0_CFG,DMA0 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA0_CFG,DMA0 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA0_CFG,DMA0 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_PRV,DMA0 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA0_ADDR_CUR,DMA0 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA0_ADDR_CUR,DMA0 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA0_STAT,DMA0 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA0_XCNT_CUR,DMA0 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA0_YCNT_CUR,DMA0 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA0_XCNT_CUR,DMA0 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA0_YCNT_CUR,DMA0 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA0_BWLCNT,DMA0 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA0_BWLCNT_CUR,DMA0 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA0_BWMCNT,DMA0 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA0_BWMCNT_CUR,DMA0 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA1"
|
|
base ad:0x31022080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA1_CFG,DMA1 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA1_CFG,DMA1 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA1_CFG,DMA1 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA1_CFG,DMA1 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA1_CFG,DMA1 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA1_CFG,DMA1 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_PRV,DMA1 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA1_ADDR_CUR,DMA1 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA1_ADDR_CUR,DMA1 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA1_STAT,DMA1 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA1_XCNT_CUR,DMA1 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA1_YCNT_CUR,DMA1 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA1_XCNT_CUR,DMA1 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA1_YCNT_CUR,DMA1 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA1_BWLCNT,DMA1 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA1_BWLCNT_CUR,DMA1 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA1_BWMCNT,DMA1 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA1_BWMCNT_CUR,DMA1 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0x31022100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA2_CFG,DMA2 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA2_CFG,DMA2 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA2_CFG,DMA2 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA2_CFG,DMA2 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA2_CFG,DMA2 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA2_CFG,DMA2 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_PRV,DMA2 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA2_ADDR_CUR,DMA2 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA2_ADDR_CUR,DMA2 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA2_STAT,DMA2 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA2_XCNT_CUR,DMA2 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA2_YCNT_CUR,DMA2 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA2_XCNT_CUR,DMA2 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA2_YCNT_CUR,DMA2 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA2_BWLCNT,DMA2 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA2_BWLCNT_CUR,DMA2 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA2_BWMCNT,DMA2 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA2_BWMCNT_CUR,DMA2 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA3"
|
|
base ad:0x31022180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA3_CFG,DMA3 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA3_CFG,DMA3 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA3_CFG,DMA3 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA3_CFG,DMA3 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA3_CFG,DMA3 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA3_CFG,DMA3 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_PRV,DMA3 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA3_ADDR_CUR,DMA3 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA3_ADDR_CUR,DMA3 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA3_STAT,DMA3 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA3_XCNT_CUR,DMA3 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA3_YCNT_CUR,DMA3 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA3_XCNT_CUR,DMA3 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA3_YCNT_CUR,DMA3 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA3_BWLCNT,DMA3 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA3_BWLCNT_CUR,DMA3 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA3_BWMCNT,DMA3 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA3_BWMCNT_CUR,DMA3 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA4"
|
|
base ad:0x31022200
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022200+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022200+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA4_CFG,DMA4 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA4_CFG,DMA4 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022200+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA4_CFG,DMA4 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA4_CFG,DMA4 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022200+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA4_CFG,DMA4 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA4_CFG,DMA4 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_PRV,DMA4 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022200+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA4_ADDR_CUR,DMA4 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA4_ADDR_CUR,DMA4 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA4_STAT,DMA4 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA4_XCNT_CUR,DMA4 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA4_YCNT_CUR,DMA4 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA4_XCNT_CUR,DMA4 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA4_YCNT_CUR,DMA4 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA4_BWLCNT,DMA4 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA4_BWLCNT_CUR,DMA4 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA4_BWMCNT,DMA4 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA4_BWMCNT_CUR,DMA4 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA5"
|
|
base ad:0x31022280
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022280+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022280+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA5_CFG,DMA5 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA5_CFG,DMA5 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022280+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA5_CFG,DMA5 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA5_CFG,DMA5 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022280+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA5_CFG,DMA5 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA5_CFG,DMA5 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_PRV,DMA5 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022280+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA5_ADDR_CUR,DMA5 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA5_ADDR_CUR,DMA5 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA5_STAT,DMA5 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA5_XCNT_CUR,DMA5 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA5_YCNT_CUR,DMA5 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA5_XCNT_CUR,DMA5 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA5_YCNT_CUR,DMA5 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA5_BWLCNT,DMA5 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA5_BWLCNT_CUR,DMA5 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA5_BWMCNT,DMA5 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA5_BWMCNT_CUR,DMA5 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA6"
|
|
base ad:0x31022300
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022300+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022300+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022300+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA6_CFG,DMA6 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA6_CFG,DMA6 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022300+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022300+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA6_CFG,DMA6 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA6_CFG,DMA6 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022300+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022300+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA6_CFG,DMA6 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA6_CFG,DMA6 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022300+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_PRV,DMA6 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022300+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA6_ADDR_CUR,DMA6 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA6_ADDR_CUR,DMA6 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA6_STAT,DMA6 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA6_XCNT_CUR,DMA6 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA6_YCNT_CUR,DMA6 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA6_XCNT_CUR,DMA6 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA6_YCNT_CUR,DMA6 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA6_BWLCNT,DMA6 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA6_BWLCNT_CUR,DMA6 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA6_BWMCNT,DMA6 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA6_BWMCNT_CUR,DMA6 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA7"
|
|
base ad:0x31022380
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31022380+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31022380+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022380+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA7_CFG,DMA7 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA7_CFG,DMA7 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31022380+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31022380+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA7_CFG,DMA7 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA7_CFG,DMA7 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022380+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31022380+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA7_CFG,DMA7 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA7_CFG,DMA7 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31022380+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_PRV,DMA7 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31022380+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA7_ADDR_CUR,DMA7 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA7_ADDR_CUR,DMA7 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA7_STAT,DMA7 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31022380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA7_XCNT_CUR,DMA7 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA7_YCNT_CUR,DMA7 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA7_XCNT_CUR,DMA7 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA7_YCNT_CUR,DMA7 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA7_BWLCNT,DMA7 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA7_BWLCNT_CUR,DMA7 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA7_BWMCNT,DMA7 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA7_BWMCNT_CUR,DMA7 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA8"
|
|
base ad:0x310A7000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x310A7000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x310A7000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA8_CFG,DMA8 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA8_CFG,DMA8 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x310A7000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA8_CFG,DMA8 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA8_CFG,DMA8 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310A7000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA8_CFG,DMA8 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA8_CFG,DMA8 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_PRV,DMA8 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA8_ADDR_CUR,DMA8 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA8_ADDR_CUR,DMA8 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA8_STAT,DMA8 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x310A7000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA8_XCNT_CUR,DMA8 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA8_YCNT_CUR,DMA8 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA8_XCNT_CUR,DMA8 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA8_YCNT_CUR,DMA8 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA8_BWLCNT,DMA8 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA8_BWLCNT_CUR,DMA8 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA8_BWMCNT,DMA8 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA8_BWMCNT_CUR,DMA8 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA8_BWLCNT,DMA8 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA8_BWLCNT_CUR,DMA8 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA8_BWMCNT,DMA8 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA8_BWMCNT_CUR,DMA8 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA9"
|
|
base ad:0x310A7080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x310A7080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x310A7080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA9_CFG,DMA9 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA9_CFG,DMA9 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x310A7080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA9_CFG,DMA9 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA9_CFG,DMA9 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310A7080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA9_CFG,DMA9 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA9_CFG,DMA9 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_PRV,DMA9 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA9_ADDR_CUR,DMA9 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA9_ADDR_CUR,DMA9 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA9_STAT,DMA9 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x310A7080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA9_XCNT_CUR,DMA9 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA9_YCNT_CUR,DMA9 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA9_XCNT_CUR,DMA9 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA9_YCNT_CUR,DMA9 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA9_BWLCNT,DMA9 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA9_BWLCNT_CUR,DMA9 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA9_BWMCNT,DMA9 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA9_BWMCNT_CUR,DMA9 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA9_BWLCNT,DMA9 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA9_BWLCNT_CUR,DMA9 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA9_BWMCNT,DMA9 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA9_BWMCNT_CUR,DMA9 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA18"
|
|
base ad:0x310A7100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x310A7100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x310A7100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA18_CFG,DMA18 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA18_CFG,DMA18 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x310A7100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA18_CFG,DMA18 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA18_CFG,DMA18 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310A7100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA18_CFG,DMA18 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA18_CFG,DMA18 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_PRV,DMA18 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA18_ADDR_CUR,DMA18 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA18_ADDR_CUR,DMA18 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA18_STAT,DMA18 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x310A7100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA18_XCNT_CUR,DMA18 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA18_YCNT_CUR,DMA18 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA18_XCNT_CUR,DMA18 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA18_YCNT_CUR,DMA18 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA18_BWLCNT,DMA18 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA18_BWLCNT_CUR,DMA18 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA18_BWMCNT,DMA18 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA18_BWMCNT_CUR,DMA18 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA18_BWLCNT,DMA18 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA18_BWLCNT_CUR,DMA18 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA18_BWMCNT,DMA18 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA18_BWMCNT_CUR,DMA18 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA19"
|
|
base ad:0x310A7180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x310A7180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x310A7180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA19_CFG,DMA19 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA19_CFG,DMA19 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x310A7180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x310A7180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA19_CFG,DMA19 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA19_CFG,DMA19 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310A7180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA19_CFG,DMA19 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA19_CFG,DMA19 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_PRV,DMA19 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA19_ADDR_CUR,DMA19 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA19_ADDR_CUR,DMA19 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA19_STAT,DMA19 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x310A7180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA19_XCNT_CUR,DMA19 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA19_YCNT_CUR,DMA19 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA19_XCNT_CUR,DMA19 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA19_YCNT_CUR,DMA19 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA19_BWLCNT,DMA19 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA19_BWLCNT_CUR,DMA19 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA19_BWMCNT,DMA19 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA19_BWMCNT_CUR,DMA19 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA19_BWLCNT,DMA19 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA19_BWLCNT_CUR,DMA19 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA19_BWMCNT,DMA19 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA19_BWMCNT_CUR,DMA19 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA20"
|
|
base ad:0x31026080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31026080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31026080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA20_CFG,DMA20 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA20_CFG,DMA20 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31026080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA20_CFG,DMA20 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA20_CFG,DMA20 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31026080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA20_CFG,DMA20 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA20_CFG,DMA20 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_PRV,DMA20 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31026080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA20_ADDR_CUR,DMA20 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA20_ADDR_CUR,DMA20 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA20_STAT,DMA20 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31026080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA20_XCNT_CUR,DMA20 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA20_YCNT_CUR,DMA20 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA20_XCNT_CUR,DMA20 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA20_YCNT_CUR,DMA20 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA20_BWLCNT,DMA20 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA20_BWLCNT_CUR,DMA20 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA20_BWMCNT,DMA20 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA20_BWMCNT_CUR,DMA20 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA21"
|
|
base ad:0x31026000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31026000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31026000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA21_DSCPTR_NXT,DMA21 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA21_ADDRSTART,DMA21 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA21_CFG,DMA21 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA21_XCNT,DMA21 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA21_XMOD,DMA21 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA21_DSCPTR_CUR,DMA21 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA21_DSCPTR_NXT,DMA21 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA21_ADDRSTART,DMA21 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA21_CFG,DMA21 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA21_XCNT,DMA21 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA21_XMOD,DMA21 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA21_DSCPTR_CUR,DMA21 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA21_DSCPTR_NXT,DMA21 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA21_ADDRSTART,DMA21 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31026000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA21_CFG,DMA21 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA21_CFG,DMA21 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA21_XCNT,DMA21 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA21_XMOD,DMA21 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA21_DSCPTR_CUR,DMA21 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31026000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA21_DSCPTR_NXT,DMA21 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA21_ADDRSTART,DMA21 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA21_CFG,DMA21 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA21_XCNT,DMA21 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA21_XMOD,DMA21 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA21_DSCPTR_CUR,DMA21 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA21_DSCPTR_NXT,DMA21 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA21_ADDRSTART,DMA21 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA21_CFG,DMA21 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA21_XCNT,DMA21 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA21_XMOD,DMA21 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA21_DSCPTR_CUR,DMA21 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA21_DSCPTR_PRV,DMA21 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31026000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA21_ADDR_CUR,DMA21 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA21_ADDR_CUR,DMA21 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA21_STAT,DMA21 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31026000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA21_XCNT_CUR,DMA21 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA21_YCNT_CUR,DMA21 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA21_XCNT_CUR,DMA21 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA21_YCNT_CUR,DMA21 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA21_BWLCNT,DMA21 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA21_BWLCNT_CUR,DMA21 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA21_BWMCNT,DMA21 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA21_BWMCNT_CUR,DMA21 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA22"
|
|
base ad:0x3102B000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA22_DSCPTR_NXT,DMA22 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA22_ADDRSTART,DMA22 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA22_CFG,DMA22 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA22_XCNT,DMA22 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA22_XMOD,DMA22 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA22_DSCPTR_CUR,DMA22 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA22_DSCPTR_NXT,DMA22 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA22_ADDRSTART,DMA22 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA22_CFG,DMA22 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA22_XCNT,DMA22 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA22_XMOD,DMA22 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA22_DSCPTR_CUR,DMA22 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA22_DSCPTR_NXT,DMA22 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA22_ADDRSTART,DMA22 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA22_CFG,DMA22 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA22_CFG,DMA22 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA22_XCNT,DMA22 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA22_XMOD,DMA22 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA22_DSCPTR_CUR,DMA22 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA22_DSCPTR_NXT,DMA22 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA22_ADDRSTART,DMA22 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA22_CFG,DMA22 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA22_XCNT,DMA22 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA22_XMOD,DMA22 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA22_DSCPTR_CUR,DMA22 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA22_DSCPTR_NXT,DMA22 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA22_ADDRSTART,DMA22 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA22_CFG,DMA22 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA22_XCNT,DMA22 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA22_XMOD,DMA22 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA22_DSCPTR_CUR,DMA22 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA22_DSCPTR_PRV,DMA22 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA22_ADDR_CUR,DMA22 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA22_ADDR_CUR,DMA22 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA22_STAT,DMA22 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA22_XCNT_CUR,DMA22 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA22_YCNT_CUR,DMA22 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA22_XCNT_CUR,DMA22 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA22_YCNT_CUR,DMA22 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA22_BWLCNT,DMA22 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA22_BWLCNT_CUR,DMA22 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA22_BWMCNT,DMA22 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA22_BWMCNT_CUR,DMA22 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA23"
|
|
base ad:0x3102B080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA23_DSCPTR_NXT,DMA23 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA23_ADDRSTART,DMA23 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA23_CFG,DMA23 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA23_XCNT,DMA23 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA23_XMOD,DMA23 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA23_DSCPTR_CUR,DMA23 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA23_DSCPTR_NXT,DMA23 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA23_ADDRSTART,DMA23 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA23_CFG,DMA23 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA23_XCNT,DMA23 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA23_XMOD,DMA23 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA23_DSCPTR_CUR,DMA23 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA23_DSCPTR_NXT,DMA23 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA23_ADDRSTART,DMA23 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA23_CFG,DMA23 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA23_CFG,DMA23 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA23_XCNT,DMA23 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA23_XMOD,DMA23 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA23_DSCPTR_CUR,DMA23 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA23_DSCPTR_NXT,DMA23 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA23_ADDRSTART,DMA23 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA23_CFG,DMA23 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA23_XCNT,DMA23 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA23_XMOD,DMA23 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA23_DSCPTR_CUR,DMA23 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA23_DSCPTR_NXT,DMA23 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA23_ADDRSTART,DMA23 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA23_CFG,DMA23 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA23_XCNT,DMA23 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA23_XMOD,DMA23 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA23_DSCPTR_CUR,DMA23 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA23_DSCPTR_PRV,DMA23 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA23_ADDR_CUR,DMA23 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA23_ADDR_CUR,DMA23 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA23_STAT,DMA23 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA23_XCNT_CUR,DMA23 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA23_YCNT_CUR,DMA23 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA23_XCNT_CUR,DMA23 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA23_YCNT_CUR,DMA23 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA23_BWLCNT,DMA23 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA23_BWLCNT_CUR,DMA23 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA23_BWMCNT,DMA23 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA23_BWMCNT_CUR,DMA23 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA24"
|
|
base ad:0x3102B100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA24_DSCPTR_NXT,DMA24 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA24_ADDRSTART,DMA24 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA24_CFG,DMA24 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA24_XCNT,DMA24 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA24_XMOD,DMA24 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA24_DSCPTR_CUR,DMA24 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA24_DSCPTR_NXT,DMA24 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA24_ADDRSTART,DMA24 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA24_CFG,DMA24 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA24_XCNT,DMA24 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA24_XMOD,DMA24 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA24_DSCPTR_CUR,DMA24 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA24_DSCPTR_NXT,DMA24 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA24_ADDRSTART,DMA24 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA24_CFG,DMA24 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA24_CFG,DMA24 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA24_XCNT,DMA24 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA24_XMOD,DMA24 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA24_DSCPTR_CUR,DMA24 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA24_DSCPTR_NXT,DMA24 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA24_ADDRSTART,DMA24 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA24_CFG,DMA24 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA24_XCNT,DMA24 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA24_XMOD,DMA24 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA24_DSCPTR_CUR,DMA24 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA24_DSCPTR_NXT,DMA24 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA24_ADDRSTART,DMA24 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA24_CFG,DMA24 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA24_XCNT,DMA24 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA24_XMOD,DMA24 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA24_DSCPTR_CUR,DMA24 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA24_DSCPTR_PRV,DMA24 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA24_ADDR_CUR,DMA24 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA24_ADDR_CUR,DMA24 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA24_STAT,DMA24 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA24_XCNT_CUR,DMA24 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA24_YCNT_CUR,DMA24 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA24_XCNT_CUR,DMA24 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA24_YCNT_CUR,DMA24 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA24_BWLCNT,DMA24 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA24_BWLCNT_CUR,DMA24 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA24_BWMCNT,DMA24 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA24_BWMCNT_CUR,DMA24 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA25"
|
|
base ad:0x3102B180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA25_DSCPTR_NXT,DMA25 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA25_ADDRSTART,DMA25 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA25_CFG,DMA25 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA25_XCNT,DMA25 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA25_XMOD,DMA25 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA25_DSCPTR_CUR,DMA25 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA25_DSCPTR_NXT,DMA25 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA25_ADDRSTART,DMA25 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA25_CFG,DMA25 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA25_XCNT,DMA25 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA25_XMOD,DMA25 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA25_DSCPTR_CUR,DMA25 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA25_DSCPTR_NXT,DMA25 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA25_ADDRSTART,DMA25 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA25_CFG,DMA25 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA25_CFG,DMA25 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA25_XCNT,DMA25 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA25_XMOD,DMA25 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA25_DSCPTR_CUR,DMA25 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA25_DSCPTR_NXT,DMA25 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA25_ADDRSTART,DMA25 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA25_CFG,DMA25 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA25_XCNT,DMA25 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA25_XMOD,DMA25 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA25_DSCPTR_CUR,DMA25 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA25_DSCPTR_NXT,DMA25 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA25_ADDRSTART,DMA25 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA25_CFG,DMA25 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA25_XCNT,DMA25 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA25_XMOD,DMA25 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA25_DSCPTR_CUR,DMA25 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA25_DSCPTR_PRV,DMA25 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA25_ADDR_CUR,DMA25 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA25_ADDR_CUR,DMA25 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA25_STAT,DMA25 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA25_XCNT_CUR,DMA25 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA25_YCNT_CUR,DMA25 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA25_XCNT_CUR,DMA25 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA25_YCNT_CUR,DMA25 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA25_BWLCNT,DMA25 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA25_BWLCNT_CUR,DMA25 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA25_BWMCNT,DMA25 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA25_BWMCNT_CUR,DMA25 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA26"
|
|
base ad:0x3102B200
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B200+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B200+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA26_DSCPTR_NXT,DMA26 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA26_ADDRSTART,DMA26 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA26_CFG,DMA26 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA26_XCNT,DMA26 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA26_XMOD,DMA26 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA26_DSCPTR_CUR,DMA26 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA26_DSCPTR_NXT,DMA26 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA26_ADDRSTART,DMA26 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA26_CFG,DMA26 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA26_XCNT,DMA26 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA26_XMOD,DMA26 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA26_DSCPTR_CUR,DMA26 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA26_DSCPTR_NXT,DMA26 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA26_ADDRSTART,DMA26 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B200+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA26_CFG,DMA26 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA26_CFG,DMA26 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA26_XCNT,DMA26 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA26_XMOD,DMA26 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA26_DSCPTR_CUR,DMA26 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B200+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA26_DSCPTR_NXT,DMA26 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA26_ADDRSTART,DMA26 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA26_CFG,DMA26 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA26_XCNT,DMA26 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA26_XMOD,DMA26 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA26_DSCPTR_CUR,DMA26 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA26_DSCPTR_NXT,DMA26 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA26_ADDRSTART,DMA26 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA26_CFG,DMA26 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA26_XCNT,DMA26 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA26_XMOD,DMA26 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA26_DSCPTR_CUR,DMA26 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA26_DSCPTR_PRV,DMA26 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA26_ADDR_CUR,DMA26 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA26_ADDR_CUR,DMA26 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA26_STAT,DMA26 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA26_XCNT_CUR,DMA26 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA26_YCNT_CUR,DMA26 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA26_XCNT_CUR,DMA26 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA26_YCNT_CUR,DMA26 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA26_BWLCNT,DMA26 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA26_BWLCNT_CUR,DMA26 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA26_BWMCNT,DMA26 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA26_BWMCNT_CUR,DMA26 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA27"
|
|
base ad:0x3102B280
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B280+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B280+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA27_DSCPTR_NXT,DMA27 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA27_ADDRSTART,DMA27 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA27_CFG,DMA27 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA27_XCNT,DMA27 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA27_XMOD,DMA27 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA27_DSCPTR_CUR,DMA27 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA27_DSCPTR_NXT,DMA27 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA27_ADDRSTART,DMA27 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA27_CFG,DMA27 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA27_XCNT,DMA27 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA27_XMOD,DMA27 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA27_DSCPTR_CUR,DMA27 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA27_DSCPTR_NXT,DMA27 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA27_ADDRSTART,DMA27 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B280+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA27_CFG,DMA27 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA27_CFG,DMA27 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA27_XCNT,DMA27 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA27_XMOD,DMA27 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA27_DSCPTR_CUR,DMA27 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B280+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA27_DSCPTR_NXT,DMA27 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA27_ADDRSTART,DMA27 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA27_CFG,DMA27 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA27_XCNT,DMA27 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA27_XMOD,DMA27 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA27_DSCPTR_CUR,DMA27 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA27_DSCPTR_NXT,DMA27 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA27_ADDRSTART,DMA27 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA27_CFG,DMA27 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA27_XCNT,DMA27 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA27_XMOD,DMA27 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA27_DSCPTR_CUR,DMA27 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA27_DSCPTR_PRV,DMA27 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA27_ADDR_CUR,DMA27 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA27_ADDR_CUR,DMA27 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA27_STAT,DMA27 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA27_XCNT_CUR,DMA27 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA27_YCNT_CUR,DMA27 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA27_XCNT_CUR,DMA27 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA27_YCNT_CUR,DMA27 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA27_BWLCNT,DMA27 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA27_BWLCNT_CUR,DMA27 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA27_BWMCNT,DMA27 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA27_BWMCNT_CUR,DMA27 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA28"
|
|
base ad:0x3102B300
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B300+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B300+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B300+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA28_DSCPTR_NXT,DMA28 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA28_ADDRSTART,DMA28 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA28_CFG,DMA28 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA28_XCNT,DMA28 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA28_XMOD,DMA28 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA28_DSCPTR_CUR,DMA28 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA28_DSCPTR_NXT,DMA28 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA28_ADDRSTART,DMA28 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA28_CFG,DMA28 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA28_XCNT,DMA28 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA28_XMOD,DMA28 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA28_DSCPTR_CUR,DMA28 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA28_DSCPTR_NXT,DMA28 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA28_ADDRSTART,DMA28 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B300+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B300+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA28_CFG,DMA28 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA28_CFG,DMA28 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA28_XCNT,DMA28 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA28_XMOD,DMA28 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA28_DSCPTR_CUR,DMA28 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B300+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA28_DSCPTR_NXT,DMA28 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA28_ADDRSTART,DMA28 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA28_CFG,DMA28 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA28_XCNT,DMA28 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA28_XMOD,DMA28 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA28_DSCPTR_CUR,DMA28 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA28_DSCPTR_NXT,DMA28 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA28_ADDRSTART,DMA28 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA28_CFG,DMA28 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA28_XCNT,DMA28 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA28_XMOD,DMA28 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA28_DSCPTR_CUR,DMA28 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA28_DSCPTR_PRV,DMA28 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA28_ADDR_CUR,DMA28 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA28_ADDR_CUR,DMA28 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA28_STAT,DMA28 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B300+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA28_XCNT_CUR,DMA28 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA28_YCNT_CUR,DMA28 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA28_XCNT_CUR,DMA28 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA28_YCNT_CUR,DMA28 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA28_BWLCNT,DMA28 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA28_BWLCNT_CUR,DMA28 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA28_BWMCNT,DMA28 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA28_BWMCNT_CUR,DMA28 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA29"
|
|
base ad:0x3102B380
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3102B380+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3102B380+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B380+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA29_DSCPTR_NXT,DMA29 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA29_ADDRSTART,DMA29 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA29_CFG,DMA29 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA29_XCNT,DMA29 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA29_XMOD,DMA29 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA29_DSCPTR_CUR,DMA29 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA29_DSCPTR_NXT,DMA29 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA29_ADDRSTART,DMA29 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA29_CFG,DMA29 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA29_XCNT,DMA29 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA29_XMOD,DMA29 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA29_DSCPTR_CUR,DMA29 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA29_DSCPTR_NXT,DMA29 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA29_ADDRSTART,DMA29 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3102B380+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3102B380+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA29_CFG,DMA29 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA29_CFG,DMA29 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA29_XCNT,DMA29 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA29_XMOD,DMA29 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA29_DSCPTR_CUR,DMA29 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3102B380+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA29_DSCPTR_NXT,DMA29 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA29_ADDRSTART,DMA29 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA29_CFG,DMA29 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA29_XCNT,DMA29 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA29_XMOD,DMA29 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA29_DSCPTR_CUR,DMA29 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA29_DSCPTR_NXT,DMA29 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA29_ADDRSTART,DMA29 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA29_CFG,DMA29 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA29_XCNT,DMA29 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA29_XMOD,DMA29 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA29_DSCPTR_CUR,DMA29 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA29_DSCPTR_PRV,DMA29 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA29_ADDR_CUR,DMA29 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA29_ADDR_CUR,DMA29 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA29_STAT,DMA29 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3102B380+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA29_XCNT_CUR,DMA29 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA29_YCNT_CUR,DMA29 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA29_XCNT_CUR,DMA29 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA29_YCNT_CUR,DMA29 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA29_BWLCNT,DMA29 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA29_BWLCNT_CUR,DMA29 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA29_BWMCNT,DMA29 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA29_BWMCNT_CUR,DMA29 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA30"
|
|
base ad:0x30FFF000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x30FFF000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x30FFF000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA30_DSCPTR_NXT,DMA30 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA30_ADDRSTART,DMA30 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA30_CFG,DMA30 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA30_XCNT,DMA30 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA30_XMOD,DMA30 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA30_DSCPTR_CUR,DMA30 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA30_DSCPTR_NXT,DMA30 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA30_ADDRSTART,DMA30 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA30_CFG,DMA30 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA30_XCNT,DMA30 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA30_XMOD,DMA30 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA30_DSCPTR_CUR,DMA30 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA30_DSCPTR_NXT,DMA30 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA30_ADDRSTART,DMA30 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x30FFF000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x30FFF000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA30_CFG,DMA30 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA30_CFG,DMA30 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA30_XCNT,DMA30 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA30_XMOD,DMA30 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA30_DSCPTR_CUR,DMA30 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA30_DSCPTR_NXT,DMA30 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA30_ADDRSTART,DMA30 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA30_CFG,DMA30 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA30_XCNT,DMA30 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA30_XMOD,DMA30 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA30_DSCPTR_CUR,DMA30 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA30_DSCPTR_NXT,DMA30 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA30_ADDRSTART,DMA30 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA30_CFG,DMA30 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA30_XCNT,DMA30 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA30_XMOD,DMA30 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA30_DSCPTR_CUR,DMA30 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA30_DSCPTR_PRV,DMA30 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA30_ADDR_CUR,DMA30 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA30_ADDR_CUR,DMA30 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA30_STAT,DMA30 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x30FFF000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA30_XCNT_CUR,DMA30 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA30_YCNT_CUR,DMA30 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA30_XCNT_CUR,DMA30 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA30_YCNT_CUR,DMA30 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA30_BWLCNT,DMA30 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA30_BWLCNT_CUR,DMA30 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA30_BWMCNT,DMA30 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA30_BWMCNT_CUR,DMA30 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA34"
|
|
base ad:0x31026180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31026180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31026180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA34_DSCPTR_NXT,DMA34 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA34_ADDRSTART,DMA34 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA34_CFG,DMA34 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA34_XCNT,DMA34 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA34_XMOD,DMA34 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA34_DSCPTR_CUR,DMA34 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA34_DSCPTR_NXT,DMA34 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA34_ADDRSTART,DMA34 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA34_CFG,DMA34 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA34_XCNT,DMA34 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA34_XMOD,DMA34 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA34_DSCPTR_CUR,DMA34 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA34_DSCPTR_NXT,DMA34 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA34_ADDRSTART,DMA34 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31026180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA34_CFG,DMA34 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA34_CFG,DMA34 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA34_XCNT,DMA34 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA34_XMOD,DMA34 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA34_DSCPTR_CUR,DMA34 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31026180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA34_DSCPTR_NXT,DMA34 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA34_ADDRSTART,DMA34 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA34_CFG,DMA34 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA34_XCNT,DMA34 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA34_XMOD,DMA34 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA34_DSCPTR_CUR,DMA34 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA34_DSCPTR_NXT,DMA34 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA34_ADDRSTART,DMA34 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA34_CFG,DMA34 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA34_XCNT,DMA34 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA34_XMOD,DMA34 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA34_DSCPTR_CUR,DMA34 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA34_DSCPTR_PRV,DMA34 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31026180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA34_ADDR_CUR,DMA34 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA34_ADDR_CUR,DMA34 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA34_STAT,DMA34 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31026180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA34_XCNT_CUR,DMA34 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA34_YCNT_CUR,DMA34 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA34_XCNT_CUR,DMA34 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA34_YCNT_CUR,DMA34 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA34_BWLCNT,DMA34 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA34_BWLCNT_CUR,DMA34 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA34_BWMCNT,DMA34 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA34_BWMCNT_CUR,DMA34 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA35"
|
|
base ad:0x31026100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31026100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31026100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA35_DSCPTR_NXT,DMA35 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA35_ADDRSTART,DMA35 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA35_CFG,DMA35 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA35_XCNT,DMA35 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA35_XMOD,DMA35 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA35_DSCPTR_CUR,DMA35 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA35_DSCPTR_NXT,DMA35 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA35_ADDRSTART,DMA35 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA35_CFG,DMA35 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA35_XCNT,DMA35 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA35_XMOD,DMA35 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA35_DSCPTR_CUR,DMA35 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA35_DSCPTR_NXT,DMA35 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA35_ADDRSTART,DMA35 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31026100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA35_CFG,DMA35 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA35_CFG,DMA35 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA35_XCNT,DMA35 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA35_XMOD,DMA35 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA35_DSCPTR_CUR,DMA35 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31026100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA35_DSCPTR_NXT,DMA35 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA35_ADDRSTART,DMA35 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA35_CFG,DMA35 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA35_XCNT,DMA35 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA35_XMOD,DMA35 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA35_DSCPTR_CUR,DMA35 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA35_DSCPTR_NXT,DMA35 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA35_ADDRSTART,DMA35 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA35_CFG,DMA35 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA35_XCNT,DMA35 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA35_XMOD,DMA35 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA35_DSCPTR_CUR,DMA35 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA35_DSCPTR_PRV,DMA35 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31026100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA35_ADDR_CUR,DMA35 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA35_ADDR_CUR,DMA35 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA35_STAT,DMA35 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31026100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA35_XCNT_CUR,DMA35 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA35_YCNT_CUR,DMA35 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA35_XCNT_CUR,DMA35 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA35_YCNT_CUR,DMA35 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA35_BWLCNT,DMA35 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA35_BWLCNT_CUR,DMA35 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA35_BWMCNT,DMA35 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA35_BWMCNT_CUR,DMA35 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA36"
|
|
base ad:0x30FFF080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x30FFF080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x30FFF080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA36_DSCPTR_NXT,DMA36 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA36_ADDRSTART,DMA36 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA36_CFG,DMA36 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA36_XCNT,DMA36 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA36_XMOD,DMA36 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA36_DSCPTR_CUR,DMA36 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA36_DSCPTR_NXT,DMA36 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA36_ADDRSTART,DMA36 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA36_CFG,DMA36 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA36_XCNT,DMA36 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA36_XMOD,DMA36 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA36_DSCPTR_CUR,DMA36 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA36_DSCPTR_NXT,DMA36 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA36_ADDRSTART,DMA36 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x30FFF080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x30FFF080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA36_CFG,DMA36 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA36_CFG,DMA36 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA36_XCNT,DMA36 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA36_XMOD,DMA36 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA36_DSCPTR_CUR,DMA36 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA36_DSCPTR_NXT,DMA36 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA36_ADDRSTART,DMA36 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA36_CFG,DMA36 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA36_XCNT,DMA36 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA36_XMOD,DMA36 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA36_DSCPTR_CUR,DMA36 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA36_DSCPTR_NXT,DMA36 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA36_ADDRSTART,DMA36 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA36_CFG,DMA36 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA36_XCNT,DMA36 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA36_XMOD,DMA36 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA36_DSCPTR_CUR,DMA36 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA36_DSCPTR_PRV,DMA36 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA36_ADDR_CUR,DMA36 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA36_ADDR_CUR,DMA36 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA36_STAT,DMA36 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x30FFF080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA36_XCNT_CUR,DMA36 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA36_YCNT_CUR,DMA36 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA36_XCNT_CUR,DMA36 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA36_YCNT_CUR,DMA36 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA36_BWLCNT,DMA36 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA36_BWLCNT_CUR,DMA36 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA36_BWMCNT,DMA36 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA36_BWMCNT_CUR,DMA36 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA37"
|
|
base ad:0x31026280
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31026280+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31026280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026280+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA37_DSCPTR_NXT,DMA37 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA37_ADDRSTART,DMA37 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA37_CFG,DMA37 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA37_XCNT,DMA37 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA37_XMOD,DMA37 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA37_DSCPTR_CUR,DMA37 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA37_DSCPTR_NXT,DMA37 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA37_ADDRSTART,DMA37 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA37_CFG,DMA37 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA37_XCNT,DMA37 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA37_XMOD,DMA37 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA37_DSCPTR_CUR,DMA37 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA37_DSCPTR_NXT,DMA37 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA37_ADDRSTART,DMA37 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31026280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026280+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA37_CFG,DMA37 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA37_CFG,DMA37 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA37_XCNT,DMA37 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA37_XMOD,DMA37 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA37_DSCPTR_CUR,DMA37 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31026280+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA37_DSCPTR_NXT,DMA37 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA37_ADDRSTART,DMA37 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA37_CFG,DMA37 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA37_XCNT,DMA37 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA37_XMOD,DMA37 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA37_DSCPTR_CUR,DMA37 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA37_DSCPTR_NXT,DMA37 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA37_ADDRSTART,DMA37 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA37_CFG,DMA37 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA37_XCNT,DMA37 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA37_XMOD,DMA37 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA37_DSCPTR_CUR,DMA37 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA37_DSCPTR_PRV,DMA37 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31026280+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA37_ADDR_CUR,DMA37 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA37_ADDR_CUR,DMA37 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA37_STAT,DMA37 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31026280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA37_XCNT_CUR,DMA37 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA37_YCNT_CUR,DMA37 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA37_XCNT_CUR,DMA37 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA37_YCNT_CUR,DMA37 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA37_BWLCNT,DMA37 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA37_BWLCNT_CUR,DMA37 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA37_BWMCNT,DMA37 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA37_BWMCNT_CUR,DMA37 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA38"
|
|
base ad:0x31026200
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x31026200+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x31026200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026200+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA38_DSCPTR_NXT,DMA38 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA38_ADDRSTART,DMA38 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA38_CFG,DMA38 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA38_XCNT,DMA38 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA38_XMOD,DMA38 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA38_DSCPTR_CUR,DMA38 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA38_DSCPTR_NXT,DMA38 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA38_ADDRSTART,DMA38 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA38_CFG,DMA38 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA38_XCNT,DMA38 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA38_XMOD,DMA38 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA38_DSCPTR_CUR,DMA38 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA38_DSCPTR_NXT,DMA38 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA38_ADDRSTART,DMA38 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x31026200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x31026200+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA38_CFG,DMA38 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA38_CFG,DMA38 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA38_XCNT,DMA38 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA38_XMOD,DMA38 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA38_DSCPTR_CUR,DMA38 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x31026200+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA38_DSCPTR_NXT,DMA38 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA38_ADDRSTART,DMA38 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA38_CFG,DMA38 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA38_XCNT,DMA38 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA38_XMOD,DMA38 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA38_DSCPTR_CUR,DMA38 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA38_DSCPTR_NXT,DMA38 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA38_ADDRSTART,DMA38 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA38_CFG,DMA38 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA38_XCNT,DMA38 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA38_XMOD,DMA38 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x31026200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA38_DSCPTR_CUR,DMA38 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA38_DSCPTR_PRV,DMA38 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x31026200+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA38_ADDR_CUR,DMA38 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA38_ADDR_CUR,DMA38 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA38_STAT,DMA38 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x31026200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA38_XCNT_CUR,DMA38 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA38_YCNT_CUR,DMA38 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA38_XCNT_CUR,DMA38 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA38_YCNT_CUR,DMA38 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA38_BWLCNT,DMA38 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA38_BWLCNT_CUR,DMA38 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA38_BWMCNT,DMA38 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA38_BWMCNT_CUR,DMA38 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA39"
|
|
base ad:0x3109A000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3109A000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3109A000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109A000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA39_DSCPTR_NXT,DMA39 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA39_ADDRSTART,DMA39 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA39_CFG,DMA39 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA39_XCNT,DMA39 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA39_XMOD,DMA39 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA39_DSCPTR_CUR,DMA39 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA39_DSCPTR_NXT,DMA39 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA39_ADDRSTART,DMA39 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA39_CFG,DMA39 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA39_XCNT,DMA39 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA39_XMOD,DMA39 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA39_DSCPTR_CUR,DMA39 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA39_DSCPTR_NXT,DMA39 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA39_ADDRSTART,DMA39 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3109A000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109A000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA39_CFG,DMA39 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA39_CFG,DMA39 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA39_XCNT,DMA39 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA39_XMOD,DMA39 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA39_DSCPTR_CUR,DMA39 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3109A000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA39_DSCPTR_NXT,DMA39 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA39_ADDRSTART,DMA39 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA39_CFG,DMA39 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA39_XCNT,DMA39 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA39_XMOD,DMA39 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA39_DSCPTR_CUR,DMA39 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA39_DSCPTR_NXT,DMA39 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA39_ADDRSTART,DMA39 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA39_CFG,DMA39 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA39_XCNT,DMA39 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA39_XMOD,DMA39 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA39_DSCPTR_CUR,DMA39 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA39_DSCPTR_PRV,DMA39 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA39_ADDR_CUR,DMA39 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA39_ADDR_CUR,DMA39 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA39_STAT,DMA39 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3109A000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA39_XCNT_CUR,DMA39 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA39_YCNT_CUR,DMA39 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA39_XCNT_CUR,DMA39 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA39_YCNT_CUR,DMA39 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA39_BWLCNT,DMA39 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA39_BWLCNT_CUR,DMA39 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA39_BWMCNT,DMA39 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA39_BWMCNT_CUR,DMA39 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA39_BWLCNT,DMA39 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA39_BWLCNT_CUR,DMA39 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA39_BWMCNT,DMA39 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA39_BWMCNT_CUR,DMA39 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA40"
|
|
base ad:0x3109A080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3109A080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3109A080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109A080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA40_DSCPTR_NXT,DMA40 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA40_ADDRSTART,DMA40 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA40_CFG,DMA40 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA40_XCNT,DMA40 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA40_XMOD,DMA40 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA40_DSCPTR_CUR,DMA40 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA40_DSCPTR_NXT,DMA40 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA40_ADDRSTART,DMA40 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA40_CFG,DMA40 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA40_XCNT,DMA40 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA40_XMOD,DMA40 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA40_DSCPTR_CUR,DMA40 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA40_DSCPTR_NXT,DMA40 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA40_ADDRSTART,DMA40 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3109A080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109A080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA40_CFG,DMA40 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA40_CFG,DMA40 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA40_XCNT,DMA40 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA40_XMOD,DMA40 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA40_DSCPTR_CUR,DMA40 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3109A080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA40_DSCPTR_NXT,DMA40 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA40_ADDRSTART,DMA40 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA40_CFG,DMA40 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA40_XCNT,DMA40 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA40_XMOD,DMA40 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA40_DSCPTR_CUR,DMA40 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA40_DSCPTR_NXT,DMA40 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA40_ADDRSTART,DMA40 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA40_CFG,DMA40 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA40_XCNT,DMA40 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA40_XMOD,DMA40 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA40_DSCPTR_CUR,DMA40 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA40_DSCPTR_PRV,DMA40 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA40_ADDR_CUR,DMA40 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA40_ADDR_CUR,DMA40 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA40_STAT,DMA40 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3109A080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA40_XCNT_CUR,DMA40 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA40_YCNT_CUR,DMA40 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA40_XCNT_CUR,DMA40 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA40_YCNT_CUR,DMA40 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA40_BWLCNT,DMA40 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA40_BWLCNT_CUR,DMA40 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA40_BWMCNT,DMA40 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA40_BWMCNT_CUR,DMA40 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA40_BWLCNT,DMA40 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA40_BWLCNT_CUR,DMA40 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA40_BWMCNT,DMA40 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA40_BWMCNT_CUR,DMA40 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA43"
|
|
base ad:0x3109B000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3109B000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3109B000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109B000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA43_DSCPTR_NXT,DMA43 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA43_ADDRSTART,DMA43 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA43_CFG,DMA43 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA43_XCNT,DMA43 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA43_XMOD,DMA43 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA43_DSCPTR_CUR,DMA43 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA43_DSCPTR_NXT,DMA43 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA43_ADDRSTART,DMA43 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA43_CFG,DMA43 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA43_XCNT,DMA43 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA43_XMOD,DMA43 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA43_DSCPTR_CUR,DMA43 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA43_DSCPTR_NXT,DMA43 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA43_ADDRSTART,DMA43 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3109B000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109B000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA43_CFG,DMA43 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA43_CFG,DMA43 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA43_XCNT,DMA43 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA43_XMOD,DMA43 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA43_DSCPTR_CUR,DMA43 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3109B000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA43_DSCPTR_NXT,DMA43 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA43_ADDRSTART,DMA43 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA43_CFG,DMA43 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA43_XCNT,DMA43 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA43_XMOD,DMA43 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA43_DSCPTR_CUR,DMA43 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA43_DSCPTR_NXT,DMA43 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA43_ADDRSTART,DMA43 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA43_CFG,DMA43 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA43_XCNT,DMA43 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA43_XMOD,DMA43 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA43_DSCPTR_CUR,DMA43 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA43_DSCPTR_PRV,DMA43 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA43_ADDR_CUR,DMA43 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA43_ADDR_CUR,DMA43 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA43_STAT,DMA43 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3109B000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA43_XCNT_CUR,DMA43 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA43_YCNT_CUR,DMA43 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA43_XCNT_CUR,DMA43 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA43_YCNT_CUR,DMA43 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA43_BWLCNT,DMA43 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA43_BWLCNT_CUR,DMA43 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA43_BWMCNT,DMA43 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA43_BWMCNT_CUR,DMA43 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA43_BWLCNT,DMA43 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA43_BWLCNT_CUR,DMA43 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA43_BWMCNT,DMA43 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA43_BWMCNT_CUR,DMA43 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA44"
|
|
base ad:0x3109B080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3109B080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x3109B080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109B080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA44_DSCPTR_NXT,DMA44 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA44_ADDRSTART,DMA44 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA44_CFG,DMA44 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA44_XCNT,DMA44 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA44_XMOD,DMA44 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA44_DSCPTR_CUR,DMA44 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA44_DSCPTR_NXT,DMA44 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA44_ADDRSTART,DMA44 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA44_CFG,DMA44 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA44_XCNT,DMA44 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA44_XMOD,DMA44 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA44_DSCPTR_CUR,DMA44 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA44_DSCPTR_NXT,DMA44 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA44_ADDRSTART,DMA44 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x3109B080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x3109B080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA44_CFG,DMA44 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA44_CFG,DMA44 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA44_XCNT,DMA44 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA44_XMOD,DMA44 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA44_DSCPTR_CUR,DMA44 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3109B080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA44_DSCPTR_NXT,DMA44 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA44_ADDRSTART,DMA44 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA44_CFG,DMA44 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA44_XCNT,DMA44 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA44_XMOD,DMA44 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA44_DSCPTR_CUR,DMA44 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA44_DSCPTR_NXT,DMA44 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA44_ADDRSTART,DMA44 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA44_CFG,DMA44 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA44_XCNT,DMA44 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA44_XMOD,DMA44 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA44_DSCPTR_CUR,DMA44 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA44_DSCPTR_PRV,DMA44 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA44_ADDR_CUR,DMA44 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA44_ADDR_CUR,DMA44 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA44_STAT,DMA44 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x3109B080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA44_XCNT_CUR,DMA44 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA44_YCNT_CUR,DMA44 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA44_XCNT_CUR,DMA44 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA44_YCNT_CUR,DMA44 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA44_BWLCNT,DMA44 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA44_BWLCNT_CUR,DMA44 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA44_BWMCNT,DMA44 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA44_BWMCNT_CUR,DMA44 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA44_BWLCNT,DMA44 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA44_BWLCNT_CUR,DMA44 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA44_BWMCNT,DMA44 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA44_BWMCNT_CUR,DMA44 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "EMDMA (Extended Memory DMA)"
|
|
base ad:0x310C602C
|
|
width 15.
|
|
tree "EMDMA0"
|
|
if (((per.l(ad:0x310C602C+0x0))&0x04)==0x04)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "EMDMA0_CTL,EMDMA0 External Memory DMA Control Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
rbitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
rbitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
rbitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
rbitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
rbitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
rbitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
else
|
|
bitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
bitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
bitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
bitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
bitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
endif
|
|
bitfld.long 0x00 12. " INTDONE0 ,Internal DMA completion interrupt (control)" "Both channel,Channel 0"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TLEN ,Tap list DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " OFCEN ,On the fly control loading enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " WRBEN ,Write back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DFLSH ,Flush DMA FIFO" "No flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CBEN ,Circular buffering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DLEN ,Enable delay line DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHEN ,Enable chaining" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRAN ,DMA direction" "Write,Read"
|
|
bitfld.long 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "EMDMA0_CTL,EMDMA0 External Memory DMA Control Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
rbitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
rbitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
rbitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
rbitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
rbitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
rbitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
else
|
|
bitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
bitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
bitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
bitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
bitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
endif
|
|
bitfld.long 0x00 12. " INTDONE0 ,Internal DMA completion interrupt (control)" "Both channel,Channel 0"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TLEN ,Tap list DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " OFCEN ,On the fly control loading enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DFLSH ,Flush DMA FIFO" "No flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CBEN ,Circular buffering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHEN ,Enable chaining" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRAN ,DMA direction" "Write,Read"
|
|
bitfld.long 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "EMDMA0_INDX1,EMDMA0 External Index Register"
|
|
hexmask.long 0x00 0.--29. 1. " VALUE ,DMA external address index"
|
|
line.long 0x04 "EMDMA0_MOD1,EMDMA0 External Modifier Register"
|
|
hexmask.long 0x04 0.--26. 1. " VALUE ,DMA external address modifier"
|
|
line.long 0x08 "EMDMA0_CNT1,EMDMA0 External Count Register"
|
|
group.long (0x54+0x0C)++0x0B
|
|
line.long 0x00 "EMDMA0_INDX0,EMDMA0 Internal Index Register"
|
|
hexmask.long 0x00 0.--29. 1. " VALUE ,DMA buffer start address"
|
|
line.long 0x04 "EMDMA0_MOD0,EMDMA0 Internal Modifier Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,DMA address modifier"
|
|
line.long 0x08 "EMDMA0_CNT0,EMDMA0 Internal Count Register"
|
|
if (((per.l(ad:0x310C602C+0x0))&0x104)==0x104)
|
|
group.long (0x54+0x18)++0x03
|
|
line.long 0x00 "EMDMA0_CHNPTR,EMDMA0 Chain Pointer Register"
|
|
bitfld.long 0x00 31. " CPDR ,CPDR DMA direction for the next TCB" "Write,Read"
|
|
bitfld.long 0x00 30. " PCI ,Program controlled interrupt" "Entire DMA chained transfer,Current DMA sequence"
|
|
hexmask.long 0x00 0.--29. 1. " ADDR ,Next descriptor (chain) pointer address"
|
|
elif (((per.l(ad:0x310C602C+0x0))&0x104)==0x04)
|
|
group.long (0x54+0x18)++0x03
|
|
line.long 0x00 "EMDMA0_CHNPTR,EMDMA0 Chain Pointer Register"
|
|
bitfld.long 0x00 30. " PCI ,Program controlled interrupt" "Entire DMA chained transfer,Current DMA sequence"
|
|
hexmask.long 0x00 0.--29. 1. " ADDR ,Next descriptor (chain) pointer address"
|
|
else
|
|
hgroup.long (0x54+0x18)++0x03
|
|
hide.long 0x00 "EMDMA0_CHNPTR,EMDMA0 Chain Pointer Register"
|
|
endif
|
|
group.long (0x54+0x1C)++0x0B
|
|
line.long 0x00 "EMDMA0_BASE,EMDMA0 External Base Address Register"
|
|
hexmask.long 0x00 0.--29. 1. " ADDR ,External delay line base address"
|
|
line.long 0x04 "EMDMA0_TPTR,EMDMA0 Tap List Pointer Register"
|
|
hexmask.long 0x04 0.--29. 1. " VALUE ,Delay line tap list pointer"
|
|
line.long 0x08 "EMDMA0_BUFLEN,EMDMA0 Circular Buffer Length Register"
|
|
hexmask.long 0x08 0.--25. 1. " CLEN ,Delay line circular buffer length"
|
|
group.long (0x54+0x2C)++0x03
|
|
line.long 0x00 "EMDMA0_TCNT,EMDMA0 Delay Line Tap Count Register"
|
|
tree.end
|
|
tree "EMDMA1"
|
|
if (((per.l(ad:0x310C602C+0x4))&0x04)==0x04)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "EMDMA1_CTL,EMDMA1 External Memory DMA Control Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
rbitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
rbitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
rbitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
rbitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
rbitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
rbitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
else
|
|
bitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
bitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
bitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
bitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
bitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
endif
|
|
bitfld.long 0x00 12. " INTDONE0 ,Internal DMA completion interrupt (control)" "Both channel,Channel 0"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TLEN ,Tap list DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " OFCEN ,On the fly control loading enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " WRBEN ,Write back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DFLSH ,Flush DMA FIFO" "No flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CBEN ,Circular buffering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DLEN ,Enable delay line DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHEN ,Enable chaining" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRAN ,DMA direction" "Write,Read"
|
|
bitfld.long 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "EMDMA1_CTL,EMDMA1 External Memory DMA Control Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
rbitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
rbitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
rbitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
rbitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
rbitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
rbitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
else
|
|
bitfld.long 0x00 25. " DIRS ,DMA transfer direction status" "Read,Write"
|
|
bitfld.long 0x00 24. " DMAS1 ,DMA external interface status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " WBS ,Write back status" "Not active,Active"
|
|
bitfld.long 0x00 22. " TLS ,TAP list loading status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CHS ,DMA chaining status" "Not active,Active"
|
|
bitfld.long 0x00 20. " DMAS0 ,DMA transfer status" "Idle,In progress"
|
|
bitfld.long 0x00 16.--17. " DFS ,DMA FIFO status" "Empty,Partially full,,Full"
|
|
endif
|
|
bitfld.long 0x00 12. " INTDONE0 ,Internal DMA completion interrupt (control)" "Both channel,Channel 0"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TLEN ,Tap list DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " OFCEN ,On the fly control loading enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DFLSH ,Flush DMA FIFO" "No flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CBEN ,Circular buffering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHEN ,Enable chaining" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRAN ,DMA direction" "Write,Read"
|
|
bitfld.long 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "EMDMA1_INDX1,EMDMA1 External Index Register"
|
|
hexmask.long 0x00 0.--29. 1. " VALUE ,DMA external address index"
|
|
line.long 0x04 "EMDMA1_MOD1,EMDMA1 External Modifier Register"
|
|
hexmask.long 0x04 0.--26. 1. " VALUE ,DMA external address modifier"
|
|
line.long 0x08 "EMDMA1_CNT1,EMDMA1 External Count Register"
|
|
group.long (0x94+0x0C)++0x0B
|
|
line.long 0x00 "EMDMA1_INDX0,EMDMA1 Internal Index Register"
|
|
hexmask.long 0x00 0.--29. 1. " VALUE ,DMA buffer start address"
|
|
line.long 0x04 "EMDMA1_MOD0,EMDMA1 Internal Modifier Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,DMA address modifier"
|
|
line.long 0x08 "EMDMA1_CNT0,EMDMA1 Internal Count Register"
|
|
if (((per.l(ad:0x310C602C+0x4))&0x104)==0x104)
|
|
group.long (0x94+0x18)++0x03
|
|
line.long 0x00 "EMDMA1_CHNPTR,EMDMA1 Chain Pointer Register"
|
|
bitfld.long 0x00 31. " CPDR ,CPDR DMA direction for the next TCB" "Write,Read"
|
|
bitfld.long 0x00 30. " PCI ,Program controlled interrupt" "Entire DMA chained transfer,Current DMA sequence"
|
|
hexmask.long 0x00 0.--29. 1. " ADDR ,Next descriptor (chain) pointer address"
|
|
elif (((per.l(ad:0x310C602C+0x4))&0x104)==0x04)
|
|
group.long (0x94+0x18)++0x03
|
|
line.long 0x00 "EMDMA1_CHNPTR,EMDMA1 Chain Pointer Register"
|
|
bitfld.long 0x00 30. " PCI ,Program controlled interrupt" "Entire DMA chained transfer,Current DMA sequence"
|
|
hexmask.long 0x00 0.--29. 1. " ADDR ,Next descriptor (chain) pointer address"
|
|
else
|
|
hgroup.long (0x94+0x18)++0x03
|
|
hide.long 0x00 "EMDMA1_CHNPTR,EMDMA1 Chain Pointer Register"
|
|
endif
|
|
group.long (0x94+0x1C)++0x0B
|
|
line.long 0x00 "EMDMA1_BASE,EMDMA1 External Base Address Register"
|
|
hexmask.long 0x00 0.--29. 1. " ADDR ,External delay line base address"
|
|
line.long 0x04 "EMDMA1_TPTR,EMDMA1 Tap List Pointer Register"
|
|
hexmask.long 0x04 0.--29. 1. " VALUE ,Delay line tap list pointer"
|
|
line.long 0x08 "EMDMA1_BUFLEN,EMDMA1 Circular Buffer Length Register"
|
|
hexmask.long 0x08 0.--25. 1. " CLEN ,Delay line circular buffer length"
|
|
group.long (0x94+0x2C)++0x03
|
|
line.long 0x00 "EMDMA1_TCNT,EMDMA1 Delay Line Tap Count Register"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
tree "CRC0"
|
|
base ad:0x310A5000
|
|
width 20.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CRC0_CTL,CRC Control Register"
|
|
bitfld.long 0x00 22. " CMPMIRR ,COMPARE register mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " POLYMIRR ,Polynomial register mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RSLTMIRR ,Result register mirroring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FDSEL ,FIFO data select" "Unmodified,Modified"
|
|
bitfld.long 0x00 18. " W16SWP ,Word16 swapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BYTMIRR ,Byte mirroring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BITMIRR ,Bit mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IRRSTALL ,Intermediate result ready stall" "Do not stall,Stall on IRR"
|
|
bitfld.long 0x00 12. " OBRSTALL ,Output buffer ready stall" "Do not stall,Stall on OBR"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTOCLRF ,Auto clear to one" "Not Cleared,Cleared"
|
|
bitfld.long 0x00 8. " AUTOCLRZ ,Auto clear to zero" "Not Cleared,Cleared"
|
|
bitfld.long 0x00 4.--7. " OPMODE ,Operation mode" ",CRC compute/compare memory transfer,Data fill memory transfer,CRC compute/compare memory scan,Data verify memory scan,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " BLKEN ,Block enable" "Disabled,Enabled"
|
|
line.long 0x04 "CRC0_DCNT,CRC Data Word Count Register"
|
|
line.long 0x08 "CRC0_DCNTRLD,CRC Data Word Count Reload Register"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CRC0_COMP,CRC Data Compare Register"
|
|
line.long 0x04 "CRC0_FILLVAL,CRC Fill Value Register"
|
|
sif (cpuis("ADSPCM40*"))
|
|
if ((((per.l(ad:0x310A5000+0x00))&0xF0)==0x10)||(((per.l(ad:0x310A5000+0x00))&0xF0)==0x20))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CRC0_DFIFO,CRC Data FIFO Register"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRC0_DFIFO,CRC Data FIFO Register"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRC0_DFIFO,CRC Data FIFO Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRC0_INEN,CRC Interrupt Enable Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DCNTEXP_set/clr ,Data count expired (status) interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CMPERR_set/clr ,Compare error interrupt enable" "Masked,Unmasked"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRC0_POLY,CRC Polynomial Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CRC0_STAT,CRC Status Register"
|
|
rbitfld.long 0x00 20.--22. " FSTAT ,FIFO status" "Empty,1 data,2 data,3 data,Full,?..."
|
|
rbitfld.long 0x00 19. " LUTDONE ,Look up table done" "No status,LUT Generation done"
|
|
rbitfld.long 0x00 18. " IRR ,Intermediate result ready" "No status,Intermediate results ready"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " OBR ,Output buffer ready" "No status,Output buffer ready"
|
|
rbitfld.long 0x00 16. " IBR ,Input buffer ready" "No status,Input buffer ready"
|
|
eventfld.long 0x00 4. " DCNTEXP ,Data count expired" "No status,Data counter expired"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CMPERR ,Compare error" "No status,Compare error"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRC0_DCNTCAP,CRC Data Count Capture Register"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "CRC0_RESULT_FIN,CRC CRC Final Result Register"
|
|
line.long 0x04 "CRC0_RESULT_CUR,CRC CRC Current Result Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC1"
|
|
base ad:0x31001300
|
|
width 20.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CRC1_CTL,CRC Control Register"
|
|
bitfld.long 0x00 22. " CMPMIRR ,COMPARE register mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " POLYMIRR ,Polynomial register mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RSLTMIRR ,Result register mirroring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FDSEL ,FIFO data select" "Unmodified,Modified"
|
|
bitfld.long 0x00 18. " W16SWP ,Word16 swapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BYTMIRR ,Byte mirroring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BITMIRR ,Bit mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IRRSTALL ,Intermediate result ready stall" "Do not stall,Stall on IRR"
|
|
bitfld.long 0x00 12. " OBRSTALL ,Output buffer ready stall" "Do not stall,Stall on OBR"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTOCLRF ,Auto clear to one" "Not Cleared,Cleared"
|
|
bitfld.long 0x00 8. " AUTOCLRZ ,Auto clear to zero" "Not Cleared,Cleared"
|
|
bitfld.long 0x00 4.--7. " OPMODE ,Operation mode" ",CRC compute/compare memory transfer,Data fill memory transfer,CRC compute/compare memory scan,Data verify memory scan,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " BLKEN ,Block enable" "Disabled,Enabled"
|
|
line.long 0x04 "CRC1_DCNT,CRC Data Word Count Register"
|
|
line.long 0x08 "CRC1_DCNTRLD,CRC Data Word Count Reload Register"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CRC1_COMP,CRC Data Compare Register"
|
|
line.long 0x04 "CRC1_FILLVAL,CRC Fill Value Register"
|
|
sif (cpuis("ADSPCM40*"))
|
|
if ((((per.l(ad:0x31001300+0x00))&0xF0)==0x10)||(((per.l(ad:0x31001300+0x00))&0xF0)==0x20))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CRC1_DFIFO,CRC Data FIFO Register"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRC1_DFIFO,CRC Data FIFO Register"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRC1_DFIFO,CRC Data FIFO Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRC1_INEN,CRC Interrupt Enable Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DCNTEXP_set/clr ,Data count expired (status) interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CMPERR_set/clr ,Compare error interrupt enable" "Masked,Unmasked"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRC1_POLY,CRC Polynomial Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CRC1_STAT,CRC Status Register"
|
|
rbitfld.long 0x00 20.--22. " FSTAT ,FIFO status" "Empty,1 data,2 data,3 data,Full,?..."
|
|
rbitfld.long 0x00 19. " LUTDONE ,Look up table done" "No status,LUT Generation done"
|
|
rbitfld.long 0x00 18. " IRR ,Intermediate result ready" "No status,Intermediate results ready"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " OBR ,Output buffer ready" "No status,Output buffer ready"
|
|
rbitfld.long 0x00 16. " IBR ,Input buffer ready" "No status,Input buffer ready"
|
|
eventfld.long 0x00 4. " DCNTEXP ,Data count expired" "No status,Data counter expired"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CMPERR ,Compare error" "No status,Compare error"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRC1_DCNTCAP,CRC Data Count Capture Register"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "CRC1_RESULT_FIN,CRC CRC Final Result Register"
|
|
line.long 0x04 "CRC1_RESULT_CUR,CRC CRC Current Result Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "HADC (Housekeeping ADC)"
|
|
base ad:0x31016000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "HADC_CTL,HADC Control Register"
|
|
bitfld.long 0x00 13. " ENLS ,Enable level shifters" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 12. " DOUTOREOCB ,Serial data on DOUT" "EOC only,Serial"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--11. " FIXEDCNV ,Fixed conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " CONT ,Continuous conversion" "No,Yes"
|
|
bitfld.long 0x00 3.--6. " FDIV ,Frequency divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STARTCNV ,Start conversion" "No action,Start"
|
|
bitfld.long 0x00 1. " PD ,Power down" "No action,Power down"
|
|
bitfld.long 0x00 0. " NRST ,Reset" "Reset,No action"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HADC_CHAN_MSK,HADC Channel Mask Register"
|
|
sif !cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 15. " VALUE15 ,Mask for 15 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " VALUE14 ,Mask for 14 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " VALUE13 ,Mask for 13 channel" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " VALUE12 ,Mask for 12 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 11. " VALUE11 ,Mask for 11 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " VALUE10 ,Mask for 10 channel" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VALUE9 ,Mask for 9 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " VALUE8 ,Mask for 8 channel" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " VALUE7 ,Mask for 7 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " VALUE6 ,Mask for 6 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " VALUE5 ,Mask for 5 channel" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VALUE4 ,Mask for 4 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " VALUE3 ,Mask for 3 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " VALUE2 ,Mask for 2 channel" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VALUE1 ,Mask for 1 channel" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " VALUE0 ,Mask for 0 channel" "Masked,Unmasked"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HADC_IMSK,HADC Interrupt Mask Register"
|
|
bitfld.long 0x00 17. " RDY ,Mask interrupt when ADC ready to convert" "Unmask,Mask"
|
|
bitfld.long 0x00 16. " SEQ ,Mask interrupt at end of sequence completion" "Unmask,Mask"
|
|
textline " "
|
|
sif !cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 15. " CHAN15 ,Channel mask 15" "Unmask,Mask"
|
|
bitfld.long 0x00 14. " CHAN14 ,Channel mask 14" "Unmask,Mask"
|
|
bitfld.long 0x00 13. " CHAN13 ,Channel mask 13" "Unmask,Mask"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CHAN12 ,Channel mask 12" "Unmask,Mask"
|
|
bitfld.long 0x00 11. " CHAN11 ,Channel mask 11" "Unmask,Mask"
|
|
bitfld.long 0x00 10. " CHAN10 ,Channel mask 10" "Unmask,Mask"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CHAN9 ,Channel mask 9" "Unmask,Mask"
|
|
bitfld.long 0x00 8. " CHAN8 ,Channel mask 8" "Unmask,Mask"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " CHAN7 ,Channel mask 7" "Unmask,Mask"
|
|
bitfld.long 0x00 6. " CHAN6 ,Channel mask 6" "Unmask,Mask"
|
|
bitfld.long 0x00 5. " CHAN5 ,Channel mask 5" "Unmask,Mask"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHAN4 ,Channel mask 4" "Unmask,Mask"
|
|
bitfld.long 0x00 3. " CHAN3 ,Channel mask 3" "Unmask,Mask"
|
|
bitfld.long 0x00 2. " CHAN2 ,Channel mask 2" "Unmask,Mask"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHAN1 ,Channel mask 1" "Unmask,Mask"
|
|
bitfld.long 0x00 0. " CHAN0 ,Channel mask 0" "Unmask,Mask"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HADC_STAT,HADC Status Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
rbitfld.long 0x00 20. " TMUHADC_BUSY ,Temperature conversion status" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 4.--19. 1. " INTRW1C ,Conversion complete interrupt"
|
|
eventfld.long 0x00 3. " SEQOVRW1C ,End of sequence conversion" "Not end,End"
|
|
eventfld.long 0x00 2. " RDYW1C ,Ready to convert" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RDY ,ADC ready" "Not ready,Ready"
|
|
sif cpuis("ADSP-SC57?")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HADC_DATA0,HADC Channel 0 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "HADC_DATA1,HADC Channel 1 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "HADC_DATA2,HADC Channel 2 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "HADC_DATA3,HADC Channel 3 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "HADC_DATA4,HADC Channel 4 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "HADC_DATA5,HADC Channel 5 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "HADC_DATA6,HADC Channel 6 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "HADC_DATA7,HADC Channel 7 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HADC_DATA0,HADC Channel 0 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "HADC_DATA1,HADC Channel 1 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "HADC_DATA2,HADC Channel 2 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "HADC_DATA3,HADC Channel 3 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "HADC_DATA4,HADC Channel 4 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "HADC_DATA5,HADC Channel 5 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "HADC_DATA6,HADC Channel 6 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "HADC_DATA7,HADC Channel 7 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "HADC_DATA8,HADC Channel 8 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HADC_DATA9,HADC Channel 9 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "HADC_DATA10,HADC Channel 10 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "HADC_DATA11,HADC Channel 11 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "HADC_DATA12,HADC Channel 12 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "HADC_DATA13,HADC Channel 13 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "HADC_DATA14,HADC Channel 14 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "HADC_DATA15,HADC Channel 15 Data Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted data"
|
|
endif
|
|
sif !cpuis("ADSP-SC57?")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "HADC_DBG1,Debug Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " TRIM ,OTP bits for HADC"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPU (System Protection Unit)"
|
|
base ad:0x3108B000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SPU_CTL,SPU Control Register"
|
|
bitfld.long 0x00 16. " WPLCK ,Write protect register lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " PINTEN ,Protection violation interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " GLCK ,Global lock"
|
|
line.long 0x04 "SPU_STAT,SPU Status Register"
|
|
eventfld.long 0x04 31. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error" "No error,Error"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
eventfld.long 0x04 12. " VIRQ ,Violation interrupt request" "Not detected,Detected"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x04 0. " GLCK ,Global lock status" "Unlocked,Locked"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "SPU_WP58,SPU Write Protect Register 58"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "SPU_WP59,SPU Write Protect Register 59"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "SPU_WP60,SPU Write Protect Register 60"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "SPU_WP61,SPU Write Protect Register 61"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "SPU_WP62,SPU Write Protect Register 62"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "SPU_WP63,SPU Write Protect Register 63"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "SPU_WP64,SPU Write Protect Register 64"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "SPU_WP65,SPU Write Protect Register 65"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "SPU_WP66,SPU Write Protect Register 66"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "SPU_WP67,SPU Write Protect Register 67"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "SPU_WP68,SPU Write Protect Register 68"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "SPU_WP69,SPU Write Protect Register 69"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "SPU_WP70,SPU Write Protect Register 70"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "SPU_WP71,SPU Write Protect Register 71"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "SPU_WP72,SPU Write Protect Register 72"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "SPU_WP73,SPU Write Protect Register 73"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "SPU_WP74,SPU Write Protect Register 74"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "SPU_WP75,SPU Write Protect Register 75"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "SPU_WP76,SPU Write Protect Register 76"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "SPU_WP77,SPU Write Protect Register 77"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "SPU_WP78,SPU Write Protect Register 78"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "SPU_WP79,SPU Write Protect Register 79"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "SPU_WP80,SPU Write Protect Register 80"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "SPU_WP81,SPU Write Protect Register 81"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "SPU_WP82,SPU Write Protect Register 82"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "SPU_WP83,SPU Write Protect Register 83"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "SPU_WP84,SPU Write Protect Register 84"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "SPU_WP85,SPU Write Protect Register 85"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "SPU_WP86,SPU Write Protect Register 86"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "SPU_WP87,SPU Write Protect Register 87"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "SPU_WP88,SPU Write Protect Register 88"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "SPU_WP89,SPU Write Protect Register 89"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "SPU_WP90,SPU Write Protect Register 90"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "SPU_WP91,SPU Write Protect Register 91"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "SPU_WP92,SPU Write Protect Register 92"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "SPU_WP93,SPU Write Protect Register 93"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "SPU_WP94,SPU Write Protect Register 94"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "SPU_WP95,SPU Write Protect Register 95"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "SPU_WP96,SPU Write Protect Register 96"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "SPU_WP97,SPU Write Protect Register 97"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "SPU_WP98,SPU Write Protect Register 98"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "SPU_WP99,SPU Write Protect Register 99"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "SPU_WP100,SPU Write Protect Register 100"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "SPU_WP101,SPU Write Protect Register 101"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "SPU_WP102,SPU Write Protect Register 102"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "SPU_WP103,SPU Write Protect Register 103"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "SPU_WP104,SPU Write Protect Register 104"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "SPU_WP105,SPU Write Protect Register 105"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "SPU_WP106,SPU Write Protect Register 106"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "SPU_WP107,SPU Write Protect Register 107"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "SPU_WP108,SPU Write Protect Register 108"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "SPU_WP109,SPU Write Protect Register 109"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "SPU_WP110,SPU Write Protect Register 110"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "SPU_WP111,SPU Write Protect Register 111"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "SPU_WP112,SPU Write Protect Register 112"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "SPU_WP113,SPU Write Protect Register 113"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "SPU_WP114,SPU Write Protect Register 114"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "SPU_WP115,SPU Write Protect Register 115"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "SPU_WP116,SPU Write Protect Register 116"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "SPU_WP117,SPU Write Protect Register 117"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "SPU_WP118,SPU Write Protect Register 118"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "SPU_WP119,SPU Write Protect Register 119"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "SPU_WP120,SPU Write Protect Register 120"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "SPU_WP121,SPU Write Protect Register 121"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "SPU_WP122,SPU Write Protect Register 122"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "SPU_WP123,SPU Write Protect Register 123"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "SPU_WP124,SPU Write Protect Register 124"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "SPU_WP125,SPU Write Protect Register 125"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "SPU_WP126,SPU Write Protect Register 126"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "SPU_WP127,SPU Write Protect Register 127"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPU_WP128,SPU Write Protect Register 128"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SPU_WP129,SPU Write Protect Register 129"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
elif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E8++0x03
|
|
line.long 0x00 "SPU_WP58,SPU Write Protect Register 58"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "SPU_WP58,SPU Write Protect Register 58"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4EC++0x03
|
|
line.long 0x00 "SPU_WP59,SPU Write Protect Register 59"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "SPU_WP59,SPU Write Protect Register 59"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "SPU_WP60,SPU Write Protect Register 60"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "SPU_WP60,SPU Write Protect Register 60"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4F4++0x03
|
|
line.long 0x00 "SPU_WP61,SPU Write Protect Register 61"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "SPU_WP61,SPU Write Protect Register 61"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4F8++0x03
|
|
line.long 0x00 "SPU_WP62,SPU Write Protect Register 62"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "SPU_WP62,SPU Write Protect Register 62"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4FC++0x03
|
|
line.long 0x00 "SPU_WP63,SPU Write Protect Register 63"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "SPU_WP63,SPU Write Protect Register 63"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x500++0x03
|
|
line.long 0x00 "SPU_WP64,SPU Write Protect Register 64"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "SPU_WP64,SPU Write Protect Register 64"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x504++0x03
|
|
line.long 0x00 "SPU_WP65,SPU Write Protect Register 65"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "SPU_WP65,SPU Write Protect Register 65"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x508++0x03
|
|
line.long 0x00 "SPU_WP66,SPU Write Protect Register 66"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "SPU_WP66,SPU Write Protect Register 66"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x50C++0x03
|
|
line.long 0x00 "SPU_WP67,SPU Write Protect Register 67"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "SPU_WP67,SPU Write Protect Register 67"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x510++0x03
|
|
line.long 0x00 "SPU_WP68,SPU Write Protect Register 68"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "SPU_WP68,SPU Write Protect Register 68"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x514++0x03
|
|
line.long 0x00 "SPU_WP69,SPU Write Protect Register 69"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "SPU_WP69,SPU Write Protect Register 69"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x518++0x03
|
|
line.long 0x00 "SPU_WP70,SPU Write Protect Register 70"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "SPU_WP70,SPU Write Protect Register 70"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x51C++0x03
|
|
line.long 0x00 "SPU_WP71,SPU Write Protect Register 71"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "SPU_WP71,SPU Write Protect Register 71"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x520++0x03
|
|
line.long 0x00 "SPU_WP72,SPU Write Protect Register 72"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "SPU_WP72,SPU Write Protect Register 72"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x524++0x03
|
|
line.long 0x00 "SPU_WP73,SPU Write Protect Register 73"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "SPU_WP73,SPU Write Protect Register 73"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x528++0x03
|
|
line.long 0x00 "SPU_WP74,SPU Write Protect Register 74"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "SPU_WP74,SPU Write Protect Register 74"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x52C++0x03
|
|
line.long 0x00 "SPU_WP75,SPU Write Protect Register 75"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "SPU_WP75,SPU Write Protect Register 75"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x530++0x03
|
|
line.long 0x00 "SPU_WP76,SPU Write Protect Register 76"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "SPU_WP76,SPU Write Protect Register 76"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x534++0x03
|
|
line.long 0x00 "SPU_WP77,SPU Write Protect Register 77"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "SPU_WP77,SPU Write Protect Register 77"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x538++0x03
|
|
line.long 0x00 "SPU_WP78,SPU Write Protect Register 78"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "SPU_WP78,SPU Write Protect Register 78"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x53C++0x03
|
|
line.long 0x00 "SPU_WP79,SPU Write Protect Register 79"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "SPU_WP79,SPU Write Protect Register 79"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x540++0x03
|
|
line.long 0x00 "SPU_WP80,SPU Write Protect Register 80"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "SPU_WP80,SPU Write Protect Register 80"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x544++0x03
|
|
line.long 0x00 "SPU_WP81,SPU Write Protect Register 81"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "SPU_WP81,SPU Write Protect Register 81"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x548++0x03
|
|
line.long 0x00 "SPU_WP82,SPU Write Protect Register 82"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "SPU_WP82,SPU Write Protect Register 82"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x54C++0x03
|
|
line.long 0x00 "SPU_WP83,SPU Write Protect Register 83"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "SPU_WP83,SPU Write Protect Register 83"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x550++0x03
|
|
line.long 0x00 "SPU_WP84,SPU Write Protect Register 84"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "SPU_WP84,SPU Write Protect Register 84"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x554++0x03
|
|
line.long 0x00 "SPU_WP85,SPU Write Protect Register 85"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "SPU_WP85,SPU Write Protect Register 85"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x558++0x03
|
|
line.long 0x00 "SPU_WP86,SPU Write Protect Register 86"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "SPU_WP86,SPU Write Protect Register 86"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x55C++0x03
|
|
line.long 0x00 "SPU_WP87,SPU Write Protect Register 87"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "SPU_WP87,SPU Write Protect Register 87"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x560++0x03
|
|
line.long 0x00 "SPU_WP88,SPU Write Protect Register 88"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "SPU_WP88,SPU Write Protect Register 88"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x564++0x03
|
|
line.long 0x00 "SPU_WP89,SPU Write Protect Register 89"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "SPU_WP89,SPU Write Protect Register 89"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x568++0x03
|
|
line.long 0x00 "SPU_WP90,SPU Write Protect Register 90"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "SPU_WP90,SPU Write Protect Register 90"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x56C++0x03
|
|
line.long 0x00 "SPU_WP91,SPU Write Protect Register 91"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "SPU_WP91,SPU Write Protect Register 91"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x570++0x03
|
|
line.long 0x00 "SPU_WP92,SPU Write Protect Register 92"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "SPU_WP92,SPU Write Protect Register 92"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x574++0x03
|
|
line.long 0x00 "SPU_WP93,SPU Write Protect Register 93"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "SPU_WP93,SPU Write Protect Register 93"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x578++0x03
|
|
line.long 0x00 "SPU_WP94,SPU Write Protect Register 94"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "SPU_WP94,SPU Write Protect Register 94"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x57C++0x03
|
|
line.long 0x00 "SPU_WP95,SPU Write Protect Register 95"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "SPU_WP95,SPU Write Protect Register 95"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x580++0x03
|
|
line.long 0x00 "SPU_WP96,SPU Write Protect Register 96"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "SPU_WP96,SPU Write Protect Register 96"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x584++0x03
|
|
line.long 0x00 "SPU_WP97,SPU Write Protect Register 97"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "SPU_WP97,SPU Write Protect Register 97"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x588++0x03
|
|
line.long 0x00 "SPU_WP98,SPU Write Protect Register 98"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "SPU_WP98,SPU Write Protect Register 98"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x58C++0x03
|
|
line.long 0x00 "SPU_WP99,SPU Write Protect Register 99"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "SPU_WP99,SPU Write Protect Register 99"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x590++0x03
|
|
line.long 0x00 "SPU_WP100,SPU Write Protect Register 100"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "SPU_WP100,SPU Write Protect Register 100"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x594++0x03
|
|
line.long 0x00 "SPU_WP101,SPU Write Protect Register 101"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "SPU_WP101,SPU Write Protect Register 101"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x598++0x03
|
|
line.long 0x00 "SPU_WP102,SPU Write Protect Register 102"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "SPU_WP102,SPU Write Protect Register 102"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x59C++0x03
|
|
line.long 0x00 "SPU_WP103,SPU Write Protect Register 103"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "SPU_WP103,SPU Write Protect Register 103"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5A0++0x03
|
|
line.long 0x00 "SPU_WP104,SPU Write Protect Register 104"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "SPU_WP104,SPU Write Protect Register 104"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5A4++0x03
|
|
line.long 0x00 "SPU_WP105,SPU Write Protect Register 105"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "SPU_WP105,SPU Write Protect Register 105"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5A8++0x03
|
|
line.long 0x00 "SPU_WP106,SPU Write Protect Register 106"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "SPU_WP106,SPU Write Protect Register 106"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5AC++0x03
|
|
line.long 0x00 "SPU_WP107,SPU Write Protect Register 107"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "SPU_WP107,SPU Write Protect Register 107"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5B0++0x03
|
|
line.long 0x00 "SPU_WP108,SPU Write Protect Register 108"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "SPU_WP108,SPU Write Protect Register 108"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5B4++0x03
|
|
line.long 0x00 "SPU_WP109,SPU Write Protect Register 109"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "SPU_WP109,SPU Write Protect Register 109"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5B8++0x03
|
|
line.long 0x00 "SPU_WP110,SPU Write Protect Register 110"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "SPU_WP110,SPU Write Protect Register 110"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5BC++0x03
|
|
line.long 0x00 "SPU_WP111,SPU Write Protect Register 111"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "SPU_WP111,SPU Write Protect Register 111"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5C0++0x03
|
|
line.long 0x00 "SPU_WP112,SPU Write Protect Register 112"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "SPU_WP112,SPU Write Protect Register 112"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5C4++0x03
|
|
line.long 0x00 "SPU_WP113,SPU Write Protect Register 113"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "SPU_WP113,SPU Write Protect Register 113"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5C8++0x03
|
|
line.long 0x00 "SPU_WP114,SPU Write Protect Register 114"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "SPU_WP114,SPU Write Protect Register 114"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5CC++0x03
|
|
line.long 0x00 "SPU_WP115,SPU Write Protect Register 115"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "SPU_WP115,SPU Write Protect Register 115"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5D0++0x03
|
|
line.long 0x00 "SPU_WP116,SPU Write Protect Register 116"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "SPU_WP116,SPU Write Protect Register 116"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5D4++0x03
|
|
line.long 0x00 "SPU_WP117,SPU Write Protect Register 117"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "SPU_WP117,SPU Write Protect Register 117"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5D8++0x03
|
|
line.long 0x00 "SPU_WP118,SPU Write Protect Register 118"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "SPU_WP118,SPU Write Protect Register 118"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5DC++0x03
|
|
line.long 0x00 "SPU_WP119,SPU Write Protect Register 119"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "SPU_WP119,SPU Write Protect Register 119"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5E0++0x03
|
|
line.long 0x00 "SPU_WP120,SPU Write Protect Register 120"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "SPU_WP120,SPU Write Protect Register 120"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5E4++0x03
|
|
line.long 0x00 "SPU_WP121,SPU Write Protect Register 121"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "SPU_WP121,SPU Write Protect Register 121"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5E8++0x03
|
|
line.long 0x00 "SPU_WP122,SPU Write Protect Register 122"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "SPU_WP122,SPU Write Protect Register 122"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5EC++0x03
|
|
line.long 0x00 "SPU_WP123,SPU Write Protect Register 123"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "SPU_WP123,SPU Write Protect Register 123"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5F0++0x03
|
|
line.long 0x00 "SPU_WP124,SPU Write Protect Register 124"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "SPU_WP124,SPU Write Protect Register 124"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5F4++0x03
|
|
line.long 0x00 "SPU_WP125,SPU Write Protect Register 125"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "SPU_WP125,SPU Write Protect Register 125"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5F8++0x03
|
|
line.long 0x00 "SPU_WP126,SPU Write Protect Register 126"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "SPU_WP126,SPU Write Protect Register 126"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5FC++0x03
|
|
line.long 0x00 "SPU_WP127,SPU Write Protect Register 127"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "SPU_WP127,SPU Write Protect Register 127"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "SPU_WP128,SPU Write Protect Register 128"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPU_WP128,SPU Write Protect Register 128"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "SPU_WP129,SPU Write Protect Register 129"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SPU_WP129,SPU Write Protect Register 129"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x608++0x03
|
|
line.long 0x00 "SPU_WP130,SPU Write Protect Register 130"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SPU_WP130,SPU Write Protect Register 130"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x60C++0x03
|
|
line.long 0x00 "SPU_WP131,SPU Write Protect Register 131"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SPU_WP131,SPU Write Protect Register 131"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "SPU_WP132,SPU Write Protect Register 132"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SPU_WP132,SPU Write Protect Register 132"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x614++0x03
|
|
line.long 0x00 "SPU_WP133,SPU Write Protect Register 133"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SPU_WP133,SPU Write Protect Register 133"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x618++0x03
|
|
line.long 0x00 "SPU_WP134,SPU Write Protect Register 134"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SPU_WP134,SPU Write Protect Register 134"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x61C++0x03
|
|
line.long 0x00 "SPU_WP135,SPU Write Protect Register 135"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SPU_WP135,SPU Write Protect Register 135"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "SPU_WP136,SPU Write Protect Register 136"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SPU_WP136,SPU Write Protect Register 136"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x624++0x03
|
|
line.long 0x00 "SPU_WP137,SPU Write Protect Register 137"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SPU_WP137,SPU Write Protect Register 137"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x628++0x03
|
|
line.long 0x00 "SPU_WP138,SPU Write Protect Register 138"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SPU_WP138,SPU Write Protect Register 138"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x62C++0x03
|
|
line.long 0x00 "SPU_WP139,SPU Write Protect Register 139"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SPU_WP139,SPU Write Protect Register 139"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "SPU_WP140,SPU Write Protect Register 140"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SPU_WP140,SPU Write Protect Register 140"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x634++0x03
|
|
line.long 0x00 "SPU_WP141,SPU Write Protect Register 141"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SPU_WP141,SPU Write Protect Register 141"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x638++0x03
|
|
line.long 0x00 "SPU_WP142,SPU Write Protect Register 142"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SPU_WP142,SPU Write Protect Register 142"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x63C++0x03
|
|
line.long 0x00 "SPU_WP143,SPU Write Protect Register 143"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SPU_WP143,SPU Write Protect Register 143"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "SPU_WP144,SPU Write Protect Register 144"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SPU_WP144,SPU Write Protect Register 144"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x644++0x03
|
|
line.long 0x00 "SPU_WP145,SPU Write Protect Register 145"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SPU_WP145,SPU Write Protect Register 145"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x648++0x03
|
|
line.long 0x00 "SPU_WP146,SPU Write Protect Register 146"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SPU_WP146,SPU Write Protect Register 146"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x64C++0x03
|
|
line.long 0x00 "SPU_WP147,SPU Write Protect Register 147"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SPU_WP147,SPU Write Protect Register 147"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x650++0x03
|
|
line.long 0x00 "SPU_WP148,SPU Write Protect Register 148"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SPU_WP148,SPU Write Protect Register 148"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "SPU_WP149,SPU Write Protect Register 149"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SPU_WP149,SPU Write Protect Register 149"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "SPU_WP150,SPU Write Protect Register 150"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SPU_WP150,SPU Write Protect Register 150"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x65C++0x03
|
|
line.long 0x00 "SPU_WP151,SPU Write Protect Register 151"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SPU_WP151,SPU Write Protect Register 151"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "SPU_WP152,SPU Write Protect Register 152"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SPU_WP152,SPU Write Protect Register 152"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x664++0x03
|
|
line.long 0x00 "SPU_WP153,SPU Write Protect Register 153"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SPU_WP153,SPU Write Protect Register 153"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x668++0x03
|
|
line.long 0x00 "SPU_WP154,SPU Write Protect Register 154"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SPU_WP154,SPU Write Protect Register 154"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x66C++0x03
|
|
line.long 0x00 "SPU_WP155,SPU Write Protect Register 155"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SPU_WP155,SPU Write Protect Register 155"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "SPU_WP156,SPU Write Protect Register 156"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SPU_WP156,SPU Write Protect Register 156"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x674++0x03
|
|
line.long 0x00 "SPU_WP157,SPU Write Protect Register 157"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SPU_WP157,SPU Write Protect Register 157"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x678++0x03
|
|
line.long 0x00 "SPU_WP158,SPU Write Protect Register 158"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SPU_WP158,SPU Write Protect Register 158"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x67C++0x03
|
|
line.long 0x00 "SPU_WP159,SPU Write Protect Register 159"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SPU_WP159,SPU Write Protect Register 159"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x680++0x03
|
|
line.long 0x00 "SPU_WP160,SPU Write Protect Register 160"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SPU_WP160,SPU Write Protect Register 160"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x684++0x03
|
|
line.long 0x00 "SPU_WP161,SPU Write Protect Register 161"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SPU_WP161,SPU Write Protect Register 161"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "SPU_WP162,SPU Write Protect Register 162"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SPU_WP162,SPU Write Protect Register 162"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "SPU_WP163,SPU Write Protect Register 163"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SPU_WP163,SPU Write Protect Register 163"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "SPU_WP164,SPU Write Protect Register 164"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SPU_WP164,SPU Write Protect Register 164"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x694++0x03
|
|
line.long 0x00 "SPU_WP165,SPU Write Protect Register 165"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SPU_WP165,SPU Write Protect Register 165"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x698++0x03
|
|
line.long 0x00 "SPU_WP166,SPU Write Protect Register 166"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SPU_WP166,SPU Write Protect Register 166"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "SPU_WP167,SPU Write Protect Register 167"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SPU_WP167,SPU Write Protect Register 167"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "SPU_WP168,SPU Write Protect Register 168"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SPU_WP168,SPU Write Protect Register 168"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6A4++0x03
|
|
line.long 0x00 "SPU_WP169,SPU Write Protect Register 169"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SPU_WP169,SPU Write Protect Register 169"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6A8++0x03
|
|
line.long 0x00 "SPU_WP170,SPU Write Protect Register 170"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SPU_WP170,SPU Write Protect Register 170"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "SPU_WP171,SPU Write Protect Register 171"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SPU_WP171,SPU Write Protect Register 171"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "SPU_WP172,SPU Write Protect Register 172"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SPU_WP172,SPU Write Protect Register 172"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6B4++0x03
|
|
line.long 0x00 "SPU_WP173,SPU Write Protect Register 173"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SPU_WP173,SPU Write Protect Register 173"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6B8++0x03
|
|
line.long 0x00 "SPU_WP174,SPU Write Protect Register 174"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SPU_WP174,SPU Write Protect Register 174"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "SPU_WP175,SPU Write Protect Register 175"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SPU_WP175,SPU Write Protect Register 175"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6C0++0x03
|
|
line.long 0x00 "SPU_WP176,SPU Write Protect Register 176"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SPU_WP176,SPU Write Protect Register 176"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6C4++0x03
|
|
line.long 0x00 "SPU_WP177,SPU Write Protect Register 177"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SPU_WP177,SPU Write Protect Register 177"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6C8++0x03
|
|
line.long 0x00 "SPU_WP178,SPU Write Protect Register 178"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SPU_WP178,SPU Write Protect Register 178"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "SPU_WP179,SPU Write Protect Register 179"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SPU_WP179,SPU Write Protect Register 179"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "SPU_WP180,SPU Write Protect Register 180"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SPU_WP180,SPU Write Protect Register 180"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6D4++0x03
|
|
line.long 0x00 "SPU_WP181,SPU Write Protect Register 181"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SPU_WP181,SPU Write Protect Register 181"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6D8++0x03
|
|
line.long 0x00 "SPU_WP182,SPU Write Protect Register 182"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SPU_WP182,SPU Write Protect Register 182"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "SPU_WP183,SPU Write Protect Register 183"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SPU_WP183,SPU Write Protect Register 183"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "SPU_WP184,SPU Write Protect Register 184"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SPU_WP184,SPU Write Protect Register 184"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "SPU_WP185,SPU Write Protect Register 185"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SPU_WP185,SPU Write Protect Register 185"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "SPU_WP186,SPU Write Protect Register 186"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SPU_WP186,SPU Write Protect Register 186"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "SPU_WP187,SPU Write Protect Register 187"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SPU_WP187,SPU Write Protect Register 187"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0x10000)==0x10000)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "SPU_WP188,SPU Write Protect Register 188"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SPU_WP188,SPU Write Protect Register 188"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SPU_SECURECTL,SPU Secure Control Register"
|
|
bitfld.long 0x00 16. " SCRLCK ,Secure register lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 14. " SINTEN ,Secure violation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MSECCLR ,Master secure clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSECCLR ,Slave secure clear" "No action,Clear"
|
|
rgroup.long 0x84C++0x03
|
|
line.long 0x00 "SPU_SECURECHK,SPU Secure Check Register"
|
|
if (((per.l(ad:0x3108B000+0x840))&0x10000)==0x00)&&(((per.l(ad:0x3108B000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SPU_SECUREC0,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
rgroup.long 0x984++0x03
|
|
line.long 0x00 "SPU_SECUREC1,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SPU_SECUREC2,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC30++0x03
|
|
line.long 0x00 "SPU_SECUREP140,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC34++0x03
|
|
line.long 0x00 "SPU_SECUREP141,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC38++0x03
|
|
line.long 0x00 "SPU_SECUREP142,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC3C++0x03
|
|
line.long 0x00 "SPU_SECUREP143,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "SPU_SECUREP144,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC44++0x03
|
|
line.long 0x00 "SPU_SECUREP145,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "SPU_SECUREP146,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC4C++0x03
|
|
line.long 0x00 "SPU_SECUREP147,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "SPU_SECUREP148,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC54++0x03
|
|
line.long 0x00 "SPU_SECUREP149,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "SPU_SECUREP150,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC5C++0x03
|
|
line.long 0x00 "SPU_SECUREP151,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "SPU_SECUREP152,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC64++0x03
|
|
line.long 0x00 "SPU_SECUREP153,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "SPU_SECUREP154,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC6C++0x03
|
|
line.long 0x00 "SPU_SECUREP155,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC70++0x03
|
|
line.long 0x00 "SPU_SECUREP156,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC74++0x03
|
|
line.long 0x00 "SPU_SECUREP157,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC78++0x03
|
|
line.long 0x00 "SPU_SECUREP158,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC7C++0x03
|
|
line.long 0x00 "SPU_SECUREP159,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "SPU_SECUREP160,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC84++0x03
|
|
line.long 0x00 "SPU_SECUREP161,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "SPU_SECUREP162,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC8C++0x03
|
|
line.long 0x00 "SPU_SECUREP163,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "SPU_SECUREP164,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC94++0x03
|
|
line.long 0x00 "SPU_SECUREP165,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC98++0x03
|
|
line.long 0x00 "SPU_SECUREP166,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC9C++0x03
|
|
line.long 0x00 "SPU_SECUREP167,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "SPU_SECUREP168,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCA4++0x03
|
|
line.long 0x00 "SPU_SECUREP169,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "SPU_SECUREP170,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCAC++0x03
|
|
line.long 0x00 "SPU_SECUREP171,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCB0++0x03
|
|
line.long 0x00 "SPU_SECUREP172,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCB4++0x03
|
|
line.long 0x00 "SPU_SECUREP173,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCB8++0x03
|
|
line.long 0x00 "SPU_SECUREP174,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCBC++0x03
|
|
line.long 0x00 "SPU_SECUREP175,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "SPU_SECUREP176,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCC4++0x03
|
|
line.long 0x00 "SPU_SECUREP177,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCC8++0x03
|
|
line.long 0x00 "SPU_SECUREP178,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCCC++0x03
|
|
line.long 0x00 "SPU_SECUREP179,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "SPU_SECUREP180,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCD4++0x03
|
|
line.long 0x00 "SPU_SECUREP181,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "SPU_SECUREP182,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCDC++0x03
|
|
line.long 0x00 "SPU_SECUREP183,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "SPU_SECUREP184,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCE4++0x03
|
|
line.long 0x00 "SPU_SECUREP185,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "SPU_SECUREP186,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCEC++0x03
|
|
line.long 0x00 "SPU_SECUREP187,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "SPU_SECUREP188,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SPU_SECUREC0,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "SPU_SECUREC1,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SPU_SECUREC2,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "SPU_SECUREP140,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "SPU_SECUREP141,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "SPU_SECUREP142,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC3C++0x03
|
|
line.long 0x00 "SPU_SECUREP143,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "SPU_SECUREP144,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "SPU_SECUREP145,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "SPU_SECUREP146,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC4C++0x03
|
|
line.long 0x00 "SPU_SECUREP147,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "SPU_SECUREP148,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "SPU_SECUREP149,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "SPU_SECUREP150,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC5C++0x03
|
|
line.long 0x00 "SPU_SECUREP151,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "SPU_SECUREP152,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "SPU_SECUREP153,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "SPU_SECUREP154,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC6C++0x03
|
|
line.long 0x00 "SPU_SECUREP155,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "SPU_SECUREP156,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "SPU_SECUREP157,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "SPU_SECUREP158,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC7C++0x03
|
|
line.long 0x00 "SPU_SECUREP159,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "SPU_SECUREP160,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "SPU_SECUREP161,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "SPU_SECUREP162,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC8C++0x03
|
|
line.long 0x00 "SPU_SECUREP163,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "SPU_SECUREP164,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "SPU_SECUREP165,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "SPU_SECUREP166,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC9C++0x03
|
|
line.long 0x00 "SPU_SECUREP167,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "SPU_SECUREP168,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "SPU_SECUREP169,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "SPU_SECUREP170,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCAC++0x03
|
|
line.long 0x00 "SPU_SECUREP171,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "SPU_SECUREP172,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "SPU_SECUREP173,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "SPU_SECUREP174,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCBC++0x03
|
|
line.long 0x00 "SPU_SECUREP175,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "SPU_SECUREP176,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCC4++0x03
|
|
line.long 0x00 "SPU_SECUREP177,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "SPU_SECUREP178,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "SPU_SECUREP179,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "SPU_SECUREP180,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "SPU_SECUREP181,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "SPU_SECUREP182,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCDC++0x03
|
|
line.long 0x00 "SPU_SECUREP183,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "SPU_SECUREP184,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCE4++0x03
|
|
line.long 0x00 "SPU_SECUREP185,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "SPU_SECUREP186,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCEC++0x03
|
|
line.long 0x00 "SPU_SECUREP187,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "SPU_SECUREP188,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PKA (Public Key Accelerator)"
|
|
base ad:0x310D4000
|
|
width 16.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PKA_APTR,PKA VECTOR_A Address"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to vector A"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PKA_BPTR,PKA VECTOR_B Address"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to vector B"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PKA_CPTR,PKA VECTOR_C Address"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to vector C"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PKA_DPTR,PKA VECTOR_D Address"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to vector D"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "PKA_ALEN,PKA VECTOR_A Length"
|
|
hexmask.long.word 0x00 0.--8. 1. " VALUE ,Length of vector A"
|
|
line.long 0x04 "PKA_BLEN,PKA VECTOR_B Length"
|
|
hexmask.long.word 0x04 0.--8. 1. " VALUE ,Length of vector B"
|
|
line.long 0x08 "PKA_SHIFT,PKA Bit Shift Value"
|
|
bitfld.long 0x08 0.--4. " VALUE ,Bits to shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "PKA_FUNC,PKA Function"
|
|
bitfld.long 0x0C 24. " STALLRSLT ,Stall result" "0,1"
|
|
bitfld.long 0x0C 15. " RUN ,Run" "Stopped,Running"
|
|
bitfld.long 0x0C 12.--14. " SEQOPS ,Sequencer operation select" "None,ExpMod-CRT,ExpMod-ACT4,ECC-ADD,ExpMod-ACT2,ECC-MUL,ExpMod-variable,ModInv"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CPY ,Copy" "Not copy,Copy"
|
|
bitfld.long 0x0C 10. " CMP ,Perform compare operation" "Not performed,Performed"
|
|
bitfld.long 0x0C 9. " MODULO ,Perform modulo operation" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " DIV ,Perform divide operation" "Not performed,Performed"
|
|
bitfld.long 0x0C 7. " LSHFT ,Perform left shift operation" "Not performed,Performed"
|
|
bitfld.long 0x0C 6. " RSHFT ,Perform right shift operation" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SUB ,Perform subtract operation" "Not performed,Performed"
|
|
bitfld.long 0x0C 4. " ADD ,Perform add operation" "Not performed,Performed"
|
|
bitfld.long 0x0C 3. " MSONE ,Most significant one" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ADDSUB ,Perform combined add/subtract operation" "Not performed,Performed"
|
|
bitfld.long 0x0C 0. " MULT ,Perform multiply operation" "Not performed,Performed"
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "PKA_COMPARE,PKA Compare Result"
|
|
bitfld.long 0x00 2. " AGTB ,Vector A is greater than vector B" "No,Yes"
|
|
bitfld.long 0x00 1. " ALTB ,Vector A is less than vector B" "No,Yes"
|
|
bitfld.long 0x00 0. " AEQB ,Vector A is equal to vector B" "No,Yes"
|
|
line.long 0x04 "PKA_RESULTMSW,PKA Most-Significant-Word Of Result Vector"
|
|
bitfld.long 0x04 15. " ZERO ,Result is zero" "No,Yes"
|
|
hexmask.long.word 0x04 0.--10. 1. " ADDR ,Address of Most-significant non-zero word"
|
|
line.long 0x08 "PKA_DIVMSW,PKA Most-Significant-Word Of Divide Remainder"
|
|
bitfld.long 0x08 15. " ZERO ,Remainder result vector is zeros" "No,Yes"
|
|
hexmask.long.word 0x08 0.--10. 1. " ADDR ,Address of Most-significant non-zero word"
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "PKA_RAM,PKA Start Of PKA RAM Space"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PKIC (Public Key Interrupt Controller)"
|
|
base ad:0x310D8000
|
|
width 23.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PKIC_POL_CTL,PKIC Polarity Control Register"
|
|
bitfld.long 0x00 5. " SLERRINT ,Slave error IRQ (level/edge)" "Low/falling,High/rising"
|
|
bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ (level/edge)" "Low/falling,High/rising"
|
|
bitfld.long 0x00 1. " PKAINT1 ,PKA completion IRQ (level/edge)" "Low/falling,High/rising"
|
|
line.long 0x04 "PKIC_TYPE_CTL,PKIC Type Control Register"
|
|
bitfld.long 0x04 5. " SLERRINT ,Slave error IRQ" "Level,Edge"
|
|
bitfld.long 0x04 3. " TRNGINT ,TRNG IRQ" "Level,Edge"
|
|
bitfld.long 0x04 1. " PKAINT1 ,PKA completion IRQ" "Level,Edge"
|
|
line.long 0x08 "PKIC_EN_CTL_set/clr,PKIC Enable Control Register"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x14 5. " SLERRINT ,Slave error IRQ" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x14 3. " TRNGINT ,TRNG IRQ" "Disabled,Enabled"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x14 1. " PKAINT1 ,PKA completion IRQ" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKIC_RAW_STAT,PKIC Raw Status Register"
|
|
bitfld.long 0x00 5. " SLERRINT ,Slave error IRQ" "Inactive,Pending"
|
|
bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "Inactive,Pending"
|
|
bitfld.long 0x00 1. " PKAINT1 ,PKA completion IRQ" "Inactive,Pending"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "PKIC_ACK,PKIC Acknowledge Register"
|
|
bitfld.long 0x00 5. " SLERRINT ,Slave error IRQ" "Not acknowledge,Acknowledge"
|
|
bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "Not acknowledge,Acknowledge"
|
|
bitfld.long 0x00 1. " PKAINT1 ,PKA completion IRQ" "Not acknowledge,Acknowledge"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PKIC_EN_STAT,PKIC Enabled Status Register"
|
|
bitfld.long 0x00 5. " SLERRINT ,Slave error IRQ" "Inactive,Pending"
|
|
bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "Inactive,Pending"
|
|
bitfld.long 0x00 1. " PKAINT1 ,PKA completion IRQ" "Inactive,Pending"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SWU (System Watchpoint Unit)"
|
|
tree "SWU0"
|
|
base ad:0x31015000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU0_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU0_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31015000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU0_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU0_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU0_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU0_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU0_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU0_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31015000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU0_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU0_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU0_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU0_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU0_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU0_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31015000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU0_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU0_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU0_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU0_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU0_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU0_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31015000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU0_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU0_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU0_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU0_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU0_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU0_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU1"
|
|
base ad:0x31091000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU1_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU1_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31091000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU1_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU1_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU1_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU1_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU1_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU1_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31091000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU1_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU1_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU1_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU1_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU1_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU1_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31091000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU1_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU1_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU1_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU1_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU1_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU1_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31091000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU1_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU1_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU1_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU1_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU1_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU1_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU2"
|
|
base ad:0x31092000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU2_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU2_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31092000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU2_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU2_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU2_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU2_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU2_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU2_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31092000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU2_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU2_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU2_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU2_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU2_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU2_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31092000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU2_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU2_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU2_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU2_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU2_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU2_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31092000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU2_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU2_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU2_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU2_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU2_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU2_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU7"
|
|
base ad:0x31140000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU7_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU7_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31140000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU7_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU7_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU7_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU7_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU7_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU7_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU7_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU7_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU7_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31140000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU7_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU7_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU7_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU7_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU7_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU7_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU7_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU7_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU7_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31140000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU7_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU7_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU7_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU7_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU7_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU7_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU7_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU7_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU7_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31140000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU7_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU7_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU7_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU7_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU7_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU7_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU7_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU7_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU7_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU8"
|
|
base ad:0x31141000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU8_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU8_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31141000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU8_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU8_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU8_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU8_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU8_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU8_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU8_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU8_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU8_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31141000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU8_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU8_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU8_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU8_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU8_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU8_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU8_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU8_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU8_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31141000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU8_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU8_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU8_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU8_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU8_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU8_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU8_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU8_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU8_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31141000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU8_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU8_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU8_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU8_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU8_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU8_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU8_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU8_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU8_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU9"
|
|
base ad:0x31142000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU9_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU9_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31142000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU9_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU9_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU9_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU9_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU9_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU9_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU9_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU9_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU9_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31142000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU9_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU9_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU9_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU9_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU9_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU9_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU9_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU9_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU9_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31142000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU9_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU9_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU9_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU9_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU9_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU9_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU9_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU9_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU9_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31142000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU9_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU9_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU9_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU9_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU9_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU9_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU9_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU9_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU9_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU10"
|
|
base ad:0x31143000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU10_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU10_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31143000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU10_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU10_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU10_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU10_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU10_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU10_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU10_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU10_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU10_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31143000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU10_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU10_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU10_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU10_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU10_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU10_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU10_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU10_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU10_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31143000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU10_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU10_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU10_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU10_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU10_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU10_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU10_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU10_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU10_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31143000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU10_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU10_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU10_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU10_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU10_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU10_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU10_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU10_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU10_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU11"
|
|
base ad:0x31097000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU11_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU11_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31097000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU11_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU11_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU11_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU11_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU11_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU11_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU11_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU11_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU11_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31097000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU11_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU11_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU11_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU11_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU11_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU11_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU11_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU11_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU11_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31097000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU11_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU11_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU11_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU11_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU11_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU11_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU11_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU11_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU11_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31097000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU11_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU11_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU11_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU11_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU11_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU11_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU11_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU11_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU11_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU12"
|
|
base ad:0x31041000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU12_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU12_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x31041000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU12_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU12_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU12_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU12_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU12_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU12_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU12_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU12_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU12_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31041000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU12_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU12_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU12_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU12_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU12_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU12_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU12_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU12_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU12_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31041000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU12_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU12_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU12_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU12_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU12_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU12_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU12_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU12_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU12_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x31041000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU12_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU12_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU12_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU12_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU12_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU12_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU12_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU12_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU12_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU13"
|
|
base ad:0x3109E000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU13_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU13_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x3109E000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU13_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU13_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU13_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU13_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU13_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU13_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU13_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU13_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU13_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x3109E000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU13_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU13_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU13_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU13_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU13_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU13_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU13_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU13_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU13_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x3109E000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU13_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU13_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU13_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU13_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU13_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU13_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU13_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU13_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU13_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x3109E000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU13_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU13_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU13_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU13_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU13_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU13_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU13_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU13_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU13_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PKTE (Security Packet Engine)"
|
|
base ad:0x310CD000
|
|
width 22.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PKTE_CTL_STAT,PKTE Packet Engine Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PADCTLSTAT ,Pad Control/Pad Status"
|
|
rbitfld.long 0x00 20.--23. " EXTERRCD ,Extended Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 19. " EXTERR ,Extended Error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " SQNMERR ,Sequence Number Error" "No error,Error"
|
|
rbitfld.long 0x00 17. " PADERR ,Pad Error" "No error,Error"
|
|
rbitfld.long 0x00 16. " AUTHERR ,Authentication Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PADVAL ,Pad Value"
|
|
bitfld.long 0x00 6.--7. " PRNGMD ,PRNG Mode" "Not used,Initialization,Generate,Test"
|
|
sif !cpuis("ADSP-SC57?")
|
|
bitfld.long 0x00 5. " ENHLTMD ,Enable Halt Mode" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " HASHFINAL ,Hash Final" "Intermediate,Final"
|
|
bitfld.long 0x00 3. " INITARC4 ,Init ARC4" "Load,Read"
|
|
bitfld.long 0x00 1. " PERDY ,Packet Engine Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOSTRDY ,Host Ready" "Not ready,Ready"
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "PKTE_SRC_ADDR,PKTE Packet Engine Source Address"
|
|
line.long 0x04 "PKTE_DEST_ADDR,PKTE Packet Engine Destination Address"
|
|
line.long 0x08 "PKTE_SA_ADDR,PKTE Packet Engine SA Address"
|
|
line.long 0x0C "PKTE_STATE_ADDR,PKTE Packet Engine State Record Address"
|
|
line.long 0x10 "PKTE_ARC4STATE_ADDR,PKTE Packet Engine ARC4 State Record Address"
|
|
line.long 0x14 "PKTE_USERID,PKTE Packet Engine User ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PKTE_LEN,PKTE Packet Engine Length Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYPASS ,Bypass"
|
|
bitfld.long 0x00 23. " PEDONE ,PE Done" "Not done,Done"
|
|
rbitfld.long 0x00 22. " HSTRDY ,Host Ready" "Not ready,Ready"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TOTLEN ,Total length"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "PKTE_CDRBASE_ADDR,PKTE Packet Engine Command Descriptor Ring Base Address"
|
|
line.long 0x04 "PKTE_RDRBASE_ADDR,PKTE Packet Engine Result Descriptor Ring Base Address"
|
|
line.long 0x08 "PKTE_RING_CFG,PKTE Packet Engine Ring Configuration"
|
|
bitfld.long 0x08 31. " ENEXTTRIG ,Enable External Trigger" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--9. 1. " RINGSZ ,Ring Size"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PKTE_RING_THRESH,PKTE Packet Engine Ring Threshold Registers"
|
|
bitfld.long 0x00 31. " TOEN ,Timeout Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--29. " RDTO ,Read Descriptor Timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " RDRTHRSH ,Result Descriptor Ring Threshold"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " CDRTHRSH ,Command Descriptor Ring Threshold"
|
|
wgroup.long 0x90++0x03
|
|
line.long 0x00 "PKTE_CDSC_INCR,PKTE Packet Engine Command Descriptor Count Increment Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Command Descriptor Count Increment"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKTE_CDSC_CNT,PKTE Packet Engine Command Descriptor Count Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Command Descriptor Count"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKTE_RDSC_CNT,PKTE Packet Engine Result Descriptor Count Registers"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Result Descriptor Count"
|
|
wgroup.long 0x94++0x03
|
|
line.long 0x00 "PKTE_RDSC_DECR,PKTE Packet Engine Result Descriptor Count Decrement Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Read Count Decrement"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKTE_RING_PTR,PKTE Packet Engine Ring Pointer Status"
|
|
hexmask.long.word 0x00 16.--25. 1. " RDRPTR ,Result Descriptor Ring Write Pointer"
|
|
hexmask.long.word 0x00 0.--9. 1. " CDRPTR ,Command Descriptor Ring Read Pointer"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PKTE_RING_STAT,PKTE Packet Engine Ring Status"
|
|
eventfld.long 0x00 1. " RDRUNFL ,Result Descriptor Ring Underflow" "Underflow,Reset"
|
|
eventfld.long 0x00 0. " CDROVFL ,Command Descriptor Ring Overflow" "Underflow,Reset"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PKTE_CFG,PKTE Packet Engine Configuration Register"
|
|
bitfld.long 0x00 18. " SWPDAT ,Swap Data" "No swap,Swap"
|
|
bitfld.long 0x00 17. " SWPSA ,Swap SA" "No swap,Swap"
|
|
bitfld.long 0x00 16. " SWPCDRD ,Swap CD RD" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENCDRUPDT ,Enable CDR Update" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " MODE ,Packet Engine Mode" "Direct host mode,Descriptor ring disabled,Descriptor ring enabled,Autonomous ring mode"
|
|
bitfld.long 0x00 1. " RSTRING ,Reset Ring" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSTPE ,Reset Packet Engine" "No reset,Reset"
|
|
if (((per.l(ad:0x310CD000+0x100))&0x100)==0x00)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "PKTE_STAT,PKTE Packet Engine Status Register"
|
|
hexmask.long.word 0x00 22.--31. 1. " OBUFFULLCNT ,Output Buffer Full Count"
|
|
hexmask.long.word 0x00 12.--21. 1. " IBUFEMPTYCNT ,Input Buffer Empty Count"
|
|
bitfld.long 0x00 11. " OBUFREQ ,Output Buffer Request Active" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IBUFREQ ,Input Buffer Request Active" "No request,Request"
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "Idle,Finished"
|
|
bitfld.long 0x00 8. " EXTERR ,Extended Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SNUMERR ,Sequence Number Error" "No error,Error"
|
|
bitfld.long 0x00 6. " PADERR ,Pad Error" "No error,Error"
|
|
bitfld.long 0x00 5. " AUTHERR ,Authentication Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUTHSHDN ,Outer Hash Done" "Busy,Done"
|
|
bitfld.long 0x00 3. " INHSHDN ,Inner Hash Done" "Busy,Done"
|
|
bitfld.long 0x00 2. " ENCRYPTDN ,Encrypt Done" "Busy,Done"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUTPTDN ,PE Output Done" "Not done,Done"
|
|
bitfld.long 0x00 0. " INPTDN ,Packet Engine Input Done" "Not done,Done"
|
|
endif
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PKTE_BUF_THRESH,PKTE Packet Engine Buffer Threshold Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OUTBUF ,Output Buffer Threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INBUF ,Input Buffer Threshold"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "PKTE_INBUF_INCR,PKTE Packet Engine Input Buffer Count Increment Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " VALUE ,Input Buffer Increment"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PKTE_INBUF_CNT,PKTE Packet Engine Input Buffer Count Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " VALUE ,Input Buffer Count"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "PKTE_OUTBUF_CNT,PKTE Packet Engine Output Buffer Count Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " VALUE ,Output Buffer Count"
|
|
wgroup.long 0x114++0x03
|
|
line.long 0x00 "PKTE_OUTBUF_DECR,PKTE Packet Engine Output Buffer Count Decrement Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " VALUE ,Output Buffer Count Decrement"
|
|
if (((per.l(ad:0x310CD000+0x100))&0x100)==0x00)
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "PKTE_BUF_PTR,PKTE Packet Engine Buffer Pointer Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OUTBUF ,Output Buffer Pointer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INBUF ,Input Buffer Pointer"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PKTE_DMA_CFG,PKTE Packet Engine DMA Configuration Register"
|
|
rbitfld.long 0x00 20. " IDLE ,Idle Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " INCR ,Increment Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " MSTRBIGEND ,Master Big Endian" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MXBRSTSZ ,Max Burst Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "PKTE_ENDIAN_CFG,PKTE Packet Engine Endian Configuration Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TGTBSWP ,Target Byte Swap"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MSTRBSWP ,Master Byte Swap"
|
|
wgroup.long 0x1E0++0x03
|
|
line.long 0x00 "PKTE_HLT_CTL,PKTE Packet Engine Halt Control Register"
|
|
bitfld.long 0x00 5. " WRRD ,Halt On Write Result Descriptor" "Do not halt,Halt"
|
|
bitfld.long 0x00 4. " WRSA ,Halt On Write SA" "Do not halt,Halt"
|
|
bitfld.long 0x00 3. " HWRDAT ,Halt On Write Data" "Do not halt,Halt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RDSA ,Halt On Read SA" "Do not halt,Halt"
|
|
bitfld.long 0x00 1. " RDCD ,Halt On Read Command Descriptor" "Do not halt,Halt"
|
|
bitfld.long 0x00 0. " EN ,Enable Halt Mode" "Disabled,Enabled"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "PKTE_HLT_STAT,PKTE Packet Engine Halt Status Register"
|
|
bitfld.long 0x00 24.--26. " DATSTATE ,Data State" "IDLE,READ,WRITE,,WAIT,PAD_READ,BYP_READ,?..."
|
|
bitfld.long 0x00 20.--23. " RDSASTATE ,Read SA State" "IDLE,READ_CMD,READ_STATE_IV,,,,READ_ARC4_STATE,READ_WAIT,,WRITE_PROT_HDR,,WRITE_IV,WRITE_DIGEST,WRITE_ARC4_IJ_PNTR,WRITE_ARC4_STATE,WRITE_WAIT"
|
|
bitfld.long 0x00 16.--19. " MNSTATE ,Main State" "IDLE,READ_CD,READ_SA,DATA,WRITE_SA,WRITE_STATUS,WRITE_CD,WRITE_RD,INIT_WAIT,HALT_READ_CD,HALT_READ_SA,HALT_DATA,HALT_WRITE_SA,MAIN_WAIT_FOR_CLOCK,,MAIN_HALT_WRITE_RD"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WRRD ,Halt On Write Result Descriptor" "Do not halt,Halt"
|
|
bitfld.long 0x00 4. " WRSA ,Halt On Write SA" "Do not halt,Halt"
|
|
bitfld.long 0x00 3. " WRDAT ,Halt On Write Data" "Do not halt,Halt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RDSA ,Halt On Read SA" "Do not halt,Halt"
|
|
bitfld.long 0x00 1. " RDCD ,Halt On Read Command Descriptor" "Do not halt,Halt"
|
|
bitfld.long 0x00 0. " EN ,Halt Mode Enabled Status" "Disabled,Enabled"
|
|
wgroup.long 0x1E4++0x03
|
|
line.long 0x00 "PKTE_CONT,PKTE PKTE Continue Register"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "PKTE_CLK_CTL,PKTE PE Clock Control Register"
|
|
bitfld.long 0x00 4. " ENHSHCLK ,Enable Hash Clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENARC4CLK ,Enable ARC4 Clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENAESCLK ,Enable AES Clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENDESCLK ,Enable DES Clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPECLK ,Enable Packet Engine Clock" "Disabled,Enabled"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PKTE_IUMSK_STAT,PKTE Interrupt Unmasked Status Register"
|
|
bitfld.long 0x00 18. " IFERR ,Interface Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HLT ,Halt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "No interrupt,Interrupt"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "PKTE_IMSK_STAT,PKTE Interrupt Masked Status Register"
|
|
bitfld.long 0x00 18. " IFERR ,Interface Error" "Masked,Unmasked"
|
|
bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "Masked,Unmasked"
|
|
bitfld.long 0x00 16. " RINGERR ,PE Ring Error" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HLT ,Halt" "Masked,Unmasked"
|
|
bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "Masked,Unmasked"
|
|
wgroup.long 0x204++0x03
|
|
line.long 0x00 "PKTE_INT_CLR,PKTE Interrupt Clear Register"
|
|
bitfld.long 0x00 18. " IFERR ,Interface Error" "No effect,Clear"
|
|
bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "No effect,Clear"
|
|
bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HLT ,Halt" "No effect,Clear"
|
|
bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "No effect,Clear"
|
|
bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "No effect,Clear"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PKTE_INT_EN,PKTE Interrupt Enable Register"
|
|
bitfld.long 0x00 18. " IFERR ,Interface Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HLT ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "Disabled,Enabled"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "PKTE_INT_CFG,PKTE Interrupt Configuration Register"
|
|
bitfld.long 0x00 1. " PULSECLR ,Clear Latched Interrupt Source After Pulse Interrupt" "Manual,Auto"
|
|
bitfld.long 0x00 0. " TYPE ,Interrupt Type" "Level,Pulse"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "PKTE_IMSK_EN,PKTE Interrupt Mask Enable Register"
|
|
bitfld.long 0x00 18. " IFERR ,Interface Error" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HLT ,Halt" "No effect,Enabled"
|
|
bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "No effect,Enabled"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "PKTE_IMSK_DIS,PKTE Interrupt Mask Disable Register"
|
|
bitfld.long 0x00 18. " IFERR ,Interface Error" "No effect,Disabled"
|
|
bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HLT ,Halt" "No effect,Disabled"
|
|
bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OPDN ,Operation Done" "No effect,Disabled"
|
|
bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "No effect,Disabled"
|
|
if (((per.l(ad:0x310CD000+0x100))&0x100)==0x00)
|
|
if (((per.l(ad:0x310CD000+0x400))&0x40000)==0x40000)
|
|
wgroup.long 0x400++0x03
|
|
line.long 0x00 "PKTE_SA_CMD0,PKTE SA Command 0"
|
|
bitfld.long 0x00 29. " SVHASH ,Save Hash" "Not saved,Saved"
|
|
bitfld.long 0x00 28. " SVIV ,Save Iv" "Not saved,Saved"
|
|
bitfld.long 0x00 26.--27. " HASHSRC ,Hash Source" "From SA,,From state,No load"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IVSRC ,Iv Source" "No load,From input buffer,From state,From internal PRNG"
|
|
bitfld.long 0x00 20.--23. " DIGESTLEN ,Digest Length" "3 Words (96-bit output),1 Word,2 Words,3 Words (IPsec),4 Words (MD5 and AES-based hash),5 Words (SHA-1),6 Words,7 Words (SHA-224),8 Words (SHA-256),,10 bytes (SRTP and TLS),?..."
|
|
bitfld.long 0x00 19. " HDRPROC ,Header Processing" "No header processing,Header processing"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXTPAD ,Ext Pad" "No,Yes"
|
|
bitfld.long 0x00 17. " SCPAD ,Stream Cipher Padding" "0,1"
|
|
bitfld.long 0x00 12.--15. " HASH ,Hash Algorithm Select" "MD5,SHA-1,SHA-224,SHA-256,,,,,,,,,,,,Null"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CIPHER ,Cipher Algorithm Select" "DES,Triple-DES,ARC4,AES,,,,,,,,,,,,Null"
|
|
bitfld.long 0x00 6.--7. " PADTYPE ,Pad Type" ",TLS/DTLS,Constant SSL,"
|
|
bitfld.long 0x00 4.--5. " OPGRP ,Operation Group" "Basic,Protocol,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction" "Outbound,Inbound"
|
|
bitfld.long 0x00 0.--2. " OPCD ,Op Code" "0,1,2,3,4,5,6,7"
|
|
else
|
|
wgroup.long 0x400++0x03
|
|
line.long 0x00 "PKTE_SA_CMD0,PKTE SA Command 0"
|
|
bitfld.long 0x00 29. " SVHASH ,Save Hash" "Not saved,Saved"
|
|
bitfld.long 0x00 28. " SVIV ,Save Iv" "Not saved,Saved"
|
|
bitfld.long 0x00 26.--27. " HASHSRC ,Hash Source" "From SA,,From state,No load"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IVSRC ,Iv Source" "No load,From input buffer,From state,From internal PRNG"
|
|
bitfld.long 0x00 20.--23. " DIGESTLEN ,Digest Length" "3 Words (96-bit output),1 Word,2 Words,3 Words (IPsec),4 Words (MD5 and AES-based hash),5 Words (SHA-1),6 Words,7 Words (SHA-224),8 Words (SHA-256),,10 bytes (SRTP and TLS),?..."
|
|
bitfld.long 0x00 19. " HDRPROC ,Header Processing" "No header processing,Header processing"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXTPAD ,Ext Pad" "No,Yes"
|
|
bitfld.long 0x00 17. " SCPAD ,Stream Cipher Padding" "0,1"
|
|
bitfld.long 0x00 12.--15. " HASH ,Hash Algorithm Select" "MD5,SHA-1,SHA-224,SHA-256,,,,,,,,,,,,Null"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CIPHER ,Cipher Algorithm Select" "DES,Triple-DES,ARC4,AES,,,,,,,,,,,,Null"
|
|
bitfld.long 0x00 6.--7. " PADTYPE ,Pad Type" "IPSec operation,PKCS#7,Constant,Zero pad"
|
|
bitfld.long 0x00 4.--5. " OPGRP ,Operation Group" "Basic,Protocol,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction" "Outbound,Inbound"
|
|
bitfld.long 0x00 0.--2. " OPCD ,Op Code" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x310CD000+0x400))&0x40000)==0x40000)
|
|
wgroup.long 0x400++0x03
|
|
line.long 0x00 "PKTE_SA_CMD0,PKTE SA Command 0"
|
|
bitfld.long 0x00 29. " SVHASH ,Save Hash" "Not saved,Saved"
|
|
bitfld.long 0x00 28. " SVIV ,Save Iv" "Not saved,Saved"
|
|
bitfld.long 0x00 26.--27. " HASHSRC ,Hash Source" "From SA,,From state,No load"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IVSRC ,Iv Source" "No load,From input buffer,From state,From internal PRNG"
|
|
bitfld.long 0x00 20.--23. " DIGESTLEN ,Digest Length" "3 Words (96-bit output),1 Word,2 Words,3 Words (IPsec),4 Words (MD5 and AES-based hash),5 Words (SHA-1),6 Words,7 Words (SHA-224),8 Words (SHA-256),,10 bytes (SRTP and TLS),?..."
|
|
bitfld.long 0x00 19. " HDRPROC ,Header Processing" "No header processing,Header processing"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXTPAD ,Ext Pad" "No,Yes"
|
|
bitfld.long 0x00 17. " SCPAD ,Stream Cipher Padding" "0,1"
|
|
bitfld.long 0x00 12.--15. " HASH ,Hash Algorithm Select" "MD5,SHA-1,SHA-224,SHA-256,,,,,,,,,,,,Null"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CIPHER ,Cipher Algorithm Select" "DES,Triple-DES,ARC4,AES,,,,,,,,,,,,Null"
|
|
bitfld.long 0x00 6.--7. " PADTYPE ,Pad Type" ",TLS/DTLS,Constant SSL,"
|
|
bitfld.long 0x00 4.--5. " OPGRP ,Operation Group" "Basic,Protocol,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction" "Outbound,Inbound"
|
|
bitfld.long 0x00 0.--2. " OPCD ,Op Code" "0,1,2,3,4,5,6,7"
|
|
else
|
|
wgroup.long 0x400++0x03
|
|
line.long 0x00 "PKTE_SA_CMD0,PKTE SA Command 0"
|
|
bitfld.long 0x00 29. " SVHASH ,Save Hash" "Not saved,Saved"
|
|
bitfld.long 0x00 28. " SVIV ,Save Iv" "Not saved,Saved"
|
|
bitfld.long 0x00 26.--27. " HASHSRC ,Hash Source" "From SA,,From state,No load"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IVSRC ,Iv Source" "No load,From input buffer,From state,From internal PRNG"
|
|
bitfld.long 0x00 20.--23. " DIGESTLEN ,Digest Length" "3 Words (96-bit output),1 Word,2 Words,3 Words (IPsec),4 Words (MD5 and AES-based hash),5 Words (SHA-1),6 Words,7 Words (SHA-224),8 Words (SHA-256),,10 bytes (SRTP and TLS),?..."
|
|
bitfld.long 0x00 19. " HDRPROC ,Header Processing" "No header processing,Header processing"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXTPAD ,Ext Pad" "No,Yes"
|
|
bitfld.long 0x00 17. " SCPAD ,Stream Cipher Padding" "0,1"
|
|
bitfld.long 0x00 12.--15. " HASH ,Hash Algorithm Select" "MD5,SHA-1,SHA-224,SHA-256,,,,,,,,,,,,Null"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CIPHER ,Cipher Algorithm Select" "DES,Triple-DES,ARC4,AES,,,,,,,,,,,,Null"
|
|
bitfld.long 0x00 6.--7. " PADTYPE ,Pad Type" "IPSec operation,PKCS#7,Constant,Zero pad"
|
|
bitfld.long 0x00 4.--5. " OPGRP ,Operation Group" "Basic,Protocol,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction" "Outbound,Inbound"
|
|
bitfld.long 0x00 0.--2. " OPCD ,Op Code" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x310CD000+0x100))&0x100)==0x00)
|
|
wgroup.long 0x404++0x03
|
|
line.long 0x00 "PKTE_SA_CMD1,PKTE SA Command 1"
|
|
bitfld.long 0x00 29. " ENSQNCHK ,Sequence Number Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " ARC4KEYLEN ,ARC4 Key Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 28. " AESDECKEY ,AES Dec Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AESKEYLEN ,AES Key Length" ",,128 Bits,192 Bits,256 Bits,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " HSHCOFFST ,Hash Crypt Offset"
|
|
bitfld.long 0x00 13. " BYTEOFFST ,Byte Offset" "32-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HMAC ,Keyed-Hash SSL Message Authentication Code" "Standard Hash,HMAC processing"
|
|
bitfld.long 0x00 11. " SSLMAC ,Ssl Mac" "Standard Hash,SSL-MAC processing"
|
|
bitfld.long 0x00 8.--9. " CIPHERMD ,Cipher Mode" "ECB,CBC,CTR,ICM"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPYPAD ,Copy Pad" "Do not copy,Copy"
|
|
bitfld.long 0x00 2. " CPYPAYLD ,Copy Payload" "Do not copy,Copy"
|
|
bitfld.long 0x00 1. " CPYHDR ,Copy Header" "Do not copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPYDGST ,Copy Digest" "Do not copy,Copy"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PKTE_SA_CMD1,PKTE SA Command 1"
|
|
bitfld.long 0x00 29. " ENSQNCHK ,Sequence Number Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " ARC4KEYLEN ,ARC4 Key Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 28. " AESDECKEY ,AES Dec Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AESKEYLEN ,AES Key Length" ",,128 Bits,192 Bits,256 Bits,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " HSHCOFFST ,Hash Crypt Offset"
|
|
bitfld.long 0x00 13. " BYTEOFFST ,Byte Offset" "32-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HMAC ,Keyed-Hash SSL Message Authentication Code" "Standard Hash,HMAC processing"
|
|
bitfld.long 0x00 11. " SSLMAC ,Ssl Mac" "Standard Hash,SSL-MAC processing"
|
|
bitfld.long 0x00 8.--9. " CIPHERMD ,Cipher Mode" "ECB,CBC,CTR,ICM"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPYPAD ,Copy Pad" "Do not copy,Copy"
|
|
bitfld.long 0x00 2. " CPYPAYLD ,Copy Payload" "Do not copy,Copy"
|
|
bitfld.long 0x00 1. " CPYHDR ,Copy Header" "Do not copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPYDGST ,Copy Digest" "Do not copy,Copy"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x408++0x03
|
|
line.long 0x00 "PKTE_SA_KEY0,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PKTE_SA_KEY0,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x40C++0x03
|
|
line.long 0x00 "PKTE_SA_KEY1,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PKTE_SA_KEY1,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x410++0x03
|
|
line.long 0x00 "PKTE_SA_KEY2,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PKTE_SA_KEY2,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x414++0x03
|
|
line.long 0x00 "PKTE_SA_KEY3,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "PKTE_SA_KEY3,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x418++0x03
|
|
line.long 0x00 "PKTE_SA_KEY4,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PKTE_SA_KEY4,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x41C++0x03
|
|
line.long 0x00 "PKTE_SA_KEY5,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "PKTE_SA_KEY5,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x420++0x03
|
|
line.long 0x00 "PKTE_SA_KEY6,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "PKTE_SA_KEY6,PKTE SA Key Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x424++0x03
|
|
line.long 0x00 "PKTE_SA_KEY7,PKTE SA Key Registers"
|
|
else
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "PKTE_SA_KEY7,PKTE SA Key Registers"
|
|
endif
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST0,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST1,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST2,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST3,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST4,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST5,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST6,PKTE SA Inner Hash Digest Registers"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "PKTE_SA_IDIGEST7,PKTE SA Inner Hash Digest Registers"
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x448++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST0,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST0,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x44C++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST1,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST1,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x450++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST2,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST2,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x454++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST3,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST3,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x458++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST4,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST4,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x45C++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST5,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST5,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x460++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST6,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST6,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
sif cpuis("ADSP-SC57?")
|
|
wgroup.long 0x464++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST7,PKTE SA Outer Hash Digest Registers"
|
|
else
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "PKTE_SA_ODIGEST7,PKTE SA Outer Hash Digest Registers"
|
|
endif
|
|
wgroup.long 0x468++0x03
|
|
line.long 0x00 "PKTE_SA_SPI,PKTE SA SPI Register"
|
|
group.long 0x46C++0x0F
|
|
line.long 0x00 "PKTE_SA_SEQNUM0,PKTE SA Sequence Number Register"
|
|
line.long 0x04 "PKTE_SA_SEQNUM1,PKTE SA Sequence Number Register"
|
|
line.long 0x08 "PKTE_SA_SEQNUM_MSK0,PKTE SA Sequence Number Mask Registers"
|
|
line.long 0x0C "PKTE_SA_SEQNUM_MSK1,PKTE SA Sequence Number Mask Registers"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "PKTE_SA_ARC4IJPTR,PKTE ARC4 i and j Pointer Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " JPTR ,J Pointer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IPTR ,I Pointer"
|
|
if (((per.l(ad:0x310CD000+0x100))&0x100)==0x00)
|
|
wgroup.long 0x47C++0x03
|
|
line.long 0x00 "PKTE_SA_RDY,PKTE SA Ready Indicator"
|
|
else
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "PKTE_SA_NONCE,PKTE SA Initialization Vector Register"
|
|
endif
|
|
group.long 0x500++0xF
|
|
line.long 0x00 "PKTE_STATE_IV0,PKTE State Initialization Vector Register"
|
|
line.long 0x04 "PKTE_STATE_IV1,PKTE State Initialization Vector Register"
|
|
line.long 0x08 "PKTE_STATE_IV2,PKTE State Initialization Vector Register"
|
|
line.long 0x0C "PKTE_STATE_IV3,PKTE State Initialization Vector Register"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "PKTE_STATE_BYTE_CNT0,PKTE State Hash Byte Count Registers"
|
|
line.long 0x04 "PKTE_STATE_BYTE_CNT1,PKTE State Hash Byte Count Registers"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST0,PKTE State Inner Digest Registers"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST1,PKTE State Inner Digest Registers"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST2,PKTE State Inner Digest Registers"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST3,PKTE State Inner Digest Registers"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST4,PKTE State Inner Digest Registers"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST5,PKTE State Inner Digest Registers"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST6,PKTE State Inner Digest Registers"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "PKTE_STATE_IDIGEST7,PKTE State Inner Digest Registers"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "PKTE_ARC4STATE_BUF,PKTE Starting Entry of 256-byte ARC4 State Buffer"
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "PKTE_DATAIO_BUF,PKTE Starting Entry of 256-byte Data Input/Output Buffer"
|
|
in
|
|
width 0x0b
|
|
tree.end
|
|
tree "TMU (Thermal Monitoring Unit)"
|
|
base ad:0x31016800
|
|
width 17.
|
|
sif cpuis("ADSP-SC57*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TMU_CTL,TMU Control Register"
|
|
bitfld.long 0x00 8. " TMEN_FORCE ,Indefinite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " SCLKDIV ,System clock divide" "21,25,29,33,37,41,45,49,53,57,61,65,69,73,77,81"
|
|
bitfld.long 0x00 3. " TMEN ,Periodic enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TMPU ,TMU enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMU_CTL,TMU Control Register"
|
|
bitfld.long 0x00 4.--7. " OSCDIV ,Oscillator divide ratio" "21,25,29,33,37,41,45,49,53,57,61,65,69,73,77,81"
|
|
bitfld.long 0x00 3. " STARTCNV ,Start conversion" "Not started,Started"
|
|
bitfld.long 0x00 1. " OSCSEL ,Oscillator select" "SCLK,Local oscillator"
|
|
bitfld.long 0x00 0. " EN ,TMU enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TMU_TEMP,TMU Temperature Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Value"
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "TMU_AVG,TMU Averaging Register"
|
|
bitfld.long 0x00 0. " VALUE ,Enables averaging on the TMU" "Disabled,Enabled"
|
|
line.long 0x04 "TMU_FLT_LIM_HI,TMU Fault High Limit Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VALUE ,Value"
|
|
line.long 0x08 "TMU_ALRT_LIM_HI,TMU Alert High Limit Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Value"
|
|
line.long 0x0C "TMU_FLT_LIM_LO,TMU Fault Low Limit Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " VALUE ,Value"
|
|
line.long 0x10 "TMU_ALRT_LIM_LO,TMU Alert Low Limit Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " VALUE ,Value"
|
|
line.long 0x14 "TMU_STAT,TMU Status Register"
|
|
rbitfld.long 0x14 7. " ALRTLO ,Alert low" "Not occurred,Occurred"
|
|
rbitfld.long 0x14 6. " FLTLO ,Fault low" "Not occurred,Occurred"
|
|
eventfld.long 0x14 5. " ALRTHI ,Alert high" "Not occurred,Occurred"
|
|
eventfld.long 0x14 4. " FLTHI ,Fault high" "Not occurred,Occurred"
|
|
group.long 0x24++0xB
|
|
sif cpuis("ADSP-SC57*")
|
|
line.long 0x00 "TMU_GAIN,TMU Gain Value Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Value"
|
|
else
|
|
line.long 0x00 "TMU_GAIN,TMU Gain Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Value"
|
|
endif
|
|
line.long 0x04 "TMU_IMSK,TMU Interrupt Mask Register"
|
|
bitfld.long 0x04 3. " ALRTLO ,Alert low mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " FLTLO ,Fault low mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " ALRTHI ,Alert high mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " FLTHI ,Fault high mask" "Not masked,Masked"
|
|
line.long 0x08 "TMU_OFFSET,TMU Offset Register"
|
|
sif cpuis("ADSP-SC57*")
|
|
hexmask.long.word 0x08 0.--12. 1. " VALUE ,Value"
|
|
else
|
|
hexmask.long.word 0x08 0.--11. 1. " VALUE ,Value"
|
|
endif
|
|
sif cpuis("ADSP-SC57*")
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TMU_CNV_BLANK,Temperature Conversion Blank Register"
|
|
bitfld.long 0x00 0.--4. " VALUE ,Blanking period (in SCLK cycles)" "50k,100k,150k,200k,250k,300k,350k,400k,450k,500k,550k,600k,650k,700k,750k,800k,850k,900k,950k,1000k,1050k,1100k,1150k,1200k,1250k,1300k,1350k,1400k,1450k,1500k,1550k,1600k"
|
|
line.long 0x04 "TMU_REFR_CNTR,Temperature Refresh Counter"
|
|
bitfld.long 0x04 0.--5. " VALUE ,Refresh period (in million system-clock cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "FIR (FIR Accelerator)"
|
|
base ad:0x310C3000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FIR_CTL1,FIR Global Control Register"
|
|
bitfld.long 0x00 14.--16. " RND ,Rounding mode" "Nearest,+ve infinity,-ve infinity,Nearest Up,Away from zero,?..."
|
|
bitfld.long 0x00 13. " TC ,Two's-Complement" "Unsigned,Signed"
|
|
bitfld.long 0x00 12. " FXD ,Fixed-Point accelerator select" "Floating-point,Fixed point"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CCINTR ,Channel complete interrupt" "All,Each"
|
|
bitfld.long 0x00 9. " CAI ,Channel auto iterate" "Idle,Continues"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 6. " BURSTEN ,Burst mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--5. " CH ,Number of channels" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0. " EN ,FIR enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1.--5. " CH ,Number of channels" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0. " EN ,FIR enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x04++0x07
|
|
hide.long 0x00 "FIR_DMASTAT,FIR DMA Status Register"
|
|
in
|
|
hide.long 0x04 "FIR_MACSTAT,FIR MAC Status Register"
|
|
in
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "FIR_DBG_CTL,FIR Debug Control Register"
|
|
bitfld.long 0x00 5. " ADRINC ,Address auto increment" "No,Yes"
|
|
bitfld.long 0x00 4. " MEM ,Local memory access" "No,Yes"
|
|
bitfld.long 0x00 2. " RUN ,Release MAC" "No effect,Released"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HLD ,Hold" "Hold,Single step"
|
|
bitfld.long 0x00 0. " EN ,Debug mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "FIR_DBG_ADDR,Debug Address Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " VALUE ,Debug address"
|
|
line.long 0x08 "FIR_DBG_WRDAT,FIR Debug Data Write Register"
|
|
line.long 0x0C "FIR_DBG_RDDAT,FIR Debug Data Read Register"
|
|
group.long 0x40++0x33
|
|
line.long 0x00 "FIR_CTL2,FIR Channel Control Register"
|
|
bitfld.long 0x00 30. " UPSAMP ,Up sampling enable" "No,Yes"
|
|
bitfld.long 0x00 29. " SRCEN ,Sample rate conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RATIO ,UP/DOWN sampling ratio" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC57*"))
|
|
hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window size"
|
|
bitfld.long 0x00 12.--13. " PRIO ,Priority level" "Level 0,Level 1,Level 2,Level 3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TAPLEN ,Tap length"
|
|
else
|
|
hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size"
|
|
hexmask.long.word 0x00 0.--11. 1. " TAPLEN ,Tap length"
|
|
endif
|
|
line.long 0x04 "FIR_INIDX,FIR Input Data Index Register"
|
|
hexmask.long 0x04 0.--29. 1. " VALUE ,Word address with lower 2 bits removed"
|
|
line.long 0x08 "FIR_INMOD,FIR Input Data Modifier Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,16-bit input data buffer modifier"
|
|
line.long 0x0C "FIR_INCNT,FIR Input Data Count Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,16-bit input data count"
|
|
line.long 0x10 "FIR_INBASE,FIR Input Data Base Register"
|
|
hexmask.long 0x10 0.--29. 1. " VALUE ,Word address with lower 2 bits removed"
|
|
line.long 0x14 "FIR_OUTIDX,FIR Output Data Index Register"
|
|
hexmask.long 0x14 0.--29. 1. " VALUE ,Word address with lower 2 bit removed"
|
|
line.long 0x18 "FIR_OUTMOD,FIR Output Data Modifier Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " VALUE ,16-bit output data modifier"
|
|
line.long 0x1C "FIR_OUTCNT,FIR Output Data Count Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " VALUE ,16-bit Output buffer count"
|
|
line.long 0x20 "FIR_OUTBASE,FIR Output Data Base Register"
|
|
hexmask.long 0x20 0.--29. 0x01 " VALUE ,Word address with lower 2 bit removed"
|
|
line.long 0x24 "FIR_COEFIDX,FIR Coefficient Index Register"
|
|
hexmask.long 0x24 0.--29. 0x01 " VALUE ,Word addresses with lower 2 bit removed"
|
|
line.long 0x28 "FIR_COEFMOD,FIR Coefficient Modifier Register"
|
|
hexmask.long.word 0x28 0.--15. 1. " VALUE ,16-bit coefficient index modifier"
|
|
line.long 0x2C "FIR_COEFCNT,FIR Coefficient Count Register"
|
|
hexmask.long.word 0x2C 0.--15. 1. " CCNT ,16-bit coefficient buffer count"
|
|
line.long 0x30 "FIR_CHNPTR,FIR Chain Pointer Register"
|
|
hexmask.long 0x30 0.--29. 1. " VALUE ,Chain pointer address"
|
|
width 0x0b
|
|
tree.end
|
|
tree "IIR (IIR Accelerator)"
|
|
base ad:0x310C4000
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IIR_CTL1,IIR Global Control Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
bitfld.long 0x00 30. " HALT ,Pause accelerator" "Not paused,Paused"
|
|
bitfld.long 0x00 17. " BURSTEN ,Burst mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--16. " RND ,Rounding mode" "To nearest,To zero,To +ve infinity,To -ve infinity,To nearest Up,Away from zero,?..."
|
|
bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point format select" "32-bit,40-bit"
|
|
bitfld.long 0x00 11. " CCINTR ,Channel complete interrupt" "All,Each"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SS ,Save biquad state" "No effect,Saved"
|
|
bitfld.long 0x00 9. " CAI ,Channel auto iterate" "Idle,Moved"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--5. " CH ,Number of channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 0. " EN ,IIR enable" "Disabled,Enabled"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "IIR_DMASTAT,IIR DMA Status"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR_MACSTAT,IIR MAC Status Register"
|
|
bitfld.long 0x00 5. " AINV ,Addition invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 4. " ARI ,Adder result infinity" "Not infinity,Infinity"
|
|
bitfld.long 0x00 3. " ARZ ,Adder result zero" "Not zero,Zero"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MINV ,Multiply invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 1. " MRI ,Multiplier result infinity" "Not infinity,Infinity"
|
|
bitfld.long 0x00 0. " MRZ ,Multiplier result zero" "Not zero,Zero"
|
|
if (((per.l(ad:0x310C4000+0x0C))&0x10)==0x10)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IIR_DBG_CTL,IIR IIR Debug Control"
|
|
bitfld.long 0x00 5. " ADRINC ,Address auto increment" "No,Yes"
|
|
bitfld.long 0x00 4. " MEM ,Local memory access" "No,Yes"
|
|
bitfld.long 0x00 2. " RUN ,Release the MAC" "No effect,Released"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HLD ,Hold or single step" "No effect,Hold data"
|
|
bitfld.long 0x00 0. " EN ,Debug mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IIR_DBG_CTL,IIR IIR Debug Control"
|
|
bitfld.long 0x00 5. " ADRINC ,Address auto increment" "No,Yes"
|
|
bitfld.long 0x00 4. " MEM ,Local memory access" "No,Yes"
|
|
bitfld.long 0x00 2. " RUN ,Release the MAC" "No effect,Released"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HLD ,Hold or single step" "No effect,Single step"
|
|
bitfld.long 0x00 0. " EN ,Debug mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "IIR_DBG_ADDR,IIR IIR Debug Address"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " VALUE ,Debug address"
|
|
line.long 0x04 "IIR_DBG_WRDAT_LO,IIR IIR Debug Write Data Low"
|
|
line.long 0x08 "IIR_DBG_WRDAT_HI,IIR IIR Debug Write Data High"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Debug write data highest 8 bits"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "IIR_DBG_RDDAT_LO,IIR IIR Debug Read Data Low"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IIR_DBG_RDDAT_HI,IIR IIR debug read data high"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug read data highest 8 bits"
|
|
group.long 0x40++0x33
|
|
line.long 0x00 "IIR_CTL2,IIR Channel Control Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window size parameter"
|
|
bitfld.long 0x00 0.--3. " BIQUADS ,Number of biquads" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.long 0x04 "IIR_INIDX,IIR Input Data Index Register"
|
|
hexmask.long 0x04 0.--29. 1. " VALUE ,Input data buffer index"
|
|
line.long 0x08 "IIR_INMOD,IIR Input Data Index Modifier Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,16-bit input data buffer index modifier"
|
|
line.long 0x0C "IIR_INLEN,IIR Input Data Buffer Length Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Input data buffer length"
|
|
line.long 0x10 "IIR_INBASE,IIR Input Buffer Base Register"
|
|
hexmask.long 0x10 0.--29. 1. " VALUE ,Input data buffer base"
|
|
line.long 0x14 "IIR_OUTIDX,IIR Output Data Buffer Index Register"
|
|
hexmask.long 0x14 0.--29. 1. " VALUE ,Output data buffer index"
|
|
line.long 0x18 "IIR_OUTMOD,IIR IIR Output Data Index Modifier"
|
|
hexmask.long.word 0x18 0.--15. 1. " VALUE ,16-bit input data buffer index modifier"
|
|
line.long 0x1C "IIR_OUTLEN,IIR IIR Output Data Buffer Length"
|
|
hexmask.long.word 0x1C 0.--15. 1. " VALUE ,16-bit output data buffer length"
|
|
line.long 0x20 "IIR_OUTBASE,IIR Output Buffer Base Register"
|
|
hexmask.long 0x20 0.--29. 1. " VALUE ,Output buffer base"
|
|
line.long 0x24 "IIR_COEFIDX,IIR Coefficient Buffer Index Register"
|
|
hexmask.long 0x24 0.--29. 1. " VALUE ,Coefficient buffer index"
|
|
line.long 0x28 "IIR_COEFMOD,IIR Coefficient Index Modifier Register"
|
|
hexmask.long.word 0x28 0.--15. 1. " VALUE ,Coefficient modifier"
|
|
line.long 0x2C "IIR_COEFLEN,IIR Coefficient Buffer Length Register"
|
|
hexmask.long.word 0x2C 0.--15. 1. " VALUE ,Coefficient length"
|
|
line.long 0x30 "IIR_CHNPTR,IIR Chain Pointer Register"
|
|
hexmask.long 0x30 0.--29. 0x01 " VALUE ,IIR chain pointer address"
|
|
width 0x0b
|
|
tree.end
|
|
tree "SCB (System Crossbars)"
|
|
base ad:0x30042100
|
|
width 19.
|
|
tree "SCB0"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SCB0_MST[0]_RQOS,Read Quality of Service for Master 0"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "SCB0_MST[1]_RQOS,Read Quality of Service for Master 1"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "SCB0_MST[2]_RQOS,Read Quality of Service for Master 2"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3000++0x03
|
|
line.long 0x00 "SCB0_MST[3]_RQOS,Read Quality of Service for Master 3"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4000++0x03
|
|
line.long 0x00 "SCB0_MST[4]_RQOS,Read Quality of Service for Master 4"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5000++0x03
|
|
line.long 0x00 "SCB0_MST[5]_RQOS,Read Quality of Service for Master 5"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6000++0x03
|
|
line.long 0x00 "SCB0_MST[6]_RQOS,Read Quality of Service for Master 6"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7000++0x03
|
|
line.long 0x00 "SCB0_MST[7]_RQOS,Read Quality of Service for Master 7"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8000++0x03
|
|
line.long 0x00 "SCB0_MST[8]_RQOS,Read Quality of Service for Master 8"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x9000++0x03
|
|
line.long 0x00 "SCB0_MST[9]_RQOS,Read Quality of Service for Master 9"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA000++0x03
|
|
line.long 0x00 "SCB0_MST[10]_RQOS,Read Quality of Service for Master 10"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB000++0x03
|
|
line.long 0x00 "SCB0_MST[11]_RQOS,Read Quality of Service for Master 11"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC000++0x03
|
|
line.long 0x00 "SCB0_MST[12]_RQOS,Read Quality of Service for Master 12"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD000++0x03
|
|
line.long 0x00 "SCB0_MST[13]_RQOS,Read Quality of Service for Master 13"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE000++0x03
|
|
line.long 0x00 "SCB0_MST[14]_RQOS,Read Quality of Service for Master 14"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xF000++0x03
|
|
line.long 0x00 "SCB0_MST[15]_RQOS,Read Quality of Service for Master 15"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "SCB0_MST[16]_RQOS,Read Quality of Service for Master 16"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x11000++0x03
|
|
line.long 0x00 "SCB0_MST[17]_RQOS,Read Quality of Service for Master 17"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x12000++0x03
|
|
line.long 0x00 "SCB0_MST[18]_RQOS,Read Quality of Service for Master 18"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x13000++0x03
|
|
line.long 0x00 "SCB0_MST[19]_RQOS,Read Quality of Service for Master 19"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14000++0x03
|
|
line.long 0x00 "SCB0_MST[20]_RQOS,Read Quality of Service for Master 20"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x15000++0x03
|
|
line.long 0x00 "SCB0_MST[21]_RQOS,Read Quality of Service for Master 21"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x16000++0x03
|
|
line.long 0x00 "SCB0_MST[22]_RQOS,Read Quality of Service for Master 22"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x17000++0x03
|
|
line.long 0x00 "SCB0_MST[23]_RQOS,Read Quality of Service for Master 23"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18000++0x03
|
|
line.long 0x00 "SCB0_MST[24]_RQOS,Read Quality of Service for Master 24"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x19000++0x03
|
|
line.long 0x00 "SCB0_MST[25]_RQOS,Read Quality of Service for Master 25"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1A000++0x03
|
|
line.long 0x00 "SCB0_MST[26]_RQOS,Read Quality of Service for Master 26"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1B000++0x03
|
|
line.long 0x00 "SCB0_MST[27]_RQOS,Read Quality of Service for Master 27"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C000++0x03
|
|
line.long 0x00 "SCB0_MST[28]_RQOS,Read Quality of Service for Master 28"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1D000++0x03
|
|
line.long 0x00 "SCB0_MST[29]_RQOS,Read Quality of Service for Master 29"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1E000++0x03
|
|
line.long 0x00 "SCB0_MST[30]_RQOS,Read Quality of Service for Master 30"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1F000++0x03
|
|
line.long 0x00 "SCB0_MST[31]_RQOS,Read Quality of Service for Master 31"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20000++0x03
|
|
line.long 0x00 "SCB0_MST[32]_RQOS,Read Quality of Service for Master 32"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x21000++0x03
|
|
line.long 0x00 "SCB0_MST[33]_RQOS,Read Quality of Service for Master 33"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x22000++0x03
|
|
line.long 0x00 "SCB0_MST[34]_RQOS,Read Quality of Service for Master 34"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x23000++0x03
|
|
line.long 0x00 "SCB0_MST[35]_RQOS,Read Quality of Service for Master 35"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24000++0x03
|
|
line.long 0x00 "SCB0_MST[36]_RQOS,Read Quality of Service for Master 36"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x25000++0x03
|
|
line.long 0x00 "SCB0_MST[37]_RQOS,Read Quality of Service for Master 37"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x26000++0x03
|
|
line.long 0x00 "SCB0_MST[38]_RQOS,Read Quality of Service for Master 38"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x27000++0x03
|
|
line.long 0x00 "SCB0_MST[39]_RQOS,Read Quality of Service for Master 39"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28000++0x03
|
|
line.long 0x00 "SCB0_MST[40]_RQOS,Read Quality of Service for Master 40"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x29000++0x03
|
|
line.long 0x00 "SCB0_MST[41]_RQOS,Read Quality of Service for Master 41"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2A000++0x03
|
|
line.long 0x00 "SCB0_MST[42]_RQOS,Read Quality of Service for Master 42"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2B000++0x03
|
|
line.long 0x00 "SCB0_MST[43]_RQOS,Read Quality of Service for Master 43"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2C000++0x03
|
|
line.long 0x00 "SCB0_MST[44]_RQOS,Read Quality of Service for Master 44"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2D000++0x03
|
|
line.long 0x00 "SCB0_MST[45]_RQOS,Read Quality of Service for Master 45"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2E000++0x03
|
|
line.long 0x00 "SCB0_MST[46]_RQOS,Read Quality of Service for Master 46"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2F000++0x03
|
|
line.long 0x00 "SCB0_MST[47]_RQOS,Read Quality of Service for Master 47"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "SCB0_MST[48]_RQOS,Read Quality of Service for Master 48"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x31000++0x03
|
|
line.long 0x00 "SCB0_MST[49]_RQOS,Read Quality of Service for Master 49"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x32000++0x03
|
|
line.long 0x00 "SCB0_MST[50]_RQOS,Read Quality of Service for Master 50"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x33000++0x03
|
|
line.long 0x00 "SCB0_MST[51]_RQOS,Read Quality of Service for Master 51"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34000++0x03
|
|
line.long 0x00 "SCB0_MST[52]_RQOS,Read Quality of Service for Master 52"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x35000++0x03
|
|
line.long 0x00 "SCB0_MST[53]_RQOS,Read Quality of Service for Master 53"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x36000++0x03
|
|
line.long 0x00 "SCB0_MST[54]_RQOS,Read Quality of Service for Master 54"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x37000++0x03
|
|
line.long 0x00 "SCB0_MST[55]_RQOS,Read Quality of Service for Master 55"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38000++0x03
|
|
line.long 0x00 "SCB0_MST[56]_RQOS,Read Quality of Service for Master 56"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x39000++0x03
|
|
line.long 0x00 "SCB0_MST[57]_RQOS,Read Quality of Service for Master 57"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3A000++0x03
|
|
line.long 0x00 "SCB0_MST[58]_RQOS,Read Quality of Service for Master 58"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3B000++0x03
|
|
line.long 0x00 "SCB0_MST[59]_RQOS,Read Quality of Service for Master 59"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C000++0x03
|
|
line.long 0x00 "SCB0_MST[60]_RQOS,Read Quality of Service for Master 60"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3D000++0x03
|
|
line.long 0x00 "SCB0_MST[61]_RQOS,Read Quality of Service for Master 61"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3E000++0x03
|
|
line.long 0x00 "SCB0_MST[62]_RQOS,Read Quality of Service for Master 62"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3F000++0x03
|
|
line.long 0x00 "SCB0_MST[63]_RQOS,Read Quality of Service for Master 63"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40000++0x03
|
|
line.long 0x00 "SCB0_MST[64]_RQOS,Read Quality of Service for Master 64"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x41000++0x03
|
|
line.long 0x00 "SCB0_MST[65]_RQOS,Read Quality of Service for Master 65"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x42000++0x03
|
|
line.long 0x00 "SCB0_MST[66]_RQOS,Read Quality of Service for Master 66"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x43000++0x03
|
|
line.long 0x00 "SCB0_MST[67]_RQOS,Read Quality of Service for Master 67"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44000++0x03
|
|
line.long 0x00 "SCB0_MST[68]_RQOS,Read Quality of Service for Master 68"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x45000++0x03
|
|
line.long 0x00 "SCB0_MST[69]_RQOS,Read Quality of Service for Master 69"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x46000++0x03
|
|
line.long 0x00 "SCB0_MST[70]_RQOS,Read Quality of Service for Master 70"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x47000++0x03
|
|
line.long 0x00 "SCB0_MST[71]_RQOS,Read Quality of Service for Master 71"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AR Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SCB0_MST[0]_WQOS,Write Quality of Service for Master 0"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "SCB0_MST[1]_WQOS,Write Quality of Service for Master 1"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2004++0x03
|
|
line.long 0x00 "SCB0_MST[2]_WQOS,Write Quality of Service for Master 2"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3004++0x03
|
|
line.long 0x00 "SCB0_MST[3]_WQOS,Write Quality of Service for Master 3"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4004++0x03
|
|
line.long 0x00 "SCB0_MST[4]_WQOS,Write Quality of Service for Master 4"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5004++0x03
|
|
line.long 0x00 "SCB0_MST[5]_WQOS,Write Quality of Service for Master 5"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6004++0x03
|
|
line.long 0x00 "SCB0_MST[6]_WQOS,Write Quality of Service for Master 6"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7004++0x03
|
|
line.long 0x00 "SCB0_MST[7]_WQOS,Write Quality of Service for Master 7"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8004++0x03
|
|
line.long 0x00 "SCB0_MST[8]_WQOS,Write Quality of Service for Master 8"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x9004++0x03
|
|
line.long 0x00 "SCB0_MST[9]_WQOS,Write Quality of Service for Master 9"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA004++0x03
|
|
line.long 0x00 "SCB0_MST[10]_WQOS,Write Quality of Service for Master 10"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB004++0x03
|
|
line.long 0x00 "SCB0_MST[11]_WQOS,Write Quality of Service for Master 11"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC004++0x03
|
|
line.long 0x00 "SCB0_MST[12]_WQOS,Write Quality of Service for Master 12"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD004++0x03
|
|
line.long 0x00 "SCB0_MST[13]_WQOS,Write Quality of Service for Master 13"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE004++0x03
|
|
line.long 0x00 "SCB0_MST[14]_WQOS,Write Quality of Service for Master 14"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xF004++0x03
|
|
line.long 0x00 "SCB0_MST[15]_WQOS,Write Quality of Service for Master 15"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10004++0x03
|
|
line.long 0x00 "SCB0_MST[16]_WQOS,Write Quality of Service for Master 16"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x11004++0x03
|
|
line.long 0x00 "SCB0_MST[17]_WQOS,Write Quality of Service for Master 17"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x12004++0x03
|
|
line.long 0x00 "SCB0_MST[18]_WQOS,Write Quality of Service for Master 18"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x13004++0x03
|
|
line.long 0x00 "SCB0_MST[19]_WQOS,Write Quality of Service for Master 19"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14004++0x03
|
|
line.long 0x00 "SCB0_MST[20]_WQOS,Write Quality of Service for Master 20"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x15004++0x03
|
|
line.long 0x00 "SCB0_MST[21]_WQOS,Write Quality of Service for Master 21"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x16004++0x03
|
|
line.long 0x00 "SCB0_MST[22]_WQOS,Write Quality of Service for Master 22"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x17004++0x03
|
|
line.long 0x00 "SCB0_MST[23]_WQOS,Write Quality of Service for Master 23"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18004++0x03
|
|
line.long 0x00 "SCB0_MST[24]_WQOS,Write Quality of Service for Master 24"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x19004++0x03
|
|
line.long 0x00 "SCB0_MST[25]_WQOS,Write Quality of Service for Master 25"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1A004++0x03
|
|
line.long 0x00 "SCB0_MST[26]_WQOS,Write Quality of Service for Master 26"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1B004++0x03
|
|
line.long 0x00 "SCB0_MST[27]_WQOS,Write Quality of Service for Master 27"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C004++0x03
|
|
line.long 0x00 "SCB0_MST[28]_WQOS,Write Quality of Service for Master 28"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1D004++0x03
|
|
line.long 0x00 "SCB0_MST[29]_WQOS,Write Quality of Service for Master 29"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1E004++0x03
|
|
line.long 0x00 "SCB0_MST[30]_WQOS,Write Quality of Service for Master 30"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1F004++0x03
|
|
line.long 0x00 "SCB0_MST[31]_WQOS,Write Quality of Service for Master 31"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20004++0x03
|
|
line.long 0x00 "SCB0_MST[32]_WQOS,Write Quality of Service for Master 32"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x21004++0x03
|
|
line.long 0x00 "SCB0_MST[33]_WQOS,Write Quality of Service for Master 33"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x22004++0x03
|
|
line.long 0x00 "SCB0_MST[34]_WQOS,Write Quality of Service for Master 34"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x23004++0x03
|
|
line.long 0x00 "SCB0_MST[35]_WQOS,Write Quality of Service for Master 35"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24004++0x03
|
|
line.long 0x00 "SCB0_MST[36]_WQOS,Write Quality of Service for Master 36"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x25004++0x03
|
|
line.long 0x00 "SCB0_MST[37]_WQOS,Write Quality of Service for Master 37"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x26004++0x03
|
|
line.long 0x00 "SCB0_MST[38]_WQOS,Write Quality of Service for Master 38"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x27004++0x03
|
|
line.long 0x00 "SCB0_MST[39]_WQOS,Write Quality of Service for Master 39"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28004++0x03
|
|
line.long 0x00 "SCB0_MST[40]_WQOS,Write Quality of Service for Master 40"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x29004++0x03
|
|
line.long 0x00 "SCB0_MST[41]_WQOS,Write Quality of Service for Master 41"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2A004++0x03
|
|
line.long 0x00 "SCB0_MST[42]_WQOS,Write Quality of Service for Master 42"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2B004++0x03
|
|
line.long 0x00 "SCB0_MST[43]_WQOS,Write Quality of Service for Master 43"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2C004++0x03
|
|
line.long 0x00 "SCB0_MST[44]_WQOS,Write Quality of Service for Master 44"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2D004++0x03
|
|
line.long 0x00 "SCB0_MST[45]_WQOS,Write Quality of Service for Master 45"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2E004++0x03
|
|
line.long 0x00 "SCB0_MST[46]_WQOS,Write Quality of Service for Master 46"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2F004++0x03
|
|
line.long 0x00 "SCB0_MST[47]_WQOS,Write Quality of Service for Master 47"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30004++0x03
|
|
line.long 0x00 "SCB0_MST[48]_WQOS,Write Quality of Service for Master 48"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x31004++0x03
|
|
line.long 0x00 "SCB0_MST[49]_WQOS,Write Quality of Service for Master 49"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x32004++0x03
|
|
line.long 0x00 "SCB0_MST[50]_WQOS,Write Quality of Service for Master 50"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x33004++0x03
|
|
line.long 0x00 "SCB0_MST[51]_WQOS,Write Quality of Service for Master 51"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34004++0x03
|
|
line.long 0x00 "SCB0_MST[52]_WQOS,Write Quality of Service for Master 52"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x35004++0x03
|
|
line.long 0x00 "SCB0_MST[53]_WQOS,Write Quality of Service for Master 53"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x36004++0x03
|
|
line.long 0x00 "SCB0_MST[54]_WQOS,Write Quality of Service for Master 54"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x37004++0x03
|
|
line.long 0x00 "SCB0_MST[55]_WQOS,Write Quality of Service for Master 55"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38004++0x03
|
|
line.long 0x00 "SCB0_MST[56]_WQOS,Write Quality of Service for Master 56"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x39004++0x03
|
|
line.long 0x00 "SCB0_MST[57]_WQOS,Write Quality of Service for Master 57"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3A004++0x03
|
|
line.long 0x00 "SCB0_MST[58]_WQOS,Write Quality of Service for Master 58"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3B004++0x03
|
|
line.long 0x00 "SCB0_MST[59]_WQOS,Write Quality of Service for Master 59"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C004++0x03
|
|
line.long 0x00 "SCB0_MST[60]_WQOS,Write Quality of Service for Master 60"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3D004++0x03
|
|
line.long 0x00 "SCB0_MST[61]_WQOS,Write Quality of Service for Master 61"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3E004++0x03
|
|
line.long 0x00 "SCB0_MST[62]_WQOS,Write Quality of Service for Master 62"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3F004++0x03
|
|
line.long 0x00 "SCB0_MST[63]_WQOS,Write Quality of Service for Master 63"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40004++0x03
|
|
line.long 0x00 "SCB0_MST[64]_WQOS,Write Quality of Service for Master 64"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x41004++0x03
|
|
line.long 0x00 "SCB0_MST[65]_WQOS,Write Quality of Service for Master 65"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x42004++0x03
|
|
line.long 0x00 "SCB0_MST[66]_WQOS,Write Quality of Service for Master 66"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x43004++0x03
|
|
line.long 0x00 "SCB0_MST[67]_WQOS,Write Quality of Service for Master 67"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44004++0x03
|
|
line.long 0x00 "SCB0_MST[68]_WQOS,Write Quality of Service for Master 68"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x45004++0x03
|
|
line.long 0x00 "SCB0_MST[69]_WQOS,Write Quality of Service for Master 69"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x46004++0x03
|
|
line.long 0x00 "SCB0_MST[70]_WQOS,Write Quality of Service for Master 70"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x47004++0x03
|
|
line.long 0x00 "SCB0_MST[71]_WQOS,Write Quality of Service for Master 71"
|
|
bitfld.long 0x00 0.--3. " VALUE ,AW Channel Quality of Service" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
base ad:0x30200020
|
|
tree "SCB1"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCB1_MST00_SYNC,Mst00 Interface Block Sync Mode"
|
|
bitfld.long 0x00 0.--2. " VALUE ,Sync Mode" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
base ad:0x30105020
|
|
tree "SCB3"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCB3_MST00_SYNC,Mst00 Ib Sync Mode"
|
|
bitfld.long 0x00 0.--2. " VALUE ,Sync Mode" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x310D0000
|
|
width 17.
|
|
if (((per.l(ad:0x310D0000+0x10))&0x01)==0x01)&&(((per.l(ad:0x310D0000+0x18))&0xF000)==0x00)
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "TRNG_OUTPUT0,TRNG Output Registers"
|
|
line.long 0x04 "TRNG_OUTPUT1,TRNG Output Registers"
|
|
line.long 0x08 "TRNG_OUTPUT2,TRNG Output Registers"
|
|
line.long 0x0C "TRNG_OUTPUT3,TRNG Output Registers"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "TRNG_OUTPUT0,TRNG Output Registers"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "TRNG_OUTPUT1,TRNG Output Registers"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "TRNG_OUTPUT2,TRNG Output Registers"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TRNG_OUTPUT3,TRNG Output Registers"
|
|
endif
|
|
if (((per.l(ad:0x310D0000+0x10))&0x100)==0x100)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TRNG_INPUT0,TRNG Input Registers"
|
|
line.long 0x04 "TRNG_INPUT1,TRNG Input Registers"
|
|
sif !cpuis("ADSP-SC57*")
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "TRNG_INPUT2,TRNG Input Registers"
|
|
line.long 0x04 "TRNG_INPUT3,TRNG Input Registers"
|
|
endif
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "TRNG_INPUT0,TRNG Input Registers"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "TRNG_INPUT1,TRNG Input Registers"
|
|
sif !cpuis("ADSP-SC57*")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "TRNG_INPUT2,TRNG Input Registers"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TRNG_INPUT3,TRNG Input Registers"
|
|
endif
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRNG_STAT,TRNG Status Register"
|
|
bitfld.long 0x00 24. " NEEDCLK ,Need clock" "Not needed,Needed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BLKAVAIL ,Blocks available"
|
|
bitfld.long 0x00 8. " TSTRDY ,Test ready" "Not ready,Ready"
|
|
bitfld.long 0x00 7. " MBITFAIL ,Monobit fail" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PKRFAIL ,Poker fail" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " LRUNFAIL ,Long run fail" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " RUNFAIL ,Run fail" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " NOISEFAIL ,Noise fail" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STUCKOUT ,Stuck out" "Not stuck,Stuck"
|
|
bitfld.long 0x00 1. " SHDNOVR ,Shutdown overflow" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " RDY ,Ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x310D0000+0x18))&0xF000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRNG_INTACK,TRNG Interrupt Acknowledge Register"
|
|
eventfld.long 0x00 7. " MBITFAIL ,Monobit fail acknowledge" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " PKRFAIL ,Poker fail acknowledge" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " LRUNFAIL ,Long run fail acknowledge" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " RUNFAIL ,Run fail acknowledge" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " NOISEFAIL ,Noise fail acknowledge" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " STUCKOUT ,Stuck out acknowledge" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " SHDNOVR ,Shutdown overflow acknowledge" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " RDY ,Ready acknowledge" "No interrupt,Interrupt"
|
|
else
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "TRNG_INTACK,TRNG Interrupt Acknowledge Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPENRDGATE ,Open read gate"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRNG_CTL,TRNG Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " STARTUPCYC ,Startup cycles"
|
|
sif cpuis("ADSP-SC57*")
|
|
textline " "
|
|
bitfld.long 0x00 15. " RESEED ,Perform Re-seed" "No,Yes"
|
|
bitfld.long 0x00 12. " PPROCEN ,Post processor enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " TRNGEN ,Enable TRNG" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TSTMODE ,Test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MBITFAILMSK ,Monobit fail mask" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " PKRFAILMSK ,Poker fail mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " LRUNFAILMSK ,Long run fail mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RUNFAILMSK ,Run fail mask" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " NOISEFAILMSK ,Noise fail mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " STUCKOUTMSK ,Stuck out mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SHDNOVRMSK ,Shutdown overflow mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RDYMSK ,Ready mask" "Masked,Not masked"
|
|
if (((per.l(ad:0x310D0000+0x14))&0x400)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRNG_CFG,TRNG Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MAXREFCYC ,Max refill cycles"
|
|
bitfld.long 0x00 12.--15. " RDTIMEOUT ,Read timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SAMPLEDIV ,Sample div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINREFCYC ,Min refill cycles"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRNG_CFG,TRNG Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MAXREFCYC ,Max refill cycles"
|
|
bitfld.long 0x00 12.--15. " RDTIMEOUT ,Read timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SAMPLEDIV ,Sample div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MINREFCYC ,Min refill cycles"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRNG_ALMCNT,TRNG Alarm Counter Register"
|
|
rbitfld.long 0x00 24.--29. " SHDNCNT ,Shutdown count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " SHDNFATAL ,Shutdown fatal" "No error,Error"
|
|
bitfld.long 0x00 16.--20. " SHDNTHRESH ,Shutdown threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STALLRUNPKR ,Stall run poker" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALMTHRESH ,Alarm threshold"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "TRNG_FROEN,TRNG FRO Enable Register"
|
|
bitfld.long 0x00 7. " FROS[7] ,Enable Free-Running oscillator 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Enable Free-Running oscillator 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable Free-Running oscillator 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable Free-Running oscillator 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Enable Free-Running oscillator 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable Free-Running oscillator 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Enable Free-Running oscillator 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable Free-Running oscillator 0" "Disabled,Enabled"
|
|
line.long 0x04 "TRNG_FRODETUNE,TRNG FRO De-tune Register"
|
|
bitfld.long 0x04 7. " FROS[7] ,FRO De-tune bit 7" "Normal,Faster"
|
|
bitfld.long 0x04 6. " [6] ,FRO De-tune bit 6" "Normal,Faster"
|
|
bitfld.long 0x04 5. " [5] ,FRO De-tune bit 5" "Normal,Faster"
|
|
bitfld.long 0x04 4. " [4] ,FRO De-tune bit 4" "Normal,Faster"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,FRO De-tune bit 3" "Normal,Faster"
|
|
bitfld.long 0x04 2. " [2] ,FRO De-tune bit 2" "Normal,Faster"
|
|
bitfld.long 0x04 1. " [1] ,FRO De-tune bit 1" "Normal,Faster"
|
|
bitfld.long 0x04 0. " [0] ,FRO De-tune bit 0" "Normal,Faster"
|
|
line.long 0x08 "TRNG_ALMMSK,TRNG Alarm Mask Register"
|
|
bitfld.long 0x08 7. " FROS[7] ,FRO 7 alarm mask" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " [6] ,FRO 6 alarm mask" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " [5] ,FRO 5 alarm mask" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " [4] ,FRO 4 alarm mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,FRO 3 alarm mask" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " [2] ,FRO 2 alarm mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " [1] ,FRO 1 alarm mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " [0] ,FRO 0 alarm mask" "Masked,Not masked"
|
|
line.long 0x0C "TRNG_ALMSTP,TRNG Alarm Stop Register"
|
|
bitfld.long 0x0C 7. " FROS[7] ,FRO alarm stop bit 7" "Not stopped,Stopped"
|
|
bitfld.long 0x0C 6. " [6] ,FRO alarm stop bit 6" "Not stopped,Stopped"
|
|
bitfld.long 0x0C 5. " [5] ,FRO alarm stop bit 5" "Not stopped,Stopped"
|
|
bitfld.long 0x0C 4. " [4] ,FRO alarm stop bit 4" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [3] ,FRO alarm stop bit 3" "Not stopped,Stopped"
|
|
bitfld.long 0x0C 2. " [2] ,FRO alarm stop bit 2" "Not stopped,Stopped"
|
|
bitfld.long 0x0C 1. " [1] ,FRO alarm stop bit 1" "Not stopped,Stopped"
|
|
bitfld.long 0x0C 0. " [0] ,FRO alarm stop bit 0" "Not stopped,Stopped"
|
|
textline " "
|
|
sif cpuis("ADSP-SC57*")
|
|
if (((per.l(ad:0x310D0000+0x14))&0x100)==0x100)
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "TRNG_LFSR_L,TRNG LFSR Access Register"
|
|
line.long 0x04 "TRNG_LFSR_M,TRNG LFSR Access Register"
|
|
line.long 0x08 "TRNG_LFSR_H,TRNG LFSR Access Register"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " VALUE ,LFSR[80:64]"
|
|
else
|
|
hgroup.long 0x30++0x0B
|
|
hide.long 0x00 "TRNG_LFSR_L,TRNG LFSR Access Register"
|
|
hide.long 0x04 "TRNG_LFSR_M,TRNG LFSR Access Register"
|
|
hide.long 0x08 "TRNG_LFSR_H,TRNG LFSR Access Register"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x310D0000+0x14))&0x100)==0x100)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRNG_CNT,TRNG Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Sample counter"
|
|
else
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "TRNG_CNT,TRNG Counter Register"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRNG_RUNCNT,TRNG Run Count Registers"
|
|
bitfld.long 0x00 24.--29. " LENMAX ,Run length max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " LENCNT ,Run length br count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " STATE ,Run state" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. " TSTCNT ,Run test count"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long (0x44-0x04)++0x03
|
|
line.long 0x00 "TRNG_KEY1,Post-Process Key Register 1"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRNG_RUN1,TRNG Run Test State And Result Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count ones"
|
|
hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count zeros"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long (0x48-0x04)++0x03
|
|
line.long 0x00 "TRNG_KEY2,Post-Process Key Register 2"
|
|
endif
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRNG_RUN2,TRNG Run Test State And Result Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count ones"
|
|
hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count zeros"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long (0x4C-0x04)++0x03
|
|
line.long 0x00 "TRNG_KEY3,Post-Process Key Register 3"
|
|
endif
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRNG_RUN3,TRNG Run Test State And Result Register 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count ones"
|
|
hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count zeros"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long (0x50-0x04)++0x03
|
|
line.long 0x00 "TRNG_KEY4,Post-Process Key Register 4"
|
|
endif
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRNG_RUN4,TRNG Run Test State And Result Register 4"
|
|
hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count ones"
|
|
hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count zeros"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long (0x54-0x04)++0x03
|
|
line.long 0x00 "TRNG_KEY5,Post-Process Key Register 5"
|
|
endif
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRNG_RUN5,TRNG Run Test State And Result Register 5"
|
|
hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count ones"
|
|
hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count zeros"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long (0x58-0x04)++0x03
|
|
line.long 0x00 "TRNG_KEY6,Post-Process Key Register 6"
|
|
endif
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRNG_RUN6,TRNG Run Test State And Result Register 6"
|
|
hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count ones"
|
|
hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count zeros"
|
|
sif cpuis("ADSP-SC57*")
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRNG_MONOBITCNT,TRNG Monobit Test Result Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " VALUE ,Monobit Count"
|
|
endif
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRNG_POKER1,TRNG Poker Test Result Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT3 ,Poker count 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CNT2 ,Poker count 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CNT1 ,Poker count 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CNT0 ,Poker count 0"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "TRNG_V1,TRNG Post-Process 'V' Value Register 1"
|
|
endif
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRNG_POKER2,TRNG Poker Test Result Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT7 ,Poker count 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CNT6 ,Poker count 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CNT5 ,Poker count 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CNT4 ,Poker count 4"
|
|
sif cpuis("ADSP-SC57*")
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TRNG_V2,TRNG Post-Process 'V' Value Register 2"
|
|
endif
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRNG_POKER3,TRNG Poker Test Result Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT11 ,Poker count 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CNT10 ,Poker count 10"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CNT9 ,Poker count 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CNT8 ,Poker count 8"
|
|
sif cpuis("ADSP-SC57*")
|
|
endif
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRNG_POKER4,TRNG Poker Test Result Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT15 ,Poker count 15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CNT14 ,Poker count 14"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CNT13 ,Poker count 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CNT12 ,Poker count 12"
|
|
sif cpuis("ADSP-SC57*")
|
|
endif
|
|
if (((per.l(ad:0x310D0000+0x14))&0x100)==0x100)
|
|
sif cpuis("ADSP-SC57*")
|
|
if ((((per.l(ad:0x310D0000+0x14))&0x1000)==0x1000)&&(((per.l(ad:0x310D0000+0x70))&0x20)==0x00))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRNG_TEST,TRNG Test Register"
|
|
bitfld.long 0x00 31. " IRQ ,Test IRQ" "Not forced,Forced"
|
|
hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test pattern"
|
|
bitfld.long 0x00 8.--12. " SEL ,Test select" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " PPROC ,Test post proc" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " RUNPKR ,Test run poker" "Stopped,Run"
|
|
bitfld.long 0x00 4. " CONTPKR ,Continue poker" "Not continue,Continue"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOLFSRFB ,No LFSR feedback" "Keep,Remove"
|
|
bitfld.long 0x00 2. " PATTDET ,Test pattern detect" "Not repeat,Repeat"
|
|
bitfld.long 0x00 1. " PATTFRO ,Test pattern FRO" "Not repeat,Repeat"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENOUT ,Test enable out" "Disabled,Enabled"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRNG_TEST,TRNG Test Register"
|
|
bitfld.long 0x00 31. " IRQ ,Test IRQ" "Not forced,Forced"
|
|
hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test pattern"
|
|
bitfld.long 0x00 8.--12. " SEL ,Test select" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " RUNPKR ,Test run poker" "Stopped,Run"
|
|
bitfld.long 0x00 4. " CONTPKR ,Continue poker" "Not continue,Continue"
|
|
bitfld.long 0x00 3. " NOLFSRFB ,No LFSR feedback" "Keep,Remove"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PATTDET ,Test pattern detect" "Not repeat,Repeat"
|
|
bitfld.long 0x00 1. " PATTFRO ,Test pattern FRO" "Not repeat,Repeat"
|
|
bitfld.long 0x00 0. " ENOUT ,Test enable out" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRNG_TEST,TRNG Test Register"
|
|
bitfld.long 0x00 31. " IRQ ,Test IRQ" "Not forced,Forced"
|
|
hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test pattern"
|
|
bitfld.long 0x00 8.--12. " SEL ,Test select" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " RUNPKR ,Test run poker" "Stopped,Run"
|
|
bitfld.long 0x00 4. " CONTPKR ,Continue poker" "Not continue,Continue"
|
|
bitfld.long 0x00 3. " NOLFSRFB ,No LFSR feedback" "Keep,Remove"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PATTDET ,Test pattern detect" "Not repeat,Repeat"
|
|
bitfld.long 0x00 1. " PATTFRO ,Test pattern FRO" "Not repeat,Repeat"
|
|
bitfld.long 0x00 0. " ENOUT ,Test enable out" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
sif cpuis("ADSP-SC57*")
|
|
if ((((per.l(ad:0x310D0000+0x14))&0x1000)==0x1000)&&(((per.l(ad:0x310D0000+0x70))&0x20)==0x00))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRNG_TEST,TRNG Test Register"
|
|
bitfld.long 0x00 31. " IRQ ,Test IRQ" "Not forced,Forced"
|
|
hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test pattern"
|
|
bitfld.long 0x00 8.--12. " SEL ,Test select" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " PPROC ,Test post proc" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " RUNPKR ,Test run poker" "Stopped,Run"
|
|
bitfld.long 0x00 4. " CONTPKR ,Continue poker" "Not continue,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOLFSRFB ,No LFSR feedback" "Keep,?..."
|
|
bitfld.long 0x00 2. " PATTDET ,Test pattern detect" "Not repeat,?..."
|
|
bitfld.long 0x00 1. " PATTFRO ,Test pattern FRO" "Not repeat,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENOUT ,Test enable out" "Disabled,?..."
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRNG_TEST,TRNG Test Register"
|
|
bitfld.long 0x00 31. " IRQ ,Test IRQ" "Not forced,Forced"
|
|
hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test pattern"
|
|
bitfld.long 0x00 8.--12. " SEL ,Test select" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " RUNPKR ,Test run poker" "Stopped,Run"
|
|
bitfld.long 0x00 4. " CONTPKR ,Continue poker" "Not continue,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOLFSRFB ,No LFSR feedback" "Keep,?..."
|
|
bitfld.long 0x00 2. " PATTDET ,Test pattern detect" "Not repeat,?..."
|
|
bitfld.long 0x00 1. " PATTFRO ,Test pattern FRO" "Not repeat,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENOUT ,Test enable out" "Disabled,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRNG_TEST,TRNG Test Register"
|
|
bitfld.long 0x00 31. " IRQ ,Test IRQ" "Not forced,Forced"
|
|
hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test pattern"
|
|
bitfld.long 0x00 8.--12. " SEL ,Test select" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " RUNPKR ,Test run poker" "Stopped,Run"
|
|
bitfld.long 0x00 4. " CONTPKR ,Continue poker" "Not continue,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOLFSRFB ,No LFSR feedback" "Keep,?..."
|
|
bitfld.long 0x00 2. " PATTDET ,Test pattern detect" "Not repeat,?..."
|
|
bitfld.long 0x00 1. " PATTFRO ,Test pattern FRO" "Not repeat,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENOUT ,Test enable out" "Disabled,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("ADSP-SC57*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRNG_BLKCNT,TRNG Block Count Register"
|
|
hexmask.long 0x00 4.--31. 1. " VALUE , Block Count"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "MEPU (Memory Error Protection Unit)"
|
|
tree "MEC0"
|
|
base ad:0x310A2000
|
|
width 21.
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A2000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MEC0_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--3. " VALUE ,Parity error global control bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MEC0_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--3. " VALUE ,Parity error global control bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MEC0_PEIRQ_GSTAT,Parity Error Interrupt Request Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Parity error global control register lock write error" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0.--3. " VALUE ,Parity error global status bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A2000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MEC0_PERR_CTL,Parity Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error control register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MEC0_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error control register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MEC0_PERR_STAT,Parity Error Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Parity error control or interrupt mask register lock write error" "Not occurred,Occurred"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error status bit"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A2000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "MEC0_PERR_IMASK,Parity Error Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error interrupt mask register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MEC0_PERR_IMASK,Parity Error Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error interrupt mask register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A2000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "MEC0_EEIRQ_GCTL,ECC Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error global control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MEC0_EEIRQ_GCTL,ECC Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error global control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MEC0_EEIRQ_GSTAT,ECC Error Interrupt Request Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,ECC error global control register lock write error" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0. " VALUE ,ECC error global status bit" "Interrupt/trigger not occurred,Interrupt/trigger occurred"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A2000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "MEC0_ECCERR_CTL,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MEC0_ECCERR_CTL,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MEC0_ECCERR_STAT,ECC Error Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,ECC error control or interrupt mask register lock write error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " VALUE ,ECC error status bit" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A2000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "MEC0_ECCERR_IMASK,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error interrupt mask register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error interrupt mask bit" "Unmasked,Masked"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MEC0_ECCERR_IMASK,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error interrupt mask register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error interrupt mask bit" "Unmasked,Masked"
|
|
endif
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "MEC0_CLR,Clear Register"
|
|
bitfld.long 0x00 0. " CLRSTAT ,Clear status bit" "Not cleared,Cleared"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x00 "MEC0_PID4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 4.--7. " SIZE ,Number of 4k blocks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--3. " JEP106CC ,JEDEC JEP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MEC0_PID5,Peripheral ID5 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x08 "MEC0_PID6,Peripheral ID6 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x0C "MEC0_PID7,Peripheral ID7 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x10 "MEC0_PID0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PARTNUM ,Part Number for component identification"
|
|
line.long 0x14 "MEC0_PID1,Peripheral ID1 Register"
|
|
bitfld.long 0x14 4.--7. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " PARTNUM ,Part Number for component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "MEC0_PID2,Peripheral ID2 Register"
|
|
bitfld.long 0x18 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 3. " JEDECASGN ,JEDEC assigned value is used" "Not used,Used"
|
|
bitfld.long 0x18 0.--2. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "MEC0_PID3,Peripheral ID3 Register"
|
|
bitfld.long 0x1C 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " CUSTMOD ,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "MEC0_CID0,Component ID0 Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
line.long 0x24 "MEC0_CID1,Component ID1 Register"
|
|
bitfld.long 0x24 4.--7. " COMPCLASS ,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 0.--3. " PREAMBLE ,Component ID preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "MEC0_CID2,Component ID2 Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
line.long 0x2C "MEC0_CID3,Component ID3 Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MEC1"
|
|
base ad:0x310A3000
|
|
width 21.
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A3000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MEC1_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--3. " VALUE ,Parity error global control bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MEC1_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--3. " VALUE ,Parity error global control bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MEC1_PEIRQ_GSTAT,Parity Error Interrupt Request Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Parity error global control register lock write error" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0.--3. " VALUE ,Parity error global status bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A3000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MEC1_PERR_CTL,Parity Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error control register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MEC1_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error control register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MEC1_PERR_STAT,Parity Error Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Parity error control or interrupt mask register lock write error" "Not occurred,Occurred"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error status bit"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A3000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "MEC1_PERR_IMASK,Parity Error Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error interrupt mask register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MEC1_PERR_IMASK,Parity Error Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error interrupt mask register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A3000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "MEC1_EEIRQ_GCTL,ECC Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error global control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MEC1_EEIRQ_GCTL,ECC Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error global control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MEC1_EEIRQ_GSTAT,ECC Error Interrupt Request Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,ECC error global control register lock write error" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0. " VALUE ,ECC error global status bit" "Interrupt/trigger not occurred,Interrupt/trigger occurred"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A3000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "MEC1_ECCERR_CTL,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MEC1_ECCERR_CTL,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MEC1_ECCERR_STAT,ECC Error Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,ECC error control or interrupt mask register lock write error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " VALUE ,ECC error status bit" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A3000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "MEC1_ECCERR_IMASK,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error interrupt mask register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error interrupt mask bit" "Unmasked,Masked"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MEC1_ECCERR_IMASK,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error interrupt mask register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error interrupt mask bit" "Unmasked,Masked"
|
|
endif
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "MEC1_CLR,Clear Register"
|
|
bitfld.long 0x00 0. " CLRSTAT ,Clear status bit" "Not cleared,Cleared"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x00 "MEC1_PID4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 4.--7. " SIZE ,Number of 4k blocks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--3. " JEP106CC ,JEDEC JEP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MEC1_PID5,Peripheral ID5 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x08 "MEC1_PID6,Peripheral ID6 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x0C "MEC1_PID7,Peripheral ID7 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x10 "MEC1_PID0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PARTNUM ,Part Number for component identification"
|
|
line.long 0x14 "MEC1_PID1,Peripheral ID1 Register"
|
|
bitfld.long 0x14 4.--7. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " PARTNUM ,Part Number for component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "MEC1_PID2,Peripheral ID2 Register"
|
|
bitfld.long 0x18 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 3. " JEDECASGN ,JEDEC assigned value is used" "Not used,Used"
|
|
bitfld.long 0x18 0.--2. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "MEC1_PID3,Peripheral ID3 Register"
|
|
bitfld.long 0x1C 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " CUSTMOD ,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "MEC1_CID0,Component ID0 Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
line.long 0x24 "MEC1_CID1,Component ID1 Register"
|
|
bitfld.long 0x24 4.--7. " COMPCLASS ,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 0.--3. " PREAMBLE ,Component ID preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "MEC1_CID2,Component ID2 Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
line.long 0x2C "MEC1_CID3,Component ID3 Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MEC2"
|
|
base ad:0x310A4000
|
|
width 21.
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A4000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MEC2_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--3. " VALUE ,Parity error global control bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MEC2_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--3. " VALUE ,Parity error global control bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MEC2_PEIRQ_GSTAT,Parity Error Interrupt Request Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Parity error global control register lock write error" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0.--3. " VALUE ,Parity error global status bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A4000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MEC2_PERR_CTL,Parity Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error control register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MEC2_PEIRQ_GCTL,Parity Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error control register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MEC2_PERR_STAT,Parity Error Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Parity error control or interrupt mask register lock write error" "Not occurred,Occurred"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error status bit"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A4000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "MEC2_PERR_IMASK,Parity Error Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error interrupt mask register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MEC2_PERR_IMASK,Parity Error Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " LOCK ,Parity error interrupt mask register lock bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--28. 1. " VALUE ,Parity error control bit"
|
|
endif
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A4000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "MEC2_EEIRQ_GCTL,ECC Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error global control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MEC2_EEIRQ_GCTL,ECC Error Interrupt Request Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error global control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error global control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MEC2_EEIRQ_GSTAT,ECC Error Interrupt Request Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,ECC error global control register lock write error" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0. " VALUE ,ECC error global status bit" "Interrupt/trigger not occurred,Interrupt/trigger occurred"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A4000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "MEC2_ECCERR_CTL,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MEC2_ECCERR_CTL,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error control register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MEC2_ECCERR_STAT,ECC Error Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,ECC error control or interrupt mask register lock write error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " VALUE ,ECC error status bit" "No error,Error"
|
|
if (((per.l(ad:0x3108B000))&0xFF)!=0xAD)&&(((per.l(ad:0x310A4000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "MEC2_ECCERR_IMASK,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error interrupt mask register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error interrupt mask bit" "Unmasked,Masked"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MEC2_ECCERR_IMASK,ECC Error Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,ECC error interrupt mask register lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " VALUE ,ECC error interrupt mask bit" "Unmasked,Masked"
|
|
endif
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "MEC2_CLR,Clear Register"
|
|
bitfld.long 0x00 0. " CLRSTAT ,Clear status bit" "Not cleared,Cleared"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x00 "MEC2_PID4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 4.--7. " SIZE ,Number of 4k blocks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--3. " JEP106CC ,JEDEC JEP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MEC2_PID5,Peripheral ID5 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x08 "MEC2_PID6,Peripheral ID6 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x0C "MEC2_PID7,Peripheral ID7 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " FUTUREUSE ,For future use"
|
|
line.long 0x10 "MEC2_PID0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PARTNUM ,Part Number for component identification"
|
|
line.long 0x14 "MEC2_PID1,Peripheral ID1 Register"
|
|
bitfld.long 0x14 4.--7. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " PARTNUM ,Part Number for component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "MEC2_PID2,Peripheral ID2 Register"
|
|
bitfld.long 0x18 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 3. " JEDECASGN ,JEDEC assigned value is used" "Not used,Used"
|
|
bitfld.long 0x18 0.--2. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "MEC2_PID3,Peripheral ID3 Register"
|
|
bitfld.long 0x1C 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " CUSTMOD ,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "MEC2_CID0,Component ID0 Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
line.long 0x24 "MEC2_CID1,Component ID1 Register"
|
|
bitfld.long 0x24 4.--7. " COMPCLASS ,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 0.--3. " PREAMBLE ,Component ID preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "MEC2_CID2,Component ID2 Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
line.long 0x2C "MEC2_CID3,Component ID3 Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PREAMBLE , Component ID preamble"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DBG (System Debug and Trace Unit)"
|
|
tree "CSPFT0"
|
|
base ad:0x31103000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Main Control Register"
|
|
bitfld.long 0x00 29. " RSENA ,Return Stack Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " CIDSZ ,Context ID Size" "No context ID,One byte,Two bytes,Three bytes"
|
|
bitfld.long 0x00 10. " PB ,Programming Bit" "Trace disabled,Trace enabled"
|
|
bitfld.long 0x00 8. " BBRAN ,Branch Broadcast" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "HWFEAT,Hardware Feature Register"
|
|
bitfld.long 0x00 24.--25. " NCIDC ,Number of Context ID Comparators" "0,1,2,3"
|
|
bitfld.long 0x00 20.--22. " NEXO ,Number of External Outputs" "0,1,2,3,4,?..."
|
|
bitfld.long 0x00 17.--19. " NEXI ,Number of External Inputs" "0,1,2,3,4,?..."
|
|
bitfld.long 0x00 13.--15. " NCNTR ,Number of Counters" "0,1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " NACMP ,Number of Pairs of Address Comparators" "No Address Comparators,1 pair,2 pairs,3 pairs,4 pairs,5 pairs,6 pairs,7 pairs,8 pairs,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TRIGGER,Trigger Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STAT,Status Register"
|
|
bitfld.long 0x00 3. " TRIG ,Trigger bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " TSS ,Trace Start/Stop Bit Status" "Not matched,Matched"
|
|
rbitfld.long 0x00 1. " PB ,Prog Bit Status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " OF ,Overflow" "No overflow,Overflow"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSSCTL,TraceEnable Start/Stop Control Register"
|
|
bitfld.long 0x00 31. " STOP[15] ,Stop Address Comparator 15 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Stop Address Comparator 14 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Stop Address Comparator 13 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Stop Address Comparator 12 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [11] ,Stop Address Comparator 11 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Stop Address Comparator 10 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Stop Address Comparator 9 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Stop Address Comparator 8 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [7] ,Stop Address Comparator 7 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Stop Address Comparator 6 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Stop Address Comparator 5 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Stop Address Comparator 4 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Stop Address Comparator 3 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Stop Address Comparator 2 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Stop Address Comparator 1 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Stop Address Comparator 0 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " START[15] ,Start Address Comparator 15 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Start Address Comparator 14 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Start Address Comparator 13 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Start Address Comparator 12 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Start Address Comparator 11 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Start Address Comparator 10 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Start Address Comparator 9 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Start Address Comparator 8 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Start Address Comparator 7 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Start Address Comparator 6 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Start Address Comparator 5 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Start Address Comparator 4 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Start Address Comparator 3 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Start Address Comparator 2 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Start Address Comparator 1 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Start Address Comparator 0 Select Bit" "Disabled,Enabled"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TEEVENT,TraceEnable Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x04 "TECTL,TraceEnable Control Register"
|
|
bitfld.long 0x04 25. " TSSCENA ,Trace Start and Stop Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " EXCL ,Include and Exclude Control" "Include,Exclude"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ARCS[7] ,Address Range Comparator Select Bit 7" "0,1"
|
|
bitfld.long 0x04 6. " [6] ,Address Range Comparator Select Bit 6" "0,1"
|
|
bitfld.long 0x04 5. " [5] ,Address Range Comparator Select Bit 5" "0,1"
|
|
bitfld.long 0x04 4. " [4] ,Address Range Comparator Select Bit 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Address Range Comparator Select Bit 3" "0,1"
|
|
bitfld.long 0x04 2. " [2] ,Address Range Comparator Select Bit 2" "0,1"
|
|
bitfld.long 0x04 1. " [1] ,Address Range Comparator Select Bit 1" "0,1"
|
|
bitfld.long 0x04 0. " [0] ,Address Range Comparator Select Bit 0" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACVR0,Address Comparator Value Register"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ACVR1,Address Comparator Value Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ACVR2,Address Comparator Value Register"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ACVR3,Address Comparator Value Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ACTR0,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ACTR1,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ACTR2,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ACTR3,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CNTRLDEVR0,Counter Reload Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CNTRLDEVR1,Counter Reload Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CNTENR0,Counter Enable Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CNTENR1,Counter Enable Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CNTVR0,Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current counter value"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CNTVR1,Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current counter value"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "EXTOUTEVR0,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "EXTOUTEVR1,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "EXTOUTEVR2,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "EXTOUTEVR3,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CIDCVR,Context ID Comparator Value"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CIDCMR,Context ID Comparator Mask Register"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SYNCFR,Synchronization Frequency Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " SFREQ ,Synchronization frequency"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "CCER,Configuration Code Extension Register"
|
|
bitfld.long 0x00 26. " VEI ,Virtualization Extensions Implement" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " RSI ,Return Stack Implement" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " TSI ,Time Stamping Implement" "Not implemented,Implemented"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TRACEIDR,CoreSight Trace ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TID ,Trace ID"
|
|
group.long 0xFA4++0x07
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x00 3. " TAGS[3] ,Claim tag set" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Claim tag set" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Claim tag set" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Claim tag set" "No effect,Set"
|
|
line.long 0x04 "CLAIMCLR,Claim Tag Clear Register"
|
|
eventfld.long 0x04 3. " TAGS[3] ,Claim tag clear" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " [2] ,Claim tag clear" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " [1] ,Claim tag clear" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " [0] ,Claim tag clear" "Not cleared,Cleared"
|
|
wgroup.long 0xFB0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xFB4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCKED ,Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCKEN ,Locking Support" "Not required,Required"
|
|
line.long 0x04 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x04 7. " ONE ,ONE" "0,1"
|
|
bitfld.long 0x04 6. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Device Type Identifier Register"
|
|
bitfld.long 0x00 4.--7. " STYPE ,Sub Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TYPE ,Device Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PID4,Peripheral ID4 Register"
|
|
bitfld.long 0x04 4.--7. " SIZE ,Number of 4K Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " JEOP106CC ,JEOP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number"
|
|
line.long 0x04 "PID1,Peripheral ID1 Register"
|
|
bitfld.long 0x04 4.--7. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " PARTNUM ,Part Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PID2,Peripheral ID2 Register"
|
|
bitfld.long 0x08 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. " JEDECASGN ,JEDEC Assigned Value Use" "Not used,Used"
|
|
bitfld.long 0x08 0.--2. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PID3,Peripheral ID3 Register"
|
|
bitfld.long 0x0C 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " COMPID[7:0] ,Component ID"
|
|
line.long 0x04 "CID1,Component ID1 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " COMPID[15:8] ,Component ID"
|
|
line.long 0x08 "CID2,Component ID2 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " COMPID[23:16] ,Component ID"
|
|
line.long 0x0C "CID3,Component ID3 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " COMPID[31:24] ,Component ID"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSPFT1"
|
|
base ad:0x31107000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Main Control Register"
|
|
bitfld.long 0x00 29. " RSENA ,Return Stack Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " CIDSZ ,Context ID Size" "No context ID,One byte,Two bytes,Three bytes"
|
|
bitfld.long 0x00 10. " PB ,Programming Bit" "Trace disabled,Trace enabled"
|
|
bitfld.long 0x00 8. " BBRAN ,Branch Broadcast" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "HWFEAT,Hardware Feature Register"
|
|
bitfld.long 0x00 24.--25. " NCIDC ,Number of Context ID Comparators" "0,1,2,3"
|
|
bitfld.long 0x00 20.--22. " NEXO ,Number of External Outputs" "0,1,2,3,4,?..."
|
|
bitfld.long 0x00 17.--19. " NEXI ,Number of External Inputs" "0,1,2,3,4,?..."
|
|
bitfld.long 0x00 13.--15. " NCNTR ,Number of Counters" "0,1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " NACMP ,Number of Pairs of Address Comparators" "No Address Comparators,1 pair,2 pairs,3 pairs,4 pairs,5 pairs,6 pairs,7 pairs,8 pairs,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TRIGGER,Trigger Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STAT,Status Register"
|
|
bitfld.long 0x00 3. " TRIG ,Trigger bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " TSS ,Trace Start/Stop Bit Status" "Not matched,Matched"
|
|
rbitfld.long 0x00 1. " PB ,Prog Bit Status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " OF ,Overflow" "No overflow,Overflow"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSSCTL,TraceEnable Start/Stop Control Register"
|
|
bitfld.long 0x00 31. " STOP[15] ,Stop Address Comparator 15 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Stop Address Comparator 14 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Stop Address Comparator 13 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Stop Address Comparator 12 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [11] ,Stop Address Comparator 11 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Stop Address Comparator 10 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Stop Address Comparator 9 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Stop Address Comparator 8 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [7] ,Stop Address Comparator 7 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Stop Address Comparator 6 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Stop Address Comparator 5 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Stop Address Comparator 4 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Stop Address Comparator 3 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Stop Address Comparator 2 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Stop Address Comparator 1 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Stop Address Comparator 0 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " START[15] ,Start Address Comparator 15 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Start Address Comparator 14 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Start Address Comparator 13 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Start Address Comparator 12 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Start Address Comparator 11 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Start Address Comparator 10 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Start Address Comparator 9 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Start Address Comparator 8 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Start Address Comparator 7 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Start Address Comparator 6 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Start Address Comparator 5 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Start Address Comparator 4 Select Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Start Address Comparator 3 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Start Address Comparator 2 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Start Address Comparator 1 Select Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Start Address Comparator 0 Select Bit" "Disabled,Enabled"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TEEVENT,TraceEnable Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x04 "TECTL,TraceEnable Control Register"
|
|
bitfld.long 0x04 25. " TSSCENA ,Trace Start and Stop Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " EXCL ,Include and Exclude Control" "Include,Exclude"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ARCS[7] ,Address Range Comparator Select Bit 7" "0,1"
|
|
bitfld.long 0x04 6. " [6] ,Address Range Comparator Select Bit 6" "0,1"
|
|
bitfld.long 0x04 5. " [5] ,Address Range Comparator Select Bit 5" "0,1"
|
|
bitfld.long 0x04 4. " [4] ,Address Range Comparator Select Bit 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Address Range Comparator Select Bit 3" "0,1"
|
|
bitfld.long 0x04 2. " [2] ,Address Range Comparator Select Bit 2" "0,1"
|
|
bitfld.long 0x04 1. " [1] ,Address Range Comparator Select Bit 1" "0,1"
|
|
bitfld.long 0x04 0. " [0] ,Address Range Comparator Select Bit 0" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACVR0,Address Comparator Value Register"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ACVR1,Address Comparator Value Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ACVR2,Address Comparator Value Register"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ACVR3,Address Comparator Value Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ACTR0,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ACTR1,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ACTR2,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ACTR3,Address Comparator Access Type Register"
|
|
bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID comparator control" "Ignored,Matched if comparator 0 matches,Matched if comparator 1 matches,Matched if comparator 2 matches"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CNTRLDEVR0,Counter Reload Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CNTRLDEVR1,Counter Reload Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CNTENR0,Counter Enable Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CNTENR1,Counter Enable Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CNTVR0,Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current counter value"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CNTVR1,Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current counter value"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "EXTOUTEVR0,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "EXTOUTEVR1,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "EXTOUTEVR2,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "EXTOUTEVR3,External Output Event Register"
|
|
bitfld.long 0x00 14.--16. " FUNC ,Logical operation that combines the two resources that define the event" "A,NOT(A),A AND B,NOT(A) AND B,NOT(A) AND NOT(B),A OR B,NOT(A) OR B,NOT(A) OR NOT(B)"
|
|
hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CIDCVR,Context ID Comparator Value"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CIDCMR,Context ID Comparator Mask Register"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SYNCFR,Synchronization Frequency Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " SFREQ ,Synchronization frequency"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "CCER,Configuration Code Extension Register"
|
|
bitfld.long 0x00 26. " VEI ,Virtualization Extensions Implement" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " RSI ,Return Stack Implement" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " TSI ,Time Stamping Implement" "Not implemented,Implemented"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TRACEIDR,CoreSight Trace ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TID ,Trace ID"
|
|
group.long 0xFA4++0x07
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x00 3. " TAGS[3] ,Claim tag set" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Claim tag set" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Claim tag set" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Claim tag set" "No effect,Set"
|
|
line.long 0x04 "CLAIMCLR,Claim Tag Clear Register"
|
|
eventfld.long 0x04 3. " TAGS[3] ,Claim tag clear" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " [2] ,Claim tag clear" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " [1] ,Claim tag clear" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " [0] ,Claim tag clear" "Not cleared,Cleared"
|
|
wgroup.long 0xFB0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xFB4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCKED ,Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCKEN ,Locking Support" "Not required,Required"
|
|
line.long 0x04 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x04 7. " ONE ,ONE" "0,1"
|
|
bitfld.long 0x04 6. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Device Type Identifier Register"
|
|
bitfld.long 0x00 4.--7. " STYPE ,Sub Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TYPE ,Device Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PID4,Peripheral ID4 Register"
|
|
bitfld.long 0x04 4.--7. " SIZE ,Number of 4K Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " JEOP106CC ,JEOP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number"
|
|
line.long 0x04 "PID1,Peripheral ID1 Register"
|
|
bitfld.long 0x04 4.--7. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " PARTNUM ,Part Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PID2,Peripheral ID2 Register"
|
|
bitfld.long 0x08 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. " JEDECASGN ,JEDEC Assigned Value Use" "Not used,Used"
|
|
bitfld.long 0x08 0.--2. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PID3,Peripheral ID3 Register"
|
|
bitfld.long 0x0C 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " COMPID[7:0] ,Component ID"
|
|
line.long 0x04 "CID1,Component ID1 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " COMPID[15:8] ,Component ID"
|
|
line.long 0x08 "CID2,Component ID2 Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " COMPID[23:16] ,Component ID"
|
|
line.long 0x0C "CID3,Component ID3 Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " COMPID[31:24] ,Component ID"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TAPC"
|
|
base ad:0x31130000
|
|
width 14.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IDCODE,IDCODE Register"
|
|
hexmask.long.byte 0x00 28.--31. 1. " REVID ,Silicon revision"
|
|
hexmask.long.word 0x00 12.--27. 1. " JTAGID ,JTAG ID"
|
|
hexmask.long.word 0x00 1.--11. 1. " MNFID ,Manufacturer ID"
|
|
bitfld.long 0x00 0. " LSB ,IDCODE LSB" "0,1"
|
|
line.long 0x04 "USERCODE,USERCODE Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDBGKEY_CTL,Secure Debug Key Control Register"
|
|
bitfld.long 0x00 0. " VALID ,SDBGKEY valid" "Not valid,Valid"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SDBGKEY_STAT,Secure Debug Key Status Register"
|
|
sif cpuis("ADSPCM40*")
|
|
bitfld.long 0x00 2. " VALID ,SDBGKEY is Valid" "Not valid,Valid"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " FAIL ,SDBGKEY match fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " PASS ,SDBGKEY match pass" "Not passed,Passed"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SDBGKEY0,Secure Debug Key 0 Register"
|
|
line.long 0x04 "SDBGKEY1,Secure Debug Key 1 Register"
|
|
line.long 0x08 "SDBGKEY2,Secure Debug Key 2 Register"
|
|
line.long 0x0C "SDBGKEY3,Secure Debug Key 3 Register"
|
|
sif cpuis("ADSPCM40*")
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "USERKEYCMP0,User Key Compare 0 Register"
|
|
line.long 0x04 "USERKEYCMP1,User Key Compare 1 Register"
|
|
line.long 0x08 "USERKEYCMP2,User Key Compare 2 Register"
|
|
line.long 0x0C "USERKEYCMP3,User Key Compare 3 Register"
|
|
if (((per.l(ad:0x31130000+0xF0))&0xAD)==0xAD)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RCMSG,Run Control Message Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ERASE_KEY ,Erase Key"
|
|
bitfld.long 0x00 15. " ERASE ,Erase on chip flash" "0,1"
|
|
bitfld.long 0x00 13. " HALTONENTRY ,Halt on Entry" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,Do Not Execute Hook Routine" "Performed,Not performed"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No Faults" "Performed,Not performed"
|
|
bitfld.long 0x00 5. " NOCACHE ,No Cache" "Initialized and enabled,Not initialized or Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No Memory Initialization" "Performed,Not performed"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Executed,Not executed"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No Vector Initialize" "Vector,Not vector"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NOKERNEL ,No Boot Kernel" "Executed,Not executed"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RCMSG,Run Control Message Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ERASE_KEY ,Erase Key"
|
|
rbitfld.long 0x00 15. " ERASE ,Erase on chip flash" "0,1"
|
|
bitfld.long 0x00 13. " HALTONENTRY ,Halt on Entry" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,Do Not Execute Hook Routine" "Performed,Not performed"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No Faults" "Performed,Not performed"
|
|
bitfld.long 0x00 5. " NOCACHE ,No Cache" "Initialized and enabled,Not initialized or Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No Memory Initialization" "Performed,Not performed"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Executed,Not executed"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No Vector Initialize" "Vector,Not vector"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NOKERNEL ,No Boot Kernel" "Executed,Not executed"
|
|
endif
|
|
group.long 0xF4++0x0B
|
|
line.long 0x00 "RCMSG_CLR,Run Control Message Clear Register"
|
|
line.long 0x04 "RCMSG_SET,Run Control Message Set Register"
|
|
line.long 0x08 "RCMSG_TOG,Run Control Message Toggle Register"
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DBGCTL,Debug Control Register"
|
|
bitfld.long 0x00 15. " SPIDENTRACE ,SPIDEN for coresight trace modules" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " NIDENTRACE ,NIDEN for coresight trace modules" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DBGENTRACE ,DBGEN for coresight trace modules" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " NIDENCTISYS ,NIDEN for system CTI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DBGENCTISYS ,DBGEN for system CTI" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SPIDENSTM ,SPIDEN for STM" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SPNIDENSTM ,SPNIDEN for STM" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " NIDENSTM ,NIDEN for STM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DBGENSTM ,DBGEN for STM" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DBGENC2 ,DBGEN for core 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DBGENC1 ,DBGEN for core 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SPIDENC0 ,SPIDEN for core 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPNIDENC0 ,SPNIDEN for core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NIDENC0 ,NIDEN for core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DBGENC0 ,DBGEN for core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIDENDAP ,SPIDEN for DAP" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
textline ""
|