2222 lines
112 KiB
Plaintext
2222 lines
112 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AC30M1x64 On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-02-06 JDU
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; 2023-11-02 NEJ
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; @Manufacturer: ABOV - ABOV Semiconductor Co., Ltd.
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; @Doc: Generated (TRACE32, build: 164232.), based on:
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; AC30M1x64.svd (Ver. 1.0)
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; @Core: Cortex-M0
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; @Chip: AC30M1332LBN, AC30M1332UB, AC30M1364LBN, AC30M1364UB, AC30M1464LBN
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perac30m1x64.per 16938 2023-11-07 18:43:11Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (12-bit Analog-to-Digital Converter)"
|
|
base ad:0x4000B000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MR,ADC Mode Register"
|
|
hexmask.long.byte 0x0 12.--16. 1. "STSEL,STSEL"
|
|
bitfld.long 0x0 8.--10. "SEQCNT,SEQCNT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 7. "ADEN,ADC Enable" "0,1"
|
|
bitfld.long 0x0 6. "ARST,ARST" "0,1"
|
|
bitfld.long 0x0 4.--5. "ADMOD,ADC convert mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TRGSEL,TRGSEL" "0,1,2,3"
|
|
line.long 0x4 "CSCR,Current Sequence/Channel Register"
|
|
bitfld.long 0x4 4.--6. "CSEQN,CSEQN" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CACH,Current Active Channel"
|
|
line.long 0x8 "CCR,Clock Control Register"
|
|
bitfld.long 0x8 15. "ADCPDA,ADC R-ADC disable to save power" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "CLKDIV,ADC clock divider"
|
|
bitfld.long 0x8 7. "ADCPD,ADC Power down" "0,1"
|
|
bitfld.long 0x8 6. "EXTCLK,ADCuse external clock" "0,1"
|
|
bitfld.long 0x8 5. "CLKINVT,divided clock inversion" "0,1"
|
|
line.long 0xC "TRG,ADC Trigger Selection Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "SEQTRG7,8th Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 24.--27. 1. "SEQTRG6,7th Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 20.--23. 1. "SEQTRG5,6th Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 16.--19. 1. "SEQTRG4,5th Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 12.--15. 1. "SEQTRG3,4th Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 8.--11. 1. "SEQTRG2,3rd Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 4.--7. 1. "SEQTRG1,2nd Sequence Trigger Source"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEQTRG0,1st Sequence Trigger Source"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SCSR,ADC Sequence Channel Selection Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SEQ7CH,8th conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SEQ6CH,7th conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SEQ5CH,6th conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SEQ4CH,5th conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "SEQ3CH,4th conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SEQ2CH,3rd conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SEQ1CH,2nd conversion sequence channel selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SEQ0CH,1st conversion sequence channel selection"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "CR,ADCn Control Register"
|
|
bitfld.long 0x0 7. "ASTOP,ADC Stop" "0,1"
|
|
bitfld.long 0x0 0. "ASTART,ADC conversion start" "0,1"
|
|
line.long 0x4 "SR,ADCn Status Register"
|
|
bitfld.long 0x4 7. "EOC,ADC End Flag" "0,1"
|
|
bitfld.long 0x4 6. "ABUSY,ADC conversion busy flag" "0,1"
|
|
bitfld.long 0x4 3. "TRGIRQ,ADC Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x4 2. "EOSIRQ,EOSIRQ" "0,1"
|
|
bitfld.long 0x4 0. "EOCIRQ,EOCIRQ" "0,1"
|
|
line.long 0x8 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x8 3. "TRGIRQE,ADC trigger conversion interrupt enable" "0,1"
|
|
bitfld.long 0x8 2. "EOSIRQE,ADC sequence conversion interrupt enable" "0,1"
|
|
bitfld.long 0x8 0. "EOCIRQE,ADC single conversion interrupt enable" "0,1"
|
|
group.long 0x30++0x1F
|
|
line.long 0x0 "DR0,ADC Data Register 0"
|
|
hexmask.long.word 0x0 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0x4 "DR1,ADC Data Register 1"
|
|
hexmask.long.word 0x4 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0x8 "DR2,ADC Data Register 2"
|
|
hexmask.long.word 0x8 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0xC "DR3,ADC Data Register 3"
|
|
hexmask.long.word 0xC 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0x10 "DR4,ADC Data Register 4"
|
|
hexmask.long.word 0x10 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0x14 "DR5,ADC Data Register 5"
|
|
hexmask.long.word 0x14 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0x18 "DR6,ADC Data Register 6"
|
|
hexmask.long.word 0x18 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
line.long 0x1C "DR7,ADC Data Register 7"
|
|
hexmask.long.word 0x1C 4.--15. 1. "ADCDATA,ADC conversion result data"
|
|
tree.end
|
|
tree "DIV64 (Divider)"
|
|
base ad:0x40000500
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR,Divider Control Register"
|
|
bitfld.long 0x0 10. "I_ERROR,Divide by zero flag" "0,1"
|
|
bitfld.long 0x0 9. "BUSY,Divider is now under operating" "0,1"
|
|
bitfld.long 0x0 8. "DONE,Divider operation done flag" "0,1"
|
|
bitfld.long 0x0 4. "MODE,Start operation mode" "0,1"
|
|
bitfld.long 0x0 0. "START,Divide operation start command." "0,1"
|
|
line.long 0x4 "AREGL,AREGL (Dividend) Low 32bit Register"
|
|
line.long 0x8 "AREGH,AREG (Dividend) High 32bit Register"
|
|
line.long 0xC "BREG,BREG (Divisor) Register"
|
|
line.long 0x10 "QREGL,QREG (Quotient) Low 32bit Register"
|
|
line.long 0x14 "QREGH,QREG (Quotient) High 32bit Register"
|
|
line.long 0x18 "RREG,RREG (Remainter) Register"
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x40000100
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "MR,Flash Memory Mode Register"
|
|
rbitfld.long 0x0 24. "IDLE,Idle mode status" "0,1"
|
|
rbitfld.long 0x0 23. "TESTEN,Flash test" "0,1"
|
|
rbitfld.long 0x0 22. "AMBAEN,AMBA mode enable" "0,1"
|
|
rbitfld.long 0x0 21. "PROTEN,Flash protection" "0,1"
|
|
rbitfld.long 0x0 17. "TRMEN,Trim Mode entry status" "0,1"
|
|
rbitfld.long 0x0 16. "TRM,Trim Mode status" "0,1"
|
|
rbitfld.long 0x0 9. "FEMOD,Flash Mode entry status" "0,1"
|
|
rbitfld.long 0x0 8. "FMOD,Flash Mode status" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ACODE,Flash Mode/Trim Mode"
|
|
line.long 0x4 "CR,Flash Memory Control Register"
|
|
bitfld.long 0x4 31. "OTP3,OTP3" "0,1"
|
|
bitfld.long 0x4 30. "OTP2,OTP2" "0,1"
|
|
bitfld.long 0x4 29. "OTP1,OTP1" "0,1"
|
|
bitfld.long 0x4 28. "OTP0,OTP0" "0,1"
|
|
bitfld.long 0x4 20. "TMREN,program timer enable" "0,1"
|
|
bitfld.long 0x4 16.--17. "TEST,TEST" "0,1,2,3"
|
|
bitfld.long 0x4 15. "VPPOUT,Charge pump Vpp Output" "0,1"
|
|
bitfld.long 0x4 14. "EVER,Erase verify Mode" "0,1"
|
|
bitfld.long 0x4 13. "PVER,Program verify mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "BLKE,128page write enable for full chip writing to save program time" "0,1"
|
|
bitfld.long 0x4 11. "DMYE,DUMMY Area enable" "0,1"
|
|
bitfld.long 0x4 10. "OTPE,OTP area a b c d enable" "0,1"
|
|
bitfld.long 0x4 9. "AEE,AEE" "0,1"
|
|
bitfld.long 0x4 8. "AEF,All Erase" "0,1"
|
|
bitfld.long 0x4 7. "SUBACT,SUBACT" "0,1"
|
|
bitfld.long 0x4 6. "PPGM,PPGM" "0,1"
|
|
bitfld.long 0x4 5. "PMODE,Pmode Enable" "0,1"
|
|
bitfld.long 0x4 4. "WE,write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PBLD,page buffer load" "0,1"
|
|
bitfld.long 0x4 2. "PGM,PGM" "0,1"
|
|
bitfld.long 0x4 1. "ERS,program mode/erase mode Enable" "0,1"
|
|
bitfld.long 0x4 0. "PBR,page buffer reset" "0,1"
|
|
line.long 0x8 "AR,Flash Memory Address Register"
|
|
hexmask.long.word 0x8 0.--14. 1. "FADDR,16K words address"
|
|
line.long 0xC "DR,Flash Memory Data Register"
|
|
hexmask.long 0xC 0.--31. 1. "FDATA,Flash PGM data"
|
|
line.long 0x10 "TMR,Flash Memory Timer Register"
|
|
hexmask.long.tbyte 0x10 0.--17. 1. "TMR,Erase/PGM timer"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "TICK,Flash Memory Tick Timer register"
|
|
hexmask.long 0x0 0.--31. 1. "FTICK,TICK"
|
|
line.long 0x4 "CRC,Flash Memory CRC value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CRC,CRC16 Value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CFG,Flash Memory CONFIG value register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WRITEKEY,WRITEKEY"
|
|
bitfld.long 0x0 15. "HRESPD,HRESPD" "0,1"
|
|
bitfld.long 0x0 12. "TESTCLK,TESTCLK" "0,1"
|
|
bitfld.long 0x0 8.--9. "WAIT,WAIT" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CRCINIT,CRCINIT" "0,1"
|
|
bitfld.long 0x0 6. "CRCEN,CRC16 Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TRIM,TRIM"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "HWID,Flash Hardware ID Register"
|
|
hexmask.long 0x0 0.--31. 1. "FHWID,FHWID Value"
|
|
line.long 0x4 "SIZE,Flash size option register"
|
|
hexmask.long 0x4 0.--31. 1. "FMSIZE,FMSIZE Value"
|
|
group.long 0x74++0xB
|
|
line.long 0x0 "BOOTCR,Boot ROM Remap Clear Register"
|
|
bitfld.long 0x0 4. "SREMAP,SRAM remap enable" "0,1"
|
|
bitfld.long 0x0 0. "BOOTROM,Boot mode" "0,1"
|
|
line.long 0x4 "WPROT,Flash Memory Write Protection Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "WPEN,WP access enable"
|
|
hexmask.long.word 0x4 0.--15. 1. "WP,Sector protect"
|
|
line.long 0x8 "RPROT,Flash Memory Read Protection Register"
|
|
tree.end
|
|
tree "FRT (Free-Run Timer)"
|
|
base ad:0x40000600
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "MR,FRT Mode Register"
|
|
bitfld.long 0x0 4.--5. "CLKSEL,FRT Counter clock source control" "0,1,2,3"
|
|
bitfld.long 0x0 2. "MCD,Counter Match Clear Disable bit" "0,1"
|
|
bitfld.long 0x0 1. "OVIE,Over Flow Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "MIE,Match Interrupt Enable bit" "0,1"
|
|
line.long 0x4 "CR,FRT Control Register"
|
|
bitfld.long 0x4 3. "RREQ,FRT Counter read request bit" "0,1"
|
|
bitfld.long 0x4 2. "CLR,FRT Counter register clear bit" "0,1"
|
|
bitfld.long 0x4 1. "HOLD,FRT Counter register hold bit" "0,1"
|
|
bitfld.long 0x4 0. "EN,FRT enable bit" "0,1"
|
|
line.long 0x8 "PER,FRTPER FRT Period Match Register"
|
|
line.long 0xC "CNT,FRTCNT FRT Counter Register"
|
|
line.long 0x10 "SR,FRTSR FRT Status Register"
|
|
bitfld.long 0x10 2. "RACK,Read Counter Acknowledge bit" "0,1"
|
|
bitfld.long 0x10 1. "OVF,Overflow Interrupt Flag" "0,1"
|
|
bitfld.long 0x10 0. "MF,Interrupt Flag" "0,1"
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x0
|
|
tree "PA"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ODR,PORT n Output Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Output level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Output level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Output level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Output level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Output level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Output level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Output level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Output level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Output level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Output level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Output level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Output level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Output level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Output level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Output level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Output level" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "IDR,PORT n Input Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Input level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Input level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Input level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Input level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Input level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Input level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Input level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Input level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Input level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Input level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Input level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Input level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Input level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Input level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Input level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Input level" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "BSR,PORT n Bit Set Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit set" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit set" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit set" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit set" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit set" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit set" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit set" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit set" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit set" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit set" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit set" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit set" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit set" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit set" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit set" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "BCR,PORT n Bit Clear Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit clear" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit clear" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit clear" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit clear" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit clear" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit clear" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit clear" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit clear" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit clear" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit clear" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit clear" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit clear" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit clear" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit clear" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit clear" "0,1"
|
|
tree.end
|
|
tree "PB"
|
|
base ad:0x40002100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ODR,PORT n Output Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Output level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Output level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Output level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Output level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Output level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Output level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Output level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Output level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Output level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Output level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Output level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Output level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Output level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Output level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Output level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Output level" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "IDR,PORT n Input Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Input level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Input level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Input level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Input level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Input level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Input level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Input level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Input level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Input level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Input level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Input level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Input level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Input level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Input level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Input level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Input level" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "BSR,PORT n Bit Set Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit set" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit set" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit set" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit set" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit set" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit set" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit set" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit set" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit set" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit set" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit set" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit set" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit set" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit set" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit set" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "BCR,PORT n Bit Clear Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit clear" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit clear" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit clear" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit clear" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit clear" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit clear" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit clear" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit clear" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit clear" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit clear" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit clear" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit clear" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit clear" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit clear" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit clear" "0,1"
|
|
tree.end
|
|
tree "PC"
|
|
base ad:0x40002200
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ODR,PORT n Output Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Output level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Output level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Output level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Output level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Output level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Output level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Output level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Output level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Output level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Output level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Output level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Output level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Output level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Output level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Output level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Output level" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "IDR,PORT n Input Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Input level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Input level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Input level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Input level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Input level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Input level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Input level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Input level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Input level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Input level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Input level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Input level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Input level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Input level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Input level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Input level" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "BSR,PORT n Bit Set Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit set" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit set" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit set" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit set" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit set" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit set" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit set" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit set" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit set" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit set" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit set" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit set" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit set" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit set" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit set" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "BCR,PORT n Bit Clear Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit clear" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit clear" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit clear" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit clear" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit clear" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit clear" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit clear" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit clear" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit clear" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit clear" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit clear" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit clear" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit clear" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit clear" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit clear" "0,1"
|
|
tree.end
|
|
tree "PD"
|
|
base ad:0x40002300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ODR,PORT n Output Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Output level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Output level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Output level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Output level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Output level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Output level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Output level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Output level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Output level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Output level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Output level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Output level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Output level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Output level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Output level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Output level" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "IDR,PORT n Input Data Register"
|
|
bitfld.long 0x0 15. "P15,P15 Input level" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 Input level" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 Input level" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 Input level" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 Input level" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 Input level" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 Input level" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 Input level" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 Input level" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 Input level" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 Input level" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 Input level" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 Input level" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 Input level" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 Input level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 Input level" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "BSR,PORT n Bit Set Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit set" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit set" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit set" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit set" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit set" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit set" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit set" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit set" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit set" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit set" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit set" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit set" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit set" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit set" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit set" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "BCR,PORT n Bit Clear Register"
|
|
bitfld.long 0x0 15. "P15,P15 bit clear" "0,1"
|
|
bitfld.long 0x0 14. "P14,P14 bit clear" "0,1"
|
|
bitfld.long 0x0 13. "P13,P13 bit clear" "0,1"
|
|
bitfld.long 0x0 12. "P12,P12 bit clear" "0,1"
|
|
bitfld.long 0x0 11. "P11,P11 bit clear" "0,1"
|
|
bitfld.long 0x0 10. "P10,P10 bit clear" "0,1"
|
|
bitfld.long 0x0 9. "P9,P9 bit clear" "0,1"
|
|
bitfld.long 0x0 8. "P8,P8 bit clear" "0,1"
|
|
bitfld.long 0x0 7. "P7,P7 bit clear" "0,1"
|
|
bitfld.long 0x0 6. "P6,P6 bit clear" "0,1"
|
|
bitfld.long 0x0 5. "P5,P5 bit clear" "0,1"
|
|
bitfld.long 0x0 4. "P4,P4 bit clear" "0,1"
|
|
bitfld.long 0x0 3. "P3,P3 bit clear" "0,1"
|
|
bitfld.long 0x0 2. "P2,P2 bit clear" "0,1"
|
|
bitfld.long 0x0 1. "P1,P1 bit clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P0,P0 bit clear" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x4000A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DR,IIC Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DR,Data"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 7. "GCALL,General call flag" "0,1"
|
|
bitfld.long 0x0 6. "TEND,1 byte transmission complete flag" "0,1"
|
|
bitfld.long 0x0 5. "STOP,Stop Flag" "0,1"
|
|
bitfld.long 0x0 4. "SSEL,slave flag" "0,1"
|
|
bitfld.long 0x0 3. "MLOST,Mastership lost flag" "0,1"
|
|
bitfld.long 0x0 2. "BUSY,busy flag" "0,1"
|
|
bitfld.long 0x0 1. "TMODE,Transmit/reciever mode flag" "0,1"
|
|
bitfld.long 0x0 0. "RXACK,RX ack flag" "0,1"
|
|
line.long 0x4 "SAR,IIC Slave Address Register"
|
|
hexmask.long.byte 0x4 1.--7. 1. "SVAD,7 bits slave address"
|
|
bitfld.long 0x4 0. "GCEN,general call enable bit" "0,1"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "CR,IIC Control Register"
|
|
bitfld.long 0x0 8.--9. "INTDEL,Interval delay value between address and data transfer" "0,1,2,3"
|
|
bitfld.long 0x0 7. "IIF,Interrupt flag bit" "0,1"
|
|
bitfld.long 0x0 5. "SOFTRST,Soft reset enable bit" "0,1"
|
|
bitfld.long 0x0 4. "INTEN,Interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "ACKEN,ACK enabit bit in receiver mode" "0,1"
|
|
bitfld.long 0x0 1. "STOP,Stop enable bit" "0,1"
|
|
bitfld.long 0x0 0. "START,transmission start bit in master mode" "0,1"
|
|
line.long 0x4 "SCLL,IIC SCL LOW duration Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SCLL,SCL Low duration value"
|
|
line.long 0x8 "SCLH,IIC SCL HIGH duration Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SCLH,SCL High duration value"
|
|
line.long 0xC "SDH,SDA Hold Register"
|
|
hexmask.long.word 0xC 0.--14. 1. "SDH,SDA Hold time"
|
|
tree.end
|
|
tree "MPWM (Motor Pulse-Width Modulator)"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x4F
|
|
line.long 0x0 "MR,MPWM Mode Register"
|
|
bitfld.long 0x0 15. "MOTORB,MOTORB" "0,1"
|
|
bitfld.long 0x0 7. "UAO,UAO" "0,1"
|
|
bitfld.long 0x0 5. "TUP,TUP" "0,1"
|
|
bitfld.long 0x0 4. "BUP,BUP" "0,1"
|
|
bitfld.long 0x0 1.--2. "MCHMOD,MCHMOD" "0,1,2,3"
|
|
bitfld.long 0x0 0. "UPDOWN,PWM counter mode" "0,1"
|
|
line.long 0x4 "OLR,MPWM Port Mode Register"
|
|
bitfld.long 0x4 5. "WHL,WHL" "0,1"
|
|
bitfld.long 0x4 4. "VHL,VHL" "0,1"
|
|
bitfld.long 0x4 3. "UHL,UHL" "0,1"
|
|
bitfld.long 0x4 2. "WLL,WLL" "0,1"
|
|
bitfld.long 0x4 1. "VLL,VLL" "0,1"
|
|
bitfld.long 0x4 0. "ULL,ULL" "0,1"
|
|
line.long 0x8 "FOLR,MPWM Force Output Level Register"
|
|
bitfld.long 0x8 5. "WHFL,WHFL" "0,1"
|
|
bitfld.long 0x8 4. "VHFL,VHFL" "0,1"
|
|
bitfld.long 0x8 3. "UHFL,UHFL" "0,1"
|
|
bitfld.long 0x8 2. "WLFL,WLFL" "0,1"
|
|
bitfld.long 0x8 1. "VLFL,VLFL" "0,1"
|
|
bitfld.long 0x8 0. "ULFL,ULFL" "0,1"
|
|
line.long 0xC "PRD,MPWM Period Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM period"
|
|
line.long 0x10 "DUH,MPWM Duty UH Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "DUTY,duty of UH output"
|
|
line.long 0x14 "DVH,MPWM Duty VH Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "DUTY,duty of VH data"
|
|
line.long 0x18 "DWH,MPWM Duty WH Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "DUTY,duty of WH output"
|
|
line.long 0x1C "DUL,MPWM Duty UL Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DUTY,duty of UL output"
|
|
line.long 0x20 "DVL,MPWM Duty UL Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "DUTY,duty of VL output"
|
|
line.long 0x24 "DWL,MPWM Duty WL Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "DUTY,duty of WL output"
|
|
line.long 0x28 "CR1,MPWM Control Register 1"
|
|
bitfld.long 0x28 8.--10. "IRQN,IRQ intervel Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 0. "PWMEN,PWMEN" "0,1"
|
|
line.long 0x2C "CR2,MPWM Control Register 2"
|
|
bitfld.long 0x2C 7. "HALT,HALT" "0,1"
|
|
bitfld.long 0x2C 0. "PSTART,PWM start" "0,1"
|
|
line.long 0x30 "SR,MPWM Status Register"
|
|
bitfld.long 0x30 15. "DOWN,PWM count up/down" "0,1"
|
|
bitfld.long 0x30 12.--14. "IRQCNT,PWM count number of period match" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x30 7. "PRDIRQ,PWM period interrupt flag" "0,1"
|
|
bitfld.long 0x30 6. "BOTIRQ,PWM bottom interrupt flag" "0,1"
|
|
bitfld.long 0x30 5. "DWHIF,DWHIF" "0,1"
|
|
bitfld.long 0x30 4. "DVHIF,DVHIF" "0,1"
|
|
bitfld.long 0x30 3. "DUHIF,DUHIF" "0,1"
|
|
bitfld.long 0x30 2. "DWLIF,DWLIF" "0,1"
|
|
bitfld.long 0x30 1. "DVLIF,DVLIF" "0,1"
|
|
bitfld.long 0x30 0. "DULIF,DULIF" "0,1"
|
|
line.long 0x34 "IER,MPWM Interrupt Enable Register"
|
|
bitfld.long 0x34 7. "PRDIEN,Period interrupt enable" "0,1"
|
|
bitfld.long 0x34 6. "BOTIE,bottom interrupt enable" "0,1"
|
|
bitfld.long 0x34 5. "WHIE,WHIE" "0,1"
|
|
bitfld.long 0x34 4. "VHIE,VHIE" "0,1"
|
|
bitfld.long 0x34 3. "UHIE,UHIE" "0,1"
|
|
bitfld.long 0x34 2. "WLIE,WLIE" "0,1"
|
|
bitfld.long 0x34 1. "VLIE,VLIE" "0,1"
|
|
bitfld.long 0x34 0. "ULIE,ULIE" "0,1"
|
|
line.long 0x38 "CNT,MPWM Counter Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "CNT,pwm counter value"
|
|
line.long 0x3C "DTR,MPWM Dead Time Register"
|
|
bitfld.long 0x3C 15. "DTEN,dead time Enable" "0,1"
|
|
bitfld.long 0x3C 14. "PSHRT,PSHRT" "0,1"
|
|
bitfld.long 0x3C 8. "DTCLK,dead time clk select" "0,1"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "DT,dead time value"
|
|
line.long 0x40 "PCR0,MPWM Protection control Register 0"
|
|
bitfld.long 0x40 15. "PROTEN,PROTEN" "0,1"
|
|
bitfld.long 0x40 14. "PROTPOL,PROTPOL" "0,1"
|
|
bitfld.long 0x40 8.--10. "PROTD,PROTD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 7. "PROTIE,PROTIE" "0,1"
|
|
bitfld.long 0x40 5. "WHPROTM,WHPROTM" "0,1"
|
|
bitfld.long 0x40 4. "VHPROTM,VHPROTM" "0,1"
|
|
bitfld.long 0x40 3. "UHPROTM,UHPROTM" "0,1"
|
|
bitfld.long 0x40 2. "WLPROTM,WLPROTM" "0,1"
|
|
bitfld.long 0x40 1. "VLPROTM,VLPROTM" "0,1"
|
|
bitfld.long 0x40 0. "ULPROTM,ULPROTM" "0,1"
|
|
line.long 0x44 "PSR0,MPWM Protection Status Register 0"
|
|
hexmask.long.byte 0x44 8.--15. 1. "PROTKEY,PROTKEY(0xCA)"
|
|
bitfld.long 0x44 7. "PROTIF,PROTIF" "0,1"
|
|
bitfld.long 0x44 5. "WHPROTF,WHPROTF" "0,1"
|
|
bitfld.long 0x44 4. "VHPROTF,VHPROTF" "0,1"
|
|
bitfld.long 0x44 3. "UHPROTF,UHPROTF" "0,1"
|
|
bitfld.long 0x44 2. "WLPROTF,WLPROTF" "0,1"
|
|
bitfld.long 0x44 1. "VLPROTF,VLPROTF" "0,1"
|
|
bitfld.long 0x44 0. "ULPROTF,ULPROTF" "0,1"
|
|
line.long 0x48 "PCR1,MPWM Protection control Register 1"
|
|
bitfld.long 0x48 15. "PROTEN,PROTEN" "0,1"
|
|
bitfld.long 0x48 14. "PROTPOL,PROTPOL" "0,1"
|
|
bitfld.long 0x48 8.--10. "PROTD,PROTD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 7. "PROTIE,PROTIE" "0,1"
|
|
bitfld.long 0x48 5. "WHPROTM,WHPROTM" "0,1"
|
|
bitfld.long 0x48 4. "VHPROTM,VHPROTM" "0,1"
|
|
bitfld.long 0x48 3. "UHPROTM,UHPROTM" "0,1"
|
|
bitfld.long 0x48 2. "WLPROTM,WLPROTM" "0,1"
|
|
bitfld.long 0x48 1. "VLPROTM,VLPROTM" "0,1"
|
|
bitfld.long 0x48 0. "ULPROTM,ULPROTM" "0,1"
|
|
line.long 0x4C "PSR1,MPWM Protection Status Register 1"
|
|
hexmask.long.byte 0x4C 8.--15. 1. "PROTKEY,PROTKEY(0xAC)"
|
|
bitfld.long 0x4C 7. "PROTIF,PROTIF" "0,1"
|
|
bitfld.long 0x4C 5. "WHPROTF,WHPROTF" "0,1"
|
|
bitfld.long 0x4C 4. "VHPROTF,VHPROTF" "0,1"
|
|
bitfld.long 0x4C 3. "UHPROTF,UHPROTF" "0,1"
|
|
bitfld.long 0x4C 2. "WLPROTF,WLPROTF" "0,1"
|
|
bitfld.long 0x4C 1. "VLPROTF,VLPROTF" "0,1"
|
|
bitfld.long 0x4C 0. "ULPROTF,ULPROTF" "0,1"
|
|
group.long 0x58++0x17
|
|
line.long 0x0 "ATR1,MPWMn ADC Trigger Counter 1 Register"
|
|
bitfld.long 0x0 19. "ATUDT,Trigger register update mode" "0,1"
|
|
bitfld.long 0x0 16.--17. "ATMOD,ADC Trigger mode register" "0,1,2,3"
|
|
hexmask.long.word 0x0 0.--15. 1. "ATCNT,ADC Trigger counter"
|
|
line.long 0x4 "ATR2,MPWMn ADC Trigger Counter 2 Register"
|
|
bitfld.long 0x4 19. "ATUDT,Trigger register update mode" "0,1"
|
|
bitfld.long 0x4 16.--17. "ATMOD,ADC Trigger mode register" "0,1,2,3"
|
|
hexmask.long.word 0x4 0.--15. 1. "ATCNT,ADC Trigger counter"
|
|
line.long 0x8 "ATR3,MPWMn ADC Trigger Counter 3 Register"
|
|
bitfld.long 0x8 19. "ATUDT,Trigger register update mode" "0,1"
|
|
bitfld.long 0x8 16.--17. "ATMOD,ADC Trigger mode register" "0,1,2,3"
|
|
hexmask.long.word 0x8 0.--15. 1. "ATCNT,ADC Trigger counter"
|
|
line.long 0xC "ATR4,MPWMn ADC Trigger Counter 4 Register"
|
|
bitfld.long 0xC 19. "ATUDT,Trigger register update mode" "0,1"
|
|
bitfld.long 0xC 16.--17. "ATMOD,ADC Trigger mode register" "0,1,2,3"
|
|
hexmask.long.word 0xC 0.--15. 1. "ATCNT,ADC Trigger counter"
|
|
line.long 0x10 "ATR5,MPWMn ADC Trigger Counter 5 Register"
|
|
bitfld.long 0x10 19. "ATUDT,Trigger register update mode" "0,1"
|
|
bitfld.long 0x10 16.--17. "ATMOD,ADC Trigger mode register" "0,1,2,3"
|
|
hexmask.long.word 0x10 0.--15. 1. "ATCNT,ADC Trigger counter"
|
|
line.long 0x14 "ATR6,MPWMn ADC Trigger Counter 6 Register"
|
|
bitfld.long 0x14 19. "ATUDT,Trigger register update mode" "0,1"
|
|
bitfld.long 0x14 16.--17. "ATMOD,ADC Trigger mode register" "0,1,2,3"
|
|
hexmask.long.word 0x14 0.--15. 1. "ATCNT,ADC Trigger counter"
|
|
tree.end
|
|
tree "PCU (Port Control Unit)"
|
|
base ad:0x0
|
|
tree "PCA"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "MR,PORT n Pin MUX Register"
|
|
bitfld.long 0x0 30.--31. "P15,P15 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "P14,P14 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "P13,P13 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "P12,P12 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "P11,P11 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "P10,P10 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "P9,P9 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "P8,P8 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "P7,P7 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "P6,P6 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "P5,P5 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "P4,P4 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "P2,P2 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 MUX SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 MUX SEL" "0,1,2,3"
|
|
line.long 0x4 "CR,PORT n Pin Control Register"
|
|
bitfld.long 0x4 30.--31. "P15,P15 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "P14,P14 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "P13,P13 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "P12,P12 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "P11,P11 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "P10,P10 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "P9,P9 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "P8,P8 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "P7,P7 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "P6,P6 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "P5,P5 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "P4,P4 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "P3,P3 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "P2,P2 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "P1,P1 control SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "P0,P0 control SEL" "0,1,2,3"
|
|
line.long 0x8 "PCR,PORT n Pull-up Resistor Control Register"
|
|
bitfld.long 0x8 15. "P15,P15 pull-up enable" "0,1"
|
|
bitfld.long 0x8 14. "P14,P14 pull-up enable" "0,1"
|
|
bitfld.long 0x8 13. "P13,P13 pull-up enable" "0,1"
|
|
bitfld.long 0x8 12. "P12,P12 pull-up enable" "0,1"
|
|
bitfld.long 0x8 11. "P11,P11 pull-up enable" "0,1"
|
|
bitfld.long 0x8 10. "P10,P10 pull-up enable" "0,1"
|
|
bitfld.long 0x8 9. "P9,P9 pull-up enable" "0,1"
|
|
bitfld.long 0x8 8. "P8,P8 pull-up enable" "0,1"
|
|
bitfld.long 0x8 7. "P7,P7 pull-up enable" "0,1"
|
|
bitfld.long 0x8 6. "P6,P6 pull-up enable" "0,1"
|
|
bitfld.long 0x8 5. "P5,P5 pull-up enable" "0,1"
|
|
bitfld.long 0x8 4. "P4,P4 pull-up enable" "0,1"
|
|
bitfld.long 0x8 3. "P3,P3 pull-up enable" "0,1"
|
|
bitfld.long 0x8 2. "P2,P2 pull-up enable" "0,1"
|
|
bitfld.long 0x8 1. "P1,P1 pull-up enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P0,P0 pull-up enable" "0,1"
|
|
line.long 0xC "DER,PORT n Debounce Enable Register"
|
|
bitfld.long 0xC 15. "P15,P15 Debounce enable" "0,1"
|
|
bitfld.long 0xC 14. "P14,P14 Debounce enable" "0,1"
|
|
bitfld.long 0xC 13. "P13,P13 Debounce enable" "0,1"
|
|
bitfld.long 0xC 12. "P12,P12 Debounce enable" "0,1"
|
|
bitfld.long 0xC 11. "P11,P11 Debounce enable" "0,1"
|
|
bitfld.long 0xC 10. "P10,P10 Debounce enable" "0,1"
|
|
bitfld.long 0xC 9. "P9,P9 Debounce enable" "0,1"
|
|
bitfld.long 0xC 8. "P8,P8 Debounce enable" "0,1"
|
|
bitfld.long 0xC 7. "P7,P7 Debounce enable" "0,1"
|
|
bitfld.long 0xC 6. "P6,P6 Debounce enable" "0,1"
|
|
bitfld.long 0xC 5. "P5,P5 Debounce enable" "0,1"
|
|
bitfld.long 0xC 4. "P4,P4 Debounce enable" "0,1"
|
|
bitfld.long 0xC 3. "P3,P3 Debounce enable" "0,1"
|
|
bitfld.long 0xC 2. "P2,P2 Debounce enable" "0,1"
|
|
bitfld.long 0xC 1. "P1,P1 Debounce enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P0,P0 Debounce enable" "0,1"
|
|
line.long 0x10 "IER,PORT n Interrupt Enable Register"
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0x14 "ISR,PORT n Interrupt Status Register"
|
|
bitfld.long 0x14 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x18 "ICR,PORT n Interrupt Control Register"
|
|
bitfld.long 0x18 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
tree.end
|
|
tree "PCB"
|
|
base ad:0x40001100
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "MR,PORT n Pin MUX Register"
|
|
bitfld.long 0x0 30.--31. "P15,P15 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "P14,P14 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "P13,P13 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "P12,P12 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "P11,P11 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "P10,P10 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "P9,P9 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "P8,P8 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "P7,P7 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "P6,P6 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "P5,P5 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "P4,P4 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "P2,P2 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 MUX SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 MUX SEL" "0,1,2,3"
|
|
line.long 0x4 "CR,PORT n Pin Control Register"
|
|
bitfld.long 0x4 30.--31. "P15,P15 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "P14,P14 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "P13,P13 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "P12,P12 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "P11,P11 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "P10,P10 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "P9,P9 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "P8,P8 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "P7,P7 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "P6,P6 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "P5,P5 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "P4,P4 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "P3,P3 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "P2,P2 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "P1,P1 control SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "P0,P0 control SEL" "0,1,2,3"
|
|
line.long 0x8 "PCR,PORT n Pull-up Resistor Control Register"
|
|
bitfld.long 0x8 15. "P15,P15 pull-up enable" "0,1"
|
|
bitfld.long 0x8 14. "P14,P14 pull-up enable" "0,1"
|
|
bitfld.long 0x8 13. "P13,P13 pull-up enable" "0,1"
|
|
bitfld.long 0x8 12. "P12,P12 pull-up enable" "0,1"
|
|
bitfld.long 0x8 11. "P11,P11 pull-up enable" "0,1"
|
|
bitfld.long 0x8 10. "P10,P10 pull-up enable" "0,1"
|
|
bitfld.long 0x8 9. "P9,P9 pull-up enable" "0,1"
|
|
bitfld.long 0x8 8. "P8,P8 pull-up enable" "0,1"
|
|
bitfld.long 0x8 7. "P7,P7 pull-up enable" "0,1"
|
|
bitfld.long 0x8 6. "P6,P6 pull-up enable" "0,1"
|
|
bitfld.long 0x8 5. "P5,P5 pull-up enable" "0,1"
|
|
bitfld.long 0x8 4. "P4,P4 pull-up enable" "0,1"
|
|
bitfld.long 0x8 3. "P3,P3 pull-up enable" "0,1"
|
|
bitfld.long 0x8 2. "P2,P2 pull-up enable" "0,1"
|
|
bitfld.long 0x8 1. "P1,P1 pull-up enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P0,P0 pull-up enable" "0,1"
|
|
line.long 0xC "DER,PORT n Debounce Enable Register"
|
|
bitfld.long 0xC 15. "P15,P15 Debounce enable" "0,1"
|
|
bitfld.long 0xC 14. "P14,P14 Debounce enable" "0,1"
|
|
bitfld.long 0xC 13. "P13,P13 Debounce enable" "0,1"
|
|
bitfld.long 0xC 12. "P12,P12 Debounce enable" "0,1"
|
|
bitfld.long 0xC 11. "P11,P11 Debounce enable" "0,1"
|
|
bitfld.long 0xC 10. "P10,P10 Debounce enable" "0,1"
|
|
bitfld.long 0xC 9. "P9,P9 Debounce enable" "0,1"
|
|
bitfld.long 0xC 8. "P8,P8 Debounce enable" "0,1"
|
|
bitfld.long 0xC 7. "P7,P7 Debounce enable" "0,1"
|
|
bitfld.long 0xC 6. "P6,P6 Debounce enable" "0,1"
|
|
bitfld.long 0xC 5. "P5,P5 Debounce enable" "0,1"
|
|
bitfld.long 0xC 4. "P4,P4 Debounce enable" "0,1"
|
|
bitfld.long 0xC 3. "P3,P3 Debounce enable" "0,1"
|
|
bitfld.long 0xC 2. "P2,P2 Debounce enable" "0,1"
|
|
bitfld.long 0xC 1. "P1,P1 Debounce enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P0,P0 Debounce enable" "0,1"
|
|
line.long 0x10 "IER,PORT n Interrupt Enable Register"
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0x14 "ISR,PORT n Interrupt Status Register"
|
|
bitfld.long 0x14 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x18 "ICR,PORT n Interrupt Control Register"
|
|
bitfld.long 0x18 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
tree.end
|
|
tree "PCC"
|
|
base ad:0x40001200
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "MR,PORT n Pin MUX Register"
|
|
bitfld.long 0x0 30.--31. "P15,P15 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "P14,P14 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "P13,P13 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "P12,P12 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "P11,P11 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "P10,P10 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "P9,P9 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "P8,P8 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "P7,P7 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "P6,P6 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "P5,P5 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "P4,P4 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "P2,P2 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 MUX SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 MUX SEL" "0,1,2,3"
|
|
line.long 0x4 "CR,PORT n Pin Control Register"
|
|
bitfld.long 0x4 30.--31. "P15,P15 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "P14,P14 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "P13,P13 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "P12,P12 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "P11,P11 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "P10,P10 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "P9,P9 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "P8,P8 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "P7,P7 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "P6,P6 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "P5,P5 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "P4,P4 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "P3,P3 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "P2,P2 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "P1,P1 control SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "P0,P0 control SEL" "0,1,2,3"
|
|
line.long 0x8 "PCR,PORT n Pull-up Resistor Control Register"
|
|
bitfld.long 0x8 15. "P15,P15 pull-up enable" "0,1"
|
|
bitfld.long 0x8 14. "P14,P14 pull-up enable" "0,1"
|
|
bitfld.long 0x8 13. "P13,P13 pull-up enable" "0,1"
|
|
bitfld.long 0x8 12. "P12,P12 pull-up enable" "0,1"
|
|
bitfld.long 0x8 11. "P11,P11 pull-up enable" "0,1"
|
|
bitfld.long 0x8 10. "P10,P10 pull-up enable" "0,1"
|
|
bitfld.long 0x8 9. "P9,P9 pull-up enable" "0,1"
|
|
bitfld.long 0x8 8. "P8,P8 pull-up enable" "0,1"
|
|
bitfld.long 0x8 7. "P7,P7 pull-up enable" "0,1"
|
|
bitfld.long 0x8 6. "P6,P6 pull-up enable" "0,1"
|
|
bitfld.long 0x8 5. "P5,P5 pull-up enable" "0,1"
|
|
bitfld.long 0x8 4. "P4,P4 pull-up enable" "0,1"
|
|
bitfld.long 0x8 3. "P3,P3 pull-up enable" "0,1"
|
|
bitfld.long 0x8 2. "P2,P2 pull-up enable" "0,1"
|
|
bitfld.long 0x8 1. "P1,P1 pull-up enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P0,P0 pull-up enable" "0,1"
|
|
line.long 0xC "DER,PORT n Debounce Enable Register"
|
|
bitfld.long 0xC 15. "P15,P15 Debounce enable" "0,1"
|
|
bitfld.long 0xC 14. "P14,P14 Debounce enable" "0,1"
|
|
bitfld.long 0xC 13. "P13,P13 Debounce enable" "0,1"
|
|
bitfld.long 0xC 12. "P12,P12 Debounce enable" "0,1"
|
|
bitfld.long 0xC 11. "P11,P11 Debounce enable" "0,1"
|
|
bitfld.long 0xC 10. "P10,P10 Debounce enable" "0,1"
|
|
bitfld.long 0xC 9. "P9,P9 Debounce enable" "0,1"
|
|
bitfld.long 0xC 8. "P8,P8 Debounce enable" "0,1"
|
|
bitfld.long 0xC 7. "P7,P7 Debounce enable" "0,1"
|
|
bitfld.long 0xC 6. "P6,P6 Debounce enable" "0,1"
|
|
bitfld.long 0xC 5. "P5,P5 Debounce enable" "0,1"
|
|
bitfld.long 0xC 4. "P4,P4 Debounce enable" "0,1"
|
|
bitfld.long 0xC 3. "P3,P3 Debounce enable" "0,1"
|
|
bitfld.long 0xC 2. "P2,P2 Debounce enable" "0,1"
|
|
bitfld.long 0xC 1. "P1,P1 Debounce enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P0,P0 Debounce enable" "0,1"
|
|
line.long 0x10 "IER,PORT n Interrupt Enable Register"
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0x14 "ISR,PORT n Interrupt Status Register"
|
|
bitfld.long 0x14 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x18 "ICR,PORT n Interrupt Control Register"
|
|
bitfld.long 0x18 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
tree.end
|
|
tree "PCD"
|
|
base ad:0x40001300
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "MR,PORT n Pin MUX Register"
|
|
bitfld.long 0x0 30.--31. "P15,P15 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "P14,P14 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "P13,P13 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "P12,P12 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "P11,P11 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "P10,P10 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "P9,P9 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "P8,P8 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "P7,P7 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "P6,P6 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "P5,P5 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "P4,P4 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "P2,P2 MUX SEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 MUX SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 MUX SEL" "0,1,2,3"
|
|
line.long 0x4 "CR,PORT n Pin Control Register"
|
|
bitfld.long 0x4 30.--31. "P15,P15 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "P14,P14 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "P13,P13 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "P12,P12 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "P11,P11 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "P10,P10 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "P9,P9 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "P8,P8 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "P7,P7 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "P6,P6 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "P5,P5 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "P4,P4 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "P3,P3 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "P2,P2 control SEL" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "P1,P1 control SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "P0,P0 control SEL" "0,1,2,3"
|
|
line.long 0x8 "PCR,PORT n Pull-up Resistor Control Register"
|
|
bitfld.long 0x8 15. "P15,P15 pull-up enable" "0,1"
|
|
bitfld.long 0x8 14. "P14,P14 pull-up enable" "0,1"
|
|
bitfld.long 0x8 13. "P13,P13 pull-up enable" "0,1"
|
|
bitfld.long 0x8 12. "P12,P12 pull-up enable" "0,1"
|
|
bitfld.long 0x8 11. "P11,P11 pull-up enable" "0,1"
|
|
bitfld.long 0x8 10. "P10,P10 pull-up enable" "0,1"
|
|
bitfld.long 0x8 9. "P9,P9 pull-up enable" "0,1"
|
|
bitfld.long 0x8 8. "P8,P8 pull-up enable" "0,1"
|
|
bitfld.long 0x8 7. "P7,P7 pull-up enable" "0,1"
|
|
bitfld.long 0x8 6. "P6,P6 pull-up enable" "0,1"
|
|
bitfld.long 0x8 5. "P5,P5 pull-up enable" "0,1"
|
|
bitfld.long 0x8 4. "P4,P4 pull-up enable" "0,1"
|
|
bitfld.long 0x8 3. "P3,P3 pull-up enable" "0,1"
|
|
bitfld.long 0x8 2. "P2,P2 pull-up enable" "0,1"
|
|
bitfld.long 0x8 1. "P1,P1 pull-up enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P0,P0 pull-up enable" "0,1"
|
|
line.long 0xC "DER,PORT n Debounce Enable Register"
|
|
bitfld.long 0xC 15. "P15,P15 Debounce enable" "0,1"
|
|
bitfld.long 0xC 14. "P14,P14 Debounce enable" "0,1"
|
|
bitfld.long 0xC 13. "P13,P13 Debounce enable" "0,1"
|
|
bitfld.long 0xC 12. "P12,P12 Debounce enable" "0,1"
|
|
bitfld.long 0xC 11. "P11,P11 Debounce enable" "0,1"
|
|
bitfld.long 0xC 10. "P10,P10 Debounce enable" "0,1"
|
|
bitfld.long 0xC 9. "P9,P9 Debounce enable" "0,1"
|
|
bitfld.long 0xC 8. "P8,P8 Debounce enable" "0,1"
|
|
bitfld.long 0xC 7. "P7,P7 Debounce enable" "0,1"
|
|
bitfld.long 0xC 6. "P6,P6 Debounce enable" "0,1"
|
|
bitfld.long 0xC 5. "P5,P5 Debounce enable" "0,1"
|
|
bitfld.long 0xC 4. "P4,P4 Debounce enable" "0,1"
|
|
bitfld.long 0xC 3. "P3,P3 Debounce enable" "0,1"
|
|
bitfld.long 0xC 2. "P2,P2 Debounce enable" "0,1"
|
|
bitfld.long 0xC 1. "P1,P1 Debounce enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P0,P0 Debounce enable" "0,1"
|
|
line.long 0x10 "IER,PORT n Interrupt Enable Register"
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0x14 "ISR,PORT n Interrupt Status Register"
|
|
bitfld.long 0x14 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x18 "ICR,PORT n Interrupt Control Register"
|
|
bitfld.long 0x18 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
tree.end
|
|
tree.end
|
|
tree "PORTEN (Port Control Mode Enable)"
|
|
base ad:0x40001FF0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "EN,Port Access Enable 0x15->0x51"
|
|
tree.end
|
|
tree "SCU (System Control Unit)"
|
|
base ad:0x40000000
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "SMR,System Mode Register"
|
|
bitfld.long 0x0 9. "LSIAON,LSIAON" "0,1"
|
|
bitfld.long 0x0 8. "VDCAON,VDCAON" "0,1"
|
|
bitfld.long 0x0 4.--5. "PREVMODE,PREVMODE" "0,1,2,3"
|
|
line.long 0x4 "SRCR,System Reset Control Register"
|
|
bitfld.long 0x4 4. "STBOP,STBOP pin output polarity select bit" "0,1"
|
|
bitfld.long 0x4 0. "SWRST,Internal soft reset activation" "0,1"
|
|
group.long 0x10++0x27
|
|
line.long 0x0 "WUER,Wakeup Source Enable Register"
|
|
bitfld.long 0x0 11. "GPIODWUE,GPIODWUE" "0,1"
|
|
bitfld.long 0x0 10. "GPIOCWUE,GPIOCWUE" "0,1"
|
|
bitfld.long 0x0 9. "GPIOBWUE,GPIOBWUE" "0,1"
|
|
bitfld.long 0x0 8. "GPIOAWUE,GPIOAWUE" "0,1"
|
|
bitfld.long 0x0 2. "FRTWUE,FRTWUE" "0,1"
|
|
bitfld.long 0x0 1. "WDTWUE,WDTWUE" "0,1"
|
|
bitfld.long 0x0 0. "LVDWUE,LVDWUE" "0,1"
|
|
line.long 0x4 "WUSR,Wakeup Source Status Register"
|
|
bitfld.long 0x4 11. "GPIODWU,GPIODWU" "0,1"
|
|
bitfld.long 0x4 10. "GPIOCWU,GPIOCWU" "0,1"
|
|
bitfld.long 0x4 9. "GPIOBWU,GPIOBWU" "0,1"
|
|
bitfld.long 0x4 8. "GPIOAWU,GPIOAWU" "0,1"
|
|
bitfld.long 0x4 2. "FRTWU,FRTWU" "0,1"
|
|
bitfld.long 0x4 1. "WDTWU,WDTWU" "0,1"
|
|
bitfld.long 0x4 0. "LVDWU,LVDWU" "0,1"
|
|
line.long 0x8 "RSER,Reset Source Enable Register"
|
|
bitfld.long 0x8 7. "LOCKUPRST,CPU Lock up reset enable bit" "0,1"
|
|
bitfld.long 0x8 6. "PINRST,external pin reset enable" "0,1"
|
|
bitfld.long 0x8 5. "CPURST,CPU request reset enable" "0,1"
|
|
bitfld.long 0x8 4. "SWRST,software reset enable" "0,1"
|
|
bitfld.long 0x8 3. "WDTRST,watch dog reset enable" "0,1"
|
|
bitfld.long 0x8 2. "MCKFRST,MCLK Clock fail reset enable" "0,1"
|
|
bitfld.long 0x8 1. "MOFRST,MOSC Clock fail reset enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "LVDRST,LVD reset enable" "0,1"
|
|
line.long 0xC "RSSR,Reset Source Status Register"
|
|
bitfld.long 0xC 8. "LOCKUPRST,CPU Lock up reset status" "0,1"
|
|
bitfld.long 0xC 7. "PORST,power on reset status" "0,1"
|
|
bitfld.long 0xC 6. "PINRST,extenral pin reset status" "0,1"
|
|
bitfld.long 0xC 5. "CPURST,cpu request reset status" "0,1"
|
|
bitfld.long 0xC 4. "SWRST,software reset status" "0,1"
|
|
bitfld.long 0xC 3. "WDTRST,watchdog timer reset status" "0,1"
|
|
bitfld.long 0xC 2. "MCKFRST,MCLK failed reset status" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "MOFRST,MOSC Clock fail reset status" "0,1"
|
|
bitfld.long 0xC 0. "LVDRST,lvd reset status" "0,1"
|
|
line.long 0x10 "PRER1,Peripheral Reset Enable Register 1"
|
|
bitfld.long 0x10 26. "FRT,FRT Reset enable" "0,1"
|
|
bitfld.long 0x10 19. "TIMER3,TIMER3 Reset enable" "0,1"
|
|
bitfld.long 0x10 18. "TIMER2,TIMER2 Reset enable" "0,1"
|
|
bitfld.long 0x10 17. "TIMER1,TIMER1 reset enable" "0,1"
|
|
bitfld.long 0x10 16. "TIMER0,TIMER0 Reset enable" "0,1"
|
|
bitfld.long 0x10 11. "GPIOD,GPIOD Reset enable" "0,1"
|
|
bitfld.long 0x10 10. "GPIOC,GPIOC Reset enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "GPIOB,GPIOB Reset enable" "0,1"
|
|
bitfld.long 0x10 8. "GPIOA,GPIOA Reset enable" "0,1"
|
|
bitfld.long 0x10 5. "DIV64,DIV64 Reset enable" "0,1"
|
|
bitfld.long 0x10 3. "PCU,Port Controller unit reset enable" "0,1"
|
|
bitfld.long 0x10 2. "WDT,WatchDog timer reset enable" "0,1"
|
|
bitfld.long 0x10 1. "FMC,Flash Memory controller Reset enable" "0,1"
|
|
bitfld.long 0x10 0. "SCU,Power Management Unit Reset enable" "0,1"
|
|
line.long 0x14 "PRER2,Peripheral Reset Enable Register 2"
|
|
bitfld.long 0x14 20. "ADC,ADC Reset enable" "0,1"
|
|
bitfld.long 0x14 16. "MPWM,MPWM Reset enable" "0,1"
|
|
bitfld.long 0x14 9. "UART1,UART1 Reset enable" "0,1"
|
|
bitfld.long 0x14 8. "UART0,UART0 Reset enable" "0,1"
|
|
bitfld.long 0x14 4. "I2C,I2C Reset enable" "0,1"
|
|
bitfld.long 0x14 0. "SPI,SPI Reset enable" "0,1"
|
|
line.long 0x18 "PER1,Peripheral Enable Register 1"
|
|
bitfld.long 0x18 26. "FRT,FRT" "0,1"
|
|
bitfld.long 0x18 19. "TIMER3,TIMER3" "0,1"
|
|
bitfld.long 0x18 18. "TIMER2,TIMER2" "0,1"
|
|
bitfld.long 0x18 17. "TIMER1,TIMER1" "0,1"
|
|
bitfld.long 0x18 16. "TIMER0,TIMER0" "0,1"
|
|
bitfld.long 0x18 11. "GPIOD,GPIOD" "0,1"
|
|
bitfld.long 0x18 10. "GPIOC,GPIOC" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "GPIOB,GPIOB" "0,1"
|
|
bitfld.long 0x18 8. "GPIOA,GPIOA" "0,1"
|
|
bitfld.long 0x18 5. "DIV64,DIV64" "0,1"
|
|
line.long 0x1C "PER2,Peripheral Enable Register 2"
|
|
bitfld.long 0x1C 20. "ADC,ADC" "0,1"
|
|
bitfld.long 0x1C 16. "MPWM,MPWM" "0,1"
|
|
bitfld.long 0x1C 9. "UART1,UART1" "0,1"
|
|
bitfld.long 0x1C 8. "UART0,UART0" "0,1"
|
|
bitfld.long 0x1C 4. "I2C,I2C" "0,1"
|
|
bitfld.long 0x1C 0. "SPI,SPI Enable" "0,1"
|
|
line.long 0x20 "PCER1,Peripheral Clock Enable Register 1"
|
|
bitfld.long 0x20 26. "FRT,FRT clock enable" "0,1"
|
|
bitfld.long 0x20 19. "TIMER3,Timer3 clock enable" "0,1"
|
|
bitfld.long 0x20 18. "TIMER2,TIMER2 clock enable" "0,1"
|
|
bitfld.long 0x20 17. "TIMER1,TIMER1 clock enable" "0,1"
|
|
bitfld.long 0x20 16. "TIMER0,TIMER0" "0,1"
|
|
bitfld.long 0x20 11. "GPIOD,GPIOD clock enable" "0,1"
|
|
bitfld.long 0x20 10. "GPIOC,GPIOC clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "GPIOB,GPIOB clock enable" "0,1"
|
|
bitfld.long 0x20 8. "GPIOA,GPIOA clock enable" "0,1"
|
|
bitfld.long 0x20 5. "DIV64,DIV64" "0,1"
|
|
line.long 0x24 "PCER2,Peripheral Clock Enable Register 2"
|
|
bitfld.long 0x24 20. "ADC,ADC clock enable" "0,1"
|
|
bitfld.long 0x24 16. "MPWM,MPWM clock enable" "0,1"
|
|
bitfld.long 0x24 9. "UART1,UART1 clock enable" "0,1"
|
|
bitfld.long 0x24 8. "UART0,UART0" "0,1"
|
|
bitfld.long 0x24 4. "I2C,I2C clock enable" "0,1"
|
|
bitfld.long 0x24 0. "SPI,SPI clock enable" "0,1"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "CSCR,Clock Source Control Register"
|
|
bitfld.long 0x0 6.--7. "SOSCCON,External crystal sub oscillator control" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "LSICON,Low speed internal oscillator control" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "HSICON,High speed internal oscillator control" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MOSCCON,External crystal main oscillator control" "0,1,2,3"
|
|
line.long 0x4 "SCCR,System Clock Control Register"
|
|
bitfld.long 0x4 0.--2. "MCLKSEL,System clock select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CMR,Clock Monitoring Register"
|
|
bitfld.long 0x8 15. "MCLKREC,MCLK failed auto recovery" "0,1"
|
|
bitfld.long 0x8 11. "SOSCMNT,Sub Oscillator monitoring enable" "0,1"
|
|
bitfld.long 0x8 10. "SOSCIE,Sub Oscillator fail interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "SOSCFAIL,Sub Oscillator fail interrupt flag" "0,1"
|
|
bitfld.long 0x8 8. "SOSCSTS,Sub Oscillator clock status" "0,1"
|
|
bitfld.long 0x8 7. "MCLKMNT,MCLK monitor enable" "0,1"
|
|
bitfld.long 0x8 6. "MCLKIE,MCLK fail Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "MCLKFAIL,MCLK Failed flag" "0,1"
|
|
bitfld.long 0x8 4. "MCLKSTS,MCLK clock status" "0,1"
|
|
bitfld.long 0x8 3. "MOSCMNT,External OSC monitor enable" "0,1"
|
|
bitfld.long 0x8 2. "MOSCIE,external OSC failed interrupt enable" "0,1"
|
|
bitfld.long 0x8 1. "MOSCFAIL,external OSC failed flag" "0,1"
|
|
bitfld.long 0x8 0. "MOSCSTS,external OSC status" "0,1"
|
|
line.long 0xC "NMIR,NMI Control Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ACODE,0xA32C to write"
|
|
bitfld.long 0xC 12. "PROTSTS,PROTSTS" "0,1"
|
|
bitfld.long 0xC 11. "OVPSTS,OVPSTS" "0,1"
|
|
bitfld.long 0xC 10. "WDTINTSTS,WDTINTSTS" "0,1"
|
|
bitfld.long 0xC 9. "MCLKFAILSTS,MCLKFAILSTS" "0,1"
|
|
bitfld.long 0xC 8. "LVDSTS,LVDSTS" "0,1"
|
|
bitfld.long 0xC 4. "PROTEN,PROTEN" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OVPEN,OVPEN" "0,1"
|
|
bitfld.long 0xC 2. "WDTINTEN,WDTINTEN" "0,1"
|
|
bitfld.long 0xC 1. "MCLKFAILEN,MCLKFAILEN" "0,1"
|
|
bitfld.long 0xC 0. "LVDEN,LVDEN" "0,1"
|
|
line.long 0x10 "COR,Clock Output Register"
|
|
bitfld.long 0x10 4. "CLKOEN,clock output enable" "0,1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "CLKODIV,clock output divider value"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "VDCCON,VDC Control Register"
|
|
bitfld.long 0x0 31. "VDCME,VDCMODE value write enable. Write only with VDCMODE value" "0,1"
|
|
bitfld.long 0x0 29. "VDCOPT,VDD18 Up Option Enable bit" "0,1"
|
|
bitfld.long 0x0 28. "STOPEN,VDC STOP MODE Enable bit" "0,1"
|
|
bitfld.long 0x0 26.--27. "TC_S,OSC TC Compensation" "0,1,2,3"
|
|
bitfld.long 0x0 25. "STOPSEL,VDC STOP MODE Select bit" "0,1"
|
|
bitfld.long 0x0 24. "BIMODE,VDC BIMODE value write enable bit" "0,1"
|
|
bitfld.long 0x0 23. "VDCTE,VDC BGR/BMR trim value write enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "VDCTRIM,VDC trim value"
|
|
bitfld.long 0x0 8. "VDCDE,VDCWDLY value write enable. Write only with VDCWDLY value" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VDCWDLY,VDC warm up delay count"
|
|
group.long 0x68++0xF
|
|
line.long 0x0 "LVDCON,LVD Control Register"
|
|
bitfld.long 0x0 15. "SELEN,SELEN" "0,1"
|
|
bitfld.long 0x0 8.--9. "LVDSEL,LVDSEL" "0,1,2,3"
|
|
rbitfld.long 0x0 1. "LVDLVL,LVDLVL" "0,1"
|
|
bitfld.long 0x0 0. "LVDEN,LVDEN" "0,1"
|
|
line.long 0x4 "HSIOSCTRIM,High Speed Internal OSC Trim Register"
|
|
bitfld.long 0x4 31. "BISCON,Build in self calibration function enable" "0,1"
|
|
bitfld.long 0x4 30. "REFSEL,Reference clock select for self-calibration" "0,1"
|
|
bitfld.long 0x4 27. "ADCALON,Adpaptive calibration clock function enable" "0,1"
|
|
bitfld.long 0x4 23. "TSLEN,TSL trim value write enable" "0,1"
|
|
bitfld.long 0x4 16.--18. "TSL,TSL trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "LTEN,LTM_LT value write enable" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "LT_LTM,Internal oscillator LT trim value"
|
|
newline
|
|
bitfld.long 0x4 7. "UDCEN,UDCH/UDCL value write enable" "0,1"
|
|
bitfld.long 0x4 3.--4. "UDCH,Internal oscillator UDC trim value" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. "UDCL,Internal oscillator UDC trim value" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "BISCCON,Build in self calibration control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "INTOSC_COMP,INTOSC_COMP"
|
|
hexmask.long.word 0x8 0.--15. 1. "XTAL_COMP,XTAL_COMP"
|
|
line.long 0xC "LSIOSC,Low Speed Internal OSC Trim Register"
|
|
bitfld.long 0xC 7. "CTRTRIMEN,CTRTRIMEN" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "CTR,CTR"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "EMOSCR,External Main Oscillator Control Register"
|
|
bitfld.long 0x0 15. "FILSKIPWEN,Write enable of bit field FILSKIPEN" "0,1"
|
|
bitfld.long 0x0 8. "FILSKIPEN,Control External Main Oscillator Filter Skip" "0,1"
|
|
bitfld.long 0x0 7. "INVCLKWEN,Write enable of bit field FILSKIPEN" "0,1"
|
|
bitfld.long 0x0 0. "INVCLKEN,Control External Main Oscillator CLK invert" "0,1"
|
|
line.long 0x4 "EMODR,External Mode Status Register"
|
|
bitfld.long 0x4 2. "SCANMD,scan mode pin level" "0,1"
|
|
bitfld.long 0x4 1. "TEST,TEST PIN level" "0,1"
|
|
bitfld.long 0x4 0. "BOOT,boot pin level" "0,1"
|
|
group.long 0x90++0x13
|
|
line.long 0x0 "MCCR1,Miscellaneous Clock Control Register 1"
|
|
bitfld.long 0x0 8.--10. "STCSEL,systick clock source sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STCDIV,systick divider"
|
|
line.long 0x4 "MCCR2,Miscellaneous Clock Control Register 2"
|
|
bitfld.long 0x4 8.--10. "PWMCSEL,MPWM Clock source sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PWMDIV,MPWM clock n divider"
|
|
line.long 0x8 "MCCR3,Miscellaneous Clock Control Register 3"
|
|
bitfld.long 0x8 24.--26. "TIMERCSEL,Timer Clock source sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 16.--23. 1. "TIMERDIV,Timer Clock divider"
|
|
bitfld.long 0x8 8.--10. "WDTCSEL,WDT clock sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDTDIV,WDT divider"
|
|
line.long 0xC "MCCR4,Miscellaneous Clock Control Register 4"
|
|
bitfld.long 0xC 24.--26. "PBDCSEL,Debounce Clock for Port B source select" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PBDDIV,PORT B Debounce Clock N divider"
|
|
bitfld.long 0xC 8.--10. "PADCSEL,Debounce Clock for Port A source select" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PADDIV,PORT A Debounce Clock N divider"
|
|
line.long 0x10 "MCCR5,Miscellaneous Clock Control Register 5"
|
|
bitfld.long 0x10 24.--26. "PDDCSEL,debouce clock for port D source clock sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 16.--23. 1. "PDDDIV,PORT D debounce divider"
|
|
bitfld.long 0x10 8.--10. "PCDCSEL,debouce clock for port C source clock sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PCDDIV,PORT C debounce divider"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "MCCR7,Miscellaneous Clock Control Register 7"
|
|
bitfld.long 0x0 24.--26. "ADCCSEL,ADC clock source select bit" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADCCDIV,ADC Clock N divider"
|
|
bitfld.long 0x0 8.--10. "UARTCSEL,UART clock source select bit" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "UARTCDIV,UART Clock N divider"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40009000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RDR,SPI n Receive Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Data"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "TDR,SPI n Transmit Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Data"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR,SPI n Control Register"
|
|
bitfld.long 0x0 20. "TXBC,Tx buffer clear bit" "0,1"
|
|
bitfld.long 0x0 19. "RXBC,Rx buffer clear bit" "0,1"
|
|
bitfld.long 0x0 16. "SSCIE,SSn Edge Change Interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 15. "TXIE,Transmit interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 14. "RXIE,Receive interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output select bit" "0,1"
|
|
bitfld.long 0x0 12. "SSOUT,SS output signal select bit" "0,1"
|
|
bitfld.long 0x0 11. "LBE,Loop-back mode select bit in master mode" "0,1"
|
|
bitfld.long 0x0 10. "SSMASK,SS Signal masking bit in slave mode" "0,1"
|
|
bitfld.long 0x0 9. "SSMO,SS output signal select bit" "0,1"
|
|
bitfld.long 0x0 8. "SSPOL,SS Signal polarity select bit" "0,1"
|
|
bitfld.long 0x0 5. "MS,master/slaver select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MSBF,MSB/LSB transmit select bit" "0,1"
|
|
bitfld.long 0x0 3. "CPHA,SPI clock phase bit" "0,1"
|
|
bitfld.long 0x0 2. "CPOL,SPI clock polarity bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "BITSZ,Transmit/receive Data bits select bit" "0,1,2,3"
|
|
line.long 0x4 "SR,SPI n Status Register"
|
|
bitfld.long 0x4 6. "SSDET,The rising edge of SS detect flag" "0,1"
|
|
bitfld.long 0x4 5. "SSON,SS signal status flag" "0,1"
|
|
bitfld.long 0x4 4. "OVRF,receive overrun error flag" "0,1"
|
|
bitfld.long 0x4 3. "UDRF,transmit underrun error flag" "0,1"
|
|
rbitfld.long 0x4 2. "TXIDLE,transmit/receive operation flag" "0,1"
|
|
rbitfld.long 0x4 1. "TRDY,Transmit buffer empty flag" "0,1"
|
|
rbitfld.long 0x4 0. "RRDY,receive buffer ready flag" "0,1"
|
|
line.long 0x8 "BR,SPI n Baud Rate Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BR,buadrate"
|
|
line.long 0xC "EN,SPI n Enable register"
|
|
bitfld.long 0xC 0. "ENABLE,SPI ENABLE bit" "0,1"
|
|
line.long 0x10 "LR,SPI n delay Length Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "SPL,Stop delay length"
|
|
hexmask.long.byte 0x10 8.--15. 1. "BTL,Burst delay length"
|
|
hexmask.long.byte 0x10 0.--7. 1. "STL,Start delay length"
|
|
tree.end
|
|
tree "TIMER (16-bit Timer)"
|
|
base ad:0x0
|
|
tree "T0"
|
|
base ad:0x40003000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CR1,Timer n Control Register 1"
|
|
bitfld.long 0x0 15. "SSYNC,Synchronize start counter with other synchronized timers" "0,1"
|
|
bitfld.long 0x0 14. "CSYNC,Synchronize clear counter with other synchronized tip" "0,1"
|
|
bitfld.long 0x0 13. "UAO,Select GRA GRB Update mode" "0,1"
|
|
bitfld.long 0x0 12. "OUTPOL,timer output polarity" "0,1"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADCTRGEN" "0,1"
|
|
bitfld.long 0x0 7. "STARTLVL,STARTLVL" "0,1"
|
|
bitfld.long 0x0 4.--6. "CKSEL,counter clock source select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "CLRMD,clear select when capture mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Timer operation mode control" "0,1,2,3"
|
|
line.long 0x4 "CR2,Timer n Control Register 2"
|
|
bitfld.long 0x4 1. "TCLR,Timer register clear" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer enable bit" "0,1"
|
|
line.long 0x8 "PRS,Timer n Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Prescaler value of count clock"
|
|
line.long 0xC "GRA,Timer n General Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA"
|
|
line.long 0x10 "GRB,Timer n General Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB"
|
|
line.long 0x14 "CNT,Timer n Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,CNT"
|
|
line.long 0x18 "SR,Timer n Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,counter overflow flag" "0,1"
|
|
line.long 0x1C "IER,Timer n Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter overflow interrupt enable" "0,1"
|
|
tree.end
|
|
tree "T1"
|
|
base ad:0x40003020
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CR1,Timer n Control Register 1"
|
|
bitfld.long 0x0 15. "SSYNC,Synchronize start counter with other synchronized timers" "0,1"
|
|
bitfld.long 0x0 14. "CSYNC,Synchronize clear counter with other synchronized tip" "0,1"
|
|
bitfld.long 0x0 13. "UAO,Select GRA GRB Update mode" "0,1"
|
|
bitfld.long 0x0 12. "OUTPOL,timer output polarity" "0,1"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADCTRGEN" "0,1"
|
|
bitfld.long 0x0 7. "STARTLVL,STARTLVL" "0,1"
|
|
bitfld.long 0x0 4.--6. "CKSEL,counter clock source select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "CLRMD,clear select when capture mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Timer operation mode control" "0,1,2,3"
|
|
line.long 0x4 "CR2,Timer n Control Register 2"
|
|
bitfld.long 0x4 1. "TCLR,Timer register clear" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer enable bit" "0,1"
|
|
line.long 0x8 "PRS,Timer n Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Prescaler value of count clock"
|
|
line.long 0xC "GRA,Timer n General Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA"
|
|
line.long 0x10 "GRB,Timer n General Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB"
|
|
line.long 0x14 "CNT,Timer n Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,CNT"
|
|
line.long 0x18 "SR,Timer n Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,counter overflow flag" "0,1"
|
|
line.long 0x1C "IER,Timer n Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter overflow interrupt enable" "0,1"
|
|
tree.end
|
|
tree "T2"
|
|
base ad:0x40003040
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CR1,Timer n Control Register 1"
|
|
bitfld.long 0x0 15. "SSYNC,Synchronize start counter with other synchronized timers" "0,1"
|
|
bitfld.long 0x0 14. "CSYNC,Synchronize clear counter with other synchronized tip" "0,1"
|
|
bitfld.long 0x0 13. "UAO,Select GRA GRB Update mode" "0,1"
|
|
bitfld.long 0x0 12. "OUTPOL,timer output polarity" "0,1"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADCTRGEN" "0,1"
|
|
bitfld.long 0x0 7. "STARTLVL,STARTLVL" "0,1"
|
|
bitfld.long 0x0 4.--6. "CKSEL,counter clock source select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "CLRMD,clear select when capture mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Timer operation mode control" "0,1,2,3"
|
|
line.long 0x4 "CR2,Timer n Control Register 2"
|
|
bitfld.long 0x4 1. "TCLR,Timer register clear" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer enable bit" "0,1"
|
|
line.long 0x8 "PRS,Timer n Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Prescaler value of count clock"
|
|
line.long 0xC "GRA,Timer n General Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA"
|
|
line.long 0x10 "GRB,Timer n General Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB"
|
|
line.long 0x14 "CNT,Timer n Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,CNT"
|
|
line.long 0x18 "SR,Timer n Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,counter overflow flag" "0,1"
|
|
line.long 0x1C "IER,Timer n Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter overflow interrupt enable" "0,1"
|
|
tree.end
|
|
tree "T3"
|
|
base ad:0x40003060
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CR1,Timer n Control Register 1"
|
|
bitfld.long 0x0 15. "SSYNC,Synchronize start counter with other synchronized timers" "0,1"
|
|
bitfld.long 0x0 14. "CSYNC,Synchronize clear counter with other synchronized tip" "0,1"
|
|
bitfld.long 0x0 13. "UAO,Select GRA GRB Update mode" "0,1"
|
|
bitfld.long 0x0 12. "OUTPOL,timer output polarity" "0,1"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADCTRGEN" "0,1"
|
|
bitfld.long 0x0 7. "STARTLVL,STARTLVL" "0,1"
|
|
bitfld.long 0x0 4.--6. "CKSEL,counter clock source select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "CLRMD,clear select when capture mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Timer operation mode control" "0,1,2,3"
|
|
line.long 0x4 "CR2,Timer n Control Register 2"
|
|
bitfld.long 0x4 1. "TCLR,Timer register clear" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer enable bit" "0,1"
|
|
line.long 0x8 "PRS,Timer n Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Prescaler value of count clock"
|
|
line.long 0xC "GRA,Timer n General Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA"
|
|
line.long 0x10 "GRB,Timer n General Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB"
|
|
line.long 0x14 "CNT,Timer n Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,CNT"
|
|
line.long 0x18 "SR,Timer n Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,counter overflow flag" "0,1"
|
|
line.long 0x1C "IER,Timer n Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match interrupt enable" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter overflow interrupt enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "U0"
|
|
base ad:0x40008000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "THR,received/transmit data"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
|
|
line.long 0x4 "IIR,UART Interrupt ID Register"
|
|
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
|
|
bitfld.long 0x4 1.--3. "IID,Interrupt source ID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
|
|
line.long 0x8 "LCR,UART Line Control Register"
|
|
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
|
|
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
|
|
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
|
|
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
|
|
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
|
|
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
|
|
line.long 0xC "DCR,UART Data Control Register"
|
|
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
|
|
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
|
|
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
|
|
line.long 0x10 "LSR,UART Line Status Register"
|
|
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
|
|
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
|
|
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
|
|
bitfld.long 0x10 3. "FE,frame error" "0,1"
|
|
bitfld.long 0x10 2. "PE,parity error" "0,1"
|
|
bitfld.long 0x10 1. "OE,overrun error" "0,1"
|
|
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
|
|
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "U1"
|
|
base ad:0x40008100
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "THR,received/transmit data"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
|
|
line.long 0x4 "IIR,UART Interrupt ID Register"
|
|
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
|
|
bitfld.long 0x4 1.--3. "IID,Interrupt source ID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
|
|
line.long 0x8 "LCR,UART Line Control Register"
|
|
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
|
|
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
|
|
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
|
|
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
|
|
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
|
|
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
|
|
line.long 0xC "DCR,UART Data Control Register"
|
|
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
|
|
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
|
|
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
|
|
line.long 0x10 "LSR,UART Line Status Register"
|
|
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
|
|
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
|
|
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
|
|
bitfld.long 0x10 3. "FE,frame error" "0,1"
|
|
bitfld.long 0x10 2. "PE,parity error" "0,1"
|
|
bitfld.long 0x10 1. "OE,overrun error" "0,1"
|
|
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
|
|
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40000200
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "LR,Watchdog Timer Load Register"
|
|
line.long 0x4 "CNT,Watchdog Timer Current Counter Register"
|
|
line.long 0x8 "CON,Watchdog Timer Control Register"
|
|
bitfld.long 0x8 15. "WDBG,WDT operation in debug mode" "0,1"
|
|
bitfld.long 0x8 8. "WUF,WDT underflow flag" "0,1"
|
|
bitfld.long 0x8 7. "WDTIE,WDT interrupt enable" "0,1"
|
|
bitfld.long 0x8 6. "WDTRE,WDT interrupt reset" "0,1"
|
|
bitfld.long 0x8 4. "WDTEN,WDT counter enable" "0,1"
|
|
bitfld.long 0x8 3. "CKSEL,WDTCLKIN clock source select" "0,1"
|
|
bitfld.long 0x8 0.--2. "WPRS,counter prescaler" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
AUTOINDENT.OFF
|