23750 lines
1.6 MiB
23750 lines
1.6 MiB
; --------------------------------------------------------------------------------
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; @Title: 66AK2Gx On-Chip Peripherals
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; @Props: Released
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; @Author: ASK, KRZ
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; @Changelog: 2016-10-14 ASK
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; 2022-04-29 KRZ
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; @Manufacturer: TI - Texas Instruments
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; @Doc: XML generated (TIXML2PER 2.04), based on:
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; 66AK2G01.xml (Ver. 1.0), 66AK2G02.xml (Ver. 1.0), 66AK2G12.xml (Ver. 1.0)
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; @Core: Cortex-A15, C646X, PRU
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; @Copyright: 1989-2018 Lauterbach GmbH, licensed for use with TRACE32 only
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; --------------------------------------------------------------------------------
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; $Id: per66ak2gx.per 15571 2022-12-22 18:04:22Z kwisniewski $
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config 16. 8.
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sif (!cpuis("66AK2G?2-ICSS?")&&cpu()!="PRU")
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sif (corename()=="CORTEXA15MPCORE")
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tree "Core Registers (Cortex-A15MPCore)"
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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width 10.
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tree "ID Registers"
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group.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
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bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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textline " "
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bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
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bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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textline " "
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bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..."
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endif
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..."
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
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textline " "
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bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4"
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rgroup.long c15:0x400++0x0
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line.long 0x0 "MIDR2,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x600++0x0
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line.long 0x0 "REVIDR,Revision ID Register"
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rgroup.long c15:0x700++0x0
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line.long 0x0 "MIDR3,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
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endif
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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endif
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..."
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endif
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
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textline " "
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..."
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..."
|
|
if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented"
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented"
|
|
bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented"
|
|
bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented"
|
|
bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "System Control and Configuration"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified"
|
|
bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented"
|
|
bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
|
|
bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled"
|
|
bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced"
|
|
bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced"
|
|
bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes"
|
|
bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes"
|
|
bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes"
|
|
bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited"
|
|
bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed"
|
|
bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced"
|
|
bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes"
|
|
bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited"
|
|
bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes"
|
|
bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes"
|
|
bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches"
|
|
textline " "
|
|
bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes"
|
|
bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x140F++0x00
|
|
line.long 0x0 "ACTLR2,Auxiliary Control Register 2"
|
|
bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
hgroup.long c15:0x140F++0x00
|
|
hide.long 0x0 "ACTLR2,Auxiliary Control Register 2"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes"
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
endif
|
|
group.long c15:0x11++0x0
|
|
line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted"
|
|
bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled"
|
|
bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group.long c15:0x0111++0x00
|
|
line.long 0x00 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable"
|
|
bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable"
|
|
bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes"
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
endif
|
|
group.long c15:0x000C++0x00
|
|
line.long 0x00 "VBAR,Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address"
|
|
group.long c15:0x010C++0x00
|
|
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup.long c15:0x001C++0x00
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x400F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]"
|
|
else
|
|
hgroup.long c15:0x400F++0x00
|
|
hide.long 0x00 "CBAR,Configuration Base Address Register"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x1609))&0x3)==0x3)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes"
|
|
bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x2)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes"
|
|
bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x1)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x0)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
endif
|
|
group.long c15:0x410F++0x00
|
|
line.long 0x00 "FILASTARTR,Peripheral port start address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region"
|
|
bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid"
|
|
group.long c15:0x420F++0x00
|
|
line.long 0x00 "FILAENDR,Peripheral port end address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
hgroup.long c15:0x1609++0x00
|
|
hide.long 0x00 "SCUCTLR,SCU Control Register"
|
|
hgroup.long c15:0x410F++0x00
|
|
hide.long 0x00 "FILASTARTR,Peripheral port start address register"
|
|
hgroup.long c15:0x420F++0x00
|
|
hide.long 0x00 "FILAENDR,Peripheral port end address register"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Memory Management Unit"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0001++0x0
|
|
line.long 0x0 "SCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x10020++0x01
|
|
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
endif
|
|
if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x11020++0x01
|
|
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
endif
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes"
|
|
bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes"
|
|
else
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High"
|
|
bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1"
|
|
bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
group.long c15:0x0003++0x00
|
|
line.long 0x00 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved"
|
|
endif
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
endif
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
endif
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
else
|
|
hgroup.long c15:0x0015++0x00
|
|
hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
endif
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved"
|
|
endif
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..."
|
|
endif
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
endif
|
|
endif
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0)
|
|
group.quad c15:0x0047++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA"
|
|
hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address"
|
|
bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure"
|
|
bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable"
|
|
bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1)
|
|
group.quad c15:0x0047++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2"
|
|
bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0)
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address"
|
|
bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate"
|
|
bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection"
|
|
bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1)
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
endif
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x002A++0x00
|
|
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x012A++0x00
|
|
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x003A++0x00
|
|
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x013A++0x00
|
|
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
hgroup.long c15:0x003A++0x00
|
|
hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x013A++0x00
|
|
hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
endif
|
|
else
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
endif
|
|
if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x400F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
hgroup.long c15:0x400F++0x00
|
|
hide.long 0x00 "CBAR,Configuration Base Address Register"
|
|
endif
|
|
textline " "
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x10d++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
else
|
|
group.long c15:0x10d++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier"
|
|
endif
|
|
group.long c15:0x020D++0x00
|
|
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
|
|
group.long c15:0x030D++0x00
|
|
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
|
|
group.long c15:0x040D++0x00
|
|
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
|
|
group.long c15:0x420D++0x00
|
|
line.long 0x00 "HTPIDR,Hyp Software Thread ID Register"
|
|
tree.end
|
|
width 15.
|
|
tree "Virtualization Extensions"
|
|
group.long c15:0x4000++0x00
|
|
line.long 0x0 "VPIDR,Virtualization Processor ID Register"
|
|
group.long c15:0x4500++0x00
|
|
line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register"
|
|
group.long c15:0x4001++0x00
|
|
line.long 0x00 "HSCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled"
|
|
group.long c15:0x4011++0x00
|
|
line.long 0x00 "HCR,Hyp Configuration Register"
|
|
bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system"
|
|
bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override"
|
|
bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled"
|
|
group.long c15:0x4111++0x00
|
|
line.long 0x00 "HDCR,Hyp Debug Control Register"
|
|
bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid"
|
|
bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid"
|
|
bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid"
|
|
bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid"
|
|
bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long c15:0x4211++0x00
|
|
line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register"
|
|
bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped"
|
|
bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped"
|
|
bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped"
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hyp Syndrome Register"
|
|
bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit"
|
|
hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome"
|
|
group.long c15:0x4311++0x00
|
|
line.long 0x00 "HSTR,Hyp System Trap Register"
|
|
bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped"
|
|
bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped"
|
|
bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped"
|
|
bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped"
|
|
bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped"
|
|
bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped"
|
|
bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped"
|
|
group.quad c15:0x14020++0x01
|
|
line.quad 0x00 "HTTBR,Hyp Translation Table Base Register"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
group.long c15:0x4202++0x00
|
|
line.long 0x00 "HTCR,Hyp Translation Control Register"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
group.quad c15:0x16020++0x01
|
|
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
group.long c15:0x4212++0x00
|
|
line.long 0x00 "VTCR,Virtualization Translation Control Register"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved"
|
|
bitfld.long 0x00 4. " S ,Sign extension bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x4015++0x00
|
|
line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register"
|
|
bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
endif
|
|
group.long c15:0x4006++0x00
|
|
line.long 0x00 "HDFAR,Hyp Data Fault Address Register"
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hyp Syndrome Register"
|
|
bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit"
|
|
hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome"
|
|
group.long c15:0x4206++0x00
|
|
line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register"
|
|
group.long c15:0x4406++0x00
|
|
line.long 0x00 "HPFAR,Hyp IPA Fault Address Register"
|
|
hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits"
|
|
textline " "
|
|
hgroup.long c15:0x407++0x00
|
|
hide.long 0x00 "NOP,No Operation Register"
|
|
in
|
|
wgroup.long c15:0x17++0x00
|
|
line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x617++0x00
|
|
line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x57++0x00
|
|
line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x157++0x00
|
|
line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x457++0x00
|
|
line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x657++0x00
|
|
line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x757++0x00
|
|
line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x167++0x00
|
|
line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x267++0x00
|
|
line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x0087++0x00
|
|
line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read"
|
|
wgroup.long c15:0x0187++0x00
|
|
line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write"
|
|
wgroup.long c15:0x0287++0x00
|
|
line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read"
|
|
wgroup.long c15:0x0387++0x00
|
|
line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write"
|
|
wgroup.long c15:0x0487++0x00
|
|
line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read"
|
|
wgroup.long c15:0x0587++0x00
|
|
line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write"
|
|
wgroup.long c15:0x0687++0x00
|
|
line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read"
|
|
wgroup.long c15:0x0787++0x00
|
|
line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write"
|
|
wgroup.long c15:0x1a7++0x00
|
|
line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x2a7++0x00
|
|
line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x4a7++0x00
|
|
line.long 0x00 "CP15DSB,Data Synchronization Barrier Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean"
|
|
wgroup.long c15:0x5a7++0x00
|
|
line.long 0x00 "CP15DMB,Data Memory Barrier Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean"
|
|
wgroup.long c15:0x1b7++0x00
|
|
line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x1e7++0x00
|
|
line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x2e7++0x00
|
|
line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x4087++0x00
|
|
line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read"
|
|
wgroup.long c15:0x4187++0x00
|
|
line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write"
|
|
wgroup.long c15:0x0038++0x00
|
|
line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable"
|
|
wgroup.long c15:0x0138++0x00
|
|
line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable"
|
|
wgroup.long c15:0x0238++0x00
|
|
line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable"
|
|
wgroup.long c15:0x0338++0x00
|
|
line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable"
|
|
wgroup.long c15:0x0058++0x00
|
|
line.long 0x00 "ITLBIALL,Invalidate instruction TLB"
|
|
wgroup.long c15:0x0158++0x00
|
|
line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA"
|
|
wgroup.long c15:0x0258++0x00
|
|
line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match"
|
|
wgroup.long c15:0x0068++0x00
|
|
line.long 0x00 "DTLBIALL,Invalidate data TLB"
|
|
wgroup.long c15:0x0168++0x00
|
|
line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA"
|
|
wgroup.long c15:0x0268++0x00
|
|
line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match"
|
|
wgroup.long c15:0x0078++0x00
|
|
line.long 0x00 "TLBIALL,Invalidate unified TLB"
|
|
wgroup.long c15:0x0178++0x00
|
|
line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA"
|
|
wgroup.long c15:0x0278++0x00
|
|
line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match"
|
|
wgroup.long c15:0x0378++0x00
|
|
line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID"
|
|
wgroup.long c15:0x4038++0x00
|
|
line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable"
|
|
wgroup.long c15:0x4138++0x00
|
|
line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable"
|
|
wgroup.long c15:0x4438++0x00
|
|
line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable"
|
|
wgroup.long c15:0x4078++0x00
|
|
line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB"
|
|
wgroup.long c15:0x4178++0x00
|
|
line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA"
|
|
wgroup.long c15:0x4478++0x00
|
|
line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB"
|
|
group.long c15:0x402A++0x00
|
|
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x412A++0x00
|
|
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x403A++0x00
|
|
line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x413A++0x00
|
|
line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
else
|
|
hgroup.long c15:0x403A++0x00
|
|
hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x413A++0x00
|
|
hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
|
|
endif
|
|
group.long c15:0x400C++0x00
|
|
line.long 0x00 "HVBAR,Hyp Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address"
|
|
tree.end
|
|
width 12.
|
|
tree "Cache Control and Configuration"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..."
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..."
|
|
endif
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c15:0x10EF++0x00
|
|
line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register"
|
|
bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved"
|
|
else
|
|
hgroup.long c15:0x10EF++0x00
|
|
hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register"
|
|
endif
|
|
tree "Level 1 memory system"
|
|
width 10.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x000F++0x00
|
|
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
|
|
group.long c15:0x010F++0x00
|
|
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
|
|
group.long c15:0x020F++0x00
|
|
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
|
|
group.long c15:0x001F++0x00
|
|
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
|
|
group.long c15:0x011F++0x00
|
|
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
|
|
group.long c15:0x021F++0x00
|
|
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
|
|
group.long c15:0x031F++0x00
|
|
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
|
|
wgroup.long c15:0x004F++0x00
|
|
line.long 0x00 "RAMINDEX,RAM Index Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
textline " "
|
|
group.quad c15:0x100F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count"
|
|
bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier"
|
|
bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x300F++0x0
|
|
line.long 0x00 "CDBGDR0,Data Register 0"
|
|
rgroup.long c15:0x310F++0x0
|
|
line.long 0x00 "CDBGDR1,Data Register 1"
|
|
rgroup.long c15:0x320F++0x0
|
|
line.long 0x00 "CDBGDR2,Data Register 2"
|
|
wgroup.long c15:0x302F++0x0
|
|
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x312F++0x0
|
|
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 31. " CW ,Cache Way" "Low,High"
|
|
hexmask.long 0x00 5.--30. 1. " SI ,Set index"
|
|
bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x304F++0x0
|
|
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 31. " CW ,Cache Way" "Low,High"
|
|
hexmask.long 0x00 5.--30. 1. " SI ,Set index"
|
|
bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x300F++0x0
|
|
line.long 0x00 "CDBGDR0,Data Register 0"
|
|
bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High"
|
|
bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High"
|
|
bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High"
|
|
bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High"
|
|
hexmask.long 0x00 0.--26. 1. " TA ,Tag Address"
|
|
rgroup.long c15:0x310F++0x0
|
|
line.long 0x00 "CDBGDR1,Data Register 1"
|
|
bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High"
|
|
rgroup.long c15:0x320F++0x0
|
|
line.long 0x00 "CDBGDR2,Data Register 2"
|
|
wgroup.long c15:0x302F++0x0
|
|
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
wgroup.long c15:0x312F++0x0
|
|
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long 0x00 6.--30. 1. " SI ,Set index"
|
|
wgroup.long c15:0x304F++0x0
|
|
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--15. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--16. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--17. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--18. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--19. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--20. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long c15:0x314F++0x0
|
|
hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
endif
|
|
if (((d.l(c15:0x324F))&0x100)==0x100)
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1"
|
|
else
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3"
|
|
bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Level 2 memory system"
|
|
width 11.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes"
|
|
bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle"
|
|
bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle"
|
|
bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
|
|
bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present"
|
|
bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes"
|
|
bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191."
|
|
rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes"
|
|
bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
group.long c15:0x100F++0x00
|
|
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced"
|
|
bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced"
|
|
bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes"
|
|
bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes"
|
|
bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes"
|
|
bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes"
|
|
bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes"
|
|
bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes"
|
|
group.long c15:0x130F++0x00
|
|
line.long 0x00 "L2PFR,L2 Prefetch Control Register"
|
|
bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
|
|
bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
|
|
bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines"
|
|
textline " "
|
|
group.quad c15:0x110F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count"
|
|
bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
|
|
hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
hgroup.quad c15:0x110F0++0x01
|
|
hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes"
|
|
rgroup.long c15:0x1609++0x00
|
|
line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1"
|
|
bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA"
|
|
bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes"
|
|
bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
|
|
bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
|
|
bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment"
|
|
bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment"
|
|
bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Monitor Select Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
|
|
group.long c15:0x1d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
|
|
bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count"
|
|
group.long c15:0x2d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
|
|
eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
group.long c15:0x3e9++0x00
|
|
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
|
|
bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
width 12.
|
|
tree "System Timer Register"
|
|
group.long c15:0x000E++0x00
|
|
line.long 0x00 "CNTFRQ,Counter Frequency Register"
|
|
group.long c15:0x001E++0x00
|
|
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
|
|
bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
textline ""
|
|
group.quad c15:0x100E0++0x01
|
|
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
|
|
group.quad c15:0x120E0++0x01
|
|
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
|
|
group.long c15:0x002E++0x00
|
|
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register"
|
|
group.long c15:0x012E++0x00
|
|
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
textline ""
|
|
group.quad c15:0x110E0++0x01
|
|
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
|
|
group.quad c15:0x130E0++0x01
|
|
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
|
|
group.long c15:0x003E++0x00
|
|
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
|
|
group.long c15:0x013E++0x00
|
|
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
group.quad c15:0x140E0++0x01
|
|
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
|
|
textline ""
|
|
group.long c15:0x401E++0x00
|
|
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
group.quad c15:0x160E0++0x01
|
|
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
|
|
group.long c15:0x402E++0x00
|
|
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
|
|
group.long c15:0x412E++0x00
|
|
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
width 15.
|
|
tree "Debug Registers"
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented"
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
wgroup.long c14:6.++0x0
|
|
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
endif
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled"
|
|
group.long c14:9.++0x0
|
|
line.long 0x00 "DBGECR,Debug Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group.long c14:32.++0x0
|
|
line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Debug Instruction Transfer Register"
|
|
rgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
endif
|
|
wgroup.long c14:35.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request"
|
|
bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running"
|
|
textline " "
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
endif
|
|
rgroup.long c14:40.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..."
|
|
rgroup.long c14:41.++0x0
|
|
line.long 0x00 "DBGCIDSR,DBGCIDSR"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register"
|
|
bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,DBGVIDSR"
|
|
endif
|
|
width 15.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register"
|
|
bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High"
|
|
bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register"
|
|
bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High"
|
|
bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High"
|
|
bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITISR,Debug Integration Input Status Register"
|
|
bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register"
|
|
bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High"
|
|
bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
rgroup.quad c14:128.++0x1
|
|
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.quad c14:256.++0x1
|
|
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
else
|
|
rgroup.long c14:128.++0x0
|
|
line.long 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.long c14:256.++0x0
|
|
line.long 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
endif
|
|
group.long c14:195.++0x00
|
|
line.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked"
|
|
else
|
|
hgroup.quad c14:128.++0x1
|
|
hide.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hgroup.quad c14:256.++0x1
|
|
hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hgroup.long c14:195.++0x00
|
|
hide.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
endif
|
|
wgroup.long c14:192.++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup.long c14:193.++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..."
|
|
group.long c14:196.++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High"
|
|
bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High"
|
|
bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High"
|
|
bitfld.long 0x00 4. " HALTED ,Halted" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High"
|
|
bitfld.long 0x00 2. " RS ,Reset Status" "Low,High"
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High"
|
|
tree "Processor ID registers"
|
|
rgroup.long c14:(832.+0.)++0x00
|
|
line.long 0x00 "PIDR0,Processor ID register 0"
|
|
rgroup.long c14:(832.+1.)++0x00
|
|
line.long 0x00 "PIDR1,Processor ID register 1"
|
|
rgroup.long c14:(832.+2.)++0x00
|
|
line.long 0x00 "PIDR2,Processor ID register 2"
|
|
rgroup.long c14:(832.+3.)++0x00
|
|
line.long 0x00 "PIDR3,Processor ID register 3"
|
|
rgroup.long c14:(832.+4.)++0x00
|
|
line.long 0x00 "PIDR4,Processor ID register 4"
|
|
rgroup.long c14:(832.+5.)++0x00
|
|
line.long 0x00 "PIDR5,Processor ID register 5"
|
|
rgroup.long c14:(832.+6.)++0x00
|
|
line.long 0x00 "PIDR6,Processor ID register 6"
|
|
rgroup.long c14:(832.+7.)++0x00
|
|
line.long 0x00 "PIDR7,Processor ID register 7"
|
|
rgroup.long c14:(832.+8.)++0x00
|
|
line.long 0x00 "PIDR8,Processor ID register 8"
|
|
rgroup.long c14:(832.+9.)++0x00
|
|
line.long 0x00 "PIDR9,Processor ID register 9"
|
|
rgroup.long c14:(832.+10.)++0x00
|
|
line.long 0x00 "PIDR10,Processor ID register 10"
|
|
rgroup.long c14:(832.+11.)++0x00
|
|
line.long 0x00 "PIDR11,Processor ID register 11"
|
|
rgroup.long c14:(832.+12.)++0x00
|
|
line.long 0x00 "PIDR12,Processor ID register 12"
|
|
rgroup.long c14:(832.+13.)++0x00
|
|
line.long 0x00 "PIDR13,Processor ID register 13"
|
|
rgroup.long c14:(832.+14.)++0x00
|
|
line.long 0x00 "PIDR14,Processor ID register 14"
|
|
rgroup.long c14:(832.+15.)++0x00
|
|
line.long 0x00 "PIDR15,Processor ID register 15"
|
|
rgroup.long c14:(832.+16.)++0x00
|
|
line.long 0x00 "PIDR16,Processor ID register 16"
|
|
rgroup.long c14:(832.+17.)++0x00
|
|
line.long 0x00 "PIDR17,Processor ID register 17"
|
|
rgroup.long c14:(832.+18.)++0x00
|
|
line.long 0x00 "PIDR18,Processor ID register 18"
|
|
rgroup.long c14:(832.+19.)++0x00
|
|
line.long 0x00 "PIDR19,Processor ID register 19"
|
|
rgroup.long c14:(832.+20.)++0x00
|
|
line.long 0x00 "PIDR20,Processor ID register 20"
|
|
rgroup.long c14:(832.+21.)++0x00
|
|
line.long 0x00 "PIDR21,Processor ID register 21"
|
|
rgroup.long c14:(832.+22.)++0x00
|
|
line.long 0x00 "PIDR22,Processor ID register 22"
|
|
rgroup.long c14:(832.+23.)++0x00
|
|
line.long 0x00 "PIDR23,Processor ID register 23"
|
|
rgroup.long c14:(832.+24.)++0x00
|
|
line.long 0x00 "PIDR24,Processor ID register 24"
|
|
rgroup.long c14:(832.+25.)++0x00
|
|
line.long 0x00 "PIDR25,Processor ID register 25"
|
|
rgroup.long c14:(832.+26.)++0x00
|
|
line.long 0x00 "PIDR26,Processor ID register 26"
|
|
rgroup.long c14:(832.+27.)++0x00
|
|
line.long 0x00 "PIDR27,Processor ID register 27"
|
|
rgroup.long c14:(832.+28.)++0x00
|
|
line.long 0x00 "PIDR28,Processor ID register 28"
|
|
rgroup.long c14:(832.+29.)++0x00
|
|
line.long 0x00 "PIDR29,Processor ID register 29"
|
|
rgroup.long c14:(832.+30.)++0x00
|
|
line.long 0x00 "PIDR30,Processor ID register 30"
|
|
rgroup.long c14:(832.+31.)++0x00
|
|
line.long 0x00 "PIDR31,Processor ID register 31"
|
|
rgroup.long c14:(832.+32.)++0x00
|
|
line.long 0x00 "PIDR32,Processor ID register 32"
|
|
rgroup.long c14:(832.+33.)++0x00
|
|
line.long 0x00 "PIDR33,Processor ID register 33"
|
|
rgroup.long c14:(832.+34.)++0x00
|
|
line.long 0x00 "PIDR34,Processor ID register 34"
|
|
rgroup.long c14:(832.+35.)++0x00
|
|
line.long 0x00 "PIDR35,Processor ID register 35"
|
|
rgroup.long c14:(832.+36.)++0x00
|
|
line.long 0x00 "PIDR36,Processor ID register 36"
|
|
rgroup.long c14:(832.+37.)++0x00
|
|
line.long 0x00 "PIDR37,Processor ID register 37"
|
|
rgroup.long c14:(832.+38.)++0x00
|
|
line.long 0x00 "PIDR38,Processor ID register 38"
|
|
rgroup.long c14:(832.+39.)++0x00
|
|
line.long 0x00 "PIDR39,Processor ID register 39"
|
|
rgroup.long c14:(832.+40.)++0x00
|
|
line.long 0x00 "PIDR40,Processor ID register 40"
|
|
rgroup.long c14:(832.+41.)++0x00
|
|
line.long 0x00 "PIDR41,Processor ID register 41"
|
|
rgroup.long c14:(832.+42.)++0x00
|
|
line.long 0x00 "PIDR42,Processor ID register 42"
|
|
rgroup.long c14:(832.+43.)++0x00
|
|
line.long 0x00 "PIDR43,Processor ID register 43"
|
|
rgroup.long c14:(832.+44.)++0x00
|
|
line.long 0x00 "PIDR44,Processor ID register 44"
|
|
rgroup.long c14:(832.+45.)++0x00
|
|
line.long 0x00 "PIDR45,Processor ID register 45"
|
|
rgroup.long c14:(832.+46.)++0x00
|
|
line.long 0x00 "PIDR46,Processor ID register 46"
|
|
rgroup.long c14:(832.+47.)++0x00
|
|
line.long 0x00 "PIDR47,Processor ID register 47"
|
|
rgroup.long c14:(832.+48.)++0x00
|
|
line.long 0x00 "PIDR48,Processor ID register 48"
|
|
rgroup.long c14:(832.+49.)++0x00
|
|
line.long 0x00 "PIDR49,Processor ID register 49"
|
|
rgroup.long c14:(832.+50.)++0x00
|
|
line.long 0x00 "PIDR50,Processor ID register 50"
|
|
rgroup.long c14:(832.+51.)++0x00
|
|
line.long 0x00 "PIDR51,Processor ID register 51"
|
|
rgroup.long c14:(832.+52.)++0x00
|
|
line.long 0x00 "PIDR52,Processor ID register 52"
|
|
rgroup.long c14:(832.+53.)++0x00
|
|
line.long 0x00 "PIDR53,Processor ID register 53"
|
|
rgroup.long c14:(832.+54.)++0x00
|
|
line.long 0x00 "PIDR54,Processor ID register 54"
|
|
rgroup.long c14:(832.+55.)++0x00
|
|
line.long 0x00 "PIDR55,Processor ID register 55"
|
|
rgroup.long c14:(832.+56.)++0x00
|
|
line.long 0x00 "PIDR56,Processor ID register 56"
|
|
rgroup.long c14:(832.+57.)++0x00
|
|
line.long 0x00 "PIDR57,Processor ID register 57"
|
|
rgroup.long c14:(832.+58.)++0x00
|
|
line.long 0x00 "PIDR58,Processor ID register 58"
|
|
rgroup.long c14:(832.+59.)++0x00
|
|
line.long 0x00 "PIDR59,Processor ID register 59"
|
|
rgroup.long c14:(832.+60.)++0x00
|
|
line.long 0x00 "PIDR60,Processor ID register 60"
|
|
rgroup.long c14:(832.+61.)++0x00
|
|
line.long 0x00 "PIDR61,Processor ID register 61"
|
|
rgroup.long c14:(832.+62.)++0x00
|
|
line.long 0x00 "PIDR62,Processor ID register 62"
|
|
rgroup.long c14:(832.+63.)++0x00
|
|
line.long 0x00 "PIDR63,Processor ID register 63"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x0
|
|
line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group.long c14:1000.++0x0
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set"
|
|
group.long c14:1001.++0x0
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
rgroup.long c14:1006.++0x0
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..."
|
|
endif
|
|
textline " "
|
|
rgroup.long c14:1010.++0x0
|
|
line.long 0x0 "DBGDEVID0,Debug Device ID Register 0"
|
|
bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..."
|
|
bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
|
|
textline " "
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Debug Device Type Register"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c14:1016.++0x00
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup.long c14:1017.++0x00
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup.long c14:1018.++0x00
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup.long c14:1019.++0x00
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup.long c14:1012.++0x00
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup.long c14:1020.++0x00
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup.long c14:1021.++0x00
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup.long c14:1022.++0x00
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup.long c14:1023.++0x00
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 10.
|
|
tree "Breakpoint Registers"
|
|
if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+0.)++0x0
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+1.)++0x0
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+2.)++0x0
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+3.)++0x0
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+4.)++0x0
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+5.)++0x0
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
group.long c14:148.++0x0
|
|
line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
group.long c14:149.++0x0
|
|
line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
tree.end
|
|
width 10.
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:(96.+0.)++0x00
|
|
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+1.)++0x00
|
|
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+2.)++0x00
|
|
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+3.)++0x00
|
|
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "Core Registers (c66x)"
|
|
config 16. 8.
|
|
width 0x0b
|
|
tree.open "Cache"
|
|
tree "L1P Cache"
|
|
base d:0x01840000
|
|
width 9.
|
|
group.long 0x20++0x7 "L1P Cache Control Registers"
|
|
line.long 0x00 "L1PCFG,L1P Configuration Register"
|
|
bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
|
|
line.long 0x04 "L1PCC,L1P Cache Control Register"
|
|
bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1"
|
|
bitfld.long 0x04 0. " OPER ,Controls the L1P freeze mode" "Disabled,Enabled"
|
|
wgroup.long 0x4020++0x3
|
|
line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation"
|
|
group.long 0x4024++0x3
|
|
line.long 0x00 "L1PIWC,L1P Invalidate Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1PIWC ,Word count for block invalidation"
|
|
group.long 0x5028++0x3
|
|
line.long 0x00 "L1PINV,L1P Invalidate Register"
|
|
bitfld.long 0x00 0. " I ,Controls the global invalidation of L1P cache" "Normal,Invalidate"
|
|
//width 13.
|
|
//wgroup.long 0xD00++0x13 "Memory Protection Lock Registers"
|
|
// line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0"
|
|
// hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0"
|
|
// line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1"
|
|
// hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32"
|
|
// line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2"
|
|
// hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64"
|
|
// line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3"
|
|
// hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96"
|
|
// line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register"
|
|
// bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset"
|
|
// bitfld.long 0x10 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked"
|
|
// bitfld.long 0x10 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
|
|
//rgroup.long 0xD14++0x3
|
|
// line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register"
|
|
// bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged"
|
|
base d:0x0184a000
|
|
width 12.
|
|
tree "Memory Page Protection Attribute Registers"
|
|
group.long 0x640++0x3f
|
|
line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16"
|
|
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x0 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x0 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17"
|
|
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18"
|
|
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x8 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x8 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19"
|
|
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0xC 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0xC 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20"
|
|
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x10 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x10 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21"
|
|
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x14 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x14 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22"
|
|
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x18 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x18 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23"
|
|
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24"
|
|
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x20 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x20 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25"
|
|
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x24 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x24 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26"
|
|
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x28 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x28 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27"
|
|
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28"
|
|
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x30 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x30 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29"
|
|
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x34 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x34 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30"
|
|
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x38 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x38 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31"
|
|
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User"
|
|
tree.end
|
|
width 11.
|
|
rgroup.long 0x400++0x7 "Memory Protection Fault Registers"
|
|
line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address"
|
|
hexmask.long 0x00 0.--31. 1. " FA ,Fault Address"
|
|
line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register"
|
|
hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of faulting requestor"
|
|
bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Local"
|
|
bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x04 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x04 1. " UW ,User write access type" "Normal,User"
|
|
group.long 0x408++0x3
|
|
line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear"
|
|
bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear"
|
|
AUTOINDENT.ON right tree
|
|
rgroup.long 0x6404++0x3 "Error Detection Registers"
|
|
line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register"
|
|
bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
|
|
bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True"
|
|
bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True"
|
|
bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True"
|
|
bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True"
|
|
group.long 0x6408++0x3
|
|
line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register"
|
|
bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
|
|
bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable"
|
|
bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable"
|
|
rgroup.long 0x640C++0x3
|
|
line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register"
|
|
hexmask.long.long 0x0 5.--31. 32. "ADDR,Contains the upper 27 bit of error location"
|
|
bitfld.long 0x0 0. "RAM,Location where error was detected" "L1P cache,L1P RAM"
|
|
AUTOINDENT.OFF
|
|
width 0xb
|
|
tree.end
|
|
tree "L1D Cache"
|
|
base d:0x01840000
|
|
width 10.
|
|
group.long 0x40++0x7 "L1D Cache Control Registers"
|
|
line.long 0x00 "L1DCFG,L1D Cache Configuration"
|
|
bitfld.long 0x00 0.--2. " L1DMODE ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
|
|
line.long 0x04 "L1DCC,L1D Cache Control Register"
|
|
bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1"
|
|
bitfld.long 0x04 0. " OPER ,Controls the L1D freeze mode" "Disabled,Enabled"
|
|
wgroup.long 0x4030++0x3
|
|
line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address"
|
|
group.long 0x4034++0x3
|
|
line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1DWIWC ,L1D Writeback-Invalidated Word Count"
|
|
wgroup.long 0x4040++0x3
|
|
line.long 0x00 "L1DWBAR,L1D Writeback Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L1DWBAR ,L1D Writeback Base Address"
|
|
group.long 0x4044++0x3
|
|
line.long 0x00 "L1DWWC,L1D Writeback Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1DWWC ,L1D Writeback Word Count"
|
|
wgroup.long 0x4048++0x3
|
|
line.long 0x00 "L1DIBAR,L1D Invalidate Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L1DIBAR ,L1D Invalidate Base Address"
|
|
group.long 0x404c++0x3
|
|
line.long 0x00 "L1DIWC,L1D Invalidate Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1DIWC ,L1D Invalidate Word Count"
|
|
group.long 0x5048++0x3
|
|
line.long 0x00 "L1DINV,L1D Invalidate Register"
|
|
bitfld.long 0x00 0. " I ,Controls the global invalidation of L1D cache" "Normal,Invalidate"
|
|
group.long 0x5040++0x3
|
|
line.long 0x00 "L1DWB,L1P Writeback Register"
|
|
bitfld.long 0x00 0. " C ,Controls the global writeback operation of L1D cache" "Normal,Write back"
|
|
group.long 0x5044++0x3
|
|
line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register"
|
|
bitfld.long 0x00 0. " C ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate"
|
|
width 11.
|
|
base d:0x0184a000
|
|
tree "Memory Protection Attribute Registers"
|
|
group.long 0xe40++0x3f
|
|
line.long 0x0 "MPPA16,Memory Protection Attribute Register"
|
|
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x0 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x0 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x4 "MPPA17,Memory Protection Attribute Register"
|
|
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x8 "MPPA18,Memory Protection Attribute Register"
|
|
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x8 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x8 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0xC "MPPA19,Memory Protection Attribute Register"
|
|
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0xC 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0xC 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x10 "MPPA20,Memory Protection Attribute Register"
|
|
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x10 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x10 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x14 "MPPA21,Memory Protection Attribute Register"
|
|
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x14 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x14 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x18 "MPPA22,Memory Protection Attribute Register"
|
|
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x18 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x18 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x1C "MPPA23,Memory Protection Attribute Register"
|
|
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x20 "MPPA24,Memory Protection Attribute Register"
|
|
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x20 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x20 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x24 "MPPA25,Memory Protection Attribute Register"
|
|
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x24 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x24 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x28 "MPPA26,Memory Protection Attribute Register"
|
|
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x28 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x28 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x2C "MPPA27,Memory Protection Attribute Register"
|
|
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x30 "MPPA28,Memory Protection Attribute Register"
|
|
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x30 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x30 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x34 "MPPA29,Memory Protection Attribute Register"
|
|
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x34 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x34 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x38 "MPPA30,Memory Protection Attribute Register"
|
|
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x38 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x38 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x3C "MPPA31,Memory Protection Attribute Register"
|
|
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User"
|
|
tree.end
|
|
base d:0x0184a000
|
|
width 10.
|
|
rgroup.long 0xc00++0x7 "Memory Protection Fault Registers"
|
|
line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " FA ,Fault Address"
|
|
line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register"
|
|
hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor"
|
|
bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor"
|
|
bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x04 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x04 1. " UW ,User write access type" "Normal,User"
|
|
group.long 0xc08++0x3
|
|
line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register"
|
|
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared"
|
|
width 13.
|
|
wgroup.long 0xd00++0xf "Memory Protection Lock Registers"
|
|
line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0"
|
|
line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1"
|
|
hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32"
|
|
line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2"
|
|
line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3"
|
|
wgroup.long 0xd10++0x3
|
|
line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register"
|
|
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
|
|
bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked"
|
|
bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
|
|
rgroup.long 0xd14++0x3
|
|
line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register"
|
|
bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged"
|
|
width 0xb
|
|
tree.end
|
|
tree "L2 Cache"
|
|
base d:0x01840000
|
|
width 9.
|
|
group.long 0x00++0x3 "L2 Cache Control Registers"
|
|
line.long 0x00 "L2CFG,L2 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--27. 1. " NUM_MM ,Number of megamodules minus one"
|
|
hexmask.long.byte 0x00 16.--19. 1. " MMID ,Contains the Megamodule ID number"
|
|
bitfld.long 0x00 9. " IP ,L1P global invalidate bit" "Normal,Invalidate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ID ,L1D global invalidate bit" "Normal,Invalidate"
|
|
bitfld.long 0x00 3. " L2CC ,Freeze mode" "Normal,Frozen"
|
|
bitfld.long 0x00 0.--2. " L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum"
|
|
wgroup.long 0x4000++0x3
|
|
line.long 0x00 "L2WBAR,L2 Writeback Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " L2WBAR ,L2 Writeback Base Address"
|
|
group.long 0x4004++0x3
|
|
line.long 0x00 "L2WWC,L2 Writeback Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " L2WWC ,L2 Writeback Word Count"
|
|
wgroup.long 0x4010++0x3
|
|
line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address"
|
|
group.long 0x4014++0x3
|
|
line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " L2WIWC ,L2 Writeback Invalidate Word Count"
|
|
wgroup.long 0x4018++0x3
|
|
line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " L2IBAR ,L2 Invalidate Base Address"
|
|
group.long 0x401c++0x3
|
|
line.long 0x00 "L2IWC,L2 Invalidate Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " L2IWC ,L2 Invalidate Word Count"
|
|
group.long 0x5000++0xb
|
|
line.long 0x00 "L2WB,L2 Writeback Register"
|
|
bitfld.long 0x00 0. " C ,Controls the global writeback operation of L2 cache" "Normal,Writeback"
|
|
line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register"
|
|
bitfld.long 0x04 0. " C ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback"
|
|
line.long 0x08 "L2INV,L2 Invalidate Register"
|
|
bitfld.long 0x08 0. " I ,Controls the global invalidation of L2 cache" "Normal,Invalidate"
|
|
tree "Memory Attribute Registers"
|
|
width 8.
|
|
base d:0x01848000
|
|
rgroup.long 0x00++0x2f
|
|
line.long 0x0 "MAR0,Memory Attribute Register 0"
|
|
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x4 "MAR1,Memory Attribute Register 1"
|
|
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x8 "MAR2,Memory Attribute Register 2"
|
|
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC "MAR3,Memory Attribute Register 3"
|
|
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x10 "MAR4,Memory Attribute Register 4"
|
|
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x14 "MAR5,Memory Attribute Register 5"
|
|
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x18 "MAR6,Memory Attribute Register 6"
|
|
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C "MAR7,Memory Attribute Register 7"
|
|
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x20 "MAR8,Memory Attribute Register 8"
|
|
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x24 "MAR9,Memory Attribute Register 9"
|
|
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x28 "MAR10,Memory Attribute Register 10"
|
|
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C "MAR11,Memory Attribute Register 11"
|
|
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
group.long 0x30++0x3cf
|
|
line.long 0x0 "MAR12,Memory Attribute Register 12"
|
|
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x4 "MAR13,Memory Attribute Register 13"
|
|
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x8 "MAR14,Memory Attribute Register 14"
|
|
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC "MAR15,Memory Attribute Register 15"
|
|
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x10 "MAR16,Memory Attribute Register 16"
|
|
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x14 "MAR17,Memory Attribute Register 17"
|
|
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x18 "MAR18,Memory Attribute Register 18"
|
|
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C "MAR19,Memory Attribute Register 19"
|
|
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x20 "MAR20,Memory Attribute Register 20"
|
|
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x24 "MAR21,Memory Attribute Register 21"
|
|
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x28 "MAR22,Memory Attribute Register 22"
|
|
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C "MAR23,Memory Attribute Register 23"
|
|
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x30 "MAR24,Memory Attribute Register 24"
|
|
bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x30 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x34 "MAR25,Memory Attribute Register 25"
|
|
bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x34 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x38 "MAR26,Memory Attribute Register 26"
|
|
bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x38 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C "MAR27,Memory Attribute Register 27"
|
|
bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x40 "MAR28,Memory Attribute Register 28"
|
|
bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x40 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x44 "MAR29,Memory Attribute Register 29"
|
|
bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x44 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x48 "MAR30,Memory Attribute Register 30"
|
|
bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x48 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x4C "MAR31,Memory Attribute Register 31"
|
|
bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x4C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x50 "MAR32,Memory Attribute Register 32"
|
|
bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x50 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x54 "MAR33,Memory Attribute Register 33"
|
|
bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x54 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x58 "MAR34,Memory Attribute Register 34"
|
|
bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x58 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x5C "MAR35,Memory Attribute Register 35"
|
|
bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x5C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x60 "MAR36,Memory Attribute Register 36"
|
|
bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x60 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x64 "MAR37,Memory Attribute Register 37"
|
|
bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x64 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x68 "MAR38,Memory Attribute Register 38"
|
|
bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x68 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x6C "MAR39,Memory Attribute Register 39"
|
|
bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x6C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x70 "MAR40,Memory Attribute Register 40"
|
|
bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x70 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x74 "MAR41,Memory Attribute Register 41"
|
|
bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x74 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x78 "MAR42,Memory Attribute Register 42"
|
|
bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x78 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x7C "MAR43,Memory Attribute Register 43"
|
|
bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x7C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x80 "MAR44,Memory Attribute Register 44"
|
|
bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x80 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x84 "MAR45,Memory Attribute Register 45"
|
|
bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x84 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x88 "MAR46,Memory Attribute Register 46"
|
|
bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x88 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x8C "MAR47,Memory Attribute Register 47"
|
|
bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x8C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x90 "MAR48,Memory Attribute Register 48"
|
|
bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x90 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x94 "MAR49,Memory Attribute Register 49"
|
|
bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x94 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x98 "MAR50,Memory Attribute Register 50"
|
|
bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x98 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x9C "MAR51,Memory Attribute Register 51"
|
|
bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x9C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xA0 "MAR52,Memory Attribute Register 52"
|
|
bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xA0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xA4 "MAR53,Memory Attribute Register 53"
|
|
bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xA4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xA8 "MAR54,Memory Attribute Register 54"
|
|
bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xA8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xAC "MAR55,Memory Attribute Register 55"
|
|
bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xAC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xB0 "MAR56,Memory Attribute Register 56"
|
|
bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xB0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xB4 "MAR57,Memory Attribute Register 57"
|
|
bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xB4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xB8 "MAR58,Memory Attribute Register 58"
|
|
bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xB8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xBC "MAR59,Memory Attribute Register 59"
|
|
bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xBC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC0 "MAR60,Memory Attribute Register 60"
|
|
bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC4 "MAR61,Memory Attribute Register 61"
|
|
bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC8 "MAR62,Memory Attribute Register 62"
|
|
bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xCC "MAR63,Memory Attribute Register 63"
|
|
bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xCC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xD0 "MAR64,Memory Attribute Register 64"
|
|
bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xD0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xD4 "MAR65,Memory Attribute Register 65"
|
|
bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xD4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xD8 "MAR66,Memory Attribute Register 66"
|
|
bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xD8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xDC "MAR67,Memory Attribute Register 67"
|
|
bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xDC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xE0 "MAR68,Memory Attribute Register 68"
|
|
bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xE0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xE4 "MAR69,Memory Attribute Register 69"
|
|
bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xE4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xE8 "MAR70,Memory Attribute Register 70"
|
|
bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xE8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xEC "MAR71,Memory Attribute Register 71"
|
|
bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xEC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xF0 "MAR72,Memory Attribute Register 72"
|
|
bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xF0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xF4 "MAR73,Memory Attribute Register 73"
|
|
bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xF4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xF8 "MAR74,Memory Attribute Register 74"
|
|
bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xF8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xFC "MAR75,Memory Attribute Register 75"
|
|
bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xFC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x100 "MAR76,Memory Attribute Register 76"
|
|
bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x100 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x104 "MAR77,Memory Attribute Register 77"
|
|
bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x104 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x108 "MAR78,Memory Attribute Register 78"
|
|
bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x108 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x10C "MAR79,Memory Attribute Register 79"
|
|
bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x10C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x110 "MAR80,Memory Attribute Register 80"
|
|
bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x110 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x114 "MAR81,Memory Attribute Register 81"
|
|
bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x114 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x118 "MAR82,Memory Attribute Register 82"
|
|
bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x118 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x11C "MAR83,Memory Attribute Register 83"
|
|
bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x11C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x120 "MAR84,Memory Attribute Register 84"
|
|
bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x120 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x124 "MAR85,Memory Attribute Register 85"
|
|
bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x124 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x128 "MAR86,Memory Attribute Register 86"
|
|
bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x128 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x12C "MAR87,Memory Attribute Register 87"
|
|
bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x12C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x130 "MAR88,Memory Attribute Register 88"
|
|
bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x130 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x134 "MAR89,Memory Attribute Register 89"
|
|
bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x134 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x138 "MAR90,Memory Attribute Register 90"
|
|
bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x138 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x13C "MAR91,Memory Attribute Register 91"
|
|
bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x13C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x140 "MAR92,Memory Attribute Register 92"
|
|
bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x140 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x144 "MAR93,Memory Attribute Register 93"
|
|
bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x144 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x148 "MAR94,Memory Attribute Register 94"
|
|
bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x148 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x14C "MAR95,Memory Attribute Register 95"
|
|
bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x14C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x150 "MAR96,Memory Attribute Register 96"
|
|
bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x150 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x154 "MAR97,Memory Attribute Register 97"
|
|
bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x154 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x158 "MAR98,Memory Attribute Register 98"
|
|
bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x158 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x15C "MAR99,Memory Attribute Register 99"
|
|
bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x15C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x160 "MAR100,Memory Attribute Register 100"
|
|
bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x160 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x164 "MAR101,Memory Attribute Register 101"
|
|
bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x164 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x168 "MAR102,Memory Attribute Register 102"
|
|
bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x168 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x16C "MAR103,Memory Attribute Register 103"
|
|
bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x16C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x170 "MAR104,Memory Attribute Register 104"
|
|
bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x170 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x174 "MAR105,Memory Attribute Register 105"
|
|
bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x174 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x178 "MAR106,Memory Attribute Register 106"
|
|
bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x178 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x17C "MAR107,Memory Attribute Register 107"
|
|
bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x17C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x180 "MAR108,Memory Attribute Register 108"
|
|
bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x180 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x184 "MAR109,Memory Attribute Register 109"
|
|
bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x184 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x188 "MAR110,Memory Attribute Register 110"
|
|
bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x188 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x18C "MAR111,Memory Attribute Register 111"
|
|
bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x18C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x190 "MAR112,Memory Attribute Register 112"
|
|
bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x190 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x194 "MAR113,Memory Attribute Register 113"
|
|
bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x194 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x198 "MAR114,Memory Attribute Register 114"
|
|
bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x198 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x19C "MAR115,Memory Attribute Register 115"
|
|
bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x19C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1A0 "MAR116,Memory Attribute Register 116"
|
|
bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1A4 "MAR117,Memory Attribute Register 117"
|
|
bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1A8 "MAR118,Memory Attribute Register 118"
|
|
bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1AC "MAR119,Memory Attribute Register 119"
|
|
bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1B0 "MAR120,Memory Attribute Register 120"
|
|
bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1B4 "MAR121,Memory Attribute Register 121"
|
|
bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1B8 "MAR122,Memory Attribute Register 122"
|
|
bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1BC "MAR123,Memory Attribute Register 123"
|
|
bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C0 "MAR124,Memory Attribute Register 124"
|
|
bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C4 "MAR125,Memory Attribute Register 125"
|
|
bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C8 "MAR126,Memory Attribute Register 126"
|
|
bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1CC "MAR127,Memory Attribute Register 127"
|
|
bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1D0 "MAR128,Memory Attribute Register 128"
|
|
bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1D4 "MAR129,Memory Attribute Register 129"
|
|
bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1D8 "MAR130,Memory Attribute Register 130"
|
|
bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1DC "MAR131,Memory Attribute Register 131"
|
|
bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1E0 "MAR132,Memory Attribute Register 132"
|
|
bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1E4 "MAR133,Memory Attribute Register 133"
|
|
bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1E8 "MAR134,Memory Attribute Register 134"
|
|
bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1EC "MAR135,Memory Attribute Register 135"
|
|
bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1F0 "MAR136,Memory Attribute Register 136"
|
|
bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1F4 "MAR137,Memory Attribute Register 137"
|
|
bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1F8 "MAR138,Memory Attribute Register 138"
|
|
bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1FC "MAR139,Memory Attribute Register 139"
|
|
bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x200 "MAR140,Memory Attribute Register 140"
|
|
bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x200 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x204 "MAR141,Memory Attribute Register 141"
|
|
bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x204 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x208 "MAR142,Memory Attribute Register 142"
|
|
bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x208 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x20C "MAR143,Memory Attribute Register 143"
|
|
bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x20C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x210 "MAR144,Memory Attribute Register 144"
|
|
bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x210 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x214 "MAR145,Memory Attribute Register 145"
|
|
bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x214 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x218 "MAR146,Memory Attribute Register 146"
|
|
bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x218 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x21C "MAR147,Memory Attribute Register 147"
|
|
bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x21C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x220 "MAR148,Memory Attribute Register 148"
|
|
bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x220 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x224 "MAR149,Memory Attribute Register 149"
|
|
bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x224 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x228 "MAR150,Memory Attribute Register 150"
|
|
bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x228 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x22C "MAR151,Memory Attribute Register 151"
|
|
bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x22C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x230 "MAR152,Memory Attribute Register 152"
|
|
bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x230 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x234 "MAR153,Memory Attribute Register 153"
|
|
bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x234 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x238 "MAR154,Memory Attribute Register 154"
|
|
bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x238 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x23C "MAR155,Memory Attribute Register 155"
|
|
bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x23C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x240 "MAR156,Memory Attribute Register 156"
|
|
bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x240 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x244 "MAR157,Memory Attribute Register 157"
|
|
bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x244 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x248 "MAR158,Memory Attribute Register 158"
|
|
bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x248 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x24C "MAR159,Memory Attribute Register 159"
|
|
bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x24C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x250 "MAR160,Memory Attribute Register 160"
|
|
bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x250 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x254 "MAR161,Memory Attribute Register 161"
|
|
bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x254 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x258 "MAR162,Memory Attribute Register 162"
|
|
bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x258 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x25C "MAR163,Memory Attribute Register 163"
|
|
bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x25C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x260 "MAR164,Memory Attribute Register 164"
|
|
bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x260 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x264 "MAR165,Memory Attribute Register 165"
|
|
bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x264 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x268 "MAR166,Memory Attribute Register 166"
|
|
bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x268 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x26C "MAR167,Memory Attribute Register 167"
|
|
bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x26C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x270 "MAR168,Memory Attribute Register 168"
|
|
bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x270 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x274 "MAR169,Memory Attribute Register 169"
|
|
bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x274 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x278 "MAR170,Memory Attribute Register 170"
|
|
bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x278 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x27C "MAR171,Memory Attribute Register 171"
|
|
bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x27C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x280 "MAR172,Memory Attribute Register 172"
|
|
bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x280 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x284 "MAR173,Memory Attribute Register 173"
|
|
bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x284 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x288 "MAR174,Memory Attribute Register 174"
|
|
bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x288 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x28C "MAR175,Memory Attribute Register 175"
|
|
bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x28C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x290 "MAR176,Memory Attribute Register 176"
|
|
bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x290 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x294 "MAR177,Memory Attribute Register 177"
|
|
bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x294 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x298 "MAR178,Memory Attribute Register 178"
|
|
bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x298 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x29C "MAR179,Memory Attribute Register 179"
|
|
bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x29C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2A0 "MAR180,Memory Attribute Register 180"
|
|
bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2A4 "MAR181,Memory Attribute Register 181"
|
|
bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2A8 "MAR182,Memory Attribute Register 182"
|
|
bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2AC "MAR183,Memory Attribute Register 183"
|
|
bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2B0 "MAR184,Memory Attribute Register 184"
|
|
bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2B4 "MAR185,Memory Attribute Register 185"
|
|
bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2B8 "MAR186,Memory Attribute Register 186"
|
|
bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2BC "MAR187,Memory Attribute Register 187"
|
|
bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C0 "MAR188,Memory Attribute Register 188"
|
|
bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C4 "MAR189,Memory Attribute Register 189"
|
|
bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C8 "MAR190,Memory Attribute Register 190"
|
|
bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2CC "MAR191,Memory Attribute Register 191"
|
|
bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2D0 "MAR192,Memory Attribute Register 192"
|
|
bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2D4 "MAR193,Memory Attribute Register 193"
|
|
bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2D8 "MAR194,Memory Attribute Register 194"
|
|
bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2DC "MAR195,Memory Attribute Register 195"
|
|
bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2E0 "MAR196,Memory Attribute Register 196"
|
|
bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2E4 "MAR197,Memory Attribute Register 197"
|
|
bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2E8 "MAR198,Memory Attribute Register 198"
|
|
bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2EC "MAR199,Memory Attribute Register 199"
|
|
bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2F0 "MAR200,Memory Attribute Register 200"
|
|
bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2F4 "MAR201,Memory Attribute Register 201"
|
|
bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2F8 "MAR202,Memory Attribute Register 202"
|
|
bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2FC "MAR203,Memory Attribute Register 203"
|
|
bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x300 "MAR204,Memory Attribute Register 204"
|
|
bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x300 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x304 "MAR205,Memory Attribute Register 205"
|
|
bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x304 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x308 "MAR206,Memory Attribute Register 206"
|
|
bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x308 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x30C "MAR207,Memory Attribute Register 207"
|
|
bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x30C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x310 "MAR208,Memory Attribute Register 208"
|
|
bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x310 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x314 "MAR209,Memory Attribute Register 209"
|
|
bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x314 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x318 "MAR210,Memory Attribute Register 210"
|
|
bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x318 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x31C "MAR211,Memory Attribute Register 211"
|
|
bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x31C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x320 "MAR212,Memory Attribute Register 212"
|
|
bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x320 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x324 "MAR213,Memory Attribute Register 213"
|
|
bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x324 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x328 "MAR214,Memory Attribute Register 214"
|
|
bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x328 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x32C "MAR215,Memory Attribute Register 215"
|
|
bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x32C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x330 "MAR216,Memory Attribute Register 216"
|
|
bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x330 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x334 "MAR217,Memory Attribute Register 217"
|
|
bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x334 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x338 "MAR218,Memory Attribute Register 218"
|
|
bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x338 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x33C "MAR219,Memory Attribute Register 219"
|
|
bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x33C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x340 "MAR220,Memory Attribute Register 220"
|
|
bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x340 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x344 "MAR221,Memory Attribute Register 221"
|
|
bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x344 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x348 "MAR222,Memory Attribute Register 222"
|
|
bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x348 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x34C "MAR223,Memory Attribute Register 223"
|
|
bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x34C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x350 "MAR224,Memory Attribute Register 224"
|
|
bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x350 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x354 "MAR225,Memory Attribute Register 225"
|
|
bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x354 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x358 "MAR226,Memory Attribute Register 226"
|
|
bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x358 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x35C "MAR227,Memory Attribute Register 227"
|
|
bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x35C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x360 "MAR228,Memory Attribute Register 228"
|
|
bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x360 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x364 "MAR229,Memory Attribute Register 229"
|
|
bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x364 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x368 "MAR230,Memory Attribute Register 230"
|
|
bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x368 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x36C "MAR231,Memory Attribute Register 231"
|
|
bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x36C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x370 "MAR232,Memory Attribute Register 232"
|
|
bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x370 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x374 "MAR233,Memory Attribute Register 233"
|
|
bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x374 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x378 "MAR234,Memory Attribute Register 234"
|
|
bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x378 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x37C "MAR235,Memory Attribute Register 235"
|
|
bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x37C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x380 "MAR236,Memory Attribute Register 236"
|
|
bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x380 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x384 "MAR237,Memory Attribute Register 237"
|
|
bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x384 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x388 "MAR238,Memory Attribute Register 238"
|
|
bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x388 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x38C "MAR239,Memory Attribute Register 239"
|
|
bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x38C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x390 "MAR240,Memory Attribute Register 240"
|
|
bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x390 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x394 "MAR241,Memory Attribute Register 241"
|
|
bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x394 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x398 "MAR242,Memory Attribute Register 242"
|
|
bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x398 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x39C "MAR243,Memory Attribute Register 243"
|
|
bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x39C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3A0 "MAR244,Memory Attribute Register 244"
|
|
bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3A4 "MAR245,Memory Attribute Register 245"
|
|
bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3A8 "MAR246,Memory Attribute Register 246"
|
|
bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3AC "MAR247,Memory Attribute Register 247"
|
|
bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3B0 "MAR248,Memory Attribute Register 248"
|
|
bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3B4 "MAR249,Memory Attribute Register 249"
|
|
bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3B8 "MAR250,Memory Attribute Register 250"
|
|
bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3BC "MAR251,Memory Attribute Register 251"
|
|
bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C0 "MAR252,Memory Attribute Register 252"
|
|
bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C4 "MAR253,Memory Attribute Register 253"
|
|
bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C8 "MAR254,Memory Attribute Register 254"
|
|
bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3CC "MAR255,Memory Attribute Register 255"
|
|
bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
tree.end
|
|
width 10.
|
|
base d:0x0184a000
|
|
tree "Memory Protection Page Attribute Registers"
|
|
group.long 0x200++0x7f
|
|
line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0"
|
|
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x0 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x0 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1"
|
|
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2"
|
|
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x8 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x8 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3"
|
|
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0xC 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0xC 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4"
|
|
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x10 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x10 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5"
|
|
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x14 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x14 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6"
|
|
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x18 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x18 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7"
|
|
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8"
|
|
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x20 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x20 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9"
|
|
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x24 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x24 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10"
|
|
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x28 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x28 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11"
|
|
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12"
|
|
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x30 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x30 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13"
|
|
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x34 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x34 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14"
|
|
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x38 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x38 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15"
|
|
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16"
|
|
bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x40 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x40 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x40 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x40 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x40 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x40 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x40 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x40 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x40 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x40 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x40 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17"
|
|
bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x44 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x44 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x44 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x44 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x44 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x44 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x44 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x44 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x44 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x44 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x44 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18"
|
|
bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x48 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x48 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x48 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x48 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x48 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x48 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x48 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x48 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x48 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x48 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x48 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19"
|
|
bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x4C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x4C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x4C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20"
|
|
bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x50 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x50 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x50 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x50 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x50 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x50 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x50 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x50 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x50 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x50 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x50 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21"
|
|
bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x54 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x54 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x54 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x54 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x54 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x54 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x54 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x54 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x54 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x54 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x54 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22"
|
|
bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x58 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x58 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x58 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x58 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x58 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x58 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x58 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x58 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x58 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x58 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x58 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23"
|
|
bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x5C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x5C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x5C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x5C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x5C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x5C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x5C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x5C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x5C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x5C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x5C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24"
|
|
bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x60 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x60 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x60 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x60 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x60 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x60 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x60 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x60 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x60 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x60 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x60 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25"
|
|
bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x64 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x64 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x64 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x64 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x64 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x64 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x64 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x64 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x64 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x64 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x64 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26"
|
|
bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x68 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x68 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x68 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x68 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x68 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x68 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x68 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x68 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x68 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x68 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x68 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27"
|
|
bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x6C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x6C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x6C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x6C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x6C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x6C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x6C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x6C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x6C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x6C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x6C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28"
|
|
bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x70 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x70 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x70 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x70 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x70 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x70 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x70 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x70 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x70 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x70 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x70 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29"
|
|
bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x74 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x74 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x74 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x74 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x74 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x74 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x74 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x74 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x74 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x74 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x74 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30"
|
|
bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x78 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x78 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x78 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x78 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x78 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x78 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x78 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x78 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x78 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x78 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x78 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31"
|
|
bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x7C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x7C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x7C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x7C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x7C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x7C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x7C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x7C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x7C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x7C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x7C 0. " UX ,User execute access type" "Normal,User"
|
|
tree.end
|
|
width 9.
|
|
rgroup.long 0x000++0x7 "Memory Protection Fault Registers"
|
|
line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " FA ,Fault Address"
|
|
line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register"
|
|
hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor"
|
|
bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor"
|
|
bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x04 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x04 1. " UW ,User write access type" "Normal,User"
|
|
group.long 0x008++0x3
|
|
line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register"
|
|
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear"
|
|
width 12.
|
|
wgroup.long 0x100++0xf "Memory Protection Lock Registers"
|
|
line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0"
|
|
hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0"
|
|
line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1"
|
|
hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32"
|
|
line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2"
|
|
hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64"
|
|
line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3"
|
|
hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96"
|
|
wgroup.long 0x110++0x3
|
|
line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register"
|
|
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
|
|
bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked"
|
|
bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register"
|
|
bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged"
|
|
AUTOINDENT.ON right tree
|
|
base d:0x01846000
|
|
rgroup.long 0x4++0x3 "Error Detection Registers"
|
|
line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register"
|
|
decmask.long.byte 0x0 16.--23. "BITPOS,Single Bit error position"
|
|
bitfld.long 0x0 8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value"
|
|
newline
|
|
bitfld.long 0x0 7. "VERR,Error occurred on L2 victims" "False,True"
|
|
bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
|
|
bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True"
|
|
newline
|
|
bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True"
|
|
bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True"
|
|
bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "L2EDCMD, L2 Error Detection Command Register"
|
|
bitfld.long 0x0 7. "VCLR,Clears the victim parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 4. "DCLR,Clears the data fetch parity error status" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
|
|
bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable"
|
|
bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "L2EDADDR,L2 Error Detection Address Register"
|
|
hexmask.long.long 0x0 5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)"
|
|
bitfld.long 0x0 8.--9. "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3"
|
|
bitfld.long 0x0 0. "RAM,Location where error was detected" "L2,RAM"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register"
|
|
hexmask.long.byte 0x0 0.--7. "CNT,Counter value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register"
|
|
hexmask.long.byte 0x0 0.--7. "CNT,Counter value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register"
|
|
bitfld.long 0x0 0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
|
|
AUTOINDENT.OFF
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "IDMA (Internal Direct Memory Access Controller)"
|
|
width 14.
|
|
base d:0x01820000
|
|
rgroup.long 0x00++0x3 "Channel 0"
|
|
line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register"
|
|
bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active"
|
|
group.long 0x04++0xf
|
|
line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register"
|
|
bitfld.long 0x00 31. " M31 ,Mask bit 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " M30 ,Mask bit 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " M29 ,Mask bit 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " M28 ,Mask bit 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " M27 ,Mask bit 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " M26 ,Mask bit 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " M25 ,Mask bit 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " M24 ,Mask bit 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " M23 ,Mask bit 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " M22 ,Mask bit 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " M21 ,Mask bit 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " M20 ,Mask bit 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " M19 ,Mask bit 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " M18 ,Mask bit 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " M17 ,Mask bit 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " M16 ,Mask bit 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " M15 ,Mask bit 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " M14 ,Mask bit 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " M13 ,Mask bit 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " M12 ,Mask bit 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " M11 ,Mask bit 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " M10 ,Mask bit 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " M9 ,Mask bit 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " M8 ,Mask bit 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " M7 ,Mask bit 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " M6 ,Mask bit 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " M5 ,Mask bit 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M4 ,Mask bit 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " M3 ,Mask bit 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " M2 ,Mask bit 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M1 ,Mask bit 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " M0 ,Mask bit 0" "Not masked,Masked"
|
|
line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register"
|
|
hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address"
|
|
line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register"
|
|
hexmask.long 0x08 5.--31. 0x20 " DESTADDR ,Destination address"
|
|
line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register"
|
|
bitfld.long 0x0c 28. " INT ,CPU interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0.--3. " COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rgroup.long 0x100++0x3 "Channel 1"
|
|
line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register"
|
|
bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active"
|
|
group.long 0x108++0xb
|
|
line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address"
|
|
line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register"
|
|
hexmask.long 0x04 2.--31. 0x4 " DESTADDR ,Destination address"
|
|
line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register"
|
|
bitfld.long 0x08 29.--31. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 28. " INT ,CPU interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " FILL ,Block fill" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Byte count"
|
|
width 0xb
|
|
tree.end
|
|
tree "XMC (Extended Memory Controller)"
|
|
width 14.
|
|
AUTOINDENT.ON right tree
|
|
base d:0x08000000
|
|
group.long 0x00++0x7F "XMC MPAX Segment Registers"
|
|
line.long 0x0 "XMPAXL0,MPAX segment 0 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x0 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x0 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x0 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x0 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x0 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x0 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x0 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x8 "XMPAXL1,MPAX segment 1 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x8 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x8 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x8 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x8 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x8 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x8 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x8 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x10 "XMPAXL2,MPAX segment 2 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x10 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x10 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x10 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x10 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x10 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x10 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x10 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x18 "XMPAXL3,MPAX segment 3 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x18 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x18 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x18 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x18 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x18 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x18 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x18 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x20 "XMPAXL4,MPAX segment 4 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x20 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x20 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x20 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x20 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x20 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x20 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x20 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x28 "XMPAXL5,MPAX segment 5 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x28 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x28 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x28 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x28 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x28 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x28 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x28 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x30 "XMPAXL6,MPAX segment 6 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x30 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x30 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x30 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x30 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x30 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x30 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x30 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x38 "XMPAXL7,MPAX segment 7 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x38 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x38 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x38 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x38 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x38 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x38 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x38 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x40 "XMPAXL8,MPAX segment 8 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x40 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x40 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x40 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x40 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x40 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x40 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x40 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x48 "XMPAXL9,MPAX segment 9 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x48 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x48 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x48 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x48 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x48 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x48 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x48 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x50 "XMPAXL10,MPAX segment 10 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x50 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x50 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x50 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x50 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x50 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x50 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x50 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x58 "XMPAXL11,MPAX segment 11 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x58 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x58 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x58 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x58 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x58 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x58 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x58 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x60 "XMPAXL12,MPAX segment 12 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x60 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x60 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x60 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x60 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x60 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x60 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x60 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x68 "XMPAXL13,MPAX segment 13 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x68 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x68 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x68 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x68 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x68 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x68 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x68 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x70 "XMPAXL14,MPAX segment 14 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x70 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x70 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x70 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x70 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x70 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x70 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x70 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x78 "XMPAXL15,MPAX segment 15 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x78 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x78 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x78 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x78 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x78 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x78 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x78 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
textline ""
|
|
rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers"
|
|
line.long 0. "XMPFAR,Memory Protection Fault Address Register"
|
|
hexmask.long 0x0 0.--31. "Fault Address,Fault Address"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0. "XMPFSR,Memory Protection Fault Status Register"
|
|
bitfld.long 0. 8. "LOCAL,Access was a LOCAL access" "False,True"
|
|
bitfld.long 0. 5. "SR,When set, indicates a supervisor read request" "False,True"
|
|
bitfld.long 0. 4. "SW,When set, indicates a supervisor write request" "False,True"
|
|
bitfld.long 0. 3. "SX,When set, indicates a supervisor program fetch request" "False,True"
|
|
bitfld.long 0. 2. "UR,When set, indicates a user read request" "False,True"
|
|
bitfld.long 0. 1. "UW,When set, indicates a user write request" "False,True"
|
|
bitfld.long 0. 0. "UX,When set, indicates a user program fetch request" "False,True"
|
|
group.long 0x208++0x3
|
|
line.long 0. "XMPFCR,Memory Protection Fault Clear Register"
|
|
bitfld.long 0. 0. "MPFCLR,Clear fault" "No effect,Clear"
|
|
group.long 0x280++0x3 "Prefetch Priority Register"
|
|
line.long 0. "MDMAARBX,MDMA Arbitration Priority Register"
|
|
bitfld.long 0. 16.--18. "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)"
|
|
rgroup.long 0x300++0x3 "Prefetch Buffer Registers"
|
|
line.long 0. "XPFCMD,Prefetch Command Register"
|
|
bitfld.long 0. 4. "ACRST,Analysis Counter Reset" "No effect,Reset"
|
|
hexmask.long.byte 0. 2.--3. "ACEN,Analysis Counter Enable"
|
|
bitfld.long 0. 1. "ACENL,Analysis Counter ENable (ACEN) Load" "False,True"
|
|
bitfld.long 0. 0. "INV,Invalidate prefetch buffer contents" "No effect,Invalidate"
|
|
rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers"
|
|
line.long 0. "XPFACS,Prefetch Analysis Counter Status"
|
|
rgroup.long 0x310++0xF
|
|
line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0"
|
|
line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1"
|
|
line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2"
|
|
line.long 0xC "XPFAC3,Prefetch Analysis Counter 3"
|
|
rgroup.long 0x400++0x1F
|
|
line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0"
|
|
line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1"
|
|
line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2"
|
|
line.long 0xC "XPFADDR3,Prefetch Address for Slot 3"
|
|
line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4"
|
|
line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5"
|
|
line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6"
|
|
line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7"
|
|
AUTOINDENT.OFF
|
|
width 0xb
|
|
tree.end
|
|
tree "Bandwith Management"
|
|
width 13.
|
|
base d:0x01841000
|
|
group.long 0x40++0xf "L1D"
|
|
line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register"
|
|
bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register"
|
|
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register"
|
|
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register"
|
|
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
width 13.
|
|
group.long 0x00++0xf "L2"
|
|
line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register"
|
|
bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register"
|
|
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register"
|
|
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register"
|
|
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
width 13.
|
|
base d:0x01820000
|
|
group.long 0x200++0xf "EMC"
|
|
line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register"
|
|
bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register"
|
|
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register"
|
|
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register"
|
|
bitfld.long 0x0c 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
width 0xb
|
|
tree.end
|
|
tree "Interrupt Controller"
|
|
width 11.
|
|
base d:0x01800000
|
|
group.long 0x00++0xf
|
|
line.long 0x00 "EVTFLAG0,Event Flag Register 0"
|
|
setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr ,State of event EVT14" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 13. 0x20 13. 0x40 13. " EF13_set/clr ,State of event EVT13" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr ,State of event EVT12" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 11. 0x20 11. 0x40 11. " EF11_set/clr ,State of event EVT11" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr ,State of event EVT9" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 8. 0x20 8. 0x40 8. " EF8_set/clr ,State of event EVT8" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr ,State of event EVT7" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 6. 0x20 6. 0x40 6. " EF6_set/clr ,State of event EVT6" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr ,State of event EVT5" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x20 4. 0x40 4. " EF4_set/clr ,State of event EVT4" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr ,State of event EVT3" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x20 2. 0x40 2. " EF2_set/clr ,State of event EVT2" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr ,State of event EVT1" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x20 0. 0x40 0. " EF0_set/clr ,State of event EVT0" "Not occurred,Occurred"
|
|
line.long 0x04 "EVTFLAG1,Event Flag Register 1"
|
|
setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr ,State of event EVT60" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 27. 0x24 27. 0x44 27. " EF59_set/clr ,State of event EVT59" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr ,State of event EVT56" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 23. 0x24 23. 0x44 23. " EF55_set/clr ,State of event EVT55" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr ,State of event EVT54" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 21. 0x24 21. 0x44 21. " EF53_set/clr ,State of event EVT53" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr ,State of event EVT51" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 18. 0x24 18. 0x44 18. " EF50_set/clr ,State of event EVT50" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr ,State of event EVT49" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 16. 0x24 16. 0x44 16. " EF48_set/clr ,State of event EVT48" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr ,State of event EVT47" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 11. 0x24 11. 0x44 11. " EF43_set/clr ,State of event EVT43" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr ,State of event EVT41" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 8. 0x24 8. 0x44 8. " EF40_set/clr ,State of event EVT40" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr ,State of event EVT39" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 6. 0x24 6. 0x44 6. " EF38_set/clr ,State of event EVT38" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr ,State of event EVT37" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 4. 0x24 4. 0x44 4. " EF36_set/clr ,State of event EVT36" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr ,State of event EVT35" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 2. 0x24 2. 0x44 2. " EF34_set/clr ,State of event EVT34" "Not occurred,Occurred"
|
|
line.long 0x08 "EVTFLAG2,Event Flag Register 2"
|
|
setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr ,State of event EVT85" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 20. 0x28 20. 0x48 20. " EF84_set/clr ,State of event EVT84" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr ,State of event EVT83" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 18. 0x28 18. 0x48 18. " EF82_set/clr ,State of event EVT82" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr ,State of event EVT81" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 16. 0x28 16. 0x48 16. " EF80_set/clr ,State of event EVT80" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr ,State of event EVT78" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 13. 0x28 13. 0x48 13. " EF77_set/clr ,State of event EVT77" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr ,State of event EVT76" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 11. 0x28 11. 0x48 11. " EF75_set/clr ,State of event EVT75" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr ,State of event EVT74" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 9. 0x28 9. 0x48 9. " EF73_set/clr ,State of event EVT73" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr ,State of event EVT72" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 7. 0x28 7. 0x48 7. " EF71_set/clr ,State of event EVT71" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr ,State of event EVT70" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 5. 0x28 5. 0x48 5. " EF69_set/clr ,State of event EVT69" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr ,State of event EVT68" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 3. 0x28 3. 0x48 3. " EF67_set/clr ,State of event EVT67" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr ,State of event EVT66" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 1. 0x28 1. 0x48 1. " EF65_set/clr ,State of event EVT65" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr ,State of event EVT64" "Not occurred,Occurred"
|
|
line.long 0x0c "EVTFLAG3,Event Flag Register 3"
|
|
setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. " EF126_set/clr ,State of event EVT126" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. " EF124_set/clr ,State of event EVT124" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. " EF122_set/clr ,State of event EVT122" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. " EF120_set/clr ,State of event EVT120" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. " EF118_set/clr ,State of event EVT118" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. " EF116_set/clr ,State of event EVT116" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. " EF97_set/clr ,State of event EVT97" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr ,State of event EVT96" "Not occurred,Occurred"
|
|
width 11.
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "EVTMASK0,Event Mask Register 0"
|
|
bitfld.long 0x00 14. " EM14 ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 13. " EM13 ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 12. " EM12 ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EM11 ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 9. " EM9 ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 8. " EM8 ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EM7 ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 6. " EM6 ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 5. " EM5 ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EM4 ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 3. " EM3 ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 2. " EM2 ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 0. " EM0 ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled"
|
|
line.long 0x04 "EVTMASK1,Event Mask Register 1"
|
|
bitfld.long 0x04 28. " EM60 ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 27. " EM59 ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 24. " EM56 ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " EM55 ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 22. " EM54 ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 21. " EM53 ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EM51 ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 18. " EM50 ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 17. " EM49 ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " EM48 ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 15. " EM47 ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 11. " EM43 ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EM41 ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 8. " EM40 ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 7. " EM39 ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EM38 ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 5. " EM37 ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 4. " EM36 ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EM35 ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 2. " EM34 ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled"
|
|
line.long 0x08 "EVTMASK2,Event Mask Register 2"
|
|
bitfld.long 0x08 21. " EM85 ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 20. " EM84 ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 19. " EM83 ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " EM82 ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 17. " EM81 ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 16. " EM80 ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " EM78 ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 13. " EM77 ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 12. " EM76 ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " EM75 ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 10. " EM74 ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 9. " EM73 ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " EM72 ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 7. " EM71 ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 6. " EM70 ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " EM69 ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 4. " EM68 ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 3. " EM67 ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EM66 ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 1. " EM65 ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 0. " EM64 ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled"
|
|
line.long 0x0c "EVTMASK3,Event Mask Register 3"
|
|
bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 30. " EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 29. " EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 27. " EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 26. " EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 24. " EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 23. " EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 21. " EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 20. " EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 1. " EM97 ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 0. " EM96 ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled"
|
|
group.long 0xc0++0xf
|
|
line.long 0x00 "EXPMASK0,Exception Mask Register 0"
|
|
bitfld.long 0x00 14. " XM14 ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 13. " XM13 ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 12. " XM12 ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XM11 ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 9. " XM9 ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 8. " XM8 ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XM7 ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 6. " XM6 ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 5. " XM5 ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XM4 ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 3. " XM3 ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 2. " XM2 ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XM1 ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 0. " XM0 ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
line.long 0x04 "EXPMASK1,Exception Mask Register 1"
|
|
bitfld.long 0x04 28. " XM60 ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 27. " XM59 ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 24. " XM56 ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " XM55 ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 22. " XM54 ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 21. " XM53 ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " XM51 ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 18. " XM50 ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 17. " XM49 ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " XM48 ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 15. " XM47 ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 11. " XM43 ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XM41 ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 8. " XM40 ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 7. " XM39 ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " XM38 ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 5. " XM37 ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 4. " XM36 ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XM35 ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 2. " XM34 ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
line.long 0x08 "EXPMASK2,Exception Mask Register 2"
|
|
bitfld.long 0x08 21. " XM85 ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 20. " XM84 ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 19. " XM83 ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " XM82 ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 17. " XM81 ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 16. " XM80 ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " XM78 ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 13. " XM77 ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 12. " XM76 ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XM75 ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 10. " XM74 ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 9. " XM73 ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XM72 ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 7. " XM71 ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 6. " XM70 ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XM69 ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 4. " XM68 ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 3. " XM67 ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " XM66 ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 1. " XM65 ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 0. " XM64 ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
line.long 0x0c "EXPMASK3,Exception Mask Register 3"
|
|
bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 30. " XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 29. " XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 27. " XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 26. " XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 24. " XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 23. " XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 21. " XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 20. " XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 1. " XM97 ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 0. " XM96 ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
width 11.
|
|
rgroup.long 0xa0++0xf
|
|
line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MEF[31:0] ,Displays content of EF when EM=0"
|
|
line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1"
|
|
hexmask.long 0x04 0.--31. 1. " MEF[63:32] ,Displays content of EF when EM=0"
|
|
line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2"
|
|
hexmask.long 0x08 0.--31. 1. " MEF[95:64] ,Displays content of EF when EM=0"
|
|
line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3"
|
|
hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0"
|
|
rgroup.long 0xe0++0xf
|
|
line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0"
|
|
line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1"
|
|
line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2"
|
|
line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3"
|
|
width 11.
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "INTMUX1,Interrupt Mux Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " INTSEL7 ,Number of the event that maps to CPUINT7"
|
|
hexmask.long.byte 0x00 16.--22. 1. " INTSEL6 ,Number of the event that maps to CPUINT6"
|
|
hexmask.long.byte 0x00 8.--14. 1. " INTSEL5 ,Number of the event that maps to CPUINT5"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INTSEL4 ,Number of the event that maps to CPUINT4"
|
|
line.long 0x04 "INTMUX2,Interrupt Mux Register 2"
|
|
hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11"
|
|
hexmask.long.byte 0x04 16.--22. 1. " INTSEL10 ,Number of the event that maps to CPUINT10"
|
|
hexmask.long.byte 0x04 8.--14. 1. " INTSEL9 ,Number of the event that maps to CPUINT9"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INTSEL8 ,Number of the event that maps to CPUINT8"
|
|
line.long 0x08 "INTMUX3,Interrupt Mux Register 3"
|
|
hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15"
|
|
hexmask.long.byte 0x08 16.--22. 1. " INTSEL14 ,Number of the event that maps to CPUINT14"
|
|
hexmask.long.byte 0x08 8.--14. 1. " INTSEL13 ,Number of the event that maps to CPUINT13"
|
|
hexmask.long.byte 0x08 0.--6. 1. " INTSEL12 ,Number of the event that maps to CPUINT12"
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x00 "INTXSTAT,Interrupt Exception Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYSINT ,System Event number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUINT ,CPU interrupt number"
|
|
bitfld.long 0x00 0. " DROP ,Dropped event flag" "No event dropped,Event dropped"
|
|
width 11.
|
|
wgroup.long 0x184++0x3
|
|
line.long 0x00 "INTXCLR,Interrupt Exception Clear Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register"
|
|
bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 14. " IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 13. " IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 11. " IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 10. " IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDM9 ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 8. " IDM8 ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 7. " IDM7 ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDM6 ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 5. " IDM5 ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 4. " IDM4 ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
width 11.
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers"
|
|
hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " AEGSEL2 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x00 8.--15. 1. " AEGSEL1 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEGSEL0 ,Advanced Event Generator Select"
|
|
line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers"
|
|
hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x04 16.--23. 1. " AEGSEL6 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x04 8.--15. 1. " AEGSEL5 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x04 0.--7. 1. " AEGSEL4 ,Advanced Event Generator Select"
|
|
width 0xb
|
|
tree.end
|
|
tree "Power-Down Controller"
|
|
width 8.
|
|
base d:0x01810000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PDCCMD,Power-Down Controller Command Register"
|
|
bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
endif
|
|
AUTOINDENT.ON center tree
|
|
tree.open "ARM_Cortex_A15_Subsystem"
|
|
tree "ARM_VBUSP"
|
|
base ad:0x1E80000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "ARM_PID,"
|
|
line.long 0x04 "ARM_INTC_PID,"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STM_DISABLE,"
|
|
group.long 0x400++0x0B
|
|
line.long 0x00 "PD_CPU0_PTCMD,"
|
|
bitfld.long 0x00 0. "GO_CPU,CPU power domain GO transition" "0,1"
|
|
line.long 0x04 "PD_CPU0_PDSTAT,"
|
|
bitfld.long 0x04 16.--18. "DOMAIN_STATE,Shows CPU power domain ACTUAL state" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--1. "NEXT_CPU,Shows programmed CPU power domain NEXT state" "0,1,2,3"
|
|
line.long 0x08 "PD_CPU0_PDCTL,"
|
|
bitfld.long 0x08 0.--1. "NEXT_CPU,CPU power domain NEXT state" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AXI2VBUS_MASTER"
|
|
base ad:0x1000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "AXI2VBUS_PID,"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AXI2VBUS_CMD_PRI,"
|
|
bitfld.long 0x00 0.--2. "PRI,Set priority of the command" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "AXI2VBUS_CPU0_END,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "BOOT_CFG"
|
|
base ad:0x2620000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "BOOTCFG_REVISION,"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BOOTCFG_JTAGID,"
|
|
bitfld.long 0x00 28.--31. "VARIANT,Variant value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "PARTNUMBER,Part number for boundary scan"
|
|
newline
|
|
hexmask.long.word 0x00 1.--11. 1. "MANUFACTURER,Indicates manufacturer"
|
|
newline
|
|
bitfld.long 0x00 0. "LSB," "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BOOTCFG_DEVSTAT,"
|
|
bitfld.long 0x00 20. "NODDR,MSMC to EMIF control" "EMIF enabled MSMC sends external traffic to..,EMIF disabled MSMC will re-direct DDR traffic.."
|
|
newline
|
|
bitfld.long 0x00 19. "MAINPLL_ODSEL,Main PLL OUTPUT_DIVIDE (OD) selection for the Boot ROM code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "AVSIFSEL,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 1.--16. 1. "BOOTMODE,Boot mode selection"
|
|
newline
|
|
rbitfld.long 0x00 0. "LENDIAN,Device Endian Mode" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BOOTCFG_DSP_BOOT_ADDR0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "ISTP_RST_VAL,DSP istp_rst_val[21:0] port value"
|
|
group.long 0xE0++0x1F
|
|
line.long 0x00 "BOOTCFG_INTR_RAW_STAT_SET,"
|
|
bitfld.long 0x00 1. "ADDR_ERR,Addressing violation error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PROT_ERR,Protection violation error" "0,1"
|
|
line.long 0x04 "BOOTCFG_INTR_ENABLED_STAT_CLR,"
|
|
bitfld.long 0x04 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
|
|
line.long 0x08 "BOOTCFG_INTR_ENABLE,"
|
|
bitfld.long 0x08 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
|
|
line.long 0x0C "BOOTCFG_INTR_ENABLE_CLR,"
|
|
bitfld.long 0x0C 1. "ADDR_ERR_EN_CLR,Addressing violation error enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "PROT_ERR_EN_CLR,Protection violation error enable" "0,1"
|
|
line.long 0x10 "BOOTCFG_EOI,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value"
|
|
line.long 0x14 "BOOTCFG_FAULT_ADDR,"
|
|
line.long 0x18 "BOOTCFG_FAULT_STAT,"
|
|
hexmask.long.byte 0x18 24.--31. 1. "BOOTCFG_TXNID,Transaction ID associated with the fault access"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--23. 1. "BOOTCFG_MSTID,Master ID associated with the fault access"
|
|
newline
|
|
bitfld.long 0x18 9.--12. "BOOTCFG_PRIVID,Privilege ID associated with the fault access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 0.--5. "FAULT_TYPE,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?..."
|
|
line.long 0x1C "BOOTCFG_FAULT_CLR,"
|
|
bitfld.long 0x1C 0. "FAULT_CLR,Fault clear" "0,1"
|
|
rgroup.long 0x110++0x07
|
|
line.long 0x00 "BOOTCFG_MACID0,"
|
|
line.long 0x04 "BOOTCFG_MACID1,"
|
|
bitfld.long 0x04 17. "FLOW,MAC Flow Control" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "BCAST,Default m/b-cast reception" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "MACID,MAC ID upper 16 bits"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BOOTCFG_PCIEVENDORID,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCIEDEVICEID,PCIe Device ID"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "PCIEVENDORID,TI Vendor ID"
|
|
group.long 0x130++0x07
|
|
line.long 0x00 "BOOTCFG_LRSTNMISTAT_CLR,"
|
|
bitfld.long 0x00 8. "NMI_STAT_0_CLR,C66x core 0 NMI pin clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LRESET_STAT_0_CLR,C66x core 0 local reset pin clear" "0,1"
|
|
line.long 0x04 "BOOTCFG_RESET_STAT_CLR,"
|
|
bitfld.long 0x04 31. "GRST_STAT_CLR,Global reset clear" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "LRST_STAT_0_CLR,C66x core 0 local reset clear" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BOOTCFG_BOOT_COMPLETE,"
|
|
bitfld.long 0x00 8. "ARM0_COMPLETE,A15 core 0 ROM boot status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DSP0_COMPLETE,C66x core 0 ROM boot status" "0,1"
|
|
rgroup.long 0x144++0x17
|
|
line.long 0x00 "BOOTCFG_RESET_STAT,"
|
|
bitfld.long 0x00 31. "GRST_STAT,Global reset status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LRST_STAT0,C66x core 0 local reset status" "0,1"
|
|
line.long 0x04 "BOOTCFG_LRSTNMISTAT,"
|
|
bitfld.long 0x04 8. "NMI_STAT,C66x core 0 NMI pin status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "LRESET_STAT,C66x core 0 local reset pin status" "0,1"
|
|
line.long 0x08 "BOOTCFG_DEVCFG,"
|
|
bitfld.long 0x08 1.--2. "PCIE_DEV_TYPE,PCIE device type" "Endpoint mode,Legacy Endpoint mode,Rootcomplex mode,?..."
|
|
newline
|
|
bitfld.long 0x08 0. "SYSCLKOUTEN,SYSCLKOUT enable" "0,1"
|
|
line.long 0x0C "BOOTCFG_PWR_STATE,"
|
|
hexmask.long 0x0C 4.--31. 1. "PWR_STATE_GENERAL,General purpose register allocated for software usage"
|
|
newline
|
|
bitfld.long 0x0C 3. "PMMC_FW_LOAD,Indicates whether PMMC firmware is loaded by host processor (A15 or DSP) or not" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--2. "PWR_MODE,Indicates device power mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "BOOTCFG_INITIATOR_PRIORITY0,"
|
|
bitfld.long 0x10 28.--30. "ICSS1_PRU1_PRI,ICSS1 PRU1 master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 24.--26. "ICSS1_PRU0_PRI,ICSS1 PRU0 master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 20.--22. "ICSS0_PRU1_PRI,ICSS0 PRU1 master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 16.--18. "ICSS0_PRU0_PRI,ICSS0 PRU0 master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 12.--14. "MMC1_PRI,MMC1 master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 8.--10. "MMC0_PRI,MMC0 master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 4.--6. "MLB_PRI,MLB master port priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "PMMC_PRI,PMMC master port priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "BOOTCFG_INITIATOR_PRIORITY1,"
|
|
bitfld.long 0x14 4.--6. "DSS_PRI_HI,DSS master port priority for high priority access (when MFLAG = 1)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "DSS_PRI_LO,DSS master port priority for low priority access (when MFLAG = 0)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "BOOTCFG_NMIGR0,"
|
|
bitfld.long 0x00 0. "NMIGR0_REG,Reads return 0" "0,1"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "BOOTCFG_IPCGR0,"
|
|
hexmask.long 0x00 4.--31. 1. "IPCGR0_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x00 0. "IPCGR0_REG,Reads return 0" "0,1"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "BOOTCFG_IPCGR8,"
|
|
hexmask.long 0x00 4.--31. 1. "IPCGR8_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x00 0. "IPCGR8_REG,Reads return 0" "0,1"
|
|
group.long 0x26C++0x17
|
|
line.long 0x00 "BOOTCFG_IPCGR11,"
|
|
hexmask.long 0x00 4.--31. 1. "IPCGR11_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x00 0. "IPCGR11_REG,Reads return 0" "0,1"
|
|
line.long 0x04 "BOOTCFG_IPCGR12,"
|
|
hexmask.long 0x04 4.--31. 1. "IPCGR12_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x04 0. "IPCGR12_REG,Reads return 0" "0,1"
|
|
line.long 0x08 "BOOTCFG_IPCGR13,"
|
|
hexmask.long 0x08 4.--31. 1. "IPCGR13_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x08 0. "IPCGR13_REG,Reads return 0" "0,1"
|
|
line.long 0x0C "BOOTCFG_IPCGR14,"
|
|
hexmask.long 0x0C 4.--31. 1. "IPCGR14_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x0C 0. "IPCGR14_REG,Reads return 0" "0,1"
|
|
line.long 0x10 "BOOTCFG_IPCGRH,"
|
|
hexmask.long 0x10 4.--31. 1. "IPCGRH_SRC,Reads return current value of internal register bit"
|
|
newline
|
|
bitfld.long 0x10 0. "IPCGRH_REG,Reads return 0" "0,1"
|
|
line.long 0x14 "BOOTCFG_IPCAR0,"
|
|
hexmask.long 0x14 4.--31. 1. "IPCGR0_SRC_CLR,Reads return current value of internal register bit"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "BOOTCFG_IPCAR8,"
|
|
hexmask.long 0x00 4.--31. 1. "IPCGR8_SRC_CLR,Reads return current value of internal register bit"
|
|
group.long 0x2AC++0x13
|
|
line.long 0x00 "BOOTCFG_IPCAR11,"
|
|
hexmask.long 0x00 4.--31. 1. "IPCGR11_SRC_CLR,Reads return current value of internal register bit"
|
|
line.long 0x04 "BOOTCFG_IPCAR12,"
|
|
hexmask.long 0x04 4.--31. 1. "IPCGR12_SRC_CLR,Reads return current value of internal register bit"
|
|
line.long 0x08 "BOOTCFG_IPCAR13,"
|
|
hexmask.long 0x08 4.--31. 1. "IPCGR13_SRC_CLR,Reads return current value of internal register bit"
|
|
line.long 0x0C "BOOTCFG_IPCAR14,"
|
|
hexmask.long 0x0C 4.--31. 1. "IPCGR14_SRC_CLR,Reads return current value of internal register bit"
|
|
line.long 0x10 "BOOTCFG_IPCARH,"
|
|
hexmask.long 0x10 4.--31. 1. "IPCGRH_SRC_CLR,Reads return current value of internal register bit"
|
|
group.long 0x2D8++0x07
|
|
line.long 0x00 "BOOTCFG_TINPSEL0,"
|
|
bitfld.long 0x00 28.--30. "TINPHSEL3,Input select for TIMER_3 high" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "TINPLSEL3,Input select for TIMER_3 low" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "TINPHSEL2,Input select for TIMER_2 high" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TINPLSEL2,Input select for TIMER_2 low" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "TINPHSEL1,Input select for TIMER_1 high" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TINPLSEL1,Input select for TIMER_1 low" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TINPHSEL0,Input select for TIMER_0 high" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TINPLSEL0,Input select for TIMER_0 low" "TIMI0,TIMI1,?..."
|
|
line.long 0x04 "BOOTCFG_TINPSEL1,"
|
|
bitfld.long 0x04 12.--14. "TINPHSEL5,Input select for TIMER_5 high" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--10. "TINPLSEL5,Input select for TIMER_5 low" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--6. "TINPHSEL4,Input select for TIMER_4 high" "TIMI0,TIMI1,?..."
|
|
newline
|
|
bitfld.long 0x04 0.--2. "TINPLSEL4,Input select for TIMER_4 low" "TIMI0,TIMI1,?..."
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "BOOTCFG_TOUTPSEL0,"
|
|
bitfld.long 0x00 8.--13. "TOUTPSEL1,Output select for TIMO1" "TOUTL0,TOUTH0,TOUTL1,TOUTH1,TOUTL2,TOUTH2,TOUTL3,TOUTH3,TOUTL4,TOUTH4,TOUTL5,TOUTH5,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "TOUTPSEL0,Output select for TIMO0" "TOUTL0,TOUTH0,TOUTL1,TOUTH1,TOUTL2,TOUTH2,TOUTL3,TOUTH3,TOUTL4,TOUTH4,TOUTL5,TOUTH5,?..."
|
|
group.long 0x350++0x17
|
|
line.long 0x00 "BOOTCFG_MAIN_PLL_CTL0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--18. 1. "PLLM,7-bit MSB of a 13-bit PLLM field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "BOOTCFG_MAIN_PLL_CTL1,"
|
|
bitfld.long 0x04 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLLoperation" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "BOOTCFG_NSS_PLL_CTL0,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
bitfld.long 0x08 23. "BYPASS,Enable bypass mode" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19.--22. "CLKOD,PLL output divider (post VCO) supported value = 1 (i.e. divide-by-2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x08 6.--18. 1. "PLLM,A 13-bit field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "BOOTCFG_NSS_PLL_CTL1,"
|
|
bitfld.long 0x0C 14. "PLLRST,PLL reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLL operation" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "BOOTCFG_DDR3A_PLL_CTL0,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
bitfld.long 0x10 23. "BYPASS,Enable bypass mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19.--22. "CLKOD,PLL output divider (post VCO) supported value = 1 (i.e. divide-by-2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 6.--18. 1. "PLLM,A 13-bit field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x10 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "BOOTCFG_DDR3A_PLL_CTL1,"
|
|
bitfld.long 0x14 31. "DDR3A_PHY_RST,DDR3 PHY reset controlFor more information see" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "PLLRST,PLL reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLL operation" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x370++0x07
|
|
line.long 0x00 "BOOTCFG_ARM_PLL_CTL0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
bitfld.long 0x00 23. "BYPASS,Enable bypass mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "CLKOD,PLL output divider (post VCO) supported value = 1 (i.e. divide-by-2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 6.--18. 1. "PLLM,A 13-bit field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "BOOTCFG_ARM_PLL_CTL1,"
|
|
bitfld.long 0x04 14. "PLLRST,PLL reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLL operation" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x380++0x17
|
|
line.long 0x00 "BOOTCFG_DSS_PLL_CTL0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
bitfld.long 0x00 23. "BYPASS,Enable bypass mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "CLKOD,PLL output divider (post VCO) supported value = 1 (i.e. divide-by-2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 6.--18. 1. "PLLM,A 13-bit field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "BOOTCFG_DSS_PLL_CTL1,"
|
|
bitfld.long 0x04 14. "PLLRST,PLL reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLL operation" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "BOOTCFG_ICSS_PLL_CTL0,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
bitfld.long 0x08 23. "BYPASS,Enable bypass mode" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19.--22. "CLKOD,PLL output divider (post VCO) supported value = 1 (i.e. divide-by-2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x08 6.--18. 1. "PLLM,A 13-bit field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "BOOTCFG_ICSS_PLL_CTL1,"
|
|
bitfld.long 0x0C 14. "PLLRST,PLL reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLL operation" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "BOOTCFG_UART_PLL_CTL0,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BWADJ,8-bit LSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment"
|
|
newline
|
|
bitfld.long 0x10 23. "BYPASS,Enable bypass mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19.--22. "CLKOD,PLL output divider (post VCO) supported value = 1 (i.e. divide-by-2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 6.--18. 1. "PLLM,A 13-bit field that selects the values for the multiplication factor"
|
|
newline
|
|
bitfld.long 0x10 0.--5. "PLLD,A 6-bit field that selects the values for the reference divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "BOOTCFG_UART_PLL_CTL1,"
|
|
bitfld.long 0x14 14. "PLLRST,PLL reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "ENSAT,Enables saturation behavior needs to be set to 1 for proper PLL operation" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--3. "BWADJ,4-bit MSB of a 12-bit BWADJ field that selects the values for the loop bandwidth adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x690++0x1F
|
|
line.long 0x00 "BOOTCFG_DDR_CLKCTL,"
|
|
bitfld.long 0x00 0. "DDR_CLK_MUXSEL,DDR PLL Reference Clock Source" "Select HF Oscillator (when SYSCLKSEL pin is low)..,Select external DDR_CLK_P/N input"
|
|
line.long 0x04 "BOOTCFG_ICSS_CLKCTL,"
|
|
bitfld.long 0x04 8. "ICSS1_PLL_MUXSEL,ICSS1 Core Clock Source" "Selects ICSS PLL output,Selects NSS PLL output"
|
|
newline
|
|
bitfld.long 0x04 0. "ICSS0_PLL_MUXSEL,ICSS0 Core Clock Source" "Selects ICSS PLL output,Selects NSS PLL output"
|
|
line.long 0x08 "BOOTCFG_ETHERNET_CLKCTL,"
|
|
bitfld.long 0x08 2. "RMII_MII_CLKOUT_EN,BOOTROM code will set this bit based on the BOOTMODE selection" "CLKOUT pin is disabled,CLKOUT pin is enabled"
|
|
newline
|
|
bitfld.long 0x08 1. "RMII_MII_CLKSEL,BOOTROM code will set this bit based on the BOOTMODE selection" "RMII_CLK will drive the CLKOUT pin,MII_CLK will drive the CLKOUT pin"
|
|
line.long 0x0C "BOOTCFG_USB0_CLKCTL,"
|
|
bitfld.long 0x0C 8.--12. "USB0_CLKCORE_DIV,USB0 Core Clock Divider Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 1. "USB0_CLKCORE_LOAD_DIV,USB0 Core Clock Load Divider Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "USB0_CLKCORE_SEL,USB0 Core Clock Source" "0,1"
|
|
line.long 0x10 "BOOTCFG_USB1_CLKCTL,"
|
|
bitfld.long 0x10 8.--12. "USB1_CLKCORE_DIV,USB1 Core Clock Divider Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x10 1. "USB1_CLKCORE_LOAD_DIV,USB1 Core Clock Load Divider Control" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "USB1_CLKCORE_SEL,USB1 Core Clock Source" "0,1"
|
|
line.long 0x14 "BOOTCFG_SERIALPORT_CLKCTL,"
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bitfld.long 0x14 12.--14. "MCBSP_CLKS_SEL,McBSP CLKS Source Selection" "AUDIO_OSCCLK,MLB_IO_CLK,MLBP_IO_CLK,SYS_OSCCLK,XREFCLK (external pin),UART_PLL/4 All others are reserved,?..."
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bitfld.long 0x14 8.--10. "MCASP2_AUXCLK_SEL,McASP2 AUXCLK Source Selection" "AUDIO_OSCCLK,MLB_IO_CLK,MLBP_IO_CLK,SYS_OSCCLK,XREFCLK (external pin),UART_PLL/4 All others are reserved,?..."
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bitfld.long 0x14 4.--6. "MCASP1_AUXCLK_SEL,McASP1 AUXCLK Source Selection" "AUDIO_OSCCLK,MLB_IO_CLK,MLBP_IO_CLK,SYS_OSCCLK,XREFCLK (external pin),UART_PLL/4 All others are reserved,?..."
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bitfld.long 0x14 0.--2. "MCASP0_AUXCLK_SEL,McASP0 AUXCLK Source Selection" "AUDIO_OSCCLK,MLB_IO_CLK,MLBP_IO_CLK,SYS_OSCCLK,XREFCLK (external pin),UART_PLL/4 All others are reserved,?..."
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line.long 0x18 "BOOTCFG_OSC_CTL,"
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bitfld.long 0x18 11. "AUDIOOSC_GZ,Audio Oscillator enable control0 - Audio Oscillator is enabled1 - Audio Oscillator is disabled" "0,1"
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bitfld.long 0x18 10. "AUDIOOSC_SW2,Selects the frequency range of the Audio oscillator SW2:SW1 control bits" "0,1"
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bitfld.long 0x18 9. "AUDIOOSC_SW1,Selects the frequency range of the Audio oscillator SW2:SW1 control bits" "0,1"
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bitfld.long 0x18 8. "AUDIOOSC_RES_SEL,Audio Oscillator Resistor" "0,1"
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newline
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bitfld.long 0x18 1. "SYSOSC_GZ,System Oscillator enable control0 - System Oscillator is enabled1 - System Oscillator is disabled" "0,1"
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bitfld.long 0x18 0. "SYSOSC_RES_SEL,System Oscillator Resistor" "0,1"
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line.long 0x1C "BOOTCFG_PCIE_CLKCTL,"
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bitfld.long 0x1C 0.--2. "PCIE_REFCLK_INPUT_SEL,PCIE PHY Reference Clock Selection" "0,1,2,3,4,5,6,7"
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group.long 0x700++0x03
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line.long 0x00 "BOOTCFG_CHIP_MISC_CTL0,"
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bitfld.long 0x00 28. "USB1_PME_EN,Enable wakeup event generation from USB1" "0,1"
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newline
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bitfld.long 0x00 18. "USB0_PME_EN,Enable wakeup event generation from USB0" "0,1"
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newline
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bitfld.long 0x00 12. "MSMC_BLOCK_PARITY_RST,Controls MSMC parity RAM reset on device reset" "0,1"
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rgroup.long 0x710++0x13
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line.long 0x00 "BOOTCFG_SYSENDSTAT,"
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bitfld.long 0x00 0. "SYSENDSTAT,System Endian Status0h - Reserved1h - System is in Little Endian mode" "0,1"
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line.long 0x04 "BOOTCFG_PLLLOCK_PINCTL,"
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bitfld.long 0x04 7. "UARTPLL_LOCK_SEL,UART PLL lock select" "0,1"
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bitfld.long 0x04 6. "ICSSPLL_LOCK_SEL,ICSS PLL lock select" "0,1"
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bitfld.long 0x04 5. "DSSPLL_LOCK_SEL,DSS PLL lock select" "0,1"
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bitfld.long 0x04 4. "ARMPLL_LOCK_SEL,ARM PLL lock select" "0,1"
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bitfld.long 0x04 3. "NSSPLL_LOCK_SEL,NSS PLL lock select" "0,1"
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bitfld.long 0x04 2. "PCIEPLL_LOCK_SEL,PCIE PHY PLL lock select" "0,1"
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bitfld.long 0x04 1. "DDR3APLL_LOCK_SEL,DDR3A PLL lock select" "0,1"
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bitfld.long 0x04 0. "MAINPLL_LOCK_SEL,Main PLL lock select" "0,1"
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line.long 0x08 "BOOTCFG_PLLLOCK_STAT,"
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bitfld.long 0x08 7. "UARTPLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 6. "ICSSPLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 5. "DSSPLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 4. "ARMPLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 3. "NSSPLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 2. "PCIEPLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 1. "DDR3APLL_LOCK_STAT," "0,1"
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bitfld.long 0x08 0. "MAINPLL_LOCK_STAT," "0,1"
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line.long 0x0C "BOOTCFG_PLLLOCK_EVAL,"
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bitfld.long 0x0C 7. "UARTPLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 6. "ICSSPLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 5. "DSSPLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 4. "ARMPLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 3. "NSSPLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 2. "PCIEPLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 1. "DDR3APLL_LOCK_EVAL," "0,1"
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bitfld.long 0x0C 0. "MAINPLL_LOCK_EVAL," "0,1"
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line.long 0x10 "BOOTCFG_PLLCLKSEL_STAT,"
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bitfld.long 0x10 0. "SYSCLKSEL_STAT,Status of SYSCLK PLL mux selection" "HF Oscillator drives the SYSCLK as reference..,SYSCLK_P and SYSCLK_N pins drive the reference.."
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group.long 0x738++0x0B
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line.long 0x00 "BOOTCFG_USB0_PHY_CTL0,"
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bitfld.long 0x00 2. "USB0_UTMI_VBUSVLDEXT,External VBUS Valid Indicator" "The VBUS signal is not valid and the pull-up..,The VBUS signal is valid and the pull-up.."
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bitfld.long 0x00 1. "USB0_UTMI_TXBITSTUFFENH,High-Byte Transmit Bit-Stuffing Enable" "Bit stuffing is disabled,Bit stuffing is enabled"
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newline
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bitfld.long 0x00 0. "USB0_UTMI_TXBITSTUFFEN,Low-Byte Transmit Bit-Stuffing Enable" "Bit stuffing is disabled,Bit stuffing is enabled"
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line.long 0x04 "BOOTCFG_USB0_PHY_CTL1,"
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bitfld.long 0x04 19. "USB0_PHY_OTG_MUX_VAL_IDDIG,Mux value for iddig if PHY_OTG_MUX_SEL_IDDIG=1" "0,1"
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bitfld.long 0x04 18. "USB0_PHY_OTG_MUX_SEL_IDDIG,Mux select for iddig" "Driven from PHY,Use PHY_OTG_MUX_SEL_IDDIG"
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newline
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bitfld.long 0x04 17. "USB0_PHY_OTG_MUX_VAL_DRVVBUS,Mux value for drvvbus if PHY_OTG_MUX_SEL_DRVVBUS=1" "0,1"
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newline
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bitfld.long 0x04 16. "USB0_PHY_OTG_MUX_SEL_DRVVBUS,Mux select for drvvbus" "Driven from controller,UsePHY_OTG_MUX_VAL_DRVVBUS"
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line.long 0x08 "BOOTCFG_USB0_PHY_CTL2,"
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bitfld.long 0x08 23.--26. "USB0_PHY_PC_TXVREFTUNE,HS DC Voltage Level Adjustment" "-10%,-8.75%,-7.5%,-6.25%,-5%,-3.75%,-2.5%,-1.25%,Design default,+1.25%,+2.5%,+3.75%,+5%,+6.25%,+7.5%,+8.75%"
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newline
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bitfld.long 0x08 21.--22. "USB0_PHY_PC_TXRISETUNE,HS Transmitter Rise/Fail Time Adjustment.This bus adjusts the rise/fail times of the high-speed waveform" "+20%,+15%,Design..,-10%"
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newline
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bitfld.long 0x08 19.--20. "USB0_PHY_PC_TXRESTUNE,USB Source impedance Adjustment" "Source impedance is increased by approximately..,Design default,Source impedance is decreased by approximately 2..,Source impedance is decreased by approximately 4.."
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newline
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bitfld.long 0x08 18. "USB0_PHY_PC_TXPREEMPPULSETUNE,HS Transmitter Pre-Emphasis Duration Control" "0,1"
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bitfld.long 0x08 16.--17. "USB0_PHY_PC_TXPREEMPAMPTUNE,HS Transmitter Pre-Emphasis Current Control" "?,HS Transmitter pre-emphasis circuit sources 1X..,HS Transmitter pre-emphasis circuit sources 2X..,HS Transmitter pre-emphasis circuit sources 3X.."
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newline
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bitfld.long 0x08 14.--15. "USB0_PHY_PC_TXHSXVTUNE,Transmitter High-Speed Crossover Adjustment" "Reserved,-15mV,+15mV,Default setting"
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newline
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bitfld.long 0x08 10.--13. "USB0_PHY_PC_TXFSLSTUNE,FS/LS Source impedance Adjustment" "+5%,+2.5%,?,Design default,?,?,?,-2.5%,?,?,?,?,?,?,?,-5% All other bit.."
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newline
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bitfld.long 0x08 7.--9. "USB0_PHY_PC_SQRXTUNE,Squelch Threshold Adjustment" "+15%,+10%,+5%,Design..,-5%,-10%,-15%,-20%"
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newline
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bitfld.long 0x08 4.--6. "USB0_PHY_PC_OTGTUNE,VBUS Valid Threshold Adjustment" "-12%,-9%,-6%,-3%,Design..,+3%,+6%,+9%"
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newline
|
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bitfld.long 0x08 0.--2. "USB0_PHY_PC_COMPDISTUNE,Disconnect Threshold Adjustment" "-6%,-4.5%,-3%,-1.5%,Design..,+1.5%,+3%,+4.5%"
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group.long 0x748++0x03
|
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line.long 0x00 "BOOTCFG_USB0_PHY_CTL4,"
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bitfld.long 0x00 22.--24. "USB0_PHY_OSC_FSEL,Reference Clock Frequency Select" "Reserved,Reserved,12MHz,19.2MHz,Reserved,24MHz (default),Reserved,50MHz"
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newline
|
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bitfld.long 0x00 19.--20. "USB0_PHY_OSC_REFCLKSEL,Reference Clock Select for PLL Block" "Crystal,External Clock,Internal Clock (default),Reserved"
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newline
|
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bitfld.long 0x00 17. "USB0_CTRL_MISC_DEBUG_EN,Enable CTL_MISC_DEBUG_DATA" "disable,enable"
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|
newline
|
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bitfld.long 0x00 16. "USB0_PHY_OTG_VBUSVLDEXTSEL,External VBUS Valid Select" "The internal Session Valid comparator is used to..,The VBUSVLDEXT input is used to generate.."
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newline
|
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bitfld.long 0x00 15. "USB0_PHY_OTG_OTGDISABLE,OTG Block Disable" "The OTG block is powered up,The OTG block is powered down"
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group.long 0x750++0x0B
|
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line.long 0x00 "BOOTCFG_USB1_PHY_CTL0,"
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bitfld.long 0x00 3. "USB1_UTMI_WORDINTERFACE," "0,1"
|
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newline
|
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bitfld.long 0x00 2. "USB1_UTMI_VBUSVLDEXT,External VBUS Valid Indicator" "The VBUS signal is not valid and the pull-up..,The VBUS signal is valid and the pull-up.."
|
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newline
|
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bitfld.long 0x00 1. "USB1_UTMI_TXBITSTUFFENH,High-Byte Transmit Bit-Stuffing Enable" "Bit stuffing is disabled,Bit stuffing is enabled"
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newline
|
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bitfld.long 0x00 0. "USB1_UTMI_TXBITSTUFFEN,Low-Byte Transmit Bit-Stuffing Enable" "Bit stuffing is disabled,Bit stuffing is enabled"
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line.long 0x04 "BOOTCFG_USB1_PHY_CTL1,"
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bitfld.long 0x04 19. "USB1_PHY_OTG_MUX_VAL_IDDIG,Mux value for iddig if PHY_OTG_MUX_SEL_IDDIG=1" "0,1"
|
|
newline
|
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bitfld.long 0x04 18. "USB1_PHY_OTG_MUX_SEL_IDDIG,Mux select for iddig" "Driven from PHY,Use PHY_OTG_MUX_SEL_IDDIG"
|
|
newline
|
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bitfld.long 0x04 17. "USB1_PHY_OTG_MUX_VAL_DRVVBUS,Mux value for drvvbus if PHY_OTG_MUX_SEL_DRVVBUS=1" "0,1"
|
|
newline
|
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bitfld.long 0x04 16. "USB1_PHY_OTG_MUX_SEL_DRVVBUS,Mux select for drvvbus" "Driven from controller,Use PHY_OTG_MUX_VAL_DRVVBUS"
|
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line.long 0x08 "BOOTCFG_USB1_PHY_CTL2,"
|
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bitfld.long 0x08 23.--26. "USB1_PHY_PC_TXVREFTUNE,HS DC Voltage Level Adjustment" "-10%,-8.75%,-7.5%,-6.25%,-5%,-3.75%,-2.5%,-1.25%,Design default,+1.25%,+2.5%,+3.75%,+5%,+6.25%,+7.5%,+8.75%"
|
|
newline
|
|
bitfld.long 0x08 21.--22. "USB1_PHY_PC_TXRISETUNE,HS Transmitter Rise/Fail Time Adjustment" "+20%,+15%,Design..,-10%"
|
|
newline
|
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bitfld.long 0x08 19.--20. "USB1_PHY_PC_TXRESTUNE,USB Source impedance Adjustment" "Source impedance is increased by approximately..,Design default,Source impedance is decreased by approximately 2..,Source impedance is decreased by approximately 4.."
|
|
newline
|
|
bitfld.long 0x08 18. "USB1_PHY_PC_TXPREEMPPULSETUNE,HS Transmitter Pre-Emphasis Duration Control" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16.--17. "USB1_PHY_PC_TXPREEMPAMPTUNE,HS Transmitter Pre-Emphasis Current Control" "?,HS Transmitter pre-emphasis circuit sources 1X..,HS Transmitter pre-emphasis circuit sources 2X..,HS Transmitter pre-emphasis circuit sources 3X.."
|
|
newline
|
|
bitfld.long 0x08 14.--15. "USB1_PHY_PC_TXHSXVTUNE,Transmitter High-Speed Crossover Adjustment" "Reserved,-15mV,+15mV,Default setting"
|
|
newline
|
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bitfld.long 0x08 10.--13. "USB1_PHY_PC_TXFSLSTUNE,FS/LS Source impedance Adjustment" "+5%,+2.5%,?,Design default,?,?,?,-2.5%,?,?,?,?,?,?,?,-5% All other bit.."
|
|
newline
|
|
bitfld.long 0x08 7.--9. "USB1_PHY_PC_SQRXTUNE,Squelch Threshold Adjustment" "+15%,+10%,+5%,Design..,-5%,-10%,-15%,-20%"
|
|
newline
|
|
bitfld.long 0x08 4.--6. "USB1_PHY_PC_OTGTUNE,VBUS Valid Threshold Adjustment" "-12%,-9%,-6%,-3%,Design..,+3%,+6%,+9%"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "USB1_PHY_PC_COMPDISTUNE,Disconnect Threshold Adjustment" "-6%,-4.5%,-3%,-1.5%,Design..,+1.5%,+3%,+4.5%"
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "BOOTCFG_USB1_PHY_CTL4,"
|
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bitfld.long 0x00 22.--24. "USB1_PHY_OSC_FSEL,Reference Clock Frequency Select" "Reserved,Reserved,12MHz,19.2MHz,Reserved,24MHz (default),Reserved,50MHz"
|
|
newline
|
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bitfld.long 0x00 19.--20. "USB1_PHY_OSC_REFCLKSEL,Reference Clock Select for PLL Block" "Crystal,External Clock,Internal Clock (default),Reserved"
|
|
newline
|
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bitfld.long 0x00 17. "USB1_CTRL_MISC_DEBUG_EN,Enable CTL_MISC_DEBUG_DATA" "disable,enable"
|
|
newline
|
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bitfld.long 0x00 16. "USB1_PHY_OTG_VBUSVLDEXTSEL,External VBUS Valid Select" "The internal Session Valid comparator is used to..,The VBUSVLDEXT input is used to generate.."
|
|
newline
|
|
bitfld.long 0x00 15. "USB1_PHY_OTG_OTGDISABLE,OTG Block Disable" "The OTG block is powered up,The OTG block is powered down"
|
|
group.long 0x768++0x07
|
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line.long 0x00 "BOOTCFG_USB0_EBC_IN_CTL,"
|
|
bitfld.long 0x00 4.--5. "EBC14_SEL0," "?,1h is driven into..,ARM TBR DMA event routed to..,Debug TBR DMA event routed to.."
|
|
newline
|
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bitfld.long 0x00 0.--1. "EBC15_SEL0," "?,1h is driven into..,ARM TBR DMA event routed to..,Debug TBR DMA event routed to.."
|
|
line.long 0x04 "BOOTCFG_USB1_EBC_IN_CTL,"
|
|
bitfld.long 0x04 4.--5. "EBC14_SEL1," "?,1h is driven into..,ARM TBR DMA event routed to..,Debug TBR DMA event routed to.."
|
|
newline
|
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bitfld.long 0x04 0.--1. "EBC15_SEL1," "?,1h is driven into..,ARM TBR DMA event routed to..,Debug TBR DMA event routed to.."
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "BOOTCFG_DSP_BOOT_ADDR0_NS,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "ISTP_RST_VAL,Non-secure boot address for C66x core"
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "BOOTCFG_OBSCLKCTL,"
|
|
bitfld.long 0x00 18. "RCOSC_OBSCLK_EN,This clock is not available in the current device" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "HFOSC_OBSCLK_EN,Controls the SYS OSC observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 16. "NSSPLL_OBSCLK_EN,Controls the NSS/IEP PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 15. "PLLCTL_OBSCLK_EN,Controls the PLL controller observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 14. "DDR3APLL_OBSCLK_EN,Controls the DDR PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 13. "ICSSPLL_OBSCLK_EN,Controls the ICSS PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 12. "UARTPLL_OBSCLK_EN,Controls the UART PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. "ARMPLL_OBSCLK_EN,Controls the ARM PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 10. "DSSPLL_OBSCLK_EN,Controls the DSS PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 9. "MAINPLL_OBSCLK_EN,Controls the MAIN PLL observation clock enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 8. "RSVD_OBSCLK_EN,This clock is not available in the current device" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PLL_OBSCLK_SEL,Controls OBSMUX to select which clock is output onto the OBSCLK[P/N] pin" "Reserved,MAIN PLL,DSS PLL,ARM PLL,UART PLL,ICSS PLL,DDR PLL,PLL Controller OBSCLK,NSS/IEP PLL,SYS OSC clock Others -..,?..."
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "BOOTCFG_EFUSE_BOOTROM,"
|
|
hexmask.long.word 0x00 16.--27. 1. "DEVICE_SPEED,12 EFUSE bits are allocated to indicate the device operating speed"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "ARM_SPEED,12 EFUSE bits are allocated to indicate the ARM operating speed"
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "BOOTCFG_DCAN_RAMINIT,"
|
|
bitfld.long 0x00 9. "DCAN1_RAMINIT_DONE,DCAN1 RAM initialization status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DCAN0_RAMINIT_DONE,DCAN0 RAM initialization status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DCAN1_RAMINIT_START,DCAN1 RAM initialization start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DCAN0_RAMINIT_START,DCAN0 RAM initialization start" "0,1"
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "BOOTCFG_ETHERNET_CFG,"
|
|
bitfld.long 0x00 4. "RGMII_ID_MODE,RGMII Internal Delay Mode Selection0h = Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "MODE_SEL,Ethernet Port Interface Mode Selection" "MII,RMII,RGMII,Reserved"
|
|
group.long 0xE30++0x0B
|
|
line.long 0x00 "BOOTCFG_MLB_SIG_IO_CTL,"
|
|
bitfld.long 0x00 16.--19. "N_TRIM,MLB NMOS LVDS output drive trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "P_TRIM,MLB PMOS LVDS output drive trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "PWRDN_RX,Power down control for MLB LVDS receiver" "Receiver is powered on,Receiver is powered down"
|
|
newline
|
|
bitfld.long 0x00 3. "EN_EXTRES,Control for internal termination resistor" "Enable internal termination resistor,Disable internal termination resistor (use.."
|
|
line.long 0x04 "BOOTCFG_MLB_DAT_IO_CTL,"
|
|
bitfld.long 0x04 16.--19. "N_TRIM,MLB NMOS LVDS output drive trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "P_TRIM,MLB PMOS LVDS output drive trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 5. "PWRDN_RX,Power down control for MLB LVDS receiver" "Receiver is powered on,Receiver is powered down"
|
|
newline
|
|
bitfld.long 0x04 3. "EN_EXTRES,Control for internal termination resistor" "Enable internal termination resistor,Disable internal termination resistor (use.."
|
|
line.long 0x08 "BOOTCFG_MLB_CLK_IO_CTL,"
|
|
bitfld.long 0x08 5. "PWRDN_RX,Power down control for MLB LVDS receiver" "Receiver is powered on,Receiver is powered down"
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "BOOTCFG_EPWM_CTL,"
|
|
bitfld.long 0x00 16. "EPWM_EALLOW,EPWM trip zone and HRPWM config register writeaccess enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 13. "EPWM_SOCB_SEL,Start of Conversion (SOCB) output source" "EPWM[5:0] SOCB outputs,ICSS0 Host INT1"
|
|
newline
|
|
bitfld.long 0x00 12. "EPWM_SOCA_SEL,Start of Conversion (SOCA) output source" "EPWM[5:0] SOCA outputs,ICSS0 Host INT0"
|
|
newline
|
|
bitfld.long 0x00 8. "EPWM3_SYNCSEL,EPWM3 SyncIn source" "EPWM3 sync is from EPWM2 (daisy chained),EPWM3 sync is from ICSS/Pin"
|
|
newline
|
|
bitfld.long 0x00 5. "EPWM5_TBCLKEN,EPWM5 timebase clock" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "EPWM4_TBCLKEN,EPWM4 timebase clock" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "EPWM3_TBCLKEN,EPWM3 timebase clock" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "EPWM2_TBCLKEN,EPWM2 timebase clock" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. "EPWM1_TBCLKEN,EPWM1 timebase clock" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "EPWM0_TBCLKEN,EPWM0 timebase clock" "Disable,Enable"
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "BOOTCFG_ECAP_CAPEVT_CTL,"
|
|
bitfld.long 0x00 8.--12. "ECAP1_CAP_EVT,Select the eCAP_1 capture event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ECAP0_CAP_EVT,Select the eCAP_0 capture event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "BOOTCFG_EQEP_STAT,"
|
|
bitfld.long 0x00 2. "PHASE_ERR2,EQEP2 phase error status" "No error,Phase error"
|
|
newline
|
|
bitfld.long 0x00 1. "PHASE_ERR1,EQEP1 phase error status" "No error,Phase error"
|
|
newline
|
|
bitfld.long 0x00 0. "PHASE_ERR0,EQEP0 phase error status" "No error,Phase error"
|
|
group.long 0xE70++0x03
|
|
line.long 0x00 "BOOTCFG_LVDS_BG_CTL,"
|
|
bitfld.long 0x00 7. "LVDS1_PWRDN_BG,Power down control for the LVDS1 bandgap buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LVDS1_TRIM_EN,LVDS1 bandgap trim enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "LVDS1_TRIM,LVDS1 bandgap trim input vbias trims for CPTS_REFCLK MLBP_SIG MLBP_DAT and MLBP_CLK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "LVDS0_PWRDN_BG,Power down control for the LVDS0 bandgap buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "LVDS0_TRIM_EN,LVDS0 bandgap trim enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "LVDS0_TRIM,LVDS0 bandgap trim input vbias trims for DDR_CLK and SYSCLK" "0,1,2,3"
|
|
group.long 0xE80++0x07
|
|
line.long 0x00 "BOOTCFG_LDO_USB_CTL,"
|
|
hexmask.long.word 0x00 16.--25. 1. "VSET,Used to program the output voltage (vddar) of GPLDOBG (General Purpose Low Drop Output with integrated BandGap)"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "BGAP_TRIM,BandGap reference magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "BOOTCFG_LDO_PCIE_CTL,"
|
|
hexmask.long.word 0x04 16.--25. 1. "VSET,Used to program the output voltage (vddar) of GPLDOBG (General Purpose Low Drop Output with integrated BandGap)"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "BGAP_TRIM,BandGap reference magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 3. (list 256. 257. 258. )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x1400)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 240. 241. 242. 243. 244. 245. 246. 247. 248. 249. 250. 251. 252. 253. 254. 255. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x13C0)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 224. 225. 226. 227. 228. 229. 230. 231. 232. 233. 234. 235. 236. 237. 238. 239. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1380)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 208. 209. 210. 211. 212. 213. 214. 215. 216. 217. 218. 219. 220. 221. 222. 223. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1340)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1300)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. 190. 191. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x12C0)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1280)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1240)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1200)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x11C0)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1180)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1140)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1100)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x10C0)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1080)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1040)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1000)++0x03
|
|
line.long 0x00 "BOOTCFG_PADCONFIG$1,"
|
|
bitfld.long 0x00 19.--20. "BUFFERCLASS,Buffer class selection (CS1 CS0)For 3.3V I/Os:0h and" "0,1,2,3"
|
|
bitfld.long 0x00 17. "PULLTYPESEL,Pull-up or pull-down resistor selection" "Pull-down is selected,Pull-up is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "PULLUDEN,Pull-up/pull-down resistor enable" "Pull-up/pull-down enabled,Pull-up/pull-down disabled"
|
|
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Primary function,Secondary function,Tertiary function,Quaternary function,Quinary function,Senary function,?..."
|
|
repeat.end
|
|
repeat 14. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
|
|
group.long ($2+0xD00)++0x03
|
|
line.long 0x00 "BOOTCFG_EVENT_MUXCTL$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EVTSEL3,Event select for Event Mux3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EVTSEL2,Event select for Event Mux2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "EVTSEL1,Event select for Event Mux1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EVTSEL0,Event select for Event Mux0"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x780)++0x03
|
|
line.long 0x00 "BOOTCFG_SCRATCH$1,"
|
|
repeat.end
|
|
repeat 2. (list 0. 8. )(list 0x00 0x20 )
|
|
group.long ($2+0x308)++0x03
|
|
line.long 0x00 "BOOTCFG_RSTMUX$1,"
|
|
bitfld.long 0x00 9. "RSTMUX_EVSTATCLR0,Clear event status" "0,1"
|
|
bitfld.long 0x00 5.--7. "RSTMUX_DELAY0,Delay cycles between NMI and local reset to C66x core incase of C66x WD timer or delay between GIC interrupt and device reset in case of A15 WD timer" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 4. "RSTMUX_EVSTAT0,Event status" "0,1"
|
|
bitfld.long 0x00 1.--3. "RSTMUX_OMODE0,Watchdog timer event operation mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "RSTMUX_LOCK0,Lock register fields" "0,1"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "BOOTCFG_KICK$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "DCAN"
|
|
tree "DCAN_0"
|
|
base ad:0x260B200
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DCAN_CTL,"
|
|
bitfld.long 0x00 24. "PDR,Request for local low power-down mode 0h (R/W) = No application request for local low power-down mode" "0,1"
|
|
bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "0,1"
|
|
bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "0,1"
|
|
bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "0,1"
|
|
bitfld.long 0x00 17. "IE1,Interrupt line 1 enable 0h (R/W) = Disabled - Module interrupt INT1 is always low" "0,1"
|
|
bitfld.long 0x00 16. "INITDBG,Internal init state while debug access 0h (R/W) = Not in debug mode or debug mode requested but not entered" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SWR,Software reset enable" "0,1"
|
|
bitfld.long 0x00 10.--13. "PMD,ECC on/offOthers: function enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9. "ABO,Auto-Bus-On enable 0h (R/W) = The Auto-Bus-On feature is disabled 1h (R/W) = The Auto-Bus-On feature is enabled" "0,1"
|
|
bitfld.long 0x00 8. "IDS,Interruption debug support enable 0h (R/W) = When Debug/Suspend mode is requested DCAN will wait for a started transmission or reception to be completed before entering Debug/Suspend mode 1h (R/W) = When Debug/Suspend mode is requested DCAN will.." "0,1"
|
|
bitfld.long 0x00 7. "TEST,Test mode enable 0h (R/W) = Normal Operation 1h (R/W) = Test Mode" "0,1"
|
|
bitfld.long 0x00 6. "CCE,Configuration change enable 0h (R/W) = The software has no write access to the configuration registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DAR,Disable automatic retransmission 0h (R/W) = Automatic retransmission of not successful messages enabled" "0,1"
|
|
bitfld.long 0x00 3. "EIE,Error interrupt enable 0h (R/W) = Disabled - PER BOFF and EWARN bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 2. "SIE,Status change interrupt enable 0h (R/W) = Disabled - WAKEUPPND RXOK TXOK and LEC bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 1. "IE0,Interrupt line 0 enable 0h (R/W) = Disabled - Module interrupt INT0 is always low" "0,1"
|
|
bitfld.long 0x00 0. "INIT,Initialization 0h (R/W) = Normal operation 1h (R/W) = Initialization mode is entered" "0,1"
|
|
line.long 0x04 "DCAN_ES,"
|
|
rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge 0h (R) = DCAN is not in local power-down mode" "0,1"
|
|
rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "0,1"
|
|
bitfld.long 0x04 8. "PER,Single/Double bit error detected" "0,1"
|
|
rbitfld.long 0x04 7. "BOFF,Bus-Off state 0h (R) = The CAN module is not bus-off state" "0,1"
|
|
rbitfld.long 0x04 6. "EWARN,Warning state 0h (R) = Both error counters are below the error warning limit of 96" "0,1"
|
|
rbitfld.long 0x04 5. "EPASS,Error passive state 0h (R) = On CAN Bus error the DCAN could send active error frames" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 4. "RXOK,Received a message successfully" "0,1"
|
|
rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "0,1"
|
|
rbitfld.long 0x04 0.--2. "LEC,Last error code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "DCAN_ERRC,"
|
|
bitfld.long 0x08 15. "RP,Receive error passive 0h (R) = The receive error counter is below the error passive level" "0,1"
|
|
hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x0C "DCAN_BTR,"
|
|
bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension.Valid programmed values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample pointValid programmed values are 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample pointValid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump WidthValid programmed values are 0 to 3" "0,1,2,3"
|
|
bitfld.long 0x0C 0.--5. "BRP,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DCAN_INT,"
|
|
hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt"
|
|
hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt"
|
|
line.long 0x14 "DCAN_TEST,"
|
|
bitfld.long 0x14 9. "RDA,RAM direct access enable 0h (R/W) = Normal operation 1h (R/W) = Direct access to the RAM is enabled while in test mode" "0,1"
|
|
bitfld.long 0x14 8. "EXL,External loopback mode" "0,1"
|
|
rbitfld.long 0x14 7. "RX,Receive pin" "0,1"
|
|
bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "0,1,2,3"
|
|
bitfld.long 0x14 4. "LBACK,Loopback mode" "0,1"
|
|
bitfld.long 0x14 3. "SILENT,Silent mode 0h (R/W) = Disabled 1h (R/W) = Enabled" "0,1"
|
|
rgroup.long 0x1C++0x17
|
|
line.long 0x00 "DCAN_PERR,"
|
|
bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)"
|
|
line.long 0x04 "DCAN_REL,"
|
|
line.long 0x08 "DCAN_ECCDIAG,"
|
|
bitfld.long 0x08 0.--3. "ECCDIAG,SECDED diagnostic mode enable/disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "DCAN_ECCDIAG_STAT,"
|
|
bitfld.long 0x0C 8. "DEFLG_DIAG,Double bit error flag diagnostic" "0,1"
|
|
bitfld.long 0x0C 0. "SEFLG_DIAG,Single bit error flag diagnostic" "0,1"
|
|
line.long 0x10 "DCAN_ECC_CS,"
|
|
bitfld.long 0x10 24.--27. "SBE_EVT_EN,Enable/disable SECDED single bit error event (CAN_SERR signal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. "ECCMODE,Enable/disable SECDED single bit error correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8. "DEFLG,Double bit error flag" "0,1"
|
|
bitfld.long 0x10 0. "SEFLG,Single bit error flag" "0,1"
|
|
line.long 0x14 "DCAN_ECC_SERR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "MESSAGE_NUMBER,Message object number where ECC single bit error has been detected"
|
|
group.long 0x80++0x53
|
|
line.long 0x00 "DCAN_ABOTR,"
|
|
line.long 0x04 "DCAN_TXRQ_X,"
|
|
bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x08 "DCAN_TXRQ12,"
|
|
line.long 0x0C "DCAN_TXRQ34,"
|
|
line.long 0x10 "DCAN_TXRQ56,"
|
|
line.long 0x14 "DCAN_TXRQ78,"
|
|
line.long 0x18 "DCAN_NWDAT_X,"
|
|
bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x1C "DCAN_NWDAT12,"
|
|
line.long 0x20 "DCAN_NWDAT34,"
|
|
line.long 0x24 "DCAN_NWDAT56,"
|
|
line.long 0x28 "DCAN_NWDAT78,"
|
|
line.long 0x2C "DCAN_INTPND_X,"
|
|
bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x30 "DCAN_INTPND12,"
|
|
line.long 0x34 "DCAN_INTPND34,"
|
|
line.long 0x38 "DCAN_INTPND56,"
|
|
line.long 0x3C "DCAN_INTPND78,"
|
|
line.long 0x40 "DCAN_MSGVAL_X,"
|
|
bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x44 "DCAN_MSGVAL12,"
|
|
line.long 0x48 "DCAN_MSGVAL34,"
|
|
line.long 0x4C "DCAN_MSGVAL56,"
|
|
line.long 0x50 "DCAN_MSGVAL78,"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "DCAN_INTMUX12,"
|
|
line.long 0x04 "DCAN_INTMUX34,"
|
|
line.long 0x08 "DCAN_INTMUX56,"
|
|
line.long 0x0C "DCAN_INTMUX78,"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "DCAN_IF1CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF1 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF1 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF1.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF1MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF1ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF1MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF1DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF1DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "DCAN_IF2CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF2 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF2 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF2 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF2.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 update The DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF2MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF2ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF2MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMask bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF2DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF2DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "DCAN_IF3OBS,"
|
|
rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data 0h (R) = No new data has been loaded since last IF3" "0,1"
|
|
rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access 0h (R) = All Data B bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access 0h (R) = All Data A bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access 0h (R) = All control section bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access 0h (R) = All Arbitration data bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access 0h (R) = All mask data bytes are already read out or are not marked to be read" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DATAB,Data B read observation 0h (R/W) = Data B section has not to be read" "0,1"
|
|
bitfld.long 0x00 3. "DATAA,Data A read observation 0h (R/W) = Data A section has not to be read" "0,1"
|
|
bitfld.long 0x00 2. "CTRL,Ctrl read observation 0h (R/W) = Ctrl section has not to be read" "0,1"
|
|
bitfld.long 0x00 1. "ARB,Arbitration data read observation 0h (R/W) = Arbitration data has not to be read" "0,1"
|
|
bitfld.long 0x00 0. "MASK,Mask data read observation 0h (R/W) = Mask data has not to be read" "0,1"
|
|
line.long 0x04 "DCAN_IF3MSK,"
|
|
rbitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
rbitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF3ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended Identifier 0h (R) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message Direction 0h (R) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28-0]: 29-bit Identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF3MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New Data 0h (R) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive) 0h (R) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt Pending 0h (R) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use Acceptance MaskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable 0h (R) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable 0h (R) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit Request 0h (R) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF3DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF3DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "DCAN_IF3UPD12,"
|
|
line.long 0x04 "DCAN_IF3UPD34,"
|
|
line.long 0x08 "DCAN_IF3UPD56,"
|
|
line.long 0x0C "DCAN_IF3UPD78,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCAN_0_DATA"
|
|
base ad:0x2604000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DCAN_CTL,"
|
|
bitfld.long 0x00 24. "PDR,Request for local low power-down mode 0h (R/W) = No application request for local low power-down mode" "0,1"
|
|
bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "0,1"
|
|
bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "0,1"
|
|
bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "0,1"
|
|
bitfld.long 0x00 17. "IE1,Interrupt line 1 enable 0h (R/W) = Disabled - Module interrupt INT1 is always low" "0,1"
|
|
bitfld.long 0x00 16. "INITDBG,Internal init state while debug access 0h (R/W) = Not in debug mode or debug mode requested but not entered" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SWR,Software reset enable" "0,1"
|
|
bitfld.long 0x00 10.--13. "PMD,ECC on/offOthers: function enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9. "ABO,Auto-Bus-On enable 0h (R/W) = The Auto-Bus-On feature is disabled 1h (R/W) = The Auto-Bus-On feature is enabled" "0,1"
|
|
bitfld.long 0x00 8. "IDS,Interruption debug support enable 0h (R/W) = When Debug/Suspend mode is requested DCAN will wait for a started transmission or reception to be completed before entering Debug/Suspend mode 1h (R/W) = When Debug/Suspend mode is requested DCAN will.." "0,1"
|
|
bitfld.long 0x00 7. "TEST,Test mode enable 0h (R/W) = Normal Operation 1h (R/W) = Test Mode" "0,1"
|
|
bitfld.long 0x00 6. "CCE,Configuration change enable 0h (R/W) = The software has no write access to the configuration registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DAR,Disable automatic retransmission 0h (R/W) = Automatic retransmission of not successful messages enabled" "0,1"
|
|
bitfld.long 0x00 3. "EIE,Error interrupt enable 0h (R/W) = Disabled - PER BOFF and EWARN bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 2. "SIE,Status change interrupt enable 0h (R/W) = Disabled - WAKEUPPND RXOK TXOK and LEC bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 1. "IE0,Interrupt line 0 enable 0h (R/W) = Disabled - Module interrupt INT0 is always low" "0,1"
|
|
bitfld.long 0x00 0. "INIT,Initialization 0h (R/W) = Normal operation 1h (R/W) = Initialization mode is entered" "0,1"
|
|
line.long 0x04 "DCAN_ES,"
|
|
rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge 0h (R) = DCAN is not in local power-down mode" "0,1"
|
|
rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "0,1"
|
|
bitfld.long 0x04 8. "PER,Single/Double bit error detected" "0,1"
|
|
rbitfld.long 0x04 7. "BOFF,Bus-Off state 0h (R) = The CAN module is not bus-off state" "0,1"
|
|
rbitfld.long 0x04 6. "EWARN,Warning state 0h (R) = Both error counters are below the error warning limit of 96" "0,1"
|
|
rbitfld.long 0x04 5. "EPASS,Error passive state 0h (R) = On CAN Bus error the DCAN could send active error frames" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 4. "RXOK,Received a message successfully" "0,1"
|
|
rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "0,1"
|
|
rbitfld.long 0x04 0.--2. "LEC,Last error code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "DCAN_ERRC,"
|
|
bitfld.long 0x08 15. "RP,Receive error passive 0h (R) = The receive error counter is below the error passive level" "0,1"
|
|
hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x0C "DCAN_BTR,"
|
|
bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension.Valid programmed values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample pointValid programmed values are 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample pointValid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump WidthValid programmed values are 0 to 3" "0,1,2,3"
|
|
bitfld.long 0x0C 0.--5. "BRP,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DCAN_INT,"
|
|
hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt"
|
|
hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt"
|
|
line.long 0x14 "DCAN_TEST,"
|
|
bitfld.long 0x14 9. "RDA,RAM direct access enable 0h (R/W) = Normal operation 1h (R/W) = Direct access to the RAM is enabled while in test mode" "0,1"
|
|
bitfld.long 0x14 8. "EXL,External loopback mode" "0,1"
|
|
rbitfld.long 0x14 7. "RX,Receive pin" "0,1"
|
|
bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "0,1,2,3"
|
|
bitfld.long 0x14 4. "LBACK,Loopback mode" "0,1"
|
|
bitfld.long 0x14 3. "SILENT,Silent mode 0h (R/W) = Disabled 1h (R/W) = Enabled" "0,1"
|
|
rgroup.long 0x1C++0x17
|
|
line.long 0x00 "DCAN_PERR,"
|
|
bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)"
|
|
line.long 0x04 "DCAN_REL,"
|
|
line.long 0x08 "DCAN_ECCDIAG,"
|
|
bitfld.long 0x08 0.--3. "ECCDIAG,SECDED diagnostic mode enable/disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "DCAN_ECCDIAG_STAT,"
|
|
bitfld.long 0x0C 8. "DEFLG_DIAG,Double bit error flag diagnostic" "0,1"
|
|
bitfld.long 0x0C 0. "SEFLG_DIAG,Single bit error flag diagnostic" "0,1"
|
|
line.long 0x10 "DCAN_ECC_CS,"
|
|
bitfld.long 0x10 24.--27. "SBE_EVT_EN,Enable/disable SECDED single bit error event (CAN_SERR signal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. "ECCMODE,Enable/disable SECDED single bit error correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8. "DEFLG,Double bit error flag" "0,1"
|
|
bitfld.long 0x10 0. "SEFLG,Single bit error flag" "0,1"
|
|
line.long 0x14 "DCAN_ECC_SERR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "MESSAGE_NUMBER,Message object number where ECC single bit error has been detected"
|
|
group.long 0x80++0x53
|
|
line.long 0x00 "DCAN_ABOTR,"
|
|
line.long 0x04 "DCAN_TXRQ_X,"
|
|
bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x08 "DCAN_TXRQ12,"
|
|
line.long 0x0C "DCAN_TXRQ34,"
|
|
line.long 0x10 "DCAN_TXRQ56,"
|
|
line.long 0x14 "DCAN_TXRQ78,"
|
|
line.long 0x18 "DCAN_NWDAT_X,"
|
|
bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x1C "DCAN_NWDAT12,"
|
|
line.long 0x20 "DCAN_NWDAT34,"
|
|
line.long 0x24 "DCAN_NWDAT56,"
|
|
line.long 0x28 "DCAN_NWDAT78,"
|
|
line.long 0x2C "DCAN_INTPND_X,"
|
|
bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x30 "DCAN_INTPND12,"
|
|
line.long 0x34 "DCAN_INTPND34,"
|
|
line.long 0x38 "DCAN_INTPND56,"
|
|
line.long 0x3C "DCAN_INTPND78,"
|
|
line.long 0x40 "DCAN_MSGVAL_X,"
|
|
bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x44 "DCAN_MSGVAL12,"
|
|
line.long 0x48 "DCAN_MSGVAL34,"
|
|
line.long 0x4C "DCAN_MSGVAL56,"
|
|
line.long 0x50 "DCAN_MSGVAL78,"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "DCAN_INTMUX12,"
|
|
line.long 0x04 "DCAN_INTMUX34,"
|
|
line.long 0x08 "DCAN_INTMUX56,"
|
|
line.long 0x0C "DCAN_INTMUX78,"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "DCAN_IF1CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF1 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF1 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF1.." "0,1"
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|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
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|
newline
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bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF1MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF1ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF1MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
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bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF1DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF1DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "DCAN_IF2CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF2 register set" "0,1"
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|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF2 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF2 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF2.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 update The DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF2MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF2ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF2MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMask bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF2DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF2DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "DCAN_IF3OBS,"
|
|
rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data 0h (R) = No new data has been loaded since last IF3" "0,1"
|
|
rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access 0h (R) = All Data B bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access 0h (R) = All Data A bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access 0h (R) = All control section bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access 0h (R) = All Arbitration data bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access 0h (R) = All mask data bytes are already read out or are not marked to be read" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DATAB,Data B read observation 0h (R/W) = Data B section has not to be read" "0,1"
|
|
bitfld.long 0x00 3. "DATAA,Data A read observation 0h (R/W) = Data A section has not to be read" "0,1"
|
|
bitfld.long 0x00 2. "CTRL,Ctrl read observation 0h (R/W) = Ctrl section has not to be read" "0,1"
|
|
bitfld.long 0x00 1. "ARB,Arbitration data read observation 0h (R/W) = Arbitration data has not to be read" "0,1"
|
|
bitfld.long 0x00 0. "MASK,Mask data read observation 0h (R/W) = Mask data has not to be read" "0,1"
|
|
line.long 0x04 "DCAN_IF3MSK,"
|
|
rbitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
rbitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF3ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended Identifier 0h (R) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message Direction 0h (R) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28-0]: 29-bit Identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF3MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New Data 0h (R) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive) 0h (R) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt Pending 0h (R) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use Acceptance MaskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable 0h (R) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable 0h (R) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit Request 0h (R) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF3DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF3DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "DCAN_IF3UPD12,"
|
|
line.long 0x04 "DCAN_IF3UPD34,"
|
|
line.long 0x08 "DCAN_IF3UPD56,"
|
|
line.long 0x0C "DCAN_IF3UPD78,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCAN_1"
|
|
base ad:0x260B400
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DCAN_CTL,"
|
|
bitfld.long 0x00 24. "PDR,Request for local low power-down mode 0h (R/W) = No application request for local low power-down mode" "0,1"
|
|
bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "0,1"
|
|
bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "0,1"
|
|
bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "0,1"
|
|
bitfld.long 0x00 17. "IE1,Interrupt line 1 enable 0h (R/W) = Disabled - Module interrupt INT1 is always low" "0,1"
|
|
bitfld.long 0x00 16. "INITDBG,Internal init state while debug access 0h (R/W) = Not in debug mode or debug mode requested but not entered" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SWR,Software reset enable" "0,1"
|
|
bitfld.long 0x00 10.--13. "PMD,ECC on/offOthers: function enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9. "ABO,Auto-Bus-On enable 0h (R/W) = The Auto-Bus-On feature is disabled 1h (R/W) = The Auto-Bus-On feature is enabled" "0,1"
|
|
bitfld.long 0x00 8. "IDS,Interruption debug support enable 0h (R/W) = When Debug/Suspend mode is requested DCAN will wait for a started transmission or reception to be completed before entering Debug/Suspend mode 1h (R/W) = When Debug/Suspend mode is requested DCAN will.." "0,1"
|
|
bitfld.long 0x00 7. "TEST,Test mode enable 0h (R/W) = Normal Operation 1h (R/W) = Test Mode" "0,1"
|
|
bitfld.long 0x00 6. "CCE,Configuration change enable 0h (R/W) = The software has no write access to the configuration registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DAR,Disable automatic retransmission 0h (R/W) = Automatic retransmission of not successful messages enabled" "0,1"
|
|
bitfld.long 0x00 3. "EIE,Error interrupt enable 0h (R/W) = Disabled - PER BOFF and EWARN bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 2. "SIE,Status change interrupt enable 0h (R/W) = Disabled - WAKEUPPND RXOK TXOK and LEC bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 1. "IE0,Interrupt line 0 enable 0h (R/W) = Disabled - Module interrupt INT0 is always low" "0,1"
|
|
bitfld.long 0x00 0. "INIT,Initialization 0h (R/W) = Normal operation 1h (R/W) = Initialization mode is entered" "0,1"
|
|
line.long 0x04 "DCAN_ES,"
|
|
rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge 0h (R) = DCAN is not in local power-down mode" "0,1"
|
|
rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "0,1"
|
|
bitfld.long 0x04 8. "PER,Single/Double bit error detected" "0,1"
|
|
rbitfld.long 0x04 7. "BOFF,Bus-Off state 0h (R) = The CAN module is not bus-off state" "0,1"
|
|
rbitfld.long 0x04 6. "EWARN,Warning state 0h (R) = Both error counters are below the error warning limit of 96" "0,1"
|
|
rbitfld.long 0x04 5. "EPASS,Error passive state 0h (R) = On CAN Bus error the DCAN could send active error frames" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 4. "RXOK,Received a message successfully" "0,1"
|
|
rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "0,1"
|
|
rbitfld.long 0x04 0.--2. "LEC,Last error code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "DCAN_ERRC,"
|
|
bitfld.long 0x08 15. "RP,Receive error passive 0h (R) = The receive error counter is below the error passive level" "0,1"
|
|
hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x0C "DCAN_BTR,"
|
|
bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension.Valid programmed values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample pointValid programmed values are 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample pointValid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump WidthValid programmed values are 0 to 3" "0,1,2,3"
|
|
bitfld.long 0x0C 0.--5. "BRP,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DCAN_INT,"
|
|
hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt"
|
|
hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt"
|
|
line.long 0x14 "DCAN_TEST,"
|
|
bitfld.long 0x14 9. "RDA,RAM direct access enable 0h (R/W) = Normal operation 1h (R/W) = Direct access to the RAM is enabled while in test mode" "0,1"
|
|
bitfld.long 0x14 8. "EXL,External loopback mode" "0,1"
|
|
rbitfld.long 0x14 7. "RX,Receive pin" "0,1"
|
|
bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "0,1,2,3"
|
|
bitfld.long 0x14 4. "LBACK,Loopback mode" "0,1"
|
|
bitfld.long 0x14 3. "SILENT,Silent mode 0h (R/W) = Disabled 1h (R/W) = Enabled" "0,1"
|
|
rgroup.long 0x1C++0x17
|
|
line.long 0x00 "DCAN_PERR,"
|
|
bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)"
|
|
line.long 0x04 "DCAN_REL,"
|
|
line.long 0x08 "DCAN_ECCDIAG,"
|
|
bitfld.long 0x08 0.--3. "ECCDIAG,SECDED diagnostic mode enable/disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "DCAN_ECCDIAG_STAT,"
|
|
bitfld.long 0x0C 8. "DEFLG_DIAG,Double bit error flag diagnostic" "0,1"
|
|
bitfld.long 0x0C 0. "SEFLG_DIAG,Single bit error flag diagnostic" "0,1"
|
|
line.long 0x10 "DCAN_ECC_CS,"
|
|
bitfld.long 0x10 24.--27. "SBE_EVT_EN,Enable/disable SECDED single bit error event (CAN_SERR signal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. "ECCMODE,Enable/disable SECDED single bit error correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8. "DEFLG,Double bit error flag" "0,1"
|
|
bitfld.long 0x10 0. "SEFLG,Single bit error flag" "0,1"
|
|
line.long 0x14 "DCAN_ECC_SERR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "MESSAGE_NUMBER,Message object number where ECC single bit error has been detected"
|
|
group.long 0x80++0x53
|
|
line.long 0x00 "DCAN_ABOTR,"
|
|
line.long 0x04 "DCAN_TXRQ_X,"
|
|
bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x08 "DCAN_TXRQ12,"
|
|
line.long 0x0C "DCAN_TXRQ34,"
|
|
line.long 0x10 "DCAN_TXRQ56,"
|
|
line.long 0x14 "DCAN_TXRQ78,"
|
|
line.long 0x18 "DCAN_NWDAT_X,"
|
|
bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x1C "DCAN_NWDAT12,"
|
|
line.long 0x20 "DCAN_NWDAT34,"
|
|
line.long 0x24 "DCAN_NWDAT56,"
|
|
line.long 0x28 "DCAN_NWDAT78,"
|
|
line.long 0x2C "DCAN_INTPND_X,"
|
|
bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x30 "DCAN_INTPND12,"
|
|
line.long 0x34 "DCAN_INTPND34,"
|
|
line.long 0x38 "DCAN_INTPND56,"
|
|
line.long 0x3C "DCAN_INTPND78,"
|
|
line.long 0x40 "DCAN_MSGVAL_X,"
|
|
bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x44 "DCAN_MSGVAL12,"
|
|
line.long 0x48 "DCAN_MSGVAL34,"
|
|
line.long 0x4C "DCAN_MSGVAL56,"
|
|
line.long 0x50 "DCAN_MSGVAL78,"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "DCAN_INTMUX12,"
|
|
line.long 0x04 "DCAN_INTMUX34,"
|
|
line.long 0x08 "DCAN_INTMUX56,"
|
|
line.long 0x0C "DCAN_INTMUX78,"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "DCAN_IF1CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF1 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF1 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF1.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF1MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF1ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF1MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF1DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF1DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "DCAN_IF2CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF2 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF2 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF2 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF2.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
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|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
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|
newline
|
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bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
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|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
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|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 update The DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
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|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF2MSK,"
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|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
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|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
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|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
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|
line.long 0x08 "DCAN_IF2ARB,"
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|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
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|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
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|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
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|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
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line.long 0x0C "DCAN_IF2MCTL,"
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bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
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bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
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bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
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bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMask bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
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bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
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|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
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|
newline
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bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
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|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
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bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
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|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x10 "DCAN_IF2DATA,"
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hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
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hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
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hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
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hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
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|
line.long 0x14 "DCAN_IF2DATB,"
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hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "DCAN_IF3OBS,"
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|
rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data 0h (R) = No new data has been loaded since last IF3" "0,1"
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|
rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access 0h (R) = All Data B bytes are already read out or are not marked to be read" "0,1"
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rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access 0h (R) = All Data A bytes are already read out or are not marked to be read" "0,1"
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rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access 0h (R) = All control section bytes are already read out or are not marked to be read" "0,1"
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|
rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access 0h (R) = All Arbitration data bytes are already read out or are not marked to be read" "0,1"
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|
rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access 0h (R) = All mask data bytes are already read out or are not marked to be read" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "DATAB,Data B read observation 0h (R/W) = Data B section has not to be read" "0,1"
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|
bitfld.long 0x00 3. "DATAA,Data A read observation 0h (R/W) = Data A section has not to be read" "0,1"
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|
bitfld.long 0x00 2. "CTRL,Ctrl read observation 0h (R/W) = Ctrl section has not to be read" "0,1"
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|
bitfld.long 0x00 1. "ARB,Arbitration data read observation 0h (R/W) = Arbitration data has not to be read" "0,1"
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|
bitfld.long 0x00 0. "MASK,Mask data read observation 0h (R/W) = Mask data has not to be read" "0,1"
|
|
line.long 0x04 "DCAN_IF3MSK,"
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rbitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
rbitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF3ARB,"
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|
bitfld.long 0x08 31. "MSGVAL,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R) = The message object is ignored by the message handler" "0,1"
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|
bitfld.long 0x08 30. "XTD,Extended Identifier 0h (R) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message Direction 0h (R) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28-0]: 29-bit Identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF3MCTL,"
|
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bitfld.long 0x0C 15. "NEWDAT,New Data 0h (R) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
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|
bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive) 0h (R) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt Pending 0h (R) = This message object is not the source of an interrupt" "0,1"
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|
bitfld.long 0x0C 12. "UMASK,Use Acceptance MaskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
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|
bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable 0h (R) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable 0h (R) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
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bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit Request 0h (R) = This message object is not waiting for a transmission" "0,1"
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|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF3DATA,"
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hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
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hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
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hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF3DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
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hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
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group.long 0x160++0x0F
|
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line.long 0x00 "DCAN_IF3UPD12,"
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line.long 0x04 "DCAN_IF3UPD34,"
|
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line.long 0x08 "DCAN_IF3UPD56,"
|
|
line.long 0x0C "DCAN_IF3UPD78,"
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width 0x0B
|
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tree.end
|
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tree "DCAN_1_DATA"
|
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base ad:0x2608000
|
|
group.long 0x00++0x17
|
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line.long 0x00 "DCAN_CTL,"
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bitfld.long 0x00 24. "PDR,Request for local low power-down mode 0h (R/W) = No application request for local low power-down mode" "0,1"
|
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bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "0,1"
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bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "0,1"
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bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "0,1"
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bitfld.long 0x00 17. "IE1,Interrupt line 1 enable 0h (R/W) = Disabled - Module interrupt INT1 is always low" "0,1"
|
|
bitfld.long 0x00 16. "INITDBG,Internal init state while debug access 0h (R/W) = Not in debug mode or debug mode requested but not entered" "0,1"
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newline
|
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bitfld.long 0x00 15. "SWR,Software reset enable" "0,1"
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bitfld.long 0x00 10.--13. "PMD,ECC on/offOthers: function enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9. "ABO,Auto-Bus-On enable 0h (R/W) = The Auto-Bus-On feature is disabled 1h (R/W) = The Auto-Bus-On feature is enabled" "0,1"
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bitfld.long 0x00 8. "IDS,Interruption debug support enable 0h (R/W) = When Debug/Suspend mode is requested DCAN will wait for a started transmission or reception to be completed before entering Debug/Suspend mode 1h (R/W) = When Debug/Suspend mode is requested DCAN will.." "0,1"
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bitfld.long 0x00 7. "TEST,Test mode enable 0h (R/W) = Normal Operation 1h (R/W) = Test Mode" "0,1"
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|
bitfld.long 0x00 6. "CCE,Configuration change enable 0h (R/W) = The software has no write access to the configuration registers" "0,1"
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newline
|
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bitfld.long 0x00 5. "DAR,Disable automatic retransmission 0h (R/W) = Automatic retransmission of not successful messages enabled" "0,1"
|
|
bitfld.long 0x00 3. "EIE,Error interrupt enable 0h (R/W) = Disabled - PER BOFF and EWARN bits can not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 2. "SIE,Status change interrupt enable 0h (R/W) = Disabled - WAKEUPPND RXOK TXOK and LEC bits can not generate an interrupt" "0,1"
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|
bitfld.long 0x00 1. "IE0,Interrupt line 0 enable 0h (R/W) = Disabled - Module interrupt INT0 is always low" "0,1"
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bitfld.long 0x00 0. "INIT,Initialization 0h (R/W) = Normal operation 1h (R/W) = Initialization mode is entered" "0,1"
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line.long 0x04 "DCAN_ES,"
|
|
rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge 0h (R) = DCAN is not in local power-down mode" "0,1"
|
|
rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "0,1"
|
|
bitfld.long 0x04 8. "PER,Single/Double bit error detected" "0,1"
|
|
rbitfld.long 0x04 7. "BOFF,Bus-Off state 0h (R) = The CAN module is not bus-off state" "0,1"
|
|
rbitfld.long 0x04 6. "EWARN,Warning state 0h (R) = Both error counters are below the error warning limit of 96" "0,1"
|
|
rbitfld.long 0x04 5. "EPASS,Error passive state 0h (R) = On CAN Bus error the DCAN could send active error frames" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 4. "RXOK,Received a message successfully" "0,1"
|
|
rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "0,1"
|
|
rbitfld.long 0x04 0.--2. "LEC,Last error code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "DCAN_ERRC,"
|
|
bitfld.long 0x08 15. "RP,Receive error passive 0h (R) = The receive error counter is below the error passive level" "0,1"
|
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hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x0C "DCAN_BTR,"
|
|
bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension.Valid programmed values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample pointValid programmed values are 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample pointValid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump WidthValid programmed values are 0 to 3" "0,1,2,3"
|
|
bitfld.long 0x0C 0.--5. "BRP,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DCAN_INT,"
|
|
hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt"
|
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hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt"
|
|
line.long 0x14 "DCAN_TEST,"
|
|
bitfld.long 0x14 9. "RDA,RAM direct access enable 0h (R/W) = Normal operation 1h (R/W) = Direct access to the RAM is enabled while in test mode" "0,1"
|
|
bitfld.long 0x14 8. "EXL,External loopback mode" "0,1"
|
|
rbitfld.long 0x14 7. "RX,Receive pin" "0,1"
|
|
bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "0,1,2,3"
|
|
bitfld.long 0x14 4. "LBACK,Loopback mode" "0,1"
|
|
bitfld.long 0x14 3. "SILENT,Silent mode 0h (R/W) = Disabled 1h (R/W) = Enabled" "0,1"
|
|
rgroup.long 0x1C++0x17
|
|
line.long 0x00 "DCAN_PERR,"
|
|
bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)"
|
|
line.long 0x04 "DCAN_REL,"
|
|
line.long 0x08 "DCAN_ECCDIAG,"
|
|
bitfld.long 0x08 0.--3. "ECCDIAG,SECDED diagnostic mode enable/disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "DCAN_ECCDIAG_STAT,"
|
|
bitfld.long 0x0C 8. "DEFLG_DIAG,Double bit error flag diagnostic" "0,1"
|
|
bitfld.long 0x0C 0. "SEFLG_DIAG,Single bit error flag diagnostic" "0,1"
|
|
line.long 0x10 "DCAN_ECC_CS,"
|
|
bitfld.long 0x10 24.--27. "SBE_EVT_EN,Enable/disable SECDED single bit error event (CAN_SERR signal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. "ECCMODE,Enable/disable SECDED single bit error correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8. "DEFLG,Double bit error flag" "0,1"
|
|
bitfld.long 0x10 0. "SEFLG,Single bit error flag" "0,1"
|
|
line.long 0x14 "DCAN_ECC_SERR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "MESSAGE_NUMBER,Message object number where ECC single bit error has been detected"
|
|
group.long 0x80++0x53
|
|
line.long 0x00 "DCAN_ABOTR,"
|
|
line.long 0x04 "DCAN_TXRQ_X,"
|
|
bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x08 "DCAN_TXRQ12,"
|
|
line.long 0x0C "DCAN_TXRQ34,"
|
|
line.long 0x10 "DCAN_TXRQ56,"
|
|
line.long 0x14 "DCAN_TXRQ78,"
|
|
line.long 0x18 "DCAN_NWDAT_X,"
|
|
bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x1C "DCAN_NWDAT12,"
|
|
line.long 0x20 "DCAN_NWDAT34,"
|
|
line.long 0x24 "DCAN_NWDAT56,"
|
|
line.long 0x28 "DCAN_NWDAT78,"
|
|
line.long 0x2C "DCAN_INTPND_X,"
|
|
bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x30 "DCAN_INTPND12,"
|
|
line.long 0x34 "DCAN_INTPND34,"
|
|
line.long 0x38 "DCAN_INTPND56,"
|
|
line.long 0x3C "DCAN_INTPND78,"
|
|
line.long 0x40 "DCAN_MSGVAL_X,"
|
|
bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3"
|
|
bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3"
|
|
line.long 0x44 "DCAN_MSGVAL12,"
|
|
line.long 0x48 "DCAN_MSGVAL34,"
|
|
line.long 0x4C "DCAN_MSGVAL56,"
|
|
line.long 0x50 "DCAN_MSGVAL78,"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "DCAN_INTMUX12,"
|
|
line.long 0x04 "DCAN_INTMUX34,"
|
|
line.long 0x08 "DCAN_INTMUX56,"
|
|
line.long 0x0C "DCAN_INTMUX78,"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "DCAN_IF1CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF1 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF1 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF1.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF1MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF1ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF1MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF1DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF1DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "DCAN_IF2CMD,"
|
|
bitfld.long 0x00 23. "WR_RD,Write/Read 0h (R/W) = Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF2 register set" "0,1"
|
|
bitfld.long 0x00 22. "MASK,Access mask bits 0h (R/W) = Mask bits will not be changed 1h (R/W) = Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF2 register set to the message object addressed by MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 21. "ARB,Access arbitration bits 0h (R/W) = Arbitration bits will not be changed 1h (R/W) = Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF2 register set to the message object addressed by.." "0,1"
|
|
bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the 0h (R/W) = Control bits will not be changed 1h (R/W) = Direction = Write: The message control bits will be transferred from the IF2.." "0,1"
|
|
bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit 0h (R/W) = IntPnd bit will not be changed 1h (R/W) = Direction = Write: This bit is ignored" "0,1"
|
|
bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in 0h (R/W) = Direction = Read:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "0,1"
|
|
bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7-0] MESSAGE_NUMBER" "0,1"
|
|
bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 update The DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers"
|
|
line.long 0x04 "DCAN_IF2MSK,"
|
|
bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
bitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R/W) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF2ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R/W) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended identifier 0h (R/W) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message direction 0h (R/W) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28-0]: 29-bit identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF2MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New data 0h (R/W) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive) 0h (R/W) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt pending 0h (R/W) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMask bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive interrupt enable 0h (R/W) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R/W) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit request 0h (R/W) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF2DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF2DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "DCAN_IF3OBS,"
|
|
rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data 0h (R) = No new data has been loaded since last IF3" "0,1"
|
|
rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access 0h (R) = All Data B bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access 0h (R) = All Data A bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access 0h (R) = All control section bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access 0h (R) = All Arbitration data bytes are already read out or are not marked to be read" "0,1"
|
|
rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access 0h (R) = All mask data bytes are already read out or are not marked to be read" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DATAB,Data B read observation 0h (R/W) = Data B section has not to be read" "0,1"
|
|
bitfld.long 0x00 3. "DATAA,Data A read observation 0h (R/W) = Data A section has not to be read" "0,1"
|
|
bitfld.long 0x00 2. "CTRL,Ctrl read observation 0h (R/W) = Ctrl section has not to be read" "0,1"
|
|
bitfld.long 0x00 1. "ARB,Arbitration data read observation 0h (R/W) = Arbitration data has not to be read" "0,1"
|
|
bitfld.long 0x00 0. "MASK,Mask data read observation 0h (R/W) = Mask data has not to be read" "0,1"
|
|
line.long 0x04 "DCAN_IF3MSK,"
|
|
rbitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ( standard ) identifiers are used for a message object the identifiers of received data frames are written into bits ID[28-18]" "0,1"
|
|
rbitfld.long 0x04 30. "MDIR,Mask Message Direction 0h (R) = The message direction bit (Dir) has no effect on the acceptance filtering" "0,1"
|
|
hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask 0h (R/W) = The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care)"
|
|
line.long 0x08 "DCAN_IF3ARB,"
|
|
bitfld.long 0x08 31. "MSGVAL,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the 0h (R) = The message object is ignored by the message handler" "0,1"
|
|
bitfld.long 0x08 30. "XTD,Extended Identifier 0h (R) = The 11-bit (standard) Identifier is used for this message object" "0,1"
|
|
bitfld.long 0x08 29. "DIR,Message Direction 0h (R) = Direction = receive: On TxRqst a remote frame with the identifier of this message object is transmitted" "0,1"
|
|
hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28-0]: 29-bit Identifier (extended frame)"
|
|
line.long 0x0C "DCAN_IF3MCTL,"
|
|
bitfld.long 0x0C 15. "NEWDAT,New Data 0h (R) = No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software" "0,1"
|
|
bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive) 0h (R) = No message lost since the last time when this bit was reset by the software" "0,1"
|
|
bitfld.long 0x0C 13. "INTPND,Interrupt Pending 0h (R) = This message object is not the source of an interrupt" "0,1"
|
|
bitfld.long 0x0C 12. "UMASK,Use Acceptance MaskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "0,1"
|
|
bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable 0h (R) = IntPnd will not be triggered after the successful transmission of a frame" "0,1"
|
|
bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable 0h (R) = IntPnd will not be triggered after the successful reception of a frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RMTEN,Remote enable 0h (R) = At the reception of a remote frame TxRqst is not changed" "0,1"
|
|
bitfld.long 0x0C 8. "TXRQST,Transmit Request 0h (R) = This message object is not waiting for a transmission" "0,1"
|
|
bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "0,1"
|
|
bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DCAN_IF3DATA,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0"
|
|
line.long 0x14 "DCAN_IF3DATB,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4"
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "DCAN_IF3UPD12,"
|
|
line.long 0x04 "DCAN_IF3UPD34,"
|
|
line.long 0x08 "DCAN_IF3UPD56,"
|
|
line.long 0x0C "DCAN_IF3UPD78,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DISPC_COMMON"
|
|
base ad:0x2550000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "DISPC_REVISION,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,TI internal data"
|
|
line.long 0x04 "DISPC_SYSCONFIG,"
|
|
bitfld.long 0x04 12.--13. "MIDLEMODE,Master interface power management standby/wait control 0h (R/W) = Force-standby.MStandby is only asserted when the module is disabled" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3"
|
|
bitfld.long 0x04 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0h (R/W) = OCP and Functional clocks can be switched off 1h (R/W) = Functional clocks can be switched off and OCP clocks are mantained during wake up period 2h (R/W) = OCP clocks can be switched.." "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3"
|
|
bitfld.long 0x04 5. "WARMRESET,Warm reset" "WARMRESET_0,WARMRESET_1"
|
|
newline
|
|
bitfld.long 0x04 3.--4. "SIDLEMODE,Slave interface power management Idle req/ack control 0h (R/W) = Force-idle.An idle request is acknowledged unconditionally 1h (R/W) = No-idle" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
|
|
bitfld.long 0x04 2. "ENWAKEUP,WakeUp feature control" "ENWAKEUP_0,ENWAKEUP_1"
|
|
bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
|
|
newline
|
|
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy 0h (R/W) = OCP clock is free-running 1h (R/W) = Automatic OCP clocks gating strategy is applied based on the OCP interface activity" "AUTOIDLE_0,AUTOIDLE_1"
|
|
line.long 0x08 "DISPC_SYSSTATUS,"
|
|
bitfld.long 0x08 1. "DISPC_VP1_RESETDONE,Reset status of DISPC VP1 pixel clock domain 0h (R) = Internal module reset is on-going 1h (R) = Reset completed" "0,1"
|
|
bitfld.long 0x08 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain 0h (R) = Internal module reset is on-going 1h (R) = Reset completed" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "DISPC_IRQ_EOI,"
|
|
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1"
|
|
line.long 0x04 "DISPC_IRQSTATUS_RAW,"
|
|
bitfld.long 0x04 13. "WAKEUP_IRQ,Wake-up" "0,1"
|
|
bitfld.long 0x04 7. "VID1_IRQ,VID1 IRQ STATUS register indicates the video pipeline 1 interrupt events 0h (R/W) = No event pending 1h (R/W) = IRQ event pending" "0,1"
|
|
bitfld.long 0x04 0. "VP1_IRQ,VP1 IRQ STATUS register indicates the Video Port 1 interrupt events 0h (R/W) = No event pending 1h (R/W) = IRQ event pending" "0,1"
|
|
line.long 0x08 "DISPC_IRQSTATUS,"
|
|
bitfld.long 0x08 13. "WAKEUP_IRQ,Wake-up" "WAKEUP_IRQ_0,WAKEUP_IRQ_1"
|
|
bitfld.long 0x08 7. "VID1_IRQ,VID1 IRQ STATUS register indicates the video pipeline 1 interrupt events 0h (R/W) = No event pending 1h (R/W) = IRQ event pending" "0,1"
|
|
bitfld.long 0x08 0. "VP1_IRQ,VP1 IRQ STATUS register indicates the Video Port 1 interrupt events 0h (R/W) = No event pending 1h (R/W) = IRQ event pending" "0,1"
|
|
line.long 0x0C "DISPC_IRQENABLE_SET,"
|
|
bitfld.long 0x0C 13. "SET_WAKEUP_IRQ,Wake Up Mask" "0,1"
|
|
bitfld.long 0x0C 7. "SET_VID1_IRQ,VID1 IRQ 0h (R/W) = interrupt disabled 1h (R/W) = interrupt enabled" "0,1"
|
|
bitfld.long 0x0C 0. "SET_VP1_IRQ,VP1 IRQ 0h (R/W) = interrupt disabled 1h (R/W) = interrupt enabled" "0,1"
|
|
line.long 0x10 "DISPC_IRQENABLE_CLR,"
|
|
bitfld.long 0x10 13. "CLR_WAKEUP_IRQ,Wake Up Mask" "0,1"
|
|
bitfld.long 0x10 7. "CLR_VID1_IRQ,VID1 IRQ 0h (R/W) = interrupt disabled 1h (R/W) = interrupt enabled" "0,1"
|
|
bitfld.long 0x10 0. "CLR_VP1_IRQ,VP1 IRQ 0h (R/W) = interrupt disabled 1h (R/W) = interrupt enabled" "0,1"
|
|
line.long 0x14 "DISPC_IRQWAKEEN,"
|
|
bitfld.long 0x14 7. "VID1_IRQWAKEEN,Wakeupen for VID1 first level interrupt" "0,1"
|
|
bitfld.long 0x14 0. "VP1_IRQWAKEEN,Wakeupen for VP1 first level interrupt" "0,1"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "DISPC_GLOBAL_MFLAG_ATTRIBUTE,"
|
|
bitfld.long 0x00 2. "MFLAG_START,0h (R/W) = reset value when the DMA buffer is empty at the beginning of the frame the MFLAG of each pipe is kept at 0 until PRELOAD is reached then based on MFLAG_CTRL MFLAG[1:0] are generated and internal logic is arbitrating between.." "0,1"
|
|
bitfld.long 0x00 0.--1. "MFLAG_CTRL,0h (R/W) = MFLAG mechanism is disabled: MFLAG[1:0] out band signals are set to 0 1h (R/W) = MFLAG mechanism is enabled: MFLAG[1:0] out band signals are always set to 1 2h (R/W) = MFLAG mechanism is enabled and MFLAG[1:0] out band signals are.." "0,1,2,3"
|
|
line.long 0x04 "DISPC_GLOBAL_BUFFER,"
|
|
bitfld.long 0x04 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "0,1"
|
|
bitfld.long 0x04 9.--11. "VID1_BUFFER,Video1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "DISPC_BA0_FLIPIMMEDIATE_EN,"
|
|
group.long 0x4C++0x0B
|
|
line.long 0x00 "DISPC_DBG_CONTROL,"
|
|
hexmask.long.byte 0x00 1.--8. 1. "DBGMUXSEL,0h (R/W) = Select first [31:0] bits of VID-1 debug bus 1h (R/W) = Select first [63:32] bits of VID-1 debug bus 2h (R/W) = Select first [95:64] bits of VID-1 debug bus 3h (R/W) = Select first [127:96] bits of VID-1 debug bus 4h (R/W) = Select.."
|
|
bitfld.long 0x00 0. "DBGEN,Enable debug ports 0h (R/W) = DBGDIS 1h (R/W) = DBGEN" "0,1"
|
|
line.long 0x04 "DISPC_DBG_STATUS,"
|
|
line.long 0x08 "DISPC_CLKGATING_DISABLE,"
|
|
bitfld.long 0x08 23. "VP1,Clock gating control for VP1 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 19. "OVR1,Clock gating control for OVR1 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 9. "VID1,Clock gating control for VID1 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "DMA_CH8,Clock gating control for DMA Channel-8 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 7. "DMA_CH7,Clock gating control for DMA Channel-7 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 6. "DMA_CH6,Clock gating control for DMA Channel-6 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "DMA_CH5,Clock gating control for DMA Channel-5 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 4. "DMA_CH4,Clock gating control for DMA Channel-4 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 3. "DMA_CH3,Clock gating control for DMA Channel-3 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "DMA_CH2,Clock gating control for DMA Channel-2 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 1. "DMA_CH1,Clock gating control for DMA Channel-1 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
bitfld.long 0x08 0. "DMA_COMMON,Clock gating control for DMA_COMMON module 0h (R/W) = Clock-Gating is enabled 1h (R/W) = Clock-gating is disabled" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DISPC_OVR1"
|
|
base ad:0x255A800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DISPC_OVR1_CONFIG,"
|
|
bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency Color Key Selection Shadow bit-field" "0,1"
|
|
bitfld.long 0x00 10. "TCKLCDENABLE,Transparency Color Key Enabled Shadow bit-field" "0,1"
|
|
bitfld.long 0x00 8.--9. "INTERLEAVED3DMODE,Define which layer contributes to odd/even lines of the line interleaving 3D format 0h (R/W) = No interleaving happens in the overlay manager 1h (R/W) = RESERVED 2h (R/W) = At even lines (all pixels) have a contribution from even.." "0,1,2,3"
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "DISPC_OVR1_DEFAULT_COLOR,"
|
|
line.long 0x04 "DISPC_OVR1_DEFAULT_COLOR2,"
|
|
hexmask.long.word 0x04 0.--15. 1. "DEFAULTCOLOR,48-bit ARGB color value to specify the default solid color to display when there is no data from the overlays"
|
|
line.long 0x08 "DISPC_OVR1_TRANS_COLOR_MAX,"
|
|
line.long 0x0C "DISPC_OVR1_TRANS_COLOR_MAX2,"
|
|
bitfld.long 0x0C 0.--3. "TRANSCOLORKEY,[35-32] Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DISPC_OVR1_TRANS_COLOR_MIN,"
|
|
line.long 0x14 "DISPC_OVR1_TRANS_COLOR_MIN2,"
|
|
bitfld.long 0x14 0.--3. "TRANSCOLORKEY,[35-32] Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DISPC_VID1"
|
|
base ad:0x2557000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DISPC_VID1_ACCUH_0,"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DISPC_VID1_ACCUH2_0,"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DISPC_VID1_ACCUV_0,"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DISPC_VID1_ACCUV2_0,"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DISPC_VID1_ATTRIBUTES,"
|
|
bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "0,1"
|
|
bitfld.long 0x00 25.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "layer above solid background color and below..,layer above layer with z-order value of 0 and..,layer above layers with z-order value of 0 and 1..,layer above layers with z-order value of 0 1 and..,layer above layers with z-order value of 0 1 2..,layer above all the other layers except cursor,?..."
|
|
newline
|
|
bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1"
|
|
bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1"
|
|
newline
|
|
bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1"
|
|
bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "VERTICALTAPS_0,VERTICALTAPS_1"
|
|
newline
|
|
bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value 0h (R/W) = H/W prefetches pixels up to the preload value defined in the preload register 1h (R/W) = H/W prefetches pixels up to high threshold value" "BUFPRELOAD_0,BUFPRELOAD_1"
|
|
bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode 0h (R/W) = The transition from SELFREFRESH <disabled> to <enabled> is controlled by SW" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1"
|
|
newline
|
|
bitfld.long 0x00 14.--16. "CHANNELOUT,Video Channel Out configuration wr: immediate 0h (R/W) = OVR1 (VP1) Others = Reserved" "CHANNELOUT_0,CHANNELOUT_1,?,?,?,?,?,?"
|
|
bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1"
|
|
newline
|
|
bitfld.long 0x00 10. "NIBBLEMODE,Video Nibble mode (only for 1- 2- and 4-bpp) 0h (R/W) = Nibble mode is disabled 1h (R/W) = Nibble mode is enabled" "0,1"
|
|
bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "RESIZEENABLE,Video Resize Enable 0h (R/W) = Disable both horizontal and vertical resize processing 1h (R/W) = Enable the horizontal resize processing 2h (R/W) = Enable the vertical resize processing 3h (R/W) = Enable both horizontal and vertical resize.." "RESIZEENABLE_0,RESIZEENABLE_1,?,?"
|
|
bitfld.long 0x00 1.--6. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Video pipeline Enable 0h (R/W) = Video disabled (video pipeline inactive and window not present) 1h (R/W) = Video enabled (video pipeline active and window present on the screen)" "ENABLE_0,ENABLE_1"
|
|
line.long 0x04 "DISPC_VID1_ATTRIBUTES2,"
|
|
bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 24. "REGION_BASED,Enable region-based mechanism 0h (R/W) = DISABLE 1h (R/W) = ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1"
|
|
bitfld.long 0x04 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "VC1_RANGE_CBCR_0,VC1_RANGE_CBCR_1,VC1_RANGE_CBCR_2,VC1_RANGE_CBCR_3,VC1_RANGE_CBCR_4,VC1_RANGE_CBCR_5,VC1_RANGE_CBCR_6,VC1_RANGE_CBCR_7"
|
|
newline
|
|
bitfld.long 0x04 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7"
|
|
bitfld.long 0x04 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1"
|
|
line.long 0x08 "DISPC_VID1_BA_0,"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DISPC_VID1_BA_UV_0,"
|
|
rgroup.long 0x38++0x53
|
|
line.long 0x00 "DISPC_VID1_BUF_SIZE_STATUS,"
|
|
hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits"
|
|
line.long 0x04 "DISPC_VID1_BUF_THRESHOLD,"
|
|
hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,Video DMA buffer High Threshold"
|
|
hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold"
|
|
line.long 0x08 "DISPC_VID1_CONV_COEF0,"
|
|
hexmask.long.word 0x08 16.--26. 1. "RCR,RCr Coefficient Encoded signed value (from -1024 to 1023)"
|
|
hexmask.long.word 0x08 0.--10. 1. "RY,RY Coefficient Encoded signed value (from -1024 to 1023)"
|
|
line.long 0x0C "DISPC_VID1_CONV_COEF1,"
|
|
hexmask.long.word 0x0C 16.--26. 1. "GY,GY Coefficient Encoded signed value (from -1024 to 1023)"
|
|
hexmask.long.word 0x0C 0.--10. 1. "RCB,RCb Coefficient Encoded signed value (from -1024 to 1023)"
|
|
line.long 0x10 "DISPC_VID1_CONV_COEF2,"
|
|
hexmask.long.word 0x10 16.--26. 1. "GCB,GCb Coefficient Encoded signed value (from -1024 to 1023)"
|
|
hexmask.long.word 0x10 0.--10. 1. "GCR,GCr Coefficient Encoded signed value (from -1024 to 1023)"
|
|
line.long 0x14 "DISPC_VID1_CONV_COEF3,"
|
|
hexmask.long.word 0x14 16.--26. 1. "BCR,BCr coefficient Encoded signed value (from -1024 to 1023)"
|
|
hexmask.long.word 0x14 0.--10. 1. "BY,BY coefficient Encoded signed value (from -1024 to 1023)"
|
|
line.long 0x18 "DISPC_VID1_CONV_COEF4,"
|
|
hexmask.long.word 0x18 0.--10. 1. "BCB,BCb Coefficient Encoded signed value (from -1024 to 1023)"
|
|
line.long 0x1C "DISPC_VID1_CONV_COEF5,"
|
|
hexmask.long.word 0x1C 19.--31. 1. "GOFFSET,G offset Encoded signed value (from -4096 to 4095)"
|
|
hexmask.long.word 0x1C 3.--15. 1. "ROFFSET,R offset Encoded signed value (from -4096 to 4095)"
|
|
line.long 0x20 "DISPC_VID1_CONV_COEF6,"
|
|
hexmask.long.word 0x20 3.--15. 1. "BOFFSET,B offset Encoded signed value (from -4096 to 4095)"
|
|
line.long 0x24 "DISPC_VID1_FIRH,"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter"
|
|
line.long 0x28 "DISPC_VID1_FIRH2,"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr"
|
|
line.long 0x2C "DISPC_VID1_FIRV,"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter"
|
|
line.long 0x30 "DISPC_VID1_FIRV2,"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr"
|
|
line.long 0x34 "DISPC_VID1_FIR_COEF_H0_0,"
|
|
hexmask.long.word 0x34 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x38 "DISPC_VID1_FIR_COEF_H0_1,"
|
|
hexmask.long.word 0x38 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x3C "DISPC_VID1_FIR_COEF_H0_2,"
|
|
hexmask.long.word 0x3C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x40 "DISPC_VID1_FIR_COEF_H0_3,"
|
|
hexmask.long.word 0x40 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x44 "DISPC_VID1_FIR_COEF_H0_4,"
|
|
hexmask.long.word 0x44 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x48 "DISPC_VID1_FIR_COEF_H0_5,"
|
|
hexmask.long.word 0x48 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x4C "DISPC_VID1_FIR_COEF_H0_6,"
|
|
hexmask.long.word 0x4C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x50 "DISPC_VID1_FIR_COEF_H0_7,"
|
|
hexmask.long.word 0x50 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
group.long 0x90++0x1F
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H0_C_0,"
|
|
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_H0_C_1,"
|
|
hexmask.long.word 0x04 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_H0_C_2,"
|
|
hexmask.long.word 0x08 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_H0_C_3,"
|
|
hexmask.long.word 0x0C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_H0_C_4,"
|
|
hexmask.long.word 0x10 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_H0_C_5,"
|
|
hexmask.long.word 0x14 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_H0_C_6,"
|
|
hexmask.long.word 0x18 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_H0_C_7,"
|
|
hexmask.long.word 0x1C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
|
|
group.long 0xB4++0x3B
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H12_0,"
|
|
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_H12_1,"
|
|
hexmask.long.word 0x04 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x04 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_H12_2,"
|
|
hexmask.long.word 0x08 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x08 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_H12_3,"
|
|
hexmask.long.word 0x0C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x0C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_H12_4,"
|
|
hexmask.long.word 0x10 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x10 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_H12_5,"
|
|
hexmask.long.word 0x14 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x14 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_H12_6,"
|
|
hexmask.long.word 0x18 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x18 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_H12_7,"
|
|
hexmask.long.word 0x1C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x1C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x20 "DISPC_VID1_FIR_COEF_H12_8,"
|
|
hexmask.long.word 0x20 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x20 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x24 "DISPC_VID1_FIR_COEF_H12_9,"
|
|
hexmask.long.word 0x24 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x24 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x28 "DISPC_VID1_FIR_COEF_H12_10,"
|
|
hexmask.long.word 0x28 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x28 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x2C "DISPC_VID1_FIR_COEF_H12_11,"
|
|
hexmask.long.word 0x2C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x2C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x30 "DISPC_VID1_FIR_COEF_H12_12,"
|
|
hexmask.long.word 0x30 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x30 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x34 "DISPC_VID1_FIR_COEF_H12_13,"
|
|
hexmask.long.word 0x34 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x34 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x38 "DISPC_VID1_FIR_COEF_H12_14,"
|
|
hexmask.long.word 0x38 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x38 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
group.long 0xF4++0x3B
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H12_C_0,"
|
|
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_H12_C_1,"
|
|
hexmask.long.word 0x04 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x04 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_H12_C_2,"
|
|
hexmask.long.word 0x08 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x08 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_H12_C_3,"
|
|
hexmask.long.word 0x0C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x0C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_H12_C_4,"
|
|
hexmask.long.word 0x10 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x10 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_H12_C_5,"
|
|
hexmask.long.word 0x14 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x14 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_H12_C_6,"
|
|
hexmask.long.word 0x18 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x18 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_H12_C_7,"
|
|
hexmask.long.word 0x1C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x1C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x20 "DISPC_VID1_FIR_COEF_H12_C_8,"
|
|
hexmask.long.word 0x20 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x20 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x24 "DISPC_VID1_FIR_COEF_H12_C_9,"
|
|
hexmask.long.word 0x24 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x24 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x28 "DISPC_VID1_FIR_COEF_H12_C_10,"
|
|
hexmask.long.word 0x28 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x28 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x2C "DISPC_VID1_FIR_COEF_H12_C_11,"
|
|
hexmask.long.word 0x2C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x2C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x30 "DISPC_VID1_FIR_COEF_H12_C_12,"
|
|
hexmask.long.word 0x30 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x30 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x34 "DISPC_VID1_FIR_COEF_H12_C_13,"
|
|
hexmask.long.word 0x34 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x34 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
line.long 0x38 "DISPC_VID1_FIR_COEF_H12_C_14,"
|
|
hexmask.long.word 0x38 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
|
|
hexmask.long.word 0x38 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
|
|
group.long 0x134++0x1F
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V0_0,"
|
|
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_V0_1,"
|
|
hexmask.long.word 0x04 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_V0_2,"
|
|
hexmask.long.word 0x08 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_V0_3,"
|
|
hexmask.long.word 0x0C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_V0_4,"
|
|
hexmask.long.word 0x10 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_V0_5,"
|
|
hexmask.long.word 0x14 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_V0_6,"
|
|
hexmask.long.word 0x18 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_V0_7,"
|
|
hexmask.long.word 0x1C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
group.long 0x158++0x1F
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V0_C_0,"
|
|
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_V0_C_1,"
|
|
hexmask.long.word 0x04 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_V0_C_2,"
|
|
hexmask.long.word 0x08 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_V0_C_3,"
|
|
hexmask.long.word 0x0C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_V0_C_4,"
|
|
hexmask.long.word 0x10 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_V0_C_5,"
|
|
hexmask.long.word 0x14 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_V0_C_6,"
|
|
hexmask.long.word 0x18 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_V0_C_7,"
|
|
hexmask.long.word 0x1C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
|
|
group.long 0x17C++0x3B
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V12_0,"
|
|
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_V12_1,"
|
|
hexmask.long.word 0x04 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x04 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_V12_2,"
|
|
hexmask.long.word 0x08 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x08 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_V12_3,"
|
|
hexmask.long.word 0x0C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x0C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_V12_4,"
|
|
hexmask.long.word 0x10 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x10 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_V12_5,"
|
|
hexmask.long.word 0x14 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x14 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_V12_6,"
|
|
hexmask.long.word 0x18 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x18 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_V12_7,"
|
|
hexmask.long.word 0x1C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x1C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x20 "DISPC_VID1_FIR_COEF_V12_8,"
|
|
hexmask.long.word 0x20 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x20 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x24 "DISPC_VID1_FIR_COEF_V12_9,"
|
|
hexmask.long.word 0x24 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x24 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x28 "DISPC_VID1_FIR_COEF_V12_10,"
|
|
hexmask.long.word 0x28 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x28 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x2C "DISPC_VID1_FIR_COEF_V12_11,"
|
|
hexmask.long.word 0x2C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x2C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x30 "DISPC_VID1_FIR_COEF_V12_12,"
|
|
hexmask.long.word 0x30 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x30 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x34 "DISPC_VID1_FIR_COEF_V12_13,"
|
|
hexmask.long.word 0x34 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x34 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x38 "DISPC_VID1_FIR_COEF_V12_14,"
|
|
hexmask.long.word 0x38 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x38 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
group.long 0x1BC++0x3B
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_V12_C_0,"
|
|
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x04 "DISPC_VID1_FIR_COEF_V12_C_1,"
|
|
hexmask.long.word 0x04 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x04 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x08 "DISPC_VID1_FIR_COEF_V12_C_2,"
|
|
hexmask.long.word 0x08 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x08 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x0C "DISPC_VID1_FIR_COEF_V12_C_3,"
|
|
hexmask.long.word 0x0C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x0C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x10 "DISPC_VID1_FIR_COEF_V12_C_4,"
|
|
hexmask.long.word 0x10 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x10 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x14 "DISPC_VID1_FIR_COEF_V12_C_5,"
|
|
hexmask.long.word 0x14 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x14 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x18 "DISPC_VID1_FIR_COEF_V12_C_6,"
|
|
hexmask.long.word 0x18 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x18 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x1C "DISPC_VID1_FIR_COEF_V12_C_7,"
|
|
hexmask.long.word 0x1C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x1C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x20 "DISPC_VID1_FIR_COEF_V12_C_8,"
|
|
hexmask.long.word 0x20 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x20 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x24 "DISPC_VID1_FIR_COEF_V12_C_9,"
|
|
hexmask.long.word 0x24 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x24 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x28 "DISPC_VID1_FIR_COEF_V12_C_10,"
|
|
hexmask.long.word 0x28 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x28 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x2C "DISPC_VID1_FIR_COEF_V12_C_11,"
|
|
hexmask.long.word 0x2C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x2C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x30 "DISPC_VID1_FIR_COEF_V12_C_12,"
|
|
hexmask.long.word 0x30 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x30 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x34 "DISPC_VID1_FIR_COEF_V12_C_13,"
|
|
hexmask.long.word 0x34 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x34 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
line.long 0x38 "DISPC_VID1_FIR_COEF_V12_C_14,"
|
|
hexmask.long.word 0x38 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
|
|
hexmask.long.word 0x38 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
|
|
group.long 0x1FC++0x2B
|
|
line.long 0x00 "DISPC_VID1_GLOBAL_ALPHA,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255"
|
|
line.long 0x04 "DISPC_VID1_IRQENABLE,"
|
|
bitfld.long 0x04 3. "VIDREGIONBASEDPIPEEND_EN,PIPE end window IRQ for region-based feature 0h (R/W) = VIDREGIONBASEDPIPEEND is masked 1h (R/W) = VIDREGIONBASEDPIPEEND generates an interrupt when it occurs" "0,1"
|
|
bitfld.long 0x04 2. "VIDREGIONBASEDPIPESTART_EN,PIPE start window IRQ for region-based feature 0h (R/W) = VIDREGIONBASEDPIPESTART is masked 1h (R/W) = VIDREGIONBASEDPIPESTART generates an interrupt when it occurs" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "VIDENDWINDOW_EN,The end of the video Window has been reached" "0,1"
|
|
bitfld.long 0x04 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "0,1"
|
|
line.long 0x08 "DISPC_VID1_IRQSTATUS,"
|
|
bitfld.long 0x08 3. "VIDREGIONBASEDPIPEEND_IRQ,PIPE end window IRQ for region-based feature 0h (R/W) = READS: Event is false" "0,1"
|
|
bitfld.long 0x08 2. "VIDREGIONBASEDPIPESTART_IRQ,PIPE start window IRQ for region-based feature 0h (R/W) = READS: Event is false" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "VIDENDWINDOW_IRQ,The end of the video Window has been reached" "0,1"
|
|
bitfld.long 0x08 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "0,1"
|
|
line.long 0x0C "DISPC_VID1_MFLAG_THRESHOLD,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1"
|
|
line.long 0x10 "DISPC_VID1_PICTURE_SIZE,"
|
|
hexmask.long.word 0x10 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus one)"
|
|
hexmask.long.word 0x10 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 4096) to specify the number of pixels of the video picture in memory (program to value minus one)"
|
|
line.long 0x14 "DISPC_VID1_PIXEL_INC,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels"
|
|
line.long 0x18 "DISPC_VID1_POSITION,"
|
|
hexmask.long.word 0x18 16.--27. 1. "POSY,Y position of the video window Encoded value (from 0 to 4095) to specify the Y position of the video window #1 .The line at the top has the Y-position 0"
|
|
hexmask.long.word 0x18 0.--11. 1. "POSX,X position of the video window Encoded value (from 0 to 4095) to specify the X position of the video window #1"
|
|
line.long 0x1C "DISPC_VID1_PRELOAD,"
|
|
hexmask.long.word 0x1C 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value"
|
|
line.long 0x20 "DISPC_VID1_ROW_INC,"
|
|
line.long 0x24 "DISPC_VID1_SIZE,"
|
|
hexmask.long.word 0x24 16.--27. 1. "SIZEY,Number of lines of the video window"
|
|
hexmask.long.word 0x24 0.--11. 1. "SIZEX,Number of pixels of the video window"
|
|
line.long 0x28 "DISPC_VID1_CLUT,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored"
|
|
hexmask.long.byte 0x28 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX"
|
|
hexmask.long.byte 0x28 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DISPC_VP1"
|
|
base ad:0x255AC00
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DISPC_VP1_CONFIG,"
|
|
bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "0,1"
|
|
bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "0,1"
|
|
bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1"
|
|
bitfld.long 0x00 21. "BT1120ENABLE,Selects BT-1120 format on the VP output" "0,1"
|
|
bitfld.long 0x00 20. "BT656ENABLE,Selects BT-656 format on the VP output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BUFFERHANDSHAKE,Controls the handshake between DMA buffer and STALL signal in order to prevent from underflow" "0,1"
|
|
bitfld.long 0x00 15. "CPR,Color Phase Rotation Control VP output). It shall be reset when ColorConvEnable bit-field is set to 1. Shadow bit-field. 0h (R/W) = Color Phase Rotation Disabled 1h (R/W) = Color Phase Rotation Enabled" "0,1"
|
|
bitfld.long 0x00 8. "EXTERNALSYNCEN,Selects between external sync and internal sync mode for the VP output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled (VP output) Shadow bit-field" "0,1"
|
|
bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled (VP output) Shadow bit-field" "0,1"
|
|
bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled (VP output) Shadow bit-field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PIXELDATAGATED,Pixel Data Gated Enabled (VP output) Shadow bit-field" "0,1"
|
|
bitfld.long 0x00 3. "HDMIMODE,Configures the timing generator in HDMI compatible mode to generate same timings as HDMI wrapper timings" "0,1"
|
|
bitfld.long 0x00 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1"
|
|
bitfld.long 0x00 0. "PIXELGATED,Pixel Gated Enable Shadow bit-field" "0,1"
|
|
line.long 0x04 "DISPC_VP1_CONTROL,"
|
|
bitfld.long 0x04 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output" "0,1,2,3"
|
|
bitfld.long 0x04 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the VP output" "0,1,2,3"
|
|
bitfld.long 0x04 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the VP output" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 21.--22. "TDMPARALLELMODE,Output Interface width (TDM mode only) for the VP output" "0,1,2,3"
|
|
bitfld.long 0x04 20. "TDMENABLE,Enable the multiple cycle format for the VP output" "0,1"
|
|
bitfld.long 0x04 14.--16. "HT,Hold Time for VP output" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 11. "STALLMODE,STALL Mode for the VP output" "0,1"
|
|
bitfld.long 0x04 8.--10. "DATALINES,Width of the data bus on VP output" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "GOBIT,GO Command for the VP output" "0,1"
|
|
bitfld.long 0x04 4. "M8B,Mono 8-bit mode of the primary LCD 0h (R/W) = Pixel data [3:0] is used to output four pixel values to the panel at each pixel clock transition" "0,1"
|
|
bitfld.long 0x04 3. "STN,LCD Display type of the primary LCD 0h (R/W) = Passive or STN display operation disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "MONOCOLOR,Monochrome/Color selection for the primary LCD 0h (R/W) = Color operation enabled (STN mode only) 1h (R/W) = Monochrome operation enabled (STN mode only)" "0,1"
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|
bitfld.long 0x04 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation 0h (R/W) = Disable modulo 1h (R/W) = Enable Modulo" "0,1"
|
|
bitfld.long 0x04 0. "VPENABLE,Enable the video port output wr:immediate 0h (R/W) = VP output disabled (at the end of the frame when the bit is reset) 1h (R/W) = VP output enabled" "0,1"
|
|
line.long 0x08 "DISPC_VP1_CPR_COEF_B,"
|
|
hexmask.long.word 0x08 22.--31. 1. "BR,BR Coefficient Encoded signed value (from -512 to 511)"
|
|
hexmask.long.word 0x08 11.--20. 1. "BG,BG Coefficient Encoded signed value (from -512 to 511)"
|
|
hexmask.long.word 0x08 0.--9. 1. "BB,BB Coefficient Encoded signed value (from -512 to 511)"
|
|
line.long 0x0C "DISPC_VP1_CPR_COEF_G,"
|
|
hexmask.long.word 0x0C 22.--31. 1. "GR,GR Coefficient Encoded signed value (from -512 to 511)"
|
|
hexmask.long.word 0x0C 11.--20. 1. "GG,GG Coefficient Encoded signed value (from -512 to 511)"
|
|
hexmask.long.word 0x0C 0.--9. 1. "GB,GB Coefficient Encoded signed value (from -512 to 511)"
|
|
line.long 0x10 "DISPC_VP1_CPR_COEF_R,"
|
|
hexmask.long.word 0x10 22.--31. 1. "RR,RR Coefficient Encoded signed value (from -512 to 511)"
|
|
hexmask.long.word 0x10 11.--20. 1. "RG,RG Coefficient Encoded signed value (from -512 to 511)"
|
|
hexmask.long.word 0x10 0.--9. 1. "RB,RB Coefficient Encoded signed value (from -512 to 511)"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DISPC_VP1_DATA_CYCLE_0,"
|
|
bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DISPC_VP1_DATA_CYCLE_1,"
|
|
bitfld.long 0x04 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DISPC_VP1_GAMMA_TABLE,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored"
|
|
hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit value used to defined the value to be stored in the gamma table"
|
|
hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit value used to defined the value to be stored in the gamma table"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit value used to defined the value to be stored in the gamma table"
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "DISPC_VP1_IRQENABLE,"
|
|
bitfld.long 0x00 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero 0h (R/W) = ACBIASCOUNTSTATUS for the primary LCD output is masked 1h (R/W) = ACBIASCOUNTSTATUS for the primary LCD output generates an interrupt when it occurs" "0,1"
|
|
bitfld.long 0x00 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
|
|
bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
|
|
bitfld.long 0x00 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
|
|
bitfld.long 0x00 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
|
|
line.long 0x04 "DISPC_VP1_IRQSTATUS,"
|
|
bitfld.long 0x04 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero 0h (R/W) = READS: Event is false" "0,1"
|
|
bitfld.long 0x04 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
|
|
bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field from interlace mode only" "0,1"
|
|
bitfld.long 0x04 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
|
|
bitfld.long 0x04 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
|
|
line.long 0x08 "DISPC_VP1_LINE_NUMBER,"
|
|
hexmask.long.word 0x08 0.--11. 1. "LINENUMBER,Display panel line number programming"
|
|
group.long 0x4C++0x0F
|
|
line.long 0x00 "DISPC_VP1_POL_FREQ,"
|
|
bitfld.long 0x00 18. "ALIGN,Defines the alignment betwwen HSYNC and VSYNC assertion" "0,1"
|
|
bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off 0h (R/W) = HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 1h (R/W) = HSYNC and VSYNC are driven according to bit 16" "0,1"
|
|
bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC Rise or Fall 0h (R/W) = HSYNC and VSYNC are driven on falling edge of pixel clock (if bit 17 set to 1) 1h (R/W) = HSYNC and VSYNC are driven on rising edge of pixel clock (if bit 17 set to 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IEO,Invert output enable 0h (R/W) = Ac-bias is active high (active display mode) 1h (R/W) = Ac-bias is active low (active display mode)" "0,1"
|
|
bitfld.long 0x00 14. "IPC,Invert pixel clock 0h (R/W) = Data is driven on the VP data lines on the rising-edge of the pixel clock 1h (R/W) = Data is driven on the VP data lines on the falling-edge of the pixel clock" "0,1"
|
|
bitfld.long 0x00 13. "IHS,Invert HSYNC 0h (R/W) = Line clock pin is active high and inactive low 1h (R/W) = Line clock pin is active low and inactive high" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "IVS,Invert VSYNC 0h (R/W) = Frame clock pin is active high and inactive low 1h (R/W) = Frame clock pin is active low and inactive high" "0,1"
|
|
bitfld.long 0x00 8.--11. "ACBI,AC Bias Pin transitions per interrupt 0h (R/W) = Line clock pin is active high and inactive low 1h (R/W) = Line clock pin is active low and inactive high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ACB,AC Bias Pin Frequency 0h (R/W) = Line clock pin is active high and inactive low 1h (R/W) = Line clock pin is active low and inactive high"
|
|
line.long 0x04 "DISPC_VP1_SIZE_SCREEN,"
|
|
hexmask.long.word 0x04 16.--27. 1. "LPP,Lines per panel Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus one)"
|
|
bitfld.long 0x04 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field 0h (R/W) = same size 1h (R/W) = odd size = even size +1 2h (R/W) = Odd size = even size -1" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--11. 1. "PPL,Pixels per line Encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus one)"
|
|
line.long 0x08 "DISPC_VP1_TIMING_H,"
|
|
hexmask.long.word 0x08 20.--31. 1. "HBP,Horizontal Back Porch"
|
|
hexmask.long.word 0x08 8.--19. 1. "HFP,Horizontal front porch"
|
|
hexmask.long.byte 0x08 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line display (program to value minus one)"
|
|
line.long 0x0C "DISPC_VP1_TIMING_V,"
|
|
hexmask.long.word 0x0C 20.--31. 1. "VBP,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame"
|
|
hexmask.long.word 0x0C 8.--19. 1. "VFP,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value (from 1 to 256) to specify the number of line clock periods to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DSSUL_0_CFG"
|
|
base ad:0x2540000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DSS_REVISION,"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "DSS_SYSCONFIG,"
|
|
bitfld.long 0x00 0.--1. "SIDLEMODE,0h (R/W) = Force-idle" "0,1,2,3"
|
|
line.long 0x04 "DSS_SYSSTATUS,"
|
|
bitfld.long 0x04 7. "RFBI_RESETDONE,Reset status of RFBI module 0h (R) = Internal module reset is on-going 1h (R) = Reset completed" "0,1"
|
|
bitfld.long 0x04 0. "DSS_RESETDONE,Reset status of DISPC/DSS 0h (R) = Internal module reset is on-going 1h (R) = Reset completed" "0,1"
|
|
line.long 0x08 "DSS_RFBI_CTRL,"
|
|
bitfld.long 0x08 0. "RFBI_ENABLE,RFBI Enable" "0,1"
|
|
line.long 0x0C "DSS_DPI_CTRL,"
|
|
bitfld.long 0x0C 0. "DPI_ENABLE,Enable DPI interface" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DSS_DEBUG_CFG,"
|
|
bitfld.long 0x00 0.--2. "CFG,Defines which debug bus to provide on the DSS debug bus connected at the top" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
tree "eCAP"
|
|
repeat 2. (list 0. 1.)(list ad:0x21D1800 ad:0x21D1C00)
|
|
tree "ECAP_$1"
|
|
base $2
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PWMSS_ECAP_TSCNT,"
|
|
line.long 0x04 "PWMSS_ECAP_CNTPHS,"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "PWMSS_ECAP_CAP1,"
|
|
line.long 0x04 "PWMSS_ECAP_CAP2,"
|
|
line.long 0x08 "PWMSS_ECAP_CAP3,"
|
|
line.long 0x0C "PWMSS_ECAP_CAP4,"
|
|
group.word 0x28++0x0B
|
|
line.word 0x00 "PWMSS_ECAP_ECCTL1,"
|
|
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 8. "CAPLDEN,Enable Loading of" "0,1"
|
|
bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x02 "PWMSS_ECAP_ECCTL2,"
|
|
bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "Output is active high (Compare value defines..,Output is active low (Compare value defines low.."
|
|
bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select 1" "0,1"
|
|
newline
|
|
bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1"
|
|
bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x02 5. "SYNCI_EN," "0,1"
|
|
bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "TSCNT stopped,TSCNT free-running"
|
|
newline
|
|
bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "Has no effect (reading always returns a 0),Arms the one-shot sequence as follows"
|
|
bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "Stop after Capture Event 1 in one-shot mode,Stop after Capture Event 2 in one-shot mode,Stop after Capture Event 3 in one-shot mode,Stop after Capture Event 4 in one-shot mode"
|
|
newline
|
|
bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "Operate in continuous mode,Operate in one-shot mode"
|
|
line.word 0x04 "PWMSS_ECAP_ECEINT,"
|
|
bitfld.word 0x04 7. "CMPEQ,Counter Equal Interrupt" "0,1"
|
|
bitfld.word 0x04 6. "PRDEQ,Counter Equal Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "Disable counter Overflow as an Interrupt source,Enable counter Overflow as an Interrupt source"
|
|
bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "Disable Capture Event 4 as an Interrupt source,Enable Capture Event 4 as an Interrupt source"
|
|
newline
|
|
bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "Disable Capture Event 3 as an Interrupt source,Enable Capture Event 3 as an Interrupt source"
|
|
bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "Disable Capture Event 2 as an Interrupt source,Enable Capture Event 2 as an Interrupt source"
|
|
newline
|
|
bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "Disable Capture Event 1 as an Interrupt source,Enable Capture Event 1 as an Interrupt source"
|
|
line.word 0x06 "PWMSS_ECAP_ECFLG,"
|
|
bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the.."
|
|
bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the period.."
|
|
newline
|
|
bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) has made the.."
|
|
bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "Indicates no event occurred,Indicates the fourth event occurred at ECAPn pin"
|
|
newline
|
|
bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "Indicates no event occurred,Indicates the third event occurred at ECAPn pin"
|
|
bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "Indicates no event occurred,Indicates the second event occurred at ECAPn pin"
|
|
newline
|
|
bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "Indicates no event occurred,Indicates the first event occurred at ECAPn pin"
|
|
bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "Indicates no interrupt generated,Indicates that an interrupt was generated"
|
|
line.word 0x08 "PWMSS_ECAP_ECCLR,"
|
|
bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=CMP flag condition"
|
|
bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=PRD flag condition"
|
|
newline
|
|
bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CNTOVF flag condition"
|
|
bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition"
|
|
newline
|
|
bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition"
|
|
bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT2 flag condition"
|
|
newline
|
|
bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT1 flag condition"
|
|
bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "Writing a 0 has no effect,Writing a 1 clears the INT flag and enable.."
|
|
line.word 0x0A "PWMSS_ECAP_ECFRC,"
|
|
bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "No effect,Writing a 1 sets the TSCNT=CMP flag bit"
|
|
bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "No effect,Writing a 1 sets the TSCNT=PRD flag bit"
|
|
newline
|
|
bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "No effect,Writing a 1 to this bit sets the CNTOVF flag bit"
|
|
bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "No effect,Writing a 1 sets the CEVT4 flag bit"
|
|
newline
|
|
bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "No effect,Writing a 1 sets the CEVT3 flag bit"
|
|
bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "No effect,Writing a 1 sets the CEVT2 flag bit"
|
|
newline
|
|
bitfld.word 0x0A 1. "CEVT1,Force Capture Event 1" "No effect,Writing a 1 sets the CEVT1 flag bit"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "PWMSS_ECAP_PID,"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "EDMA"
|
|
tree "EDMACC_0"
|
|
base ad:0x2700000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EDMACC_PID,"
|
|
line.long 0x04 "EDMACC_CCCFG,"
|
|
bitfld.long 0x04 25. "MP_EXIST,Memory protection" "0,1"
|
|
bitfld.long 0x04 24. "CHMAP_EXIST,Channel mapping" "0,1"
|
|
newline
|
|
bitfld.long 0x04 20.--21. "NUM_REGN,Number of MP and shadow regions.0h" "?,?,Reserved,8 regions"
|
|
bitfld.long 0x04 16.--18. "NUM_EVQUE,Number of queues/number of TCs.0h = Reserved" "?,2 EDMATCs/Event Queues,Reserved,4 EDMATCs/Event Queues,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "NUM_PAENTRY,Number of PaRAM sets.0h" "?,?,Reserved,128 PaRAM sets,Reserved,512 PaRAM sets,?,Reserved"
|
|
bitfld.long 0x04 8.--10. "NUM_INTCH,Number of interrupt" "?,Reserved,16 interrupt channels,Reserved,64 interrupt channels,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x04 4.--6. "NUM_QDMACH,Number of QDMA" "?,?,?,Reserved,8 QDMA channels,?,?,Reserved"
|
|
bitfld.long 0x04 0.--2. "NUM_DMACH,Number of DMA" "?,?,Reserved,16 DMA channels,Reserved,64 DMA channels,?,Reserved"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "EDMACC_QDMAQNUM,"
|
|
bitfld.long 0x00 28.--30. "E7,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 24.--26. "E6,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "E5,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 16.--18. "E4,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "E3,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 8.--10. "E2,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "E1,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 0.--2. "E0,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "EDMACC_QUETCMAP,"
|
|
bitfld.long 0x00 12.--14. "TCNUMQ3,TC number for queue 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "TCNUMQ2,TC number for queue 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TCNUMQ1,TC number for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TCNUMQ0,TC number for queue 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "EDMACC_QUEPRI,"
|
|
bitfld.long 0x04 12.--14. "PRIQ3,Priority level for queue 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. "PRIQ2,Priority level for queue 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 4.--6. "PRIQ1,Priority level for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. "PRIQ0,Priority level for queue 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x23
|
|
line.long 0x00 "EDMACC_EMR,"
|
|
line.long 0x04 "EDMACC_EMRH,"
|
|
line.long 0x08 "EDMACC_EMCR,"
|
|
line.long 0x0C "EDMACC_EMCRH,"
|
|
line.long 0x10 "EDMACC_QEMR,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "QEMR7_QEMR0,Channel 7-0 QDMA event missed.0h = No missed event"
|
|
line.long 0x14 "EDMACC_QEMCR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "QEMCR7_QEMCR0,QDMA event missed clear"
|
|
line.long 0x18 "EDMACC_CCERR,"
|
|
bitfld.long 0x18 16. "TCCERR,Transfer completion code error" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
|
|
bitfld.long 0x18 3. "QTHRXCD3,Queue threshold error for queue 3" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x18 2. "QTHRXCD2,Queue threshold error for queue 2" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
bitfld.long 0x18 1. "QTHRXCD1,Queue threshold error for queue 1" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x18 0. "QTHRXCD0,Queue threshold error for queue 0" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
line.long 0x1C "EDMACC_CCERRCLR,"
|
|
bitfld.long 0x1C 16. "TCCERR,Transfer completion code error" "0,1"
|
|
bitfld.long 0x1C 3. "QTHRXCD3,Queue threshold error clear for queue" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "QTHRXCD2,Queue threshold error clear for queue" "0,1"
|
|
bitfld.long 0x1C 1. "QTHRXCD1,Queue threshold error clear for queue" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "QTHRXCD0,Queue threshold error clear for queue" "0,1"
|
|
line.long 0x20 "EDMACC_EEVAL,"
|
|
bitfld.long 0x20 1. "SET,Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior" "0,1"
|
|
bitfld.long 0x20 0. "EVAL,Error interrupt" "0,1"
|
|
group.long 0x340++0x3F
|
|
line.long 0x00 "EDMACC_DRAE0,"
|
|
line.long 0x04 "EDMACC_DRAEH0,"
|
|
line.long 0x08 "EDMACC_DRAE1,"
|
|
line.long 0x0C "EDMACC_DRAEH1,"
|
|
line.long 0x10 "EDMACC_DRAE2,"
|
|
line.long 0x14 "EDMACC_DRAEH2,"
|
|
line.long 0x18 "EDMACC_DRAE3,"
|
|
line.long 0x1C "EDMACC_DRAEH3,"
|
|
line.long 0x20 "EDMACC_DRAE4,"
|
|
line.long 0x24 "EDMACC_DRAEH4,"
|
|
line.long 0x28 "EDMACC_DRAE5,"
|
|
line.long 0x2C "EDMACC_DRAEH5,"
|
|
line.long 0x30 "EDMACC_DRAE6,"
|
|
line.long 0x34 "EDMACC_DRAEH6,"
|
|
line.long 0x38 "EDMACC_DRAE7,"
|
|
line.long 0x3C "EDMACC_DRAEH7,"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "EDMACC_QWMTHRA,"
|
|
bitfld.long 0x00 24.--28. "Q3,Queue threshold for queue 3 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
bitfld.long 0x00 16.--20. "Q2,Queue threshold for queue 2 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "Q1,Queue threshold for queue 1 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
bitfld.long 0x00 0.--4. "Q0,Queue threshold for queue 0 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "EDMACC_CCSTAT,"
|
|
bitfld.long 0x00 19. "QUEACTV3,Queue 3" "0,1"
|
|
bitfld.long 0x00 18. "QUEACTV2,Queue 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "QUEACTV1,Queue 1" "0,1"
|
|
bitfld.long 0x00 16. "QUEACTV0,Queue 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "COMPACTV,Completion request active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. "ACTV,Channel controller active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WSTATACTV,Write status interface" "0,1"
|
|
bitfld.long 0x00 2. "TRACTV,Transfer request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "QEVTACTV,QDMA event" "0,1"
|
|
bitfld.long 0x00 0. "EVTACTV,DMA event" "0,1"
|
|
rgroup.long 0x800++0x0F
|
|
line.long 0x00 "EDMACC_MPFAR,"
|
|
line.long 0x04 "EDMACC_MPFSR,"
|
|
bitfld.long 0x04 9.--12. "FID,Faulted identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 5. "SRE,Supervisor read" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "SWE,Supervisor write" "0,1"
|
|
bitfld.long 0x04 3. "SXE,Supervisor execute" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "URE,User" "0,1"
|
|
bitfld.long 0x04 1. "UWE,User" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "UXE,User execute" "0,1"
|
|
line.long 0x08 "EDMACC_MPFCR,"
|
|
bitfld.long 0x08 0. "MPFCLR,Fault clear register.0h = DSP write of 0 has no effect" "0,1"
|
|
line.long 0x0C "EDMACC_MPPAG,"
|
|
bitfld.long 0x0C 10.--15. "AID5_AID0,Allowed ID" "Requests with Privilege ID == n are not allowed..,Requests with Privilege ID == n are permitted if..,?..."
|
|
bitfld.long 0x0C 9. "EXT,External Allowed ID.0h = Requests with Privilege ID >= 6 are not allowed to region m regardless of permission settings (UW UR SW SR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "SR,Supervisor read permission0h = Supervisor read accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x0C 4. "SW,Supervisor write permission.0h = Supervisor write accesses are not allowed to region" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "SX,Supervisor execute permission.0h = Supervisor execute accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x0C 2. "UR,User read permission.0h = User read accesses are not allowed from region" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "UW,User write permission.0h = User write accesses are not allowed to region" "0,1"
|
|
bitfld.long 0x0C 0. "UX,User execute permission.0h = User execute accesses are not allowed from region" "0,1"
|
|
rgroup.long 0x2000++0x47
|
|
line.long 0x00 "EDMACC_ER,"
|
|
line.long 0x04 "EDMACC_ERH,"
|
|
line.long 0x08 "EDMACC_ECR,"
|
|
line.long 0x0C "EDMACC_ECRH,"
|
|
line.long 0x10 "EDMACC_ESR,"
|
|
line.long 0x14 "EDMACC_ESRH,"
|
|
line.long 0x18 "EDMACC_CER,"
|
|
line.long 0x1C "EDMACC_CERH,"
|
|
line.long 0x20 "EDMACC_EER,"
|
|
line.long 0x24 "EDMACC_EERH,"
|
|
line.long 0x28 "EDMACC_EECR,"
|
|
line.long 0x2C "EDMACC_EECRH,"
|
|
line.long 0x30 "EDMACC_EESR,"
|
|
line.long 0x34 "EDMACC_EESRH,"
|
|
line.long 0x38 "EDMACC_SER,"
|
|
line.long 0x3C "EDMACC_SERH,"
|
|
line.long 0x40 "EDMACC_SECR,"
|
|
line.long 0x44 "EDMACC_SECRH,"
|
|
rgroup.long 0x2050++0x2B
|
|
line.long 0x00 "EDMACC_IER,"
|
|
line.long 0x04 "EDMACC_IERH,"
|
|
line.long 0x08 "EDMACC_IECR,"
|
|
line.long 0x0C "EDMACC_IECRH,"
|
|
line.long 0x10 "EDMACC_IESR,"
|
|
line.long 0x14 "EDMACC_IESRH,"
|
|
line.long 0x18 "EDMACC_IPR,"
|
|
line.long 0x1C "EDMACC_IPRH,"
|
|
line.long 0x20 "EDMACC_ICR,"
|
|
line.long 0x24 "EDMACC_ICRH,"
|
|
line.long 0x28 "EDMACC_IEVAL,"
|
|
bitfld.long 0x28 1. "SET,Always write 0" "0,1"
|
|
bitfld.long 0x28 0. "EVAL,Interrupt" "0,1"
|
|
rgroup.long 0x2080++0x17
|
|
line.long 0x00 "EDMACC_QER,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "QER7_QER0,QDMA event for channels"
|
|
line.long 0x04 "EDMACC_QEER,"
|
|
hexmask.long.byte 0x04 0.--7. 1. "QEER7_QEER0,QDMA event enable for channels"
|
|
line.long 0x08 "EDMACC_QEECR,"
|
|
hexmask.long.byte 0x08 0.--7. 1. "QEECR7_QEECR0,QDMA event enable clear for channels"
|
|
line.long 0x0C "EDMACC_QEESR,"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "QEESR7_QEESR0,QDMA event enable set for channels"
|
|
line.long 0x10 "EDMACC_QSER,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "QSER7_QSER0,QDMA secondary event register for channels"
|
|
line.long 0x14 "EDMACC_QSECR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "QSECR7_QSECR0,QDMA secondary event clear for channels"
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x810)++0x03
|
|
line.long 0x00 "EDMACC_MPPA$1,"
|
|
bitfld.long 0x00 10.--15. "AID5_AID0,Allowed ID" "Requests with Privilege ID == n are not allowed..,Requests with Privilege ID == n are permitted if..,?..."
|
|
bitfld.long 0x00 9. "EXT,External Allowed ID.0h = Requests with Privilege ID >= 6 are not allowed to region m regardless of permission settings (UW UR SW SR)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SR,Supervisor read permission0h = Supervisor read accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x00 4. "SW,Supervisor write permission.0h = Supervisor write accesses are not allowed to region" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SX,Supervisor execute permission.0h = Supervisor execute accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x00 2. "UR,User read permission.0h = User read accesses are not allowed from region" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UW,User write permission.0h = User write accesses are not allowed to region" "0,1"
|
|
bitfld.long 0x00 0. "UX,User execute permission.0h = User execute accesses are not allowed from region" "0,1"
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "EDMACC_QRAE$1,"
|
|
abitfld.long 0x00 0.--7. "QRAE7_QRAE0,QDMA region access enable for bit N/QDMA channel N in region" "0x00=Accesses via region,0x01=Accesses via region m address space to bit.."
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "EDMACC_DMAQNUM$1,"
|
|
bitfld.long 0x00 28.--30. "E_7_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 24.--26. "E_6_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "E_5_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 16.--18. "E_4_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "E_3_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 8.--10. "E_2_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "E_1_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 0.--2. "E_0_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "EDMACC_QCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for QDMA channel"
|
|
bitfld.long 0x00 2.--4. "TRWORD,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 15. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x140)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "EDMACC_1"
|
|
base ad:0x2728000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EDMACC_PID,"
|
|
line.long 0x04 "EDMACC_CCCFG,"
|
|
bitfld.long 0x04 25. "MP_EXIST,Memory protection" "0,1"
|
|
bitfld.long 0x04 24. "CHMAP_EXIST,Channel mapping" "0,1"
|
|
newline
|
|
bitfld.long 0x04 20.--21. "NUM_REGN,Number of MP and shadow regions.0h" "?,?,Reserved,8 regions"
|
|
bitfld.long 0x04 16.--18. "NUM_EVQUE,Number of queues/number of TCs.0h = Reserved" "?,2 EDMATCs/Event Queues,Reserved,4 EDMATCs/Event Queues,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "NUM_PAENTRY,Number of PaRAM sets.0h" "?,?,Reserved,128 PaRAM sets,Reserved,512 PaRAM sets,?,Reserved"
|
|
bitfld.long 0x04 8.--10. "NUM_INTCH,Number of interrupt" "?,Reserved,16 interrupt channels,Reserved,64 interrupt channels,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x04 4.--6. "NUM_QDMACH,Number of QDMA" "?,?,?,Reserved,8 QDMA channels,?,?,Reserved"
|
|
bitfld.long 0x04 0.--2. "NUM_DMACH,Number of DMA" "?,?,Reserved,16 DMA channels,Reserved,64 DMA channels,?,Reserved"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "EDMACC_QDMAQNUM,"
|
|
bitfld.long 0x00 28.--30. "E7,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 24.--26. "E6,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "E5,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 16.--18. "E4,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "E3,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 8.--10. "E2,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "E1,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 0.--2. "E0,QDMA queue number" "?,Event,Event,Event,?,?,?,Reserved"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "EDMACC_QUETCMAP,"
|
|
bitfld.long 0x00 12.--14. "TCNUMQ3,TC number for queue 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "TCNUMQ2,TC number for queue 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TCNUMQ1,TC number for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TCNUMQ0,TC number for queue 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "EDMACC_QUEPRI,"
|
|
bitfld.long 0x04 12.--14. "PRIQ3,Priority level for queue 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. "PRIQ2,Priority level for queue 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 4.--6. "PRIQ1,Priority level for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. "PRIQ0,Priority level for queue 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x23
|
|
line.long 0x00 "EDMACC_EMR,"
|
|
line.long 0x04 "EDMACC_EMRH,"
|
|
line.long 0x08 "EDMACC_EMCR,"
|
|
line.long 0x0C "EDMACC_EMCRH,"
|
|
line.long 0x10 "EDMACC_QEMR,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "QEMR7_QEMR0,Channel 7-0 QDMA event missed.0h = No missed event"
|
|
line.long 0x14 "EDMACC_QEMCR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "QEMCR7_QEMCR0,QDMA event missed clear"
|
|
line.long 0x18 "EDMACC_CCERR,"
|
|
bitfld.long 0x18 16. "TCCERR,Transfer completion code error" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
|
|
bitfld.long 0x18 3. "QTHRXCD3,Queue threshold error for queue 3" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x18 2. "QTHRXCD2,Queue threshold error for queue 2" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
bitfld.long 0x18 1. "QTHRXCD1,Queue threshold error for queue 1" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x18 0. "QTHRXCD0,Queue threshold error for queue 0" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
|
|
line.long 0x1C "EDMACC_CCERRCLR,"
|
|
bitfld.long 0x1C 16. "TCCERR,Transfer completion code error" "0,1"
|
|
bitfld.long 0x1C 3. "QTHRXCD3,Queue threshold error clear for queue" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "QTHRXCD2,Queue threshold error clear for queue" "0,1"
|
|
bitfld.long 0x1C 1. "QTHRXCD1,Queue threshold error clear for queue" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "QTHRXCD0,Queue threshold error clear for queue" "0,1"
|
|
line.long 0x20 "EDMACC_EEVAL,"
|
|
bitfld.long 0x20 1. "SET,Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior" "0,1"
|
|
bitfld.long 0x20 0. "EVAL,Error interrupt" "0,1"
|
|
group.long 0x340++0x3F
|
|
line.long 0x00 "EDMACC_DRAE0,"
|
|
line.long 0x04 "EDMACC_DRAEH0,"
|
|
line.long 0x08 "EDMACC_DRAE1,"
|
|
line.long 0x0C "EDMACC_DRAEH1,"
|
|
line.long 0x10 "EDMACC_DRAE2,"
|
|
line.long 0x14 "EDMACC_DRAEH2,"
|
|
line.long 0x18 "EDMACC_DRAE3,"
|
|
line.long 0x1C "EDMACC_DRAEH3,"
|
|
line.long 0x20 "EDMACC_DRAE4,"
|
|
line.long 0x24 "EDMACC_DRAEH4,"
|
|
line.long 0x28 "EDMACC_DRAE5,"
|
|
line.long 0x2C "EDMACC_DRAEH5,"
|
|
line.long 0x30 "EDMACC_DRAE6,"
|
|
line.long 0x34 "EDMACC_DRAEH6,"
|
|
line.long 0x38 "EDMACC_DRAE7,"
|
|
line.long 0x3C "EDMACC_DRAEH7,"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "EDMACC_QWMTHRA,"
|
|
bitfld.long 0x00 24.--28. "Q3,Queue threshold for queue 3 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
bitfld.long 0x00 16.--20. "Q2,Queue threshold for queue 2 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "Q1,Queue threshold for queue 1 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
bitfld.long 0x00 0.--4. "Q0,Queue threshold for queue 0 value" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,The default is 16 (maximum allowed),Disables the threshold errors,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "EDMACC_CCSTAT,"
|
|
bitfld.long 0x00 19. "QUEACTV3,Queue 3" "0,1"
|
|
bitfld.long 0x00 18. "QUEACTV2,Queue 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "QUEACTV1,Queue 1" "0,1"
|
|
bitfld.long 0x00 16. "QUEACTV0,Queue 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "COMPACTV,Completion request active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. "ACTV,Channel controller active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WSTATACTV,Write status interface" "0,1"
|
|
bitfld.long 0x00 2. "TRACTV,Transfer request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "QEVTACTV,QDMA event" "0,1"
|
|
bitfld.long 0x00 0. "EVTACTV,DMA event" "0,1"
|
|
rgroup.long 0x800++0x0F
|
|
line.long 0x00 "EDMACC_MPFAR,"
|
|
line.long 0x04 "EDMACC_MPFSR,"
|
|
bitfld.long 0x04 9.--12. "FID,Faulted identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 5. "SRE,Supervisor read" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "SWE,Supervisor write" "0,1"
|
|
bitfld.long 0x04 3. "SXE,Supervisor execute" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "URE,User" "0,1"
|
|
bitfld.long 0x04 1. "UWE,User" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "UXE,User execute" "0,1"
|
|
line.long 0x08 "EDMACC_MPFCR,"
|
|
bitfld.long 0x08 0. "MPFCLR,Fault clear register.0h = DSP write of 0 has no effect" "0,1"
|
|
line.long 0x0C "EDMACC_MPPAG,"
|
|
bitfld.long 0x0C 10.--15. "AID5_AID0,Allowed ID" "Requests with Privilege ID == n are not allowed..,Requests with Privilege ID == n are permitted if..,?..."
|
|
bitfld.long 0x0C 9. "EXT,External Allowed ID.0h = Requests with Privilege ID >= 6 are not allowed to region m regardless of permission settings (UW UR SW SR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "SR,Supervisor read permission0h = Supervisor read accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x0C 4. "SW,Supervisor write permission.0h = Supervisor write accesses are not allowed to region" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "SX,Supervisor execute permission.0h = Supervisor execute accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x0C 2. "UR,User read permission.0h = User read accesses are not allowed from region" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "UW,User write permission.0h = User write accesses are not allowed to region" "0,1"
|
|
bitfld.long 0x0C 0. "UX,User execute permission.0h = User execute accesses are not allowed from region" "0,1"
|
|
rgroup.long 0x2000++0x47
|
|
line.long 0x00 "EDMACC_ER,"
|
|
line.long 0x04 "EDMACC_ERH,"
|
|
line.long 0x08 "EDMACC_ECR,"
|
|
line.long 0x0C "EDMACC_ECRH,"
|
|
line.long 0x10 "EDMACC_ESR,"
|
|
line.long 0x14 "EDMACC_ESRH,"
|
|
line.long 0x18 "EDMACC_CER,"
|
|
line.long 0x1C "EDMACC_CERH,"
|
|
line.long 0x20 "EDMACC_EER,"
|
|
line.long 0x24 "EDMACC_EERH,"
|
|
line.long 0x28 "EDMACC_EECR,"
|
|
line.long 0x2C "EDMACC_EECRH,"
|
|
line.long 0x30 "EDMACC_EESR,"
|
|
line.long 0x34 "EDMACC_EESRH,"
|
|
line.long 0x38 "EDMACC_SER,"
|
|
line.long 0x3C "EDMACC_SERH,"
|
|
line.long 0x40 "EDMACC_SECR,"
|
|
line.long 0x44 "EDMACC_SECRH,"
|
|
rgroup.long 0x2050++0x2B
|
|
line.long 0x00 "EDMACC_IER,"
|
|
line.long 0x04 "EDMACC_IERH,"
|
|
line.long 0x08 "EDMACC_IECR,"
|
|
line.long 0x0C "EDMACC_IECRH,"
|
|
line.long 0x10 "EDMACC_IESR,"
|
|
line.long 0x14 "EDMACC_IESRH,"
|
|
line.long 0x18 "EDMACC_IPR,"
|
|
line.long 0x1C "EDMACC_IPRH,"
|
|
line.long 0x20 "EDMACC_ICR,"
|
|
line.long 0x24 "EDMACC_ICRH,"
|
|
line.long 0x28 "EDMACC_IEVAL,"
|
|
bitfld.long 0x28 1. "SET,Always write 0" "0,1"
|
|
bitfld.long 0x28 0. "EVAL,Interrupt" "0,1"
|
|
rgroup.long 0x2080++0x17
|
|
line.long 0x00 "EDMACC_QER,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "QER7_QER0,QDMA event for channels"
|
|
line.long 0x04 "EDMACC_QEER,"
|
|
hexmask.long.byte 0x04 0.--7. 1. "QEER7_QEER0,QDMA event enable for channels"
|
|
line.long 0x08 "EDMACC_QEECR,"
|
|
hexmask.long.byte 0x08 0.--7. 1. "QEECR7_QEECR0,QDMA event enable clear for channels"
|
|
line.long 0x0C "EDMACC_QEESR,"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "QEESR7_QEESR0,QDMA event enable set for channels"
|
|
line.long 0x10 "EDMACC_QSER,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "QSER7_QSER0,QDMA secondary event register for channels"
|
|
line.long 0x14 "EDMACC_QSECR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "QSECR7_QSECR0,QDMA secondary event clear for channels"
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x810)++0x03
|
|
line.long 0x00 "EDMACC_MPPA$1,"
|
|
bitfld.long 0x00 10.--15. "AID5_AID0,Allowed ID" "Requests with Privilege ID == n are not allowed..,Requests with Privilege ID == n are permitted if..,?..."
|
|
bitfld.long 0x00 9. "EXT,External Allowed ID.0h = Requests with Privilege ID >= 6 are not allowed to region m regardless of permission settings (UW UR SW SR)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SR,Supervisor read permission0h = Supervisor read accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x00 4. "SW,Supervisor write permission.0h = Supervisor write accesses are not allowed to region" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SX,Supervisor execute permission.0h = Supervisor execute accesses are not allowed from region" "0,1"
|
|
bitfld.long 0x00 2. "UR,User read permission.0h = User read accesses are not allowed from region" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UW,User write permission.0h = User write accesses are not allowed to region" "0,1"
|
|
bitfld.long 0x00 0. "UX,User execute permission.0h = User execute accesses are not allowed from region" "0,1"
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "EDMACC_QRAE$1,"
|
|
abitfld.long 0x00 0.--7. "QRAE7_QRAE0,QDMA region access enable for bit N/QDMA channel N in region" "0x00=Accesses via region,0x01=Accesses via region m address space to bit.."
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "EDMACC_DMAQNUM$1,"
|
|
bitfld.long 0x00 28.--30. "E_7_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 24.--26. "E_6_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "E_5_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 16.--18. "E_4_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "E_3_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 8.--10. "E_2_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "E_1_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
bitfld.long 0x00 0.--2. "E_0_N_8,DMA queue number" "Event,Event,Event,Event,?,?,?,Reserved"
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "EDMACC_QCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for QDMA channel"
|
|
bitfld.long 0x00 2.--4. "TRWORD,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 15. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x140)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "EDMACC_DCHMAP$1,"
|
|
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,Points to the PaRAM set number for DMA channel"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "EDMACC_0_TC_0"
|
|
base ad:0x2760000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EDMATC_PID,"
|
|
line.long 0x04 "EDMATC_TCCFG,"
|
|
bitfld.long 0x04 8.--9. "DREGDEPTH,Destination register FIFO depth parameterization.0h" "?,Reserved,4 entry,Reserved"
|
|
bitfld.long 0x04 4.--5. "BUSWIDTH,Destination register FIFO depth parameterization.0h" "?,Reserved,128-bit,256-bit"
|
|
bitfld.long 0x04 0.--2. "FIFOSIZE,FIFO size.0h" "?,?,?,Reserved,512-byte FIFO,1024-byte FIFO,?,Reserved"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "EDMATC_TCSTAT,"
|
|
bitfld.long 0x00 11.--12. "DFSTRTPTR,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "DSTACTV,Destination active state" "?,Destination FIFO contains 1 TR,Destination FIFO contains 2 TRs,Destination FIFO contains 3 TRs,Destination FIFO contains 4 TRs,?,?,Reserved"
|
|
bitfld.long 0x00 2. "WSACTV,Write status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SRCACTV,Source active state.0h = Source controller is idle" "0,1"
|
|
bitfld.long 0x00 0. "PROGBUSY,Program register set" "0,1"
|
|
rgroup.long 0x120++0x13
|
|
line.long 0x00 "EDMATC_ERRSTAT,"
|
|
bitfld.long 0x00 3. "MMRAERR,MMR address" "0,1"
|
|
bitfld.long 0x00 2. "TRERR,Transfer request (TR) error" "0,1"
|
|
bitfld.long 0x00 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x04 "EDMATC_ERREN,"
|
|
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for MMR address error (MMRAERR).0h = MMRAERR is disabled" "0,1"
|
|
bitfld.long 0x04 2. "TRERR,Interrupt enable for transfer request error (TRERR).0h = TRERR is disabled" "0,1"
|
|
bitfld.long 0x04 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x08 "EDMATC_ERRCLR,"
|
|
bitfld.long 0x08 3. "MMRAERR,Interrupt enable clear for the MMRAERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the MMRAERR bit in"
|
|
bitfld.long 0x08 2. "TRERR,Interrupt enable clear for the TRERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the TRERR bit in"
|
|
bitfld.long 0x08 0. "BUSERR,Interrupt clear for the BUSERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the BUSERR bit in"
|
|
line.long 0x0C "EDMATC_ERRDET,"
|
|
bitfld.long 0x0C 17. "TCCHEN,Transfer completion chaining enable" "0,1"
|
|
bitfld.long 0x0C 16. "TCINTEN,Transfer completion interrupt enable" "0,1"
|
|
bitfld.long 0x0C 8.--13. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "STAT,Transaction status" "?,?,?,?,?,?,?,Read error,Fh = Write error,?..."
|
|
line.long 0x10 "EDMATC_ERRCMD,"
|
|
bitfld.long 0x10 1. "SET,Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior" "0,1"
|
|
bitfld.long 0x10 0. "EVAL,Error" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EDMATC_RDRATE,"
|
|
bitfld.long 0x00 0.--2. "RDRATE,Read rate" "?,4 cycles between reads,8 cycles between reads,16 cycles between reads,32 cycles between reads,?,?,Reserved"
|
|
group.long 0x240++0x23
|
|
line.long 0x00 "EDMATC_SAOPT,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_SASRC,"
|
|
line.long 0x08 "EDMATC_SACNT,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A dimension count"
|
|
line.long 0x0C "EDMATC_SADST,"
|
|
line.long 0x10 "EDMATC_SABIDX,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,B-Index offset between source arrays"
|
|
line.long 0x14 "EDMATC_SAMPPRXY,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "EDMATC_SACNTRLD,"
|
|
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x1C "EDMATC_SASRCBREF,"
|
|
line.long 0x20 "EDMATC_SADSTBREF,"
|
|
rgroup.long 0x280++0x0B
|
|
line.long 0x00 "EDMATC_DFCNTRLD,"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x04 "EDMATC_DFSRCBREF,"
|
|
line.long 0x08 "EDMATC_DFDSTBREF,"
|
|
group.long 0x300++0x17
|
|
line.long 0x00 "EDMATC_DFOPT0,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC0,"
|
|
line.long 0x08 "EDMATC_DFCNT0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST0,"
|
|
line.long 0x10 "EDMATC_DFBIDX0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY0,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x340++0x17
|
|
line.long 0x00 "EDMATC_DFOPT1,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC1,"
|
|
line.long 0x08 "EDMATC_DFCNT1,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST1,"
|
|
line.long 0x10 "EDMATC_DFBIDX1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY1,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x380++0x17
|
|
line.long 0x00 "EDMATC_DFOPT2,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC2,"
|
|
line.long 0x08 "EDMATC_DFCNT2,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST2,"
|
|
line.long 0x10 "EDMATC_DFBIDX2,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY2,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C0++0x17
|
|
line.long 0x00 "EDMATC_DFOPT3,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC3,"
|
|
line.long 0x08 "EDMATC_DFCNT3,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST3,"
|
|
line.long 0x10 "EDMATC_DFBIDX3,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY3,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EDMACC_0_TC_1"
|
|
base ad:0x2768000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EDMATC_PID,"
|
|
line.long 0x04 "EDMATC_TCCFG,"
|
|
bitfld.long 0x04 8.--9. "DREGDEPTH,Destination register FIFO depth parameterization.0h" "?,Reserved,4 entry,Reserved"
|
|
bitfld.long 0x04 4.--5. "BUSWIDTH,Destination register FIFO depth parameterization.0h" "?,Reserved,128-bit,256-bit"
|
|
bitfld.long 0x04 0.--2. "FIFOSIZE,FIFO size.0h" "?,?,?,Reserved,512-byte FIFO,1024-byte FIFO,?,Reserved"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "EDMATC_TCSTAT,"
|
|
bitfld.long 0x00 11.--12. "DFSTRTPTR,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "DSTACTV,Destination active state" "?,Destination FIFO contains 1 TR,Destination FIFO contains 2 TRs,Destination FIFO contains 3 TRs,Destination FIFO contains 4 TRs,?,?,Reserved"
|
|
bitfld.long 0x00 2. "WSACTV,Write status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SRCACTV,Source active state.0h = Source controller is idle" "0,1"
|
|
bitfld.long 0x00 0. "PROGBUSY,Program register set" "0,1"
|
|
rgroup.long 0x120++0x13
|
|
line.long 0x00 "EDMATC_ERRSTAT,"
|
|
bitfld.long 0x00 3. "MMRAERR,MMR address" "0,1"
|
|
bitfld.long 0x00 2. "TRERR,Transfer request (TR) error" "0,1"
|
|
bitfld.long 0x00 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x04 "EDMATC_ERREN,"
|
|
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for MMR address error (MMRAERR).0h = MMRAERR is disabled" "0,1"
|
|
bitfld.long 0x04 2. "TRERR,Interrupt enable for transfer request error (TRERR).0h = TRERR is disabled" "0,1"
|
|
bitfld.long 0x04 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x08 "EDMATC_ERRCLR,"
|
|
bitfld.long 0x08 3. "MMRAERR,Interrupt enable clear for the MMRAERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the MMRAERR bit in"
|
|
bitfld.long 0x08 2. "TRERR,Interrupt enable clear for the TRERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the TRERR bit in"
|
|
bitfld.long 0x08 0. "BUSERR,Interrupt clear for the BUSERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the BUSERR bit in"
|
|
line.long 0x0C "EDMATC_ERRDET,"
|
|
bitfld.long 0x0C 17. "TCCHEN,Transfer completion chaining enable" "0,1"
|
|
bitfld.long 0x0C 16. "TCINTEN,Transfer completion interrupt enable" "0,1"
|
|
bitfld.long 0x0C 8.--13. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "STAT,Transaction status" "?,?,?,?,?,?,?,Read error,Fh = Write error,?..."
|
|
line.long 0x10 "EDMATC_ERRCMD,"
|
|
bitfld.long 0x10 1. "SET,Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior" "0,1"
|
|
bitfld.long 0x10 0. "EVAL,Error" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EDMATC_RDRATE,"
|
|
bitfld.long 0x00 0.--2. "RDRATE,Read rate" "?,4 cycles between reads,8 cycles between reads,16 cycles between reads,32 cycles between reads,?,?,Reserved"
|
|
group.long 0x240++0x23
|
|
line.long 0x00 "EDMATC_SAOPT,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_SASRC,"
|
|
line.long 0x08 "EDMATC_SACNT,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A dimension count"
|
|
line.long 0x0C "EDMATC_SADST,"
|
|
line.long 0x10 "EDMATC_SABIDX,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,B-Index offset between source arrays"
|
|
line.long 0x14 "EDMATC_SAMPPRXY,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "EDMATC_SACNTRLD,"
|
|
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x1C "EDMATC_SASRCBREF,"
|
|
line.long 0x20 "EDMATC_SADSTBREF,"
|
|
rgroup.long 0x280++0x0B
|
|
line.long 0x00 "EDMATC_DFCNTRLD,"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x04 "EDMATC_DFSRCBREF,"
|
|
line.long 0x08 "EDMATC_DFDSTBREF,"
|
|
group.long 0x300++0x17
|
|
line.long 0x00 "EDMATC_DFOPT0,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC0,"
|
|
line.long 0x08 "EDMATC_DFCNT0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST0,"
|
|
line.long 0x10 "EDMATC_DFBIDX0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY0,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x340++0x17
|
|
line.long 0x00 "EDMATC_DFOPT1,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC1,"
|
|
line.long 0x08 "EDMATC_DFCNT1,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST1,"
|
|
line.long 0x10 "EDMATC_DFBIDX1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY1,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x380++0x17
|
|
line.long 0x00 "EDMATC_DFOPT2,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC2,"
|
|
line.long 0x08 "EDMATC_DFCNT2,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST2,"
|
|
line.long 0x10 "EDMATC_DFBIDX2,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY2,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C0++0x17
|
|
line.long 0x00 "EDMATC_DFOPT3,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC3,"
|
|
line.long 0x08 "EDMATC_DFCNT3,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST3,"
|
|
line.long 0x10 "EDMATC_DFBIDX3,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY3,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EDMACC_1_TC_0"
|
|
base ad:0x27B0000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EDMATC_PID,"
|
|
line.long 0x04 "EDMATC_TCCFG,"
|
|
bitfld.long 0x04 8.--9. "DREGDEPTH,Destination register FIFO depth parameterization.0h" "?,Reserved,4 entry,Reserved"
|
|
bitfld.long 0x04 4.--5. "BUSWIDTH,Destination register FIFO depth parameterization.0h" "?,Reserved,128-bit,256-bit"
|
|
bitfld.long 0x04 0.--2. "FIFOSIZE,FIFO size.0h" "?,?,?,Reserved,512-byte FIFO,1024-byte FIFO,?,Reserved"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "EDMATC_TCSTAT,"
|
|
bitfld.long 0x00 11.--12. "DFSTRTPTR,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "DSTACTV,Destination active state" "?,Destination FIFO contains 1 TR,Destination FIFO contains 2 TRs,Destination FIFO contains 3 TRs,Destination FIFO contains 4 TRs,?,?,Reserved"
|
|
bitfld.long 0x00 2. "WSACTV,Write status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SRCACTV,Source active state.0h = Source controller is idle" "0,1"
|
|
bitfld.long 0x00 0. "PROGBUSY,Program register set" "0,1"
|
|
rgroup.long 0x120++0x13
|
|
line.long 0x00 "EDMATC_ERRSTAT,"
|
|
bitfld.long 0x00 3. "MMRAERR,MMR address" "0,1"
|
|
bitfld.long 0x00 2. "TRERR,Transfer request (TR) error" "0,1"
|
|
bitfld.long 0x00 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x04 "EDMATC_ERREN,"
|
|
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for MMR address error (MMRAERR).0h = MMRAERR is disabled" "0,1"
|
|
bitfld.long 0x04 2. "TRERR,Interrupt enable for transfer request error (TRERR).0h = TRERR is disabled" "0,1"
|
|
bitfld.long 0x04 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x08 "EDMATC_ERRCLR,"
|
|
bitfld.long 0x08 3. "MMRAERR,Interrupt enable clear for the MMRAERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the MMRAERR bit in"
|
|
bitfld.long 0x08 2. "TRERR,Interrupt enable clear for the TRERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the TRERR bit in"
|
|
bitfld.long 0x08 0. "BUSERR,Interrupt clear for the BUSERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the BUSERR bit in"
|
|
line.long 0x0C "EDMATC_ERRDET,"
|
|
bitfld.long 0x0C 17. "TCCHEN,Transfer completion chaining enable" "0,1"
|
|
bitfld.long 0x0C 16. "TCINTEN,Transfer completion interrupt enable" "0,1"
|
|
bitfld.long 0x0C 8.--13. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "STAT,Transaction status" "?,?,?,?,?,?,?,Read error,Fh = Write error,?..."
|
|
line.long 0x10 "EDMATC_ERRCMD,"
|
|
bitfld.long 0x10 1. "SET,Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior" "0,1"
|
|
bitfld.long 0x10 0. "EVAL,Error" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EDMATC_RDRATE,"
|
|
bitfld.long 0x00 0.--2. "RDRATE,Read rate" "?,4 cycles between reads,8 cycles between reads,16 cycles between reads,32 cycles between reads,?,?,Reserved"
|
|
group.long 0x240++0x23
|
|
line.long 0x00 "EDMATC_SAOPT,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_SASRC,"
|
|
line.long 0x08 "EDMATC_SACNT,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A dimension count"
|
|
line.long 0x0C "EDMATC_SADST,"
|
|
line.long 0x10 "EDMATC_SABIDX,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,B-Index offset between source arrays"
|
|
line.long 0x14 "EDMATC_SAMPPRXY,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "EDMATC_SACNTRLD,"
|
|
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x1C "EDMATC_SASRCBREF,"
|
|
line.long 0x20 "EDMATC_SADSTBREF,"
|
|
rgroup.long 0x280++0x0B
|
|
line.long 0x00 "EDMATC_DFCNTRLD,"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x04 "EDMATC_DFSRCBREF,"
|
|
line.long 0x08 "EDMATC_DFDSTBREF,"
|
|
group.long 0x300++0x17
|
|
line.long 0x00 "EDMATC_DFOPT0,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC0,"
|
|
line.long 0x08 "EDMATC_DFCNT0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST0,"
|
|
line.long 0x10 "EDMATC_DFBIDX0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY0,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x340++0x17
|
|
line.long 0x00 "EDMATC_DFOPT1,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC1,"
|
|
line.long 0x08 "EDMATC_DFCNT1,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST1,"
|
|
line.long 0x10 "EDMATC_DFBIDX1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY1,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x380++0x17
|
|
line.long 0x00 "EDMATC_DFOPT2,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC2,"
|
|
line.long 0x08 "EDMATC_DFCNT2,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST2,"
|
|
line.long 0x10 "EDMATC_DFBIDX2,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY2,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C0++0x17
|
|
line.long 0x00 "EDMATC_DFOPT3,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC3,"
|
|
line.long 0x08 "EDMATC_DFCNT3,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST3,"
|
|
line.long 0x10 "EDMATC_DFBIDX3,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY3,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EDMACC_1_TC_1"
|
|
base ad:0x27B8000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "EDMATC_PID,"
|
|
line.long 0x04 "EDMATC_TCCFG,"
|
|
bitfld.long 0x04 8.--9. "DREGDEPTH,Destination register FIFO depth parameterization.0h" "?,Reserved,4 entry,Reserved"
|
|
bitfld.long 0x04 4.--5. "BUSWIDTH,Destination register FIFO depth parameterization.0h" "?,Reserved,128-bit,256-bit"
|
|
bitfld.long 0x04 0.--2. "FIFOSIZE,FIFO size.0h" "?,?,?,Reserved,512-byte FIFO,1024-byte FIFO,?,Reserved"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "EDMATC_TCSTAT,"
|
|
bitfld.long 0x00 11.--12. "DFSTRTPTR,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "DSTACTV,Destination active state" "?,Destination FIFO contains 1 TR,Destination FIFO contains 2 TRs,Destination FIFO contains 3 TRs,Destination FIFO contains 4 TRs,?,?,Reserved"
|
|
bitfld.long 0x00 2. "WSACTV,Write status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SRCACTV,Source active state.0h = Source controller is idle" "0,1"
|
|
bitfld.long 0x00 0. "PROGBUSY,Program register set" "0,1"
|
|
rgroup.long 0x120++0x13
|
|
line.long 0x00 "EDMATC_ERRSTAT,"
|
|
bitfld.long 0x00 3. "MMRAERR,MMR address" "0,1"
|
|
bitfld.long 0x00 2. "TRERR,Transfer request (TR) error" "0,1"
|
|
bitfld.long 0x00 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x04 "EDMATC_ERREN,"
|
|
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for MMR address error (MMRAERR).0h = MMRAERR is disabled" "0,1"
|
|
bitfld.long 0x04 2. "TRERR,Interrupt enable for transfer request error (TRERR).0h = TRERR is disabled" "0,1"
|
|
bitfld.long 0x04 0. "BUSERR,Bus error" "0,1"
|
|
line.long 0x08 "EDMATC_ERRCLR,"
|
|
bitfld.long 0x08 3. "MMRAERR,Interrupt enable clear for the MMRAERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the MMRAERR bit in"
|
|
bitfld.long 0x08 2. "TRERR,Interrupt enable clear for the TRERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the TRERR bit in"
|
|
bitfld.long 0x08 0. "BUSERR,Interrupt clear for the BUSERR bit in the error status register (EDMATC_ERRSTAT)" "No effect,Clears the BUSERR bit in"
|
|
line.long 0x0C "EDMATC_ERRDET,"
|
|
bitfld.long 0x0C 17. "TCCHEN,Transfer completion chaining enable" "0,1"
|
|
bitfld.long 0x0C 16. "TCINTEN,Transfer completion interrupt enable" "0,1"
|
|
bitfld.long 0x0C 8.--13. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "STAT,Transaction status" "?,?,?,?,?,?,?,Read error,Fh = Write error,?..."
|
|
line.long 0x10 "EDMATC_ERRCMD,"
|
|
bitfld.long 0x10 1. "SET,Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior" "0,1"
|
|
bitfld.long 0x10 0. "EVAL,Error" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EDMATC_RDRATE,"
|
|
bitfld.long 0x00 0.--2. "RDRATE,Read rate" "?,4 cycles between reads,8 cycles between reads,16 cycles between reads,32 cycles between reads,?,?,Reserved"
|
|
group.long 0x240++0x23
|
|
line.long 0x00 "EDMATC_SAOPT,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_SASRC,"
|
|
line.long 0x08 "EDMATC_SACNT,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A dimension count"
|
|
line.long 0x0C "EDMATC_SADST,"
|
|
line.long 0x10 "EDMATC_SABIDX,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,B-Index offset between source arrays"
|
|
line.long 0x14 "EDMATC_SAMPPRXY,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "EDMATC_SACNTRLD,"
|
|
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x1C "EDMATC_SASRCBREF,"
|
|
line.long 0x20 "EDMATC_SADSTBREF,"
|
|
rgroup.long 0x280++0x0B
|
|
line.long 0x00 "EDMATC_DFCNTRLD,"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-count reload value"
|
|
line.long 0x04 "EDMATC_DFSRCBREF,"
|
|
line.long 0x08 "EDMATC_DFDSTBREF,"
|
|
group.long 0x300++0x17
|
|
line.long 0x00 "EDMATC_DFOPT0,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC0,"
|
|
line.long 0x08 "EDMATC_DFCNT0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST0,"
|
|
line.long 0x10 "EDMATC_DFBIDX0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY0,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x340++0x17
|
|
line.long 0x00 "EDMATC_DFOPT1,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC1,"
|
|
line.long 0x08 "EDMATC_DFCNT1,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST1,"
|
|
line.long 0x10 "EDMATC_DFBIDX1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY1,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x380++0x17
|
|
line.long 0x00 "EDMATC_DFOPT2,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC2,"
|
|
line.long 0x08 "EDMATC_DFCNT2,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST2,"
|
|
line.long 0x10 "EDMATC_DFBIDX2,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY2,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C0++0x17
|
|
line.long 0x00 "EDMATC_DFOPT3,"
|
|
bitfld.long 0x00 22. "TCCHEN,Transfer completion chaining" "0,1"
|
|
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt" "0,1"
|
|
bitfld.long 0x00 12.--17. "TCC,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "FWID,FIFO width" "?,FIFO width is 16-bit,FIFO width is 32-bit,FIFO width is 64-bit,FIFO width is 128-bit,FIFO width is 256-bit,?,Reserved"
|
|
bitfld.long 0x00 4.--6. "PRI,Transfer priority.0h = Priority" "Highest priority,?,?,?,?,?,Priority 1 to priority 6,Lowest priority"
|
|
bitfld.long 0x00 1. "DAM,Destination address mode within an" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SAM,Source address mode within an" "0,1"
|
|
line.long 0x04 "EDMATC_DFSRC3,"
|
|
line.long 0x08 "EDMATC_DFCNT3,"
|
|
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-dimension count"
|
|
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-dimension count"
|
|
line.long 0x0C "EDMATC_DFDST3,"
|
|
line.long 0x10 "EDMATC_DFBIDX3,"
|
|
hexmask.long.word 0x10 16.--31. 1. "DSTBIDX,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRCBIDX,Always reads as 0"
|
|
line.long 0x14 "EDMATC_DFMPPRXY3,"
|
|
bitfld.long 0x14 8. "PRIV,Privilege level" "User-level privilege,Supervisor-level privilege"
|
|
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ELM"
|
|
base ad:0x21C8000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ELM_REVISION,"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "ELM_SYSCONFIG,"
|
|
bitfld.long 0x00 8. "CLOCKACTIVITYOCP,ELM_CLK activity when module is in IDLE mode 0h (R/W) = ELM_CLK can be switched off" "CLOCKACTIVITYOCP_0,CLOCKACTIVITYOCP_1"
|
|
bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE req/ack control) 0h (R/W) = Force-idle" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
|
|
bitfld.long 0x00 1. "SOFTRESET,Module software reset 0h (R/W) = Normal mode 1h (R/W) = Start soft reset sequence" "SOFTRESET_0,SOFTRESET_1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTOGATING,Internal ELM_CLK gating strategy 0h (R/W) = ELM_CLK is free-running" "AUTOGATING_0,AUTOGATING_1"
|
|
line.long 0x04 "ELM_SYSSTATUS,"
|
|
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring 0h (R) = Reset is ongoing" "RESETDONE_0,RESETDONE_1"
|
|
line.long 0x08 "ELM_IRQSTATUS,"
|
|
bitfld.long 0x08 8. "PAGE_VALID,Error-location status for a full page based on the mask definition" "PAGE_VALID_0,PAGE_VALID_1"
|
|
bitfld.long 0x08 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "LOC_VALID_7_0,LOC_VALID_7_1"
|
|
bitfld.long 0x08 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "LOC_VALID_6_0,LOC_VALID_6_1"
|
|
newline
|
|
bitfld.long 0x08 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "LOC_VALID_5_0,LOC_VALID_5_1"
|
|
bitfld.long 0x08 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "LOC_VALID_4_0,LOC_VALID_4_1"
|
|
bitfld.long 0x08 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "LOC_VALID_3_0,LOC_VALID_3_1"
|
|
newline
|
|
bitfld.long 0x08 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "LOC_VALID_2_0,LOC_VALID_2_1"
|
|
bitfld.long 0x08 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "LOC_VALID_1_0,LOC_VALID_1_1"
|
|
bitfld.long 0x08 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "LOC_VALID_0_0,LOC_VALID_0_1"
|
|
line.long 0x0C "ELM_IRQENABLE,"
|
|
bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "PAGE_MASK_0,PAGE_MASK_1"
|
|
bitfld.long 0x0C 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "LOCATION_MASK_7_0,LOCATION_MASK_7_1"
|
|
bitfld.long 0x0C 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "LOCATION_MASK_6_0,LOCATION_MASK_6_1"
|
|
newline
|
|
bitfld.long 0x0C 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "LOCATION_MASK_5_0,LOCATION_MASK_5_1"
|
|
bitfld.long 0x0C 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "LOCATION_MASK_4_0,LOCATION_MASK_4_1"
|
|
bitfld.long 0x0C 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "LOCATION_MASK_3_0,LOCATION_MASK_3_1"
|
|
newline
|
|
bitfld.long 0x0C 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "LOCATION_MASK_2_0,LOCATION_MASK_2_1"
|
|
bitfld.long 0x0C 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "LOCATION_MASK_1_0,LOCATION_MASK_1_1"
|
|
bitfld.long 0x0C 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "LOCATION_MASK_0_0,LOCATION_MASK_0_1"
|
|
line.long 0x10 "ELM_LOCATION_CONFIG,"
|
|
hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)"
|
|
bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "ECC_BCH_LEVEL_0,ECC_BCH_LEVEL_1,ECC_BCH_LEVEL_2,ECC_BCH_LEVEL_3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ELM_PAGE_CTRL,"
|
|
bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode" "SECTOR_7_0,SECTOR_7_1"
|
|
bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode" "SECTOR_6_0,SECTOR_6_1"
|
|
bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode" "SECTOR_5_0,SECTOR_5_1"
|
|
newline
|
|
bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode" "SECTOR_4_0,SECTOR_4_1"
|
|
bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode" "SECTOR_3_0,SECTOR_3_1"
|
|
bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode" "SECTOR_2_0,SECTOR_2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode" "SECTOR_1_0,SECTOR_1_1"
|
|
bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode" "SECTOR_0_0,SECTOR_0_1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "EMIF"
|
|
tree "DDR_PHY"
|
|
base ad:0x2329000
|
|
group.long 0x04++0x2B
|
|
line.long 0x00 "DDR_PHY_PIR,"
|
|
bitfld.long 0x00 31. "INITBYP,Initialization Bypass: Bypasses or stops if set all initialization routines currently running including PHY initialization DRAM initialization and PHY training" "0,1"
|
|
bitfld.long 0x00 30. "ZCALBYP,Impedance Calibration Bypass: Bypasses or stops if set impedance calibration of all ZQ control blocks that automatically triggers after reset" "0,1"
|
|
bitfld.long 0x00 29. "DCALBYP,Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops if set DDL calibration that automatically triggers after reset" "0,1"
|
|
bitfld.long 0x00 28. "LOCKBYP,PLL Lock Bypass: Bypasses or stops if set the waiting of PLLs to lock" "0,1"
|
|
bitfld.long 0x00 27. "CLRSR,Clear Status Registers: A write of '1' to this bit will clear (reset to '0') all status registers including PGSR and DXnGSR" "0,1"
|
|
bitfld.long 0x00 18. "CTLDINIT,Controller DRAM Initialization: Indicates if set that DRAM initialization will be performed by the controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "PLLBYP,PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode" "0,1"
|
|
bitfld.long 0x00 16. "ICPC,Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization" "0,1"
|
|
bitfld.long 0x00 15. "WREYE,Write Data Eye Training: Executes a PUB training routine to maximize the write data eye" "0,1"
|
|
bitfld.long 0x00 14. "RDEYE,Read Data Eye Training: Executes a PUB training routine to maximize the read data eye" "0,1"
|
|
bitfld.long 0x00 13. "WRDSKW,Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during" "0,1"
|
|
bitfld.long 0x00 12. "RDDSKW,Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "WLADJ,Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that readjusts the write latency used during write in case the write leveling routine changed the expected latency" "0,1"
|
|
bitfld.long 0x00 10. "QSGATE,Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins" "0,1"
|
|
bitfld.long 0x00 9. "WL,Write Leveling (DDR3 Only): Executes a PUB write leveling routine" "0,1"
|
|
bitfld.long 0x00 8. "DRAMINIT,DRAM Initialization: Executes the DRAM initialization sequence" "0,1"
|
|
bitfld.long 0x00 7. "DRAMRST,DRAM Reset: Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us" "0,1"
|
|
bitfld.long 0x00 6. "PHYRST,PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DCAL,Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration" "0,1"
|
|
bitfld.long 0x00 4. "PLLINIT,PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down reset and gear shift pins and then waiting for the PHY PLLs to lock" "0,1"
|
|
bitfld.long 0x00 1. "ZCAL,Impedance Calibration: Performs PHY impedance calibration" "0,1"
|
|
bitfld.long 0x00 0. "INIT,Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization including PHY initialization DRAM initialization and PHY training" "0,1"
|
|
line.long 0x04 "DDR_PHY_PGCR0,"
|
|
bitfld.long 0x04 26.--31. "CKEN,CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 14.--18. "DTOSEL,Digital Test Output Select: Selects the PHY digital test output that should be driven onto PHY digital test output (phy_dto) pin: Valid values are" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 12.--13. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active" "0,1,2,3"
|
|
bitfld.long 0x04 9.--11. "OSCDIV,Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8. "OSCEN,Oscillator Enable: Enables if set the delay line oscillation" "0,1"
|
|
bitfld.long 0x04 7. "DLTST,Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement" "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "DLTMODE,Delay Line Test Mode: Selects if set the delay line oscillator test mode" "0,1"
|
|
bitfld.long 0x04 5. "RDBVT,Read Data BDL VT Compensation: Enables if set the VT drift compensation of the read data bit delay lines" "0,1"
|
|
bitfld.long 0x04 4. "WDBVT,Write Data BDL VT Compensation: Enables if set the VT drift compensation of the write data bit delay lines" "0,1"
|
|
bitfld.long 0x04 3. "RGLVT,Read DQS Gating LCDL Delay VT Compensation: Enables if set the VT drift compensation of the read DQS gating LCDL" "0,1"
|
|
bitfld.long 0x04 2. "RDLVT,Read DQS LCDL Delay VT Compensation: Enables if set the VT drift compensation of the read DQS LCDL" "0,1"
|
|
bitfld.long 0x04 1. "WDLVT,Write DQ LCDL Delay VT Compensation: Enables if set the VT drift compensation of the write DQ LCDL" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "WLLVT,Write Leveling LCDL Delay VT Compensation: Enables if set the VT drift compensation of the write leveling LCDL" "0,1"
|
|
line.long 0x08 "DDR_PHY_PGCR1,"
|
|
bitfld.long 0x08 31. "LBMODE,Loopback Mode: Indicates if set that the PHY/PUB is in loopback mode" "0,1"
|
|
bitfld.long 0x08 29.--30. "LBGDQS,Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode including BIST loopback mode" "0,1,2,3"
|
|
bitfld.long 0x08 28. "LBDQSS,Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye" "0,1"
|
|
bitfld.long 0x08 27. "IOLB,I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens" "0,1"
|
|
bitfld.long 0x08 26. "INHVT,VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values" "0,1"
|
|
bitfld.long 0x08 25. "PHYHRST,PHY High-Speed Reset: A write of '0' to this bit resets the AC and DATX8 macros without resetting PUB RTL logic" "0,1"
|
|
newline
|
|
bitfld.long 0x08 23.--24. "ZCKSEL,Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM" "0,1,2,3"
|
|
hexmask.long.byte 0x08 15.--22. 1. "DLDLMT,Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift)"
|
|
bitfld.long 0x08 13.--14. "FDEPTH,Filter" "0,1,2,3"
|
|
bitfld.long 0x08 11.--12. "LPFDEPTH,Low-Pass Filter" "0,1,2,3"
|
|
bitfld.long 0x08 10. "LPFEN,Low-Pass Filter Enable: Enables if set the low pass filtering of MDL period measurements" "0,1"
|
|
bitfld.long 0x08 9. "MDLEN,Master Delay Line Enable: Enables if set the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered" "0,1"
|
|
newline
|
|
bitfld.long 0x08 7.--8. "IODDRM,This field should be programmed to 1h if using DDR3 and 2h if using DDR3L" "0,1,2,3"
|
|
bitfld.long 0x08 6. "WLSELT,Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines" "0,1"
|
|
bitfld.long 0x08 2. "WLSTEP,Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling" "0,1"
|
|
bitfld.long 0x08 1. "WLMODE,Write Leveling (Software) Mode: Indicates if set that the PHY is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to" "0,1"
|
|
bitfld.long 0x08 0. "PDDISDX,Power Down Disabled Byte: Indicates if set that the PLL and I/Os of a disabled byte should be powered down" "0,1"
|
|
line.long 0x0C "DDR_PHY_PGSR0,"
|
|
bitfld.long 0x0C 31. "APLOCK,AC PLL Lock: Indicates if set that AC PLL has locked" "0,1"
|
|
bitfld.long 0x0C 27. "WEERR,Write Eye Training Error: Indicates if set that there is an error in write eye training" "0,1"
|
|
bitfld.long 0x0C 26. "REERR,Read Eye Training Error: Indicates if set that there is an error in read eye training" "0,1"
|
|
bitfld.long 0x0C 25. "WDERR,Write Bit Deskew Error: Indicates if set that there is an error in write bit deskew" "0,1"
|
|
bitfld.long 0x0C 24. "RDERR,Read Bit Deskew Error: Indicates if set that there is an error in read bit deskew" "0,1"
|
|
bitfld.long 0x0C 23. "WLAERR,Write Leveling Adjustment Error: Indicates if set that there is an error in write leveling adjustment" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. "QSGERR,DQS Gate Training Error: Indicates if set that there is an error in DQS gate training" "0,1"
|
|
bitfld.long 0x0C 21. "WLERR,Write Leveling Error: Indicates if set that there is an error in write leveling" "0,1"
|
|
bitfld.long 0x0C 20. "ZCERR,Impedance Calibration Error: Indicates if set that there is an error in impedance calibration" "0,1"
|
|
bitfld.long 0x0C 11. "WEDONE,Write Eye Training Done: Indicates if set that write eye training has completed" "0,1"
|
|
bitfld.long 0x0C 10. "REDONE,Read Eye Training Done: Indicates if set that read eye training has completed" "0,1"
|
|
bitfld.long 0x0C 9. "WDDONE,Write Bit Deskew Done: Indicates if set that write bit deskew has completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "RDDONE,Read Bit Deskew Done: Indicates if set that read bit deskew has completed" "0,1"
|
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bitfld.long 0x0C 7. "WLADONE,Write Leveling Adjustment Done: Indicates if set that write leveling adjustment has completed" "0,1"
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bitfld.long 0x0C 6. "QSGDONE,DQS Gate Training Done: Indicates if set that DQS gate training has completed" "0,1"
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bitfld.long 0x0C 5. "WLDONE,Write Leveling Done: Indicates if set that write leveling has completed" "0,1"
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bitfld.long 0x0C 4. "DIDONE,DRAM Initialization Done: Indicates if set that DRAM initialization has completed" "0,1"
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bitfld.long 0x0C 3. "ZCDONE,Impedance Calibration Done: Indicates if set that impedance calibration has completed" "0,1"
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bitfld.long 0x0C 2. "DCDONE,Digital Delay Line (DDL) Calibration Done: Indicates if set that DDL calibration has completed" "0,1"
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bitfld.long 0x0C 1. "PLDONE,PLL Lock Done: Indicates if set that PLL locking has completed" "0,1"
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bitfld.long 0x0C 0. "IDONE,Initialization Done: Indicates if set that the DDR system initialization has completed" "0,1"
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line.long 0x10 "DDR_PHY_PGSR1,"
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bitfld.long 0x10 30. "VTSTOP,VT Stop: Indicates if set that the VT calculation logic has stopped computing the next values for the VT compensated delay line values" "0,1"
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hexmask.long.tbyte 0x10 1.--24. 1. "DLTCODE,Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output"
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bitfld.long 0x10 0. "DLTDONE,Delay Line Test Done: Indicates if set that the PHY control block has finished doing period measurement of the AC delay line digital test output" "0,1"
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line.long 0x14 "DDR_PHY_PLLCR,"
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bitfld.long 0x14 31. "BYP,PLL Bypass: Bypasses the PLL if set to 1" "0,1"
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bitfld.long 0x14 30. "PLLRST,PLL Rest: Resets the PLLs by driving the PLL reset pin" "0,1"
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bitfld.long 0x14 29. "PLLPD,PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin" "0,1"
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bitfld.long 0x14 18.--19. "FRQSEL,PHY PLL reference frequency select: Selects the operating range of the PHY PLL" "0,1,2,3"
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bitfld.long 0x14 17. "QPMODE,PLL Quadrature Phase Mode: Enables if set the quadrature phase clock outputs" "0,1"
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bitfld.long 0x14 13.--16. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x14 11.--12. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3"
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rbitfld.long 0x14 10. "GSHIFT,Gear Shift: Enables if set rapid locking mode" "0,1"
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line.long 0x18 "DDR_PHY_PTR0,"
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hexmask.long.word 0x18 21.--31. 1. "TPLLPD,PLL Power-Down Time: Number of VBUSP_CLK cycles that the PLL must remain in power-down mode that is number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted"
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hexmask.long.word 0x18 6.--20. 1. "TPLLGS,PLL Gear Shift Time: Number of VBUSP_CLK cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted"
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bitfld.long 0x18 0.--5. "TPHYRST,PHY Reset Time: Number of VBUSP_CLK cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x1C "DDR_PHY_PTR1,"
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hexmask.long.word 0x1C 16.--31. 1. "TPLLLOCK,PLL Lock Time: Number of VBUSP_CLK cycles for the PLL to stabilize and lock that is number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use"
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hexmask.long.word 0x1C 0.--12. 1. "TPLLRST,PLL Reset Time: Number of VBUSP_CLK cycles that the PLL must remain in reset mode that is number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted"
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line.long 0x20 "DDR_PHY_PTR2,"
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bitfld.long 0x20 15.--19. "TWLDLYS,Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 10.--14. "TCALH,Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 5.--9. "TCALS,Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 0.--4. "TCALON,Calibration On Time: Number of controller clock cycles that the calibration clock is enabled (cal_clk_en asserted)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x24 "DDR_PHY_PTR3,"
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hexmask.long.word 0x24 20.--28. 1. "TDINIT1,DRAM Initialization Time"
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hexmask.long.tbyte 0x24 0.--19. 1. "TDINIT0,DRAM Initialization Time"
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line.long 0x28 "DDR_PHY_PTR4,"
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hexmask.long.word 0x28 18.--27. 1. "TDINIT3,DRAM Initialization Time"
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hexmask.long.tbyte 0x28 0.--17. 1. "TDINIT2,DRAM Initialization Time"
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group.long 0x38++0x07
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line.long 0x00 "DDR_PHY_ACIOCR,"
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bitfld.long 0x00 30.--31. "ACSR,Address/Command Slew Rate: Selects slew rate of the I/O for all address and command pins" "very fast..,fast,medium,slow"
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line.long 0x04 "DDR_PHY_DXCCR,"
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bitfld.long 0x04 28.--31. "DDPDRCDO,Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 24.--27. "DDPDDCDO,Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 23. "DYNDXPDR,Data Power Down Receiver: Dynamically powers down when set the input receiver on I/O for the DQ pins of the active DATX8 macros" "0,1"
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bitfld.long 0x04 22. "DYNDXPDD,Dynamic Data Power Down Driver: Dynamically powers down when set the output driver on I/O for the DQ pins of the active DATX8 macros" "0,1"
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bitfld.long 0x04 21. "UDQIOM,Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins" "0,1"
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bitfld.long 0x04 20. "UDQPDR,Unused DQ Power Down Receiver: Powers down when set the input receiver on the I/O for unused DQ pins" "0,1"
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bitfld.long 0x04 19. "UDQPDD,Unused DQ Power Down Driver: Powers down when set the output driver on the I/O for unused DQ pins" "0,1"
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bitfld.long 0x04 18. "UDQODT,Unused DQ On-Die Termination: Enables when set the on-die termination on the I/O for unused DQ pins" "0,1"
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bitfld.long 0x04 15.--17. "MSBUDQ,Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 13.--14. "DXSR,Data Slew Rate: Selects slew rate of the I/O for DQ DM and DQS/DQS# pins of all DATX8 macros" "very fast..,fast,medium,slow"
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bitfld.long 0x04 9.--12. "DQSNRES,DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 5.--8. "DQSRES,DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins" "Open,688 ohms,611 ohms,550 ohms,500 ohms,458 ohms,393 ohms,344 ohms,?..."
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bitfld.long 0x04 4. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for DQ DM and DQS/DQS# pins of all DATX8 macros" "0,1"
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bitfld.long 0x04 3. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of all DATX8 macros" "0,1"
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bitfld.long 0x04 2. "MDLEN,Master Delay Line Enable: Enables if set all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered" "0,1"
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bitfld.long 0x04 1. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of all DATX8 macros" "0,1"
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bitfld.long 0x04 0. "DXODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ DM and DQS/DQS# pins of all DATX8 macros" "0,1"
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group.long 0x44++0x27
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line.long 0x00 "DDR_PHY_DCR,"
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bitfld.long 0x00 29. "UDIMM,Un-buffered DIMM Address Mirroring: Indicates if set that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS1)" "0,1"
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bitfld.long 0x00 27. "NOSRA,No Simultaneous Rank Access: Specifies if set that simultaneous rank access on the same clock cycle is not allowed" "0,1"
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hexmask.long.byte 0x00 10.--17. 1. "BYTEMASK,Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training"
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bitfld.long 0x00 7. "MPRDQ,Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads" "0,1"
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bitfld.long 0x00 4.--6. "PDQ,Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3. "DDR8BNK,DDR" "0,1"
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bitfld.long 0x00 0.--2. "DDRMD,DDR Mode: Set to 3h for DDR3 mode" "0,1,2,3,4,5,6,7"
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line.long 0x04 "DDR_PHY_DTPR0,"
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bitfld.long 0x04 26.--31. "TRC,Activate to activate command delay (same bank)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 22.--25. "TRRD,Activate to activate command delay (different banks)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--21. "TRAS,Activate to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 12.--15. "TRCD,Activate to read or write delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "TRP,Precharge command period: The minimum time between a precharge command and any other command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. "TWTR,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 0.--3. "TRTP,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "DDR_PHY_DTPR1,"
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bitfld.long 0x08 26.--29. "TWLO,Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the PHY to when the results from the SDRAM on DQ is sampled by the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--25. "TWLMRD,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 11.--19. 1. "TRFC,Refresh-to-Refresh: Indicates the minimum time in clock cycles between two refresh commands or between a refresh and an active command"
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bitfld.long 0x08 5.--10. "TFAW,4-bank activate period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 2.--4. "TMOD,Load mode update delay" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--1. "TMRD,Load mode cycle time: The minimum time between a load mode register command and any other command" "0,1,2,3"
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line.long 0x0C "DDR_PHY_DTPR2,"
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bitfld.long 0x0C 31. "TCCD,Read to read and write to write command delay" "0,1"
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bitfld.long 0x0C 30. "TRTW,Read to Write command delay" "0,1"
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bitfld.long 0x0C 29. "TRTODT,Read to ODT delay" "0,1"
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hexmask.long.word 0x0C 19.--28. 1. "TDLLK,DLL locking time"
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bitfld.long 0x0C 15.--18. "TCKE,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 10.--14. "TXP,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.word 0x0C 0.--9. 1. "TXS,Self refresh exit delay"
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line.long 0x10 "DDR_PHY_MR0,"
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bitfld.long 0x10 12. "PD,Power-Down Control: Controls the exit time for power-down modes" "0,1"
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bitfld.long 0x10 9.--11. "WR,Write Recovery: This is the value of the write recovery in clock cycles" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "DR,DLL Reset: Writing a '1' to this bit will reset the SDRAM DLL" "0,1"
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bitfld.long 0x10 7. "TM,Operating Mode: Always set to 0 for normal operating mode" "0,1"
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bitfld.long 0x10 4.--6. "CL,CAS Latency: The delay in clock cycles between SDRAM read command to data available" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 3. "BT,Burst type: Set to 0 for sequential burst (interleaved burst is not supported)" "0,1"
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newline
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bitfld.long 0x10 2. "CL,This is the least significant bit of the CL field" "0,1"
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bitfld.long 0x10 0.--1. "BL,Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command" "0,1,2,3"
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line.long 0x14 "DDR_PHY_MR1,"
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bitfld.long 0x14 12. "QOFF,Output Enable/Disable: Program to '0' for all outputs to function as normal" "0,1"
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bitfld.long 0x14 11. "TDQS,Termination Data Strobe: This must always be set to 0" "0,1"
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bitfld.long 0x14 9. "RTT,On Die Termination: Selects the effective resistance for SDRAM on die termination" "0,1"
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bitfld.long 0x14 7. "LEVEL,Write Leveling Enable: Enables write-leveling when set" "0,1"
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bitfld.long 0x14 6. "RTT,On Die Termination: Selects the effective resistance for SDRAM on die termination" "0,1"
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bitfld.long 0x14 5. "DIC,Output Driver Impedance Control: Controls the output drive strength" "0,1"
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newline
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bitfld.long 0x14 3.--4. "AL,Posted CAS Additive Latency: the controller does not support this feature" "0,1,2,3"
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bitfld.long 0x14 2. "RTT,On Die Termination: Selects the effective resistance for SDRAM on die termination" "0,1"
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bitfld.long 0x14 1. "DIC,Output Driver Impedance Control: Controls the output drive strength" "0,1"
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bitfld.long 0x14 0. "DE,DLL Enable/Disable: Enable (0) or disable (1) the DLL" "0,1"
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line.long 0x18 "DDR_PHY_MR2,"
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bitfld.long 0x18 9.--10. "RTTWR,Dynamic ODT: Selects RTT for dynamic ODT" "0,1,2,3"
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bitfld.long 0x18 7. "SRT,Self-Refresh Temperature Range: Selects either normal ('0') or extended ('1') operating temperature range during self-refresh" "0,1"
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bitfld.long 0x18 6. "ASR,Auto Self-Refresh: When enabled ('1') SDRAM automatically provides self-refresh power management functions for all supported operating temperature values" "0,1"
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bitfld.long 0x18 3.--5. "CWL,CAS Write Latency: The delay in clock cycles between when the SDRAM registers a write command to when write data is available" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 0.--2. "PASR,Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered" "0,1,2,3,4,5,6,7"
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line.long 0x1C "DDR_PHY_MR3,"
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bitfld.long 0x1C 2. "MPR,Multi-Purpose Register Enable: Enables if set that read data should come from the Multi-Purpose Register" "0,1"
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bitfld.long 0x1C 0.--1. "MPRLOC,Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are" "0,1,2,3"
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line.long 0x20 "DDR_PHY_ODTCR,"
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bitfld.long 0x20 28.--31. "WRODT3,Write ODT: Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a write command is sent to rank n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 24.--27. "WRODT2,See description for WRODT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "WRODT1,See description for WRODT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "WRODT0,See description for WRODT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 12.--15. "RDODT3,Read ODT: Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a read command is sent to rank n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--11. "RDODT2,See description for RDODT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 4.--7. "RDODT1,See description for RDODT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "RDODT0,See description for RDODT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "DDR_PHY_DTCR,"
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bitfld.long 0x24 28.--31. "RFSHDT,Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. "RANKEN,Rank Enable: Specifies the ranks that are enabled for data-training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 22. "DTEXD,Data Training Extended Write DQS: Enables if set an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes" "0,1"
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bitfld.long 0x24 21. "DTDSTP,Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step" "0,1"
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bitfld.long 0x24 20. "DTDEN,Data Training Debug Enable: Enables if set the data training debug mode" "0,1"
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bitfld.long 0x24 16.--19. "DTDBS,Data Training Debug Byte Select: Selects the byte during data training debug mod" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 13. "DTBDC,Data Training Bit Deskew Centering: Enables if set eye centering capability during write and read bit deskew training" "0,1"
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bitfld.long 0x24 12. "DTWBDDM,Data Training Write Bit Deskew Data Mask" "0,1"
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bitfld.long 0x24 8.--11. "DTWDQM,Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ lcdl can be moved during training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 7. "DTCMPD,Data Training Compare Data: Specifies if set that DQS gate training should also check if the returning read data is correct" "0,1"
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bitfld.long 0x24 6. "DTMPR,Data Training Using MPR (DDR3 Only): Specifies if set that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register" "0,1"
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bitfld.long 0x24 4.--5. "DTRANK,Data Training Rank: Selects the SDRAM rank to be used during data bit deskew and eye centering" "0,1,2,3"
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newline
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bitfld.long 0x24 0.--3. "DTRPTN,Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x8C++0x03
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line.long 0x00 "DDR_PHY_PGCR2,"
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bitfld.long 0x00 31. "DYNACPDD,Dynamic AC Power Down Driver: Powers down when set the output driver on I/O for the address and bank address lines" "0,1"
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hexmask.long.byte 0x00 20.--27. 1. "DTPMXTMR,Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training"
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bitfld.long 0x00 19. "FXDLAT,Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency" "0,1"
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bitfld.long 0x00 18. "NOBUB,No Bubbles: Specified whether reads should be returned to the controller with no bubbles" "0,1"
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hexmask.long.tbyte 0x00 0.--17. 1. "TREFPRD,Refresh Period: Indicates the period in clock cycles after which the PUB has to issue a refresh command to the SDRAM"
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group.long 0x180++0x2F
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line.long 0x00 "DDR_PHY_ZQ0CR0,"
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bitfld.long 0x00 31. "ZQPD,ZQ Power Down: Powers down if set the impedance control block" "0,1"
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bitfld.long 0x00 30. "ZCALEN,Impedance Calibration Enable: Enables if set the impedance calibration of the ZQn control block when impedance calibration is triggered using either the ZCAL bit of" "0,1"
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bitfld.long 0x00 29. "ZCALBYP,Impedance Calibration Bypass: Bypasses if set impedance calibration of the ZQn control block when impedance calibration is already in progress" "0,1"
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bitfld.long 0x00 28. "ZDEN,Impedance Over-ride Enable: When this bit is set it allows users to directly drive the impedance control using the data programmed in the ZDATA field" "0,1"
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hexmask.long 0x00 0.--27. 1. "ZDATA,Impedance Over-Ride Data: Data used to directly drive the impedance control"
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line.long 0x04 "DDR_PHY_ZQ0CR1,"
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rbitfld.long 0x04 16. "DFIPU0,Impedance Calibration Enable: Setting to 1 enables the PHY to request periodic updates to compensate for VT drifts that might result in decreased timing margin" "0,1"
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hexmask.long.byte 0x04 0.--7. 1. "ZPROG,Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows"
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line.long 0x08 "DDR_PHY_ZQ0SR0,"
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bitfld.long 0x08 31. "ZDONE,Impedance Calibration Done: Indicates that impedance calibration has completed" "0,1"
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bitfld.long 0x08 30. "ZERR,Impedance Calibration Error: If set indicates that there was an error during impedance calibration" "0,1"
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hexmask.long 0x08 0.--27. 1. "ZCTRL,Impedance Control: Current value of impedance control"
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line.long 0x0C "DDR_PHY_ZQ0SR1,"
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bitfld.long 0x0C 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
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bitfld.long 0x0C 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
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bitfld.long 0x0C 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
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bitfld.long 0x0C 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
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line.long 0x10 "DDR_PHY_ZQ1CR0,"
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bitfld.long 0x10 31. "ZQPD,ZQ Power Down: Powers down if set the impedance control block" "0,1"
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bitfld.long 0x10 30. "ZCALEN,Impedance Calibration Enable: Enables if set the impedance calibration of the ZQn control block when impedance calibration is triggered using either the ZCAL bit of" "0,1"
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bitfld.long 0x10 29. "ZCALBYP,Impedance Calibration Bypass: Bypasses if set impedance calibration of the ZQn control block when impedance calibration is already in progress" "0,1"
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bitfld.long 0x10 28. "ZDEN,Impedance Over-ride Enable: When this bit is set it allows users to directly drive the impedance control using the data programmed in the ZDATA field" "0,1"
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hexmask.long 0x10 0.--27. 1. "ZDATA,Impedance Over-Ride Data: Data used to directly drive the impedance control"
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line.long 0x14 "DDR_PHY_ZQ1CR1,"
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rbitfld.long 0x14 16. "DFIPU0,Impedance Calibration Enable: Setting to 1 enables the PHY to request periodic updates to compensate for VT drifts that might result in decreased timing margin" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "ZPROG,Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows"
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line.long 0x18 "DDR_PHY_ZQ1SR0,"
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bitfld.long 0x18 31. "ZDONE,Impedance Calibration Done: Indicates that impedance calibration has completed" "0,1"
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bitfld.long 0x18 30. "ZERR,Impedance Calibration Error: If set indicates that there was an error during impedance calibration" "0,1"
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hexmask.long 0x18 0.--27. 1. "ZCTRL,Impedance Control: Current value of impedance control"
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line.long 0x1C "DDR_PHY_ZQ1SR1,"
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bitfld.long 0x1C 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
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bitfld.long 0x1C 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
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bitfld.long 0x1C 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
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bitfld.long 0x1C 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
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line.long 0x20 "DDR_PHY_ZQ2CR0,"
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bitfld.long 0x20 31. "ZQPD,ZQ Power Down: Powers down if set the impedance control block" "0,1"
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bitfld.long 0x20 30. "ZCALEN,Impedance Calibration Enable: Enables if set the impedance calibration of the ZQn control block when impedance calibration is triggered using either the ZCAL bit of" "0,1"
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bitfld.long 0x20 29. "ZCALBYP,Impedance Calibration Bypass: Bypasses if set impedance calibration of the ZQn control block when impedance calibration is already in progress" "0,1"
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bitfld.long 0x20 28. "ZDEN,Impedance Over-ride Enable: When this bit is set it allows users to directly drive the impedance control using the data programmed in the ZDATA field" "0,1"
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hexmask.long 0x20 0.--27. 1. "ZDATA,Impedance Over-Ride Data: Data used to directly drive the impedance control"
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line.long 0x24 "DDR_PHY_ZQ2CR1,"
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rbitfld.long 0x24 16. "DFIPU0,Impedance Calibration Enable: Setting to 1 enables the PHY to request periodic updates to compensate for VT drifts that might result in decreased timing margin" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "ZPROG,Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows"
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line.long 0x28 "DDR_PHY_ZQ2SR0,"
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bitfld.long 0x28 31. "ZDONE,Impedance Calibration Done: Indicates that impedance calibration has completed" "0,1"
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bitfld.long 0x28 30. "ZERR,Impedance Calibration Error: If set indicates that there was an error during impedance calibration" "0,1"
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hexmask.long 0x28 0.--27. 1. "ZCTRL,Impedance Control: Current value of impedance control"
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line.long 0x2C "DDR_PHY_ZQ2SR1,"
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bitfld.long 0x2C 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
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bitfld.long 0x2C 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
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bitfld.long 0x2C 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
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bitfld.long 0x2C 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
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group.long 0x1C0++0x07
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line.long 0x00 "DDR_PHY_DX0GCR,"
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bitfld.long 0x00 31. "CALBYP,Calibration Bypass: Prevents if set period measurement calibration from automatically triggering after PHY initialization" "0,1"
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bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable: Enables if set the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered" "0,1"
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bitfld.long 0x00 26.--29. "WLRNKEN,Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "PLLBYP,PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin" "0,1"
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bitfld.long 0x00 18. "GSHIFT,Gear Shift: Enables if set rapid locking mode on the byte PLL" "0,1"
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bitfld.long 0x00 17. "PLLPD,PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin" "0,1"
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newline
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bitfld.long 0x00 16. "PLLRST,PLL Rest: Resets the byte PLL by driving the PLL reset pin" "0,1"
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bitfld.long 0x00 14.--15. "DXOEO,Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value" "0,1,2,3"
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bitfld.long 0x00 13. "RTTOAL,RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles" "0,1"
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bitfld.long 0x00 11.--12. "RTTOH,RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control" "0,1,2,3"
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bitfld.long 0x00 10. "DQRTT,DQ Dynamic RTT Control: Indicates if set that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
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bitfld.long 0x00 9. "DQSRTT,DQS Dynamic RTT Control: Indicates if set that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
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newline
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bitfld.long 0x00 7.--8. "DSEN,Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted" "0,1,2,3"
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bitfld.long 0x00 6. "DQSRPD,DQSR Power Down: Powers down if set the PDQSR cell" "0,1"
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bitfld.long 0x00 5. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
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bitfld.long 0x00 4. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
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bitfld.long 0x00 3. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
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bitfld.long 0x00 2. "DQODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ and DM pins of the byte" "0,1"
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newline
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bitfld.long 0x00 1. "DQSODT,DQS On-Die Termination: Enables when set the on-die termination on the I/O for DQS/DQS# pin of the byte" "0,1"
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bitfld.long 0x00 0. "DXEN,Data Byte Enable: Enables if set the data byte" "0,1"
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line.long 0x04 "DDR_PHY_DX0GSR0,"
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bitfld.long 0x04 28. "WLDQ,Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling" "0,1"
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bitfld.long 0x04 24.--27. "QSGERR,DQS Gate Training Error: Indicates if set that there is an error in DQS gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x04 16.--23. 1. "GDQSPRD,Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration"
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bitfld.long 0x04 15. "DPLOCK,DATX8 PLL Lock: Indicates if set that the DATX8 PLL has locked" "0,1"
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hexmask.long.byte 0x04 7.--14. 1. "WLPRD,Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration"
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bitfld.long 0x04 6. "WLERR,Write Leveling Error: Indicates if set that there is a write leveling error in the DATX8" "0,1"
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newline
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bitfld.long 0x04 5. "WLDONE,Write Leveling Done: Indicates if set that the DATX8 has completed write leveling" "0,1"
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bitfld.long 0x04 4. "WLCAL,Write Leveling Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line" "0,1"
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bitfld.long 0x04 3. "GDQSCAL,Read DQS gating Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL" "0,1"
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bitfld.long 0x04 2. "RDQSNCAL,Read DQS# Calibration (Type B/B1 PHY Only): Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL" "0,1"
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bitfld.long 0x04 1. "RDQSCAL,Read DQS Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS LCDL" "0,1"
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bitfld.long 0x04 0. "WDQCAL,Write DQ Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write DQ LCDL" "0,1"
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group.long 0x1E0++0x17
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line.long 0x00 "DDR_PHY_DX0LCDLR0,"
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hexmask.long.byte 0x00 24.--31. 1. "R3WLD,Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL"
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hexmask.long.byte 0x00 16.--23. 1. "R2WLD,Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL"
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hexmask.long.byte 0x00 8.--15. 1. "R1WLD,Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL"
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hexmask.long.byte 0x00 0.--7. 1. "R0WLD,Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL"
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line.long 0x04 "DDR_PHY_DX0LCDLR1,"
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hexmask.long.byte 0x04 16.--23. 1. "RDQSND,Read DQSN Delay: Delay select for the read DQSN (RDQS) LCDL"
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hexmask.long.byte 0x04 8.--15. 1. "RDQSD,Read DQS Delay: Delay select for the read DQS (RDQS) LCDL"
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hexmask.long.byte 0x04 0.--7. 1. "WDQD,Write Data Delay: Delay select for the write data (WDQ) LCDL"
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line.long 0x08 "DDR_PHY_DX0LCDLR2,"
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hexmask.long.byte 0x08 24.--31. 1. "R3DQSGD,Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL"
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hexmask.long.byte 0x08 16.--23. 1. "R2DQSGD,Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL"
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hexmask.long.byte 0x08 8.--15. 1. "R1DQSGD,Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL"
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hexmask.long.byte 0x08 0.--7. 1. "R0DQSGD,Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL"
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line.long 0x0C "DDR_PHY_DX0MDLR,"
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hexmask.long.byte 0x0C 16.--23. 1. "MDLD,MDL Delay: Delay select for the LCDL for the Master Delay Line"
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hexmask.long.byte 0x0C 8.--15. 1. "TPRD,Target Period: Target period measured by the master delay line calibration for VT drift compensation"
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hexmask.long.byte 0x0C 0.--7. 1. "IPRD,Initial Period: Initial period measured by the master delay line calibration for VT drift compensation"
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line.long 0x10 "DDR_PHY_DX0GTR,"
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bitfld.long 0x10 18.--19. "R3WLSL,Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling" "0,1,2,3"
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bitfld.long 0x10 16.--17. "R2WLSL,See description for R3WLSL" "0,1,2,3"
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bitfld.long 0x10 14.--15. "R1WLSL,See description for R3WLSL" "0,1,2,3"
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bitfld.long 0x10 12.--13. "R0WLSL,See description for R3WLSL" "0,1,2,3"
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bitfld.long 0x10 9.--11. "R3DGSL,Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 6.--8. "R2DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x10 3.--5. "R1DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 0.--2. "R0DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
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line.long 0x14 "DDR_PHY_DX0GSR2,"
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bitfld.long 0x14 8.--11. "ESTAT,Error Status: If an error occurred for this lane as indicated by RDERR WDERR REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 7. "WEWN,Write Eye Centering Warning: Indicates if set that the byte lane" "0,1"
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bitfld.long 0x14 6. "WEERR,Write Eye Centering Error: Indicates if set that the byte lane" "0,1"
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bitfld.long 0x14 5. "REWN,Read Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
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bitfld.long 0x14 4. "REERR,Read Eye Centering Error: Indicates if set that the byte lane" "0,1"
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bitfld.long 0x14 3. "WDWN,Write Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
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newline
|
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bitfld.long 0x14 2. "WDERR,Write Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
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bitfld.long 0x14 1. "RDWN,Read Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 0. "RDERR,Read Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
group.long 0x200++0x07
|
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line.long 0x00 "DDR_PHY_DX1GCR,"
|
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bitfld.long 0x00 31. "CALBYP,Calibration Bypass: Prevents if set period measurement calibration from automatically triggering after PHY initialization" "0,1"
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|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable: Enables if set the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered" "0,1"
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bitfld.long 0x00 26.--29. "WLRNKEN,Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "PLLBYP,PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin" "0,1"
|
|
bitfld.long 0x00 18. "GSHIFT,Gear Shift: Enables if set rapid locking mode on the byte PLL" "0,1"
|
|
bitfld.long 0x00 17. "PLLPD,PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PLLRST,PLL Rest: Resets the byte PLL by driving the PLL reset pin" "0,1"
|
|
bitfld.long 0x00 14.--15. "DXOEO,Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value" "0,1,2,3"
|
|
bitfld.long 0x00 13. "RTTOAL,RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles" "0,1"
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bitfld.long 0x00 11.--12. "RTTOH,RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control" "0,1,2,3"
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bitfld.long 0x00 10. "DQRTT,DQ Dynamic RTT Control: Indicates if set that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
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bitfld.long 0x00 9. "DQSRTT,DQS Dynamic RTT Control: Indicates if set that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
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|
newline
|
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bitfld.long 0x00 7.--8. "DSEN,Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down: Powers down if set the PDQSR cell" "0,1"
|
|
bitfld.long 0x00 5. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 4. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 3. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 2. "DQODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ and DM pins of the byte" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "DQSODT,DQS On-Die Termination: Enables when set the on-die termination on the I/O for DQS/DQS# pin of the byte" "0,1"
|
|
bitfld.long 0x00 0. "DXEN,Data Byte Enable: Enables if set the data byte" "0,1"
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|
line.long 0x04 "DDR_PHY_DX1GSR0,"
|
|
bitfld.long 0x04 28. "WLDQ,Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling" "0,1"
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|
bitfld.long 0x04 24.--27. "QSGERR,DQS Gate Training Error: Indicates if set that there is an error in DQS gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.byte 0x04 16.--23. 1. "GDQSPRD,Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration"
|
|
bitfld.long 0x04 15. "DPLOCK,DATX8 PLL Lock: Indicates if set that the DATX8 PLL has locked" "0,1"
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|
hexmask.long.byte 0x04 7.--14. 1. "WLPRD,Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration"
|
|
bitfld.long 0x04 6. "WLERR,Write Leveling Error: Indicates if set that there is a write leveling error in the DATX8" "0,1"
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|
newline
|
|
bitfld.long 0x04 5. "WLDONE,Write Leveling Done: Indicates if set that the DATX8 has completed write leveling" "0,1"
|
|
bitfld.long 0x04 4. "WLCAL,Write Leveling Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line" "0,1"
|
|
bitfld.long 0x04 3. "GDQSCAL,Read DQS gating Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL" "0,1"
|
|
bitfld.long 0x04 2. "RDQSNCAL,Read DQS# Calibration (Type B/B1 PHY Only): Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL" "0,1"
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|
bitfld.long 0x04 1. "RDQSCAL,Read DQS Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS LCDL" "0,1"
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|
bitfld.long 0x04 0. "WDQCAL,Write DQ Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write DQ LCDL" "0,1"
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|
group.long 0x220++0x17
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|
line.long 0x00 "DDR_PHY_DX1LCDLR0,"
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|
hexmask.long.byte 0x00 24.--31. 1. "R3WLD,Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 16.--23. 1. "R2WLD,Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL"
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|
hexmask.long.byte 0x00 8.--15. 1. "R1WLD,Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL"
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|
hexmask.long.byte 0x00 0.--7. 1. "R0WLD,Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL"
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|
line.long 0x04 "DDR_PHY_DX1LCDLR1,"
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hexmask.long.byte 0x04 16.--23. 1. "RDQSND,Read DQSN Delay: Delay select for the read DQSN (RDQS) LCDL"
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|
hexmask.long.byte 0x04 8.--15. 1. "RDQSD,Read DQS Delay: Delay select for the read DQS (RDQS) LCDL"
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hexmask.long.byte 0x04 0.--7. 1. "WDQD,Write Data Delay: Delay select for the write data (WDQ) LCDL"
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|
line.long 0x08 "DDR_PHY_DX1LCDLR2,"
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hexmask.long.byte 0x08 24.--31. 1. "R3DQSGD,Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL"
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hexmask.long.byte 0x08 16.--23. 1. "R2DQSGD,Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL"
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hexmask.long.byte 0x08 8.--15. 1. "R1DQSGD,Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL"
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hexmask.long.byte 0x08 0.--7. 1. "R0DQSGD,Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL"
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line.long 0x0C "DDR_PHY_DX1MDLR,"
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hexmask.long.byte 0x0C 16.--23. 1. "MDLD,MDL Delay: Delay select for the LCDL for the Master Delay Line"
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hexmask.long.byte 0x0C 8.--15. 1. "TPRD,Target Period: Target period measured by the master delay line calibration for VT drift compensation"
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hexmask.long.byte 0x0C 0.--7. 1. "IPRD,Initial Period: Initial period measured by the master delay line calibration for VT drift compensation"
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line.long 0x10 "DDR_PHY_DX1GTR,"
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bitfld.long 0x10 18.--19. "R3WLSL,Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling" "0,1,2,3"
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|
bitfld.long 0x10 16.--17. "R2WLSL,See description for R3WLSL" "0,1,2,3"
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bitfld.long 0x10 14.--15. "R1WLSL,See description for R3WLSL" "0,1,2,3"
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bitfld.long 0x10 12.--13. "R0WLSL,See description for R3WLSL" "0,1,2,3"
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bitfld.long 0x10 9.--11. "R3DGSL,Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 6.--8. "R2DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x10 3.--5. "R1DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 0.--2. "R0DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
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line.long 0x14 "DDR_PHY_DX1GSR2,"
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bitfld.long 0x14 8.--11. "ESTAT,Error Status: If an error occurred for this lane as indicated by RDERR WDERR REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x14 7. "WEWN,Write Eye Centering Warning: Indicates if set that the byte lane" "0,1"
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bitfld.long 0x14 6. "WEERR,Write Eye Centering Error: Indicates if set that the byte lane" "0,1"
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|
bitfld.long 0x14 5. "REWN,Read Eye Centering Warning: Indicates if set that the byte lane" "0,1"
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|
bitfld.long 0x14 4. "REERR,Read Eye Centering Error: Indicates if set that the byte lane" "0,1"
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|
bitfld.long 0x14 3. "WDWN,Write Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
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|
newline
|
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bitfld.long 0x14 2. "WDERR,Write Bit Deskew Error: Indicates if set that the byte lane" "0,1"
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bitfld.long 0x14 1. "RDWN,Read Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
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bitfld.long 0x14 0. "RDERR,Read Bit Deskew Error: Indicates if set that the byte lane" "0,1"
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|
group.long 0x240++0x07
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line.long 0x00 "DDR_PHY_DX2GCR,"
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bitfld.long 0x00 31. "CALBYP,Calibration Bypass: Prevents if set period measurement calibration from automatically triggering after PHY initialization" "0,1"
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bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable: Enables if set the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered" "0,1"
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bitfld.long 0x00 26.--29. "WLRNKEN,Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "PLLBYP,PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin" "0,1"
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bitfld.long 0x00 18. "GSHIFT,Gear Shift: Enables if set rapid locking mode on the byte PLL" "0,1"
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bitfld.long 0x00 17. "PLLPD,PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin" "0,1"
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newline
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bitfld.long 0x00 16. "PLLRST,PLL Rest: Resets the byte PLL by driving the PLL reset pin" "0,1"
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bitfld.long 0x00 14.--15. "DXOEO,Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value" "0,1,2,3"
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bitfld.long 0x00 13. "RTTOAL,RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles" "0,1"
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bitfld.long 0x00 11.--12. "RTTOH,RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control" "0,1,2,3"
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bitfld.long 0x00 10. "DQRTT,DQ Dynamic RTT Control: Indicates if set that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
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bitfld.long 0x00 9. "DQSRTT,DQS Dynamic RTT Control: Indicates if set that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
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|
newline
|
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bitfld.long 0x00 7.--8. "DSEN,Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted" "0,1,2,3"
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bitfld.long 0x00 6. "DQSRPD,DQSR Power Down: Powers down if set the PDQSR cell" "0,1"
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|
bitfld.long 0x00 5. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
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|
bitfld.long 0x00 4. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
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|
bitfld.long 0x00 3. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
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bitfld.long 0x00 2. "DQODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ and DM pins of the byte" "0,1"
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newline
|
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bitfld.long 0x00 1. "DQSODT,DQS On-Die Termination: Enables when set the on-die termination on the I/O for DQS/DQS# pin of the byte" "0,1"
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bitfld.long 0x00 0. "DXEN,Data Byte Enable: Enables if set the data byte" "0,1"
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line.long 0x04 "DDR_PHY_DX2GSR0,"
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bitfld.long 0x04 28. "WLDQ,Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling" "0,1"
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bitfld.long 0x04 24.--27. "QSGERR,DQS Gate Training Error: Indicates if set that there is an error in DQS gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x04 16.--23. 1. "GDQSPRD,Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration"
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bitfld.long 0x04 15. "DPLOCK,DATX8 PLL Lock: Indicates if set that the DATX8 PLL has locked" "0,1"
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hexmask.long.byte 0x04 7.--14. 1. "WLPRD,Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration"
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bitfld.long 0x04 6. "WLERR,Write Leveling Error: Indicates if set that there is a write leveling error in the DATX8" "0,1"
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|
newline
|
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bitfld.long 0x04 5. "WLDONE,Write Leveling Done: Indicates if set that the DATX8 has completed write leveling" "0,1"
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bitfld.long 0x04 4. "WLCAL,Write Leveling Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line" "0,1"
|
|
bitfld.long 0x04 3. "GDQSCAL,Read DQS gating Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL" "0,1"
|
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bitfld.long 0x04 2. "RDQSNCAL,Read DQS# Calibration (Type B/B1 PHY Only): Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL" "0,1"
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bitfld.long 0x04 1. "RDQSCAL,Read DQS Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS LCDL" "0,1"
|
|
bitfld.long 0x04 0. "WDQCAL,Write DQ Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write DQ LCDL" "0,1"
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group.long 0x260++0x17
|
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line.long 0x00 "DDR_PHY_DX2LCDLR0,"
|
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hexmask.long.byte 0x00 24.--31. 1. "R3WLD,Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 16.--23. 1. "R2WLD,Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL"
|
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hexmask.long.byte 0x00 8.--15. 1. "R1WLD,Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL"
|
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hexmask.long.byte 0x00 0.--7. 1. "R0WLD,Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL"
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line.long 0x04 "DDR_PHY_DX2LCDLR1,"
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hexmask.long.byte 0x04 16.--23. 1. "RDQSND,Read DQSN Delay: Delay select for the read DQSN (RDQS) LCDL"
|
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hexmask.long.byte 0x04 8.--15. 1. "RDQSD,Read DQS Delay: Delay select for the read DQS (RDQS) LCDL"
|
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hexmask.long.byte 0x04 0.--7. 1. "WDQD,Write Data Delay: Delay select for the write data (WDQ) LCDL"
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line.long 0x08 "DDR_PHY_DX2LCDLR2,"
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hexmask.long.byte 0x08 24.--31. 1. "R3DQSGD,Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 16.--23. 1. "R2DQSGD,Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 8.--15. 1. "R1DQSGD,Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 0.--7. 1. "R0DQSGD,Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL"
|
|
line.long 0x0C "DDR_PHY_DX2MDLR,"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "MDLD,MDL Delay: Delay select for the LCDL for the Master Delay Line"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "TPRD,Target Period: Target period measured by the master delay line calibration for VT drift compensation"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "IPRD,Initial Period: Initial period measured by the master delay line calibration for VT drift compensation"
|
|
line.long 0x10 "DDR_PHY_DX2GTR,"
|
|
bitfld.long 0x10 18.--19. "R3WLSL,Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "R2WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "R1WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "R0WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 9.--11. "R3DGSL,Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 6.--8. "R2DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 3.--5. "R1DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "R0DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "DDR_PHY_DX2GSR2,"
|
|
bitfld.long 0x14 8.--11. "ESTAT,Error Status: If an error occurred for this lane as indicated by RDERR WDERR REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 7. "WEWN,Write Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 6. "WEERR,Write Eye Centering Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 5. "REWN,Read Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 4. "REERR,Read Eye Centering Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 3. "WDWN,Write Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "WDERR,Write Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 1. "RDWN,Read Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 0. "RDERR,Read Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "DDR_PHY_DX3GCR,"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass: Prevents if set period measurement calibration from automatically triggering after PHY initialization" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable: Enables if set the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered" "0,1"
|
|
bitfld.long 0x00 26.--29. "WLRNKEN,Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "PLLBYP,PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin" "0,1"
|
|
bitfld.long 0x00 18. "GSHIFT,Gear Shift: Enables if set rapid locking mode on the byte PLL" "0,1"
|
|
bitfld.long 0x00 17. "PLLPD,PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PLLRST,PLL Rest: Resets the byte PLL by driving the PLL reset pin" "0,1"
|
|
bitfld.long 0x00 14.--15. "DXOEO,Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value" "0,1,2,3"
|
|
bitfld.long 0x00 13. "RTTOAL,RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles" "0,1"
|
|
bitfld.long 0x00 11.--12. "RTTOH,RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control" "0,1,2,3"
|
|
bitfld.long 0x00 10. "DQRTT,DQ Dynamic RTT Control: Indicates if set that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
|
|
bitfld.long 0x00 9. "DQSRTT,DQS Dynamic RTT Control: Indicates if set that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "DSEN,Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down: Powers down if set the PDQSR cell" "0,1"
|
|
bitfld.long 0x00 5. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 4. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 3. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 2. "DQODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ and DM pins of the byte" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DQSODT,DQS On-Die Termination: Enables when set the on-die termination on the I/O for DQS/DQS# pin of the byte" "0,1"
|
|
bitfld.long 0x00 0. "DXEN,Data Byte Enable: Enables if set the data byte" "0,1"
|
|
line.long 0x04 "DDR_PHY_DX3GSR0,"
|
|
bitfld.long 0x04 28. "WLDQ,Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling" "0,1"
|
|
bitfld.long 0x04 24.--27. "QSGERR,DQS Gate Training Error: Indicates if set that there is an error in DQS gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. "GDQSPRD,Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration"
|
|
bitfld.long 0x04 15. "DPLOCK,DATX8 PLL Lock: Indicates if set that the DATX8 PLL has locked" "0,1"
|
|
hexmask.long.byte 0x04 7.--14. 1. "WLPRD,Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration"
|
|
bitfld.long 0x04 6. "WLERR,Write Leveling Error: Indicates if set that there is a write leveling error in the DATX8" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "WLDONE,Write Leveling Done: Indicates if set that the DATX8 has completed write leveling" "0,1"
|
|
bitfld.long 0x04 4. "WLCAL,Write Leveling Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line" "0,1"
|
|
bitfld.long 0x04 3. "GDQSCAL,Read DQS gating Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL" "0,1"
|
|
bitfld.long 0x04 2. "RDQSNCAL,Read DQS# Calibration (Type B/B1 PHY Only): Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL" "0,1"
|
|
bitfld.long 0x04 1. "RDQSCAL,Read DQS Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS LCDL" "0,1"
|
|
bitfld.long 0x04 0. "WDQCAL,Write DQ Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write DQ LCDL" "0,1"
|
|
group.long 0x2A0++0x17
|
|
line.long 0x00 "DDR_PHY_DX3LCDLR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "R3WLD,Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 16.--23. 1. "R2WLD,Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 8.--15. 1. "R1WLD,Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 0.--7. 1. "R0WLD,Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL"
|
|
line.long 0x04 "DDR_PHY_DX3LCDLR1,"
|
|
hexmask.long.byte 0x04 16.--23. 1. "RDQSND,Read DQSN Delay: Delay select for the read DQSN (RDQS) LCDL"
|
|
hexmask.long.byte 0x04 8.--15. 1. "RDQSD,Read DQS Delay: Delay select for the read DQS (RDQS) LCDL"
|
|
hexmask.long.byte 0x04 0.--7. 1. "WDQD,Write Data Delay: Delay select for the write data (WDQ) LCDL"
|
|
line.long 0x08 "DDR_PHY_DX3LCDLR2,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "R3DQSGD,Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 16.--23. 1. "R2DQSGD,Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 8.--15. 1. "R1DQSGD,Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 0.--7. 1. "R0DQSGD,Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL"
|
|
line.long 0x0C "DDR_PHY_DX3MDLR,"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "MDLD,MDL Delay: Delay select for the LCDL for the Master Delay Line"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "TPRD,Target Period: Target period measured by the master delay line calibration for VT drift compensation"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "IPRD,Initial Period: Initial period measured by the master delay line calibration for VT drift compensation"
|
|
line.long 0x10 "DDR_PHY_DX3GTR,"
|
|
bitfld.long 0x10 18.--19. "R3WLSL,Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "R2WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "R1WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "R0WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 9.--11. "R3DGSL,Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 6.--8. "R2DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 3.--5. "R1DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "R0DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "DDR_PHY_DX3GSR2,"
|
|
bitfld.long 0x14 8.--11. "ESTAT,Error Status: If an error occurred for this lane as indicated by RDERR WDERR REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 7. "WEWN,Write Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 6. "WEERR,Write Eye Centering Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 5. "REWN,Read Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 4. "REERR,Read Eye Centering Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 3. "WDWN,Write Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "WDERR,Write Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 1. "RDWN,Read Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 0. "RDERR,Read Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
group.long 0x3C0++0x07
|
|
line.long 0x00 "DDR_PHY_DX8GCR,"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass: Prevents if set period measurement calibration from automatically triggering after PHY initialization" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable: Enables if set the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered" "0,1"
|
|
bitfld.long 0x00 26.--29. "WLRNKEN,Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "PLLBYP,PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin" "0,1"
|
|
bitfld.long 0x00 18. "GSHIFT,Gear Shift: Enables if set rapid locking mode on the byte PLL" "0,1"
|
|
bitfld.long 0x00 17. "PLLPD,PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PLLRST,PLL Rest: Resets the byte PLL by driving the PLL reset pin" "0,1"
|
|
bitfld.long 0x00 14.--15. "DXOEO,Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value" "0,1,2,3"
|
|
bitfld.long 0x00 13. "RTTOAL,RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles" "0,1"
|
|
bitfld.long 0x00 11.--12. "RTTOH,RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control" "0,1,2,3"
|
|
bitfld.long 0x00 10. "DQRTT,DQ Dynamic RTT Control: Indicates if set that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
|
|
bitfld.long 0x00 9. "DQSRTT,DQS Dynamic RTT Control: Indicates if set that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0') during any other cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "DSEN,Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down: Powers down if set the PDQSR cell" "0,1"
|
|
bitfld.long 0x00 5. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 4. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 3. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of the byte" "0,1"
|
|
bitfld.long 0x00 2. "DQODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ and DM pins of the byte" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DQSODT,DQS On-Die Termination: Enables when set the on-die termination on the I/O for DQS/DQS# pin of the byte" "0,1"
|
|
bitfld.long 0x00 0. "DXEN,Data Byte Enable: Enables if set the data byte" "0,1"
|
|
line.long 0x04 "DDR_PHY_DX8GSR0,"
|
|
bitfld.long 0x04 28. "WLDQ,Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling" "0,1"
|
|
bitfld.long 0x04 24.--27. "QSGERR,DQS Gate Training Error: Indicates if set that there is an error in DQS gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. "GDQSPRD,Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration"
|
|
bitfld.long 0x04 15. "DPLOCK,DATX8 PLL Lock: Indicates if set that the DATX8 PLL has locked" "0,1"
|
|
hexmask.long.byte 0x04 7.--14. 1. "WLPRD,Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration"
|
|
bitfld.long 0x04 6. "WLERR,Write Leveling Error: Indicates if set that there is a write leveling error in the DATX8" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "WLDONE,Write Leveling Done: Indicates if set that the DATX8 has completed write leveling" "0,1"
|
|
bitfld.long 0x04 4. "WLCAL,Write Leveling Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line" "0,1"
|
|
bitfld.long 0x04 3. "GDQSCAL,Read DQS gating Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL" "0,1"
|
|
bitfld.long 0x04 2. "RDQSNCAL,Read DQS# Calibration (Type B/B1 PHY Only): Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL" "0,1"
|
|
bitfld.long 0x04 1. "RDQSCAL,Read DQS Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the read DQS LCDL" "0,1"
|
|
bitfld.long 0x04 0. "WDQCAL,Write DQ Calibration: Indicates if set that the DATX8 has finished doing period measurement calibration for the write DQ LCDL" "0,1"
|
|
group.long 0x3E0++0x17
|
|
line.long 0x00 "DDR_PHY_DX8LCDLR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "R3WLD,Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 16.--23. 1. "R2WLD,Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 8.--15. 1. "R1WLD,Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL"
|
|
hexmask.long.byte 0x00 0.--7. 1. "R0WLD,Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL"
|
|
line.long 0x04 "DDR_PHY_DX8LCDLR1,"
|
|
hexmask.long.byte 0x04 16.--23. 1. "RDQSND,Read DQSN Delay: Delay select for the read DQSN (RDQS) LCDL"
|
|
hexmask.long.byte 0x04 8.--15. 1. "RDQSD,Read DQS Delay: Delay select for the read DQS (RDQS) LCDL"
|
|
hexmask.long.byte 0x04 0.--7. 1. "WDQD,Write Data Delay: Delay select for the write data (WDQ) LCDL"
|
|
line.long 0x08 "DDR_PHY_DX8LCDLR2,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "R3DQSGD,Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 16.--23. 1. "R2DQSGD,Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 8.--15. 1. "R1DQSGD,Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL"
|
|
hexmask.long.byte 0x08 0.--7. 1. "R0DQSGD,Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL"
|
|
line.long 0x0C "DDR_PHY_DX8MDLR,"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "MDLD,MDL Delay: Delay select for the LCDL for the Master Delay Line"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "TPRD,Target Period: Target period measured by the master delay line calibration for VT drift compensation"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "IPRD,Initial Period: Initial period measured by the master delay line calibration for VT drift compensation"
|
|
line.long 0x10 "DDR_PHY_DX8GTR,"
|
|
bitfld.long 0x10 18.--19. "R3WLSL,Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "R2WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "R1WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "R0WLSL,See description for R3WLSL" "0,1,2,3"
|
|
bitfld.long 0x10 9.--11. "R3DGSL,Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 6.--8. "R2DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 3.--5. "R1DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "R0DGSL,See description for R3DGSL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "DDR_PHY_DX8GSR2,"
|
|
bitfld.long 0x14 8.--11. "ESTAT,Error Status: If an error occurred for this lane as indicated by RDERR WDERR REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 7. "WEWN,Write Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 6. "WEERR,Write Eye Centering Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 5. "REWN,Read Eye Centering Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 4. "REERR,Read Eye Centering Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 3. "WDWN,Write Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "WDERR,Write Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 1. "RDWN,Read Bit Deskew Warning: Indicates if set that the byte lane" "0,1"
|
|
bitfld.long 0x14 0. "RDERR,Read Bit Deskew Error: Indicates if set that the byte lane" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMIF"
|
|
base ad:0x21010000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "EMIF_MIDR,"
|
|
line.long 0x04 "EMIF_STATUS,"
|
|
bitfld.long 0x04 31. "BE,Indicates whether the EMIF is in big or little-endian mode" "0,1"
|
|
bitfld.long 0x04 28. "OBF_STAT,Obfuscation Status" "0,1"
|
|
bitfld.long 0x04 27. "SELF_REF,Self refresh mode status" "0,1"
|
|
bitfld.long 0x04 26. "PWRDN,Power down status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "IFRDY,EMIF controller interface logic ready bit" "0,1"
|
|
line.long 0x08 "EMIF_SDCFG,"
|
|
bitfld.long 0x08 29.--31. "SDRAM_TYPE,SDRAM type selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 25.--27. "DDR_TERM,Defines termination resistor value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 22.--23. "DYN_ODT,Dynamic On-Die Termination All other values reserved" "0,1,2,3"
|
|
bitfld.long 0x08 14.--16. "CWL,CAS Write Latency" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 12.--13. "NM,DDR3 data bus width" "0,1,2,3"
|
|
bitfld.long 0x08 8.--11. "CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 5.--6. "IBANK,Internal SDRAM bank setup bits" "0,1,2,3"
|
|
bitfld.long 0x08 3. "EBANK,External chip select setup" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "PAGESIZE,Page size bits" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EMIF_SDRFC,"
|
|
bitfld.long 0x00 31. "INITREF_DIS,Refresh Disable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "REFRESH_RATE,The value in this field is used to define the rate at which connected SDRAM devices will be refreshed.REFRESH_RATE = Refresh period * DDR3 clock frequency"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "EMIF_SDTIM1,"
|
|
bitfld.long 0x00 25.--29. "T_WR,These bits specify the minimum number of DDR3_CLKOUT cycles from the last write transfer to a precharge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 18.--24. 1. "T_RAS,These bits specify the minimum number of DDR3_CLKOUT cycles from an activate command to precharge command minus 1"
|
|
hexmask.long.byte 0x00 10.--17. 1. "T_RC,These bits specify the minimum number of DDR3_CLKOUT cycles from an activate command to an activate command minus 1"
|
|
bitfld.long 0x00 4.--9. "T_RRD,These bits specify the minimum number of DDR3_CLKOUT cycles from an activate to an activate in a different bank minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "T_WTR,These bits specify the minimum number of DDR3_CLKOUT cycles from the last write to a read command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "EMIF_SDTIM2,"
|
|
bitfld.long 0x04 10.--12. "T_RTW,Minimum number of DDR3_CLKOUT cycles between read and write date phases minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 5.--9. "T_RP,These bits specify the minimum number of DDR3_CLKOUT cycles from a precharge command to a refresh or activate command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. "T_RCD,These bits specify the minimum number of DDR3_CLKOUT cycles from an activate command to a read or write command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "EMIF_SDTIM3,"
|
|
bitfld.long 0x08 28.--31. "T_XP,These bits specify the minimum number of DDR3_CLKOUT cycles from Power down exit to any command other than a read command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x08 18.--27. 1. "T_XSNR,These bits specify the minimum number of DDR3_CLKOUT cycles from a self-refresh exit to a command that does not require a locked DLL minus 1"
|
|
hexmask.long.word 0x08 8.--17. 1. "T_XSRD,These bits specify the minimum number of DDR3_CLKOUT cycles from a self-refresh exit to a command that requires a locked DLL minus 1"
|
|
bitfld.long 0x08 4.--7. "T_RTP,These bits specify the minimum number of DDR3_CLKOUT cycles from the last read to precharge command minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 0.--3. "T_CKE,These bits specify the minimum number of DDR3_CLKOUT cycles between transitions on the DDR3_CKE pin minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EMIF_SDTIM4,"
|
|
bitfld.long 0x00 28.--31. "T_CSTA,Minimum DDR3_CLKOUT cycles between write-to-write or read-to-read data phases to different chip selects minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "T_CKESR,Value = 0Minimum DDR3_CLKOUT cycles for which DDR3 should remain in self-refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ZQ_ZQCS,These bits specify the minimum number of DDR3_CLKOUT cycles for a ZQCS command minus 1"
|
|
hexmask.long.word 0x00 4.--13. 1. "T_RFC,These bits specify the minimum number of DDR3_CLKOUT cycles from a refresh or load mode command to a refresh or activate command minus 1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "T_RAS_MAX,This field must always be programmed to Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "EMIF_PMCTL,"
|
|
bitfld.long 0x00 12.--15. "PD_TIM,Power Management timer for power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--10. "LP_MODE,Automatic power management enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--7. "SR_TIM,Power management timer for self-refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "EMIF_VBUSM_CONFIG,"
|
|
hexmask.long.byte 0x00 16.--23. 1. "COS_COUNT_1,Priority raise counter for Class of Service 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "COS_COUNT_2,Priority raise counter for Class of Service 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PR_OLD_COUNT,Priority raise old counter"
|
|
rgroup.long 0x80++0x13
|
|
line.long 0x00 "EMIF_PERF_CNT_1,"
|
|
line.long 0x04 "EMIF_PERF_CNT_2,"
|
|
line.long 0x08 "EMIF_PERF_CNT_CFG,"
|
|
bitfld.long 0x08 31. "CNTR2_MSTID_EN,Master ID filter enable for Performance Counter 2 Register" "0,1"
|
|
bitfld.long 0x08 30. "CNTR2_REGION_EN,Memory space region enable for Performance Counter 2 Register" "0,1"
|
|
bitfld.long 0x08 16.--19. "CNTR2_CFG,Filter configuration selected for Performance Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 15. "CNTR1_MSTID_EN,Master ID filter enable for Performance Counter 1 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x08 14. "CNTR1_REGION_EN,Memory space region enable for Performance Counter 1 Register" "0,1"
|
|
bitfld.long 0x08 0.--3. "CNTR1_CFG,Filter configuration selected for Performance Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "EMIF_PERF_CNT_SEL,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "MSTID2,Master ID for Performance Counter 2 Register"
|
|
bitfld.long 0x0C 16.--19. "REGION_SEL2,Region select for Performance Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "MSTID1,Master ID for Performance Counter 1 Register"
|
|
bitfld.long 0x0C 0.--3. "REGION_SEL1,Region select for Performance Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "EMIF_PERF_CNT_TIM,"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "EMIF_IRQSTATUS_RAW_SYS,"
|
|
bitfld.long 0x00 5. "_1B_ECC_ERR_SYS,Value = 0hRaw status of 1-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 4. "_2B_ECC_ERR_SYS,Value = 0hRaw status of 2-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Value = 0hRaw status of write ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 0. "ERR_SYS,Value = 0hRaw status of system VBUSM interrupt for command or address error" "0,1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "EMIF_IRQSTATUS_SYS,"
|
|
bitfld.long 0x00 5. "_1B_ECC_ERR_SYS,Value = 0hEnabled status of 1-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 4. "_2B_ECC_ERR_SYS,Value = 0hEnabled status of 2-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Value = 0hEnabled status of write ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 0. "ERR_SYS,Value = 0hEnabled status of system VBUSM interrupt for command or address error" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "EMIF_IRQENABLE_SET_SYS,"
|
|
bitfld.long 0x00 5. "_1B_ECC_ERR_SYS,Value = 0hEnabled set for 1-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 4. "_2B_ECC_ERR_SYS,Value = 0hEnabled set for 2-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Value = 0hEnabled set for write ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 0. "ERR_SYS,Value = 0hEnable set for system VBUSM interrupt for command or address error" "0,1"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "EMIF_IRQENABLE_CLR_SYS,"
|
|
bitfld.long 0x00 5. "_1B_ECC_ERR_SYS,Value = 0hEnabled clear for 1-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 4. "_2B_ECC_ERR_SYS,Value = 0hEnabled clear for 2-bit ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Value = 0hEnabled clear for write ECC error interrupt" "0,1"
|
|
bitfld.long 0x00 0. "ERR_SYS,Value = 0hEnable clear for system VBUSM interrupt for command or address error" "0,1"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "EMIF_ZQ_CONFIG,"
|
|
bitfld.long 0x00 31. "ZQ_CS1EN,ZQ calibration for CS1" "0,1"
|
|
bitfld.long 0x00 30. "ZQ_CS0EN,ZQ calibration for CS0" "0,1"
|
|
bitfld.long 0x00 29. "ZQ_DUALCALEN,ZQ Dual Calibration enable" "0,1"
|
|
bitfld.long 0x00 28. "ZQ_SFEXITEN,ZQCL on Self-refresh Active power-down and precharge power-down exit enable.Set this value to 1 to issue a ZQCL command upon self-refresh exit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "ZQ_ZQCL_MULT,Number of ZQCS intervals that make up a ZQCL interval minus one" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. "ZQ_REFINTERVAL,Number of refresh periods between ZQCS commands minus one"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "EMIF_PRI_COS_MAP,"
|
|
bitfld.long 0x00 31. "PRI_COS_MAP_EN,Priority to Class-of-service mapping" "0,1"
|
|
bitfld.long 0x00 14.--15. "PRI_7_COS,Class-of-service for commands with priority of 7 (lowest priority)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PRI_6_COS,Class-of-service for commands with priority of 6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "PRI_5_COS,Class-of-service for commands with priority of 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PRI_4_COS,Class-of-service for commands with priority of 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_3_COS,Class-of-service for commands with priority of 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PRI_2_COS,Class-of-service for commands with priority of 2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PRI_1_COS,Class-of-service for commands with priority of 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PRI_0_COS,Class-of-service for commands with priority of 0 (highest priority)" "0,1,2,3"
|
|
line.long 0x04 "EMIF_MSTID_COS_1_MAP,"
|
|
bitfld.long 0x04 31. "MSTID_COS_1_MAP_EN,Master ID to Class-of-service 1 mapping" "0,1"
|
|
hexmask.long.byte 0x04 23.--30. 1. "MSTID_1_COS_1,Master ID value 1 for Class-of-service 1"
|
|
bitfld.long 0x04 20.--22. "MSK_1_COS_1,Mask for master ID value 1 for Class-of-service 1" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 12.--19. 1. "MSTID_2_COS_1,Master ID value 2 for Class-of-service 1"
|
|
newline
|
|
bitfld.long 0x04 10.--11. "MSK_2_COS_1,Mask for master ID value 2 for Class-of-service 1" "0,1,2,3"
|
|
hexmask.long.byte 0x04 2.--9. 1. "MSTID_3_COS_1,Master ID value 3 for Class-of-service 1"
|
|
bitfld.long 0x04 0.--1. "MSK_3_COS_1,Mask for master ID value 3 for Class-of-service 1" "0,1,2,3"
|
|
line.long 0x08 "EMIF_MSTID_COS_2_MAP,"
|
|
bitfld.long 0x08 31. "MSTID_COS_2_MAP_EN,Master ID to Class-of-service 2 mapping" "0,1"
|
|
hexmask.long.byte 0x08 23.--30. 1. "MSTID_1_COS_2,Master ID value 1 for Class-of-service 2"
|
|
bitfld.long 0x08 20.--22. "MSK_1_COS_2,Mask for master ID value 1 for Class-of-service 2" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x08 12.--19. 1. "MSTID_2_COS_2,Master ID value 2 for Class-of-service 2"
|
|
newline
|
|
bitfld.long 0x08 10.--11. "MSK_2_COS_2,Mask for master ID value 2 for Class-of-service 2" "0,1,2,3"
|
|
hexmask.long.byte 0x08 2.--9. 1. "MSTID_3_COS_2,Master ID value 3 for Class-of-service 2"
|
|
bitfld.long 0x08 0.--1. "MSK_3_COS_2,Mask for master ID value 3 for Class-of-service 2" "0,1,2,3"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "EMIF_ECCCTL,"
|
|
bitfld.long 0x00 31. "ECC_EN,ECC enable" "0,1"
|
|
bitfld.long 0x00 30. "ECC_ADDR_RNG_PROT,This bit is used to determine whether ECC calculation is allowed within address ranges described by ECC Address Range 1 and 2 Registers provided ECC_EN is set to enable ECC" "0,1"
|
|
bitfld.long 0x00 29. "ECC_VERIFY_EN,This field is ignored if ECC_EN=0" "0,1"
|
|
bitfld.long 0x00 28. "RMW_EN,This field is ignored if ECC_EN=0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ECC_ADDR_RNG_2_EN,ECC Address Range 2 enable" "0,1"
|
|
bitfld.long 0x00 0. "ECC_ADDR_RNG_1_EN,ECC Address Range 1 enable" "0,1"
|
|
line.long 0x04 "EMIF_ECCADDR1,"
|
|
hexmask.long.word 0x04 16.--31. 1. "ECC_END_ADDR_1,End address [32-17] of 33-bit address for ECC address range 1"
|
|
hexmask.long.word 0x04 0.--15. 1. "ECC_STRT_ADDR_1,Start address [32-17] of 33-bit address for ECC address range 1"
|
|
line.long 0x08 "EMIF_ECCADDR2,"
|
|
hexmask.long.word 0x08 16.--31. 1. "ECC_END_ADDR_2,End address [32-17] of 33-bit address for ECC address range 2"
|
|
hexmask.long.word 0x08 0.--15. 1. "ECC_STRT_ADDR_2,Start address [32-17] of 33-bit address for ECC address range 2"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "EMIF_RWTHRESH,"
|
|
bitfld.long 0x00 8.--12. "WR_THRSH,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "RD_THRSH,Read Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x130++0x17
|
|
line.long 0x00 "EMIF_ONE_BIT_ECC_ERR_CNT,"
|
|
line.long 0x04 "EMIF_ONE_BIT_ECC_ERR_THRSH,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "_1B_ECC_ERR_THRSH,1-bit ECC error threshold"
|
|
hexmask.long.word 0x04 0.--15. 1. "_1B_ECC_ERR_WIN,1-bit ECC error window in number of refresh periods"
|
|
line.long 0x08 "EMIF_ONE_BIT_ECC_ERR_DIST_1,"
|
|
line.long 0x0C "EMIF_ONE_BIT_ECC_ERR_ADDR_LOG,"
|
|
line.long 0x10 "EMIF_TWO_BIT_ECC_ERR_ADDR_LOG,"
|
|
line.long 0x14 "EMIF_ONE_BIT_ECC_ERR_DIST_2,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "ePWM"
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5.)(list ad:0x21D0000 ad:0x21D0400 ad:0x21D0800 ad:0x21D0C00 ad:0x21D1000 ad:0x21D1400)
|
|
tree "EPWM_$1"
|
|
base $2
|
|
group.word 0x00++0x0B
|
|
line.word 0x00 "EPWM_TBCTL,"
|
|
bitfld.word 0x00 14.--15. "FREE_SOFT," "0,1,2,3"
|
|
bitfld.word 0x00 13. "PHSDIR," "0,1"
|
|
bitfld.word 0x00 10.--12. "CLKDIV," "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. "HSPCLKDIV," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. "SWFSYNC," "0,1"
|
|
bitfld.word 0x00 4.--5. "SYNCOSEL," "0,1,2,3"
|
|
bitfld.word 0x00 3. "PRDLD," "0,1"
|
|
bitfld.word 0x00 2. "PHSEN," "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. "CTRMODE," "0,1,2,3"
|
|
line.word 0x02 "EPWM_TBSTS,"
|
|
bitfld.word 0x02 2. "CTRMAX," "0,1"
|
|
bitfld.word 0x02 1. "SYNCI," "0,1"
|
|
rbitfld.word 0x02 0. "CTRDIR," "0,1"
|
|
line.word 0x04 "HRPWM_TBPHSHR,"
|
|
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,"
|
|
line.word 0x06 "EPWM_TBPHS,"
|
|
line.word 0x08 "EPWM_TBCNT,"
|
|
line.word 0x0A "EPWM_TBPRD,"
|
|
group.word 0x0E++0x17
|
|
line.word 0x00 "EPWM_CMPCTL,"
|
|
rbitfld.word 0x00 9. "SHDWBFULL," "0,1"
|
|
rbitfld.word 0x00 8. "SHDWAFULL," "0,1"
|
|
bitfld.word 0x00 6. "SHDWBMODE," "0,1"
|
|
bitfld.word 0x00 4. "SHDWAMODE," "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. "LOADBMODE," "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. "LOADAMODE," "0,1,2,3"
|
|
line.word 0x02 "HRPWM_CMPAHR,"
|
|
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,"
|
|
line.word 0x04 "EPWM_CMPA,"
|
|
line.word 0x06 "EPWM_CMPB,"
|
|
line.word 0x08 "EPWM_AQCTLA,"
|
|
bitfld.word 0x08 10.--11. "CBD," "0,1,2,3"
|
|
bitfld.word 0x08 8.--9. "CBU," "0,1,2,3"
|
|
bitfld.word 0x08 6.--7. "CAD," "0,1,2,3"
|
|
bitfld.word 0x08 4.--5. "CAU," "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x08 2.--3. "PRD," "0,1,2,3"
|
|
bitfld.word 0x08 0.--1. "ZRO," "0,1,2,3"
|
|
line.word 0x0A "EPWM_AQCTLB,"
|
|
bitfld.word 0x0A 10.--11. "CBD," "0,1,2,3"
|
|
bitfld.word 0x0A 8.--9. "CBU," "0,1,2,3"
|
|
bitfld.word 0x0A 6.--7. "CAD," "0,1,2,3"
|
|
bitfld.word 0x0A 4.--5. "CAU," "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0A 2.--3. "PRD," "0,1,2,3"
|
|
bitfld.word 0x0A 0.--1. "ZRO," "0,1,2,3"
|
|
line.word 0x0C "EPWM_AQSFRC,"
|
|
bitfld.word 0x0C 6.--7. "RLDCSF," "0,1,2,3"
|
|
bitfld.word 0x0C 5. "OTSFB," "0,1"
|
|
bitfld.word 0x0C 3.--4. "ACTSFB," "0,1,2,3"
|
|
bitfld.word 0x0C 2. "OTSFA," "0,1"
|
|
newline
|
|
bitfld.word 0x0C 0.--1. "ACTSFA," "0,1,2,3"
|
|
line.word 0x0E "EPWM_AQCSFRC,"
|
|
bitfld.word 0x0E 2.--3. "CSFB," "0,1,2,3"
|
|
bitfld.word 0x0E 0.--1. "CSFA," "0,1,2,3"
|
|
line.word 0x10 "EPWM_DBCTL,"
|
|
bitfld.word 0x10 4.--5. "IN_MODE," "0,1,2,3"
|
|
bitfld.word 0x10 2.--3. "POLSEL," "0,1,2,3"
|
|
bitfld.word 0x10 0.--1. "OUT_MODE," "0,1,2,3"
|
|
line.word 0x12 "EPWM_DBRED,"
|
|
hexmask.word 0x12 0.--9. 1. "DEL,"
|
|
line.word 0x14 "EPWM_DBFED,"
|
|
hexmask.word 0x14 0.--9. 1. "DEL,"
|
|
line.word 0x16 "EPWM_TZSEL,"
|
|
bitfld.word 0x16 13. "OSHT6," "0,1"
|
|
bitfld.word 0x16 12. "OSHT5," "0,1"
|
|
bitfld.word 0x16 11. "OSHT4," "0,1"
|
|
bitfld.word 0x16 10. "OSHT3," "0,1"
|
|
newline
|
|
bitfld.word 0x16 9. "OSHT2," "0,1"
|
|
bitfld.word 0x16 8. "OSHT1," "0,1"
|
|
bitfld.word 0x16 5. "CBC5," "0,1"
|
|
bitfld.word 0x16 4. "CBC4," "0,1"
|
|
newline
|
|
bitfld.word 0x16 3. "CBC3," "0,1"
|
|
bitfld.word 0x16 2. "CBC2," "0,1"
|
|
bitfld.word 0x16 1. "CBC1," "0,1"
|
|
bitfld.word 0x16 0. "CBC0," "0,1"
|
|
group.word 0x28++0x15
|
|
line.word 0x00 "EPWM_TZCTL,"
|
|
bitfld.word 0x00 2.--3. "TZB," "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. "TZA," "0,1,2,3"
|
|
line.word 0x02 "EPWM_TZEINT,"
|
|
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation"
|
|
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation"
|
|
line.word 0x04 "EPWM_TZFLG,"
|
|
bitfld.word 0x04 2. "OST," "0,1"
|
|
bitfld.word 0x04 1. "CBC," "0,1"
|
|
bitfld.word 0x04 0. "INT," "0,1"
|
|
line.word 0x06 "EPWM_TZCLR,"
|
|
bitfld.word 0x06 2. "OST," "0,1"
|
|
bitfld.word 0x06 1. "CBC," "0,1"
|
|
bitfld.word 0x06 0. "INT," "0,1"
|
|
line.word 0x08 "EPWM_TZFRC,"
|
|
bitfld.word 0x08 2. "OST," "0,1"
|
|
bitfld.word 0x08 1. "CBC," "0,1"
|
|
line.word 0x0A "EPWM_ETSEL,"
|
|
bitfld.word 0x0A 15. "SOCB,Enable SOCB pulse when set to 1" "0,1"
|
|
bitfld.word 0x0A 12.--14. "SOCBSEL,EPWMxSOCB Selection Options:0h: Reserved1h: Enable event time-base counter equal to zero (CNT_zero" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0A 11. "SOCA,Enable SOCA pulse when set to 1" "0,1"
|
|
bitfld.word 0x0A 8.--10. "SOCASEL,EPWMxSOCA Selection Options:0h: Reserved1h: Enable event time-base counter equal to zero (CNT_zero" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x0A 3. "INTEN," "0,1"
|
|
bitfld.word 0x0A 0.--2. "INTSEL," "0,1,2,3,4,5,6,7"
|
|
line.word 0x0C "EPWM_ETPS,"
|
|
rbitfld.word 0x0C 14.--15. "SOCBCNT,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred:0h: No" "0,1,2,3"
|
|
bitfld.word 0x0C 12.--13. "SOCBPRD,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated:0h: Disable" "0,1,2,3"
|
|
rbitfld.word 0x0C 10.--11. "SOCACNT,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred:0h: No" "0,1,2,3"
|
|
bitfld.word 0x0C 8.--9. "SOCAPRD,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated:0h: Disable" "0,1,2,3"
|
|
newline
|
|
rbitfld.word 0x0C 2.--3. "INTCNT," "0,1,2,3"
|
|
bitfld.word 0x0C 0.--1. "INTPRD," "0,1,2,3"
|
|
line.word 0x0E "EPWM_ETFLG,"
|
|
bitfld.word 0x0E 3. "SOCB,Latched SOCB Flag Bit Status:0h: Indicates no event occurred.1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB.Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set" "0,1"
|
|
bitfld.word 0x0E 2. "SOCA,Latched SOCA Flag Bit Status:0h: Indicates no event occurred.1h: Indicates that a start of conversion pulse was generated on ePWMxSOCA.Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
|
|
bitfld.word 0x0E 0. "INT," "0,1"
|
|
line.word 0x10 "EPWM_ETCLR,"
|
|
bitfld.word 0x10 3. "SOCB,SOCB Flag Clear" "0,1"
|
|
bitfld.word 0x10 2. "SOCA,SOCA Flag Clear" "0,1"
|
|
bitfld.word 0x10 0. "INT," "0,1"
|
|
line.word 0x12 "EPWM_ETFRC,"
|
|
bitfld.word 0x12 3. "SOCB,SOCB Force" "0,1"
|
|
bitfld.word 0x12 2. "SOCA,SOCA Force" "0,1"
|
|
bitfld.word 0x12 0. "INT," "0,1"
|
|
line.word 0x14 "EPWM_PCCTL,"
|
|
bitfld.word 0x14 8.--10. "CHPDUTY," "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x14 5.--7. "CHPFREQ," "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x14 1.--4. "OSHTWTH," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x14 0. "CHPEN," "0,1"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "HRPWM_HRCTL,"
|
|
bitfld.word 0x00 3. "PULSESEL," "0,1"
|
|
bitfld.word 0x00 2. "DELBUSSEL," "0,1"
|
|
bitfld.word 0x00 0.--1. "DELMODE,Edge Mode Bits" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "eQEP"
|
|
repeat 3. (list 0. 1. 2.)(list ad:0x21C0000 ad:0x21C0400 ad:0x21C0800)
|
|
tree "EQEP_$1"
|
|
base $2
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "EQEP_QPOSCNT,"
|
|
line.long 0x04 "EQEP_QPOSINIT,"
|
|
line.long 0x08 "EQEP_QPOSMAX,"
|
|
line.long 0x0C "EQEP_QPOSCMP,"
|
|
line.long 0x10 "EQEP_QPOSILAT,"
|
|
line.long 0x14 "EQEP_QPOSSLAT,"
|
|
line.long 0x18 "EQEP_QPOSLAT,"
|
|
line.long 0x1C "EQEP_QUTMR,"
|
|
line.long 0x20 "EQEP_QUPRD,"
|
|
group.word 0x24++0x1D
|
|
line.word 0x00 "EQEP_QWDTMR,"
|
|
line.word 0x02 "EQEP_QWDPRD,"
|
|
line.word 0x04 "EQEP_QDECCTL,"
|
|
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "Quadrature count mode (QCLK = iCLK QDIR = iDIR),Direction-count mode (QCLK = xCLK QDIR = xDIR),UP count mode for frequency measurement (QCLK =..,DOWN count mode for frequency measurement (QCLK.."
|
|
bitfld.word 0x04 13. "SOEN,Sync output-enable" "Disable position-compare sync output,Enable position-compare sync output"
|
|
newline
|
|
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "Index pin is used for sync output,Strobe pin is used for sync output"
|
|
bitfld.word 0x04 11. "XCR,External clock rate" "2x resolution,1x resolution"
|
|
newline
|
|
bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "Quadrature-clock inputs are not swapped,Quadrature-clock inputs are swapped"
|
|
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe"
|
|
newline
|
|
bitfld.word 0x04 8. "QAP,QEPA input polarity" "No effect,Negates QEPA input"
|
|
bitfld.word 0x04 7. "QBP,QEPB input polarity" "No effect,Negates QEPB input"
|
|
newline
|
|
bitfld.word 0x04 6. "QIP,QEPI input polarity" "No effect,Negates QEPI input"
|
|
bitfld.word 0x04 5. "QSP,QEPS input polarity" "No effect,Negates QEPS input"
|
|
line.word 0x06 "EQEP_QEPCTL,"
|
|
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "?,x continues to count until the rollover,x is unaffected by emulation suspend,x is unaffected by emulation suspend"
|
|
bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "Position counter reset on an index event,Position counter reset on the maximum position,Position counter reset on the first index event,Position counter reset on a unit time event"
|
|
newline
|
|
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "Does nothing (action disabled),Does nothing (action disabled),Initializes the position counter on rising edge..,Clockwise Direction"
|
|
bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "Do nothing (action disabled),Do nothing (action disabled),Initializes the position counter on the rising..,Initializes the position counter on the falling.."
|
|
newline
|
|
bitfld.word 0x06 7. "SWI,Software initialization of position counter" "Do nothing (action disabled),Initialize position counter this bit is cleared.."
|
|
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
|
|
newline
|
|
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "Reserved,Latches position counter on rising edge of the..,Latches position counter on falling edge of the..,Software index marker"
|
|
bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "Reset the eQEP peripheral internal operating..,eQEP position counter is enabled"
|
|
newline
|
|
bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "0,1"
|
|
bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "Disable eQEP unit timer,Enable unit timer"
|
|
newline
|
|
bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "Disable the eQEP watchdog timer,Enable the eQEP watchdog timer"
|
|
line.word 0x08 "EQEP_QCAPCTL,"
|
|
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "eQEP capture unit is disabled,eQEP capture unit is enabled"
|
|
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "CAPCLK = SYSCLKOUT/1,CAPCLK = SYSCLKOUT/2,CAPCLK = SYSCLKOUT/4,CAPCLK = SYSCLKOUT/8,CAPCLK = SYSCLKOUT/16,CAPCLK = SYSCLKOUT/32,CAPCLK = SYSCLKOUT/64,CAPCLK = SYSCLKOUT/128"
|
|
newline
|
|
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "UPEVNT = QCLK/1,UPEVNT = QCLK/2,UPEVNT = QCLK/4,UPEVNT = QCLK/8,UPEVNT = QCLK/16,UPEVNT = QCLK/32,UPEVNT = QCLK/64,UPEVNT = QCLK/128,UPEVNT = QCLK/256,UPEVNT = QCLK/512,UPEVNT = QCLK/1024,UPEVNT = QCLK/2048,Reserved,Reserved,Reserved,Reserved"
|
|
line.word 0x0A "EQEP_QPOSCTL,"
|
|
bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "Shadow disabled load Immediate,Shadow enabled"
|
|
bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "Load on QPOSCNT = 0,Load when QPOSCNT = QPOSCMP"
|
|
newline
|
|
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "Active HIGH pulse output,Active LOW pulse output"
|
|
bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "Disable position compare unit,Enable position compare unit"
|
|
newline
|
|
abitfld.word 0x0A 0.--11. "PCSPW,Select-position-compare sync output pulse width" "0x000=1 x 4 x SYSCLKOUT cycles,0x001=2 x 4 x SYSCLKOUT cycles,0x002=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x..,0xFFF=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x.."
|
|
line.word 0x0C "EQEP_QEINT,"
|
|
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "Interrupt is disabled,Interrupt is enabled"
|
|
line.word 0x0E "EQEP_QFLG,"
|
|
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "No interrupt generated,Set by eQEP unit timer period match"
|
|
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to.."
|
|
newline
|
|
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT.."
|
|
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "No interrupt generated,This bit is set on position-compare match"
|
|
newline
|
|
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "No interrupt generated,This bit is set after transferring the shadow.."
|
|
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "No interrupt generated,This bit is set on position counter overflow"
|
|
newline
|
|
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "No interrupt generated,This bit is set on position counter underflow"
|
|
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "No interrupt generated,Set by watch dog timeout"
|
|
newline
|
|
bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "No interrupt generated,This bit is set during change of direction"
|
|
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "No interrupt generated,Set on simultaneous transition of QEPA and QEPB"
|
|
newline
|
|
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "No interrupt generated,Position counter error"
|
|
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "No interrupt generated,Interrupt was generated"
|
|
line.word 0x10 "EQEP_QCLR,"
|
|
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "No effect,Clears the interrupt flag"
|
|
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "No effect,Clears the interrupt flag"
|
|
newline
|
|
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "No effect,Clears the interrupt flag"
|
|
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "No effect,Clears the interrupt flag"
|
|
newline
|
|
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "No effect,Clears the interrupt flag"
|
|
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "No effect,Clears the interrupt flag"
|
|
newline
|
|
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "No effect,Clears the interrupt flag"
|
|
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "No effect,Clears the interrupt flag"
|
|
newline
|
|
bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "No effect,Clears the interrupt flag"
|
|
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "No effect,Clears the interrupt flag"
|
|
newline
|
|
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "No effect,Clears the interrupt flag"
|
|
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "No effect,Clears the interrupt flag.."
|
|
line.word 0x12 "EQEP_QFRC,"
|
|
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "No effect,Force the interrupt"
|
|
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "No effect,Force the interrupt"
|
|
newline
|
|
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "No effect,Force the interrupt"
|
|
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "No effect,Force the interrupt"
|
|
newline
|
|
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "No effect,Force the interrupt"
|
|
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "No effect,Force the interrupt"
|
|
newline
|
|
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "No effect,Force the interrupt"
|
|
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "No effect,Force the interrupt"
|
|
newline
|
|
bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "No effect,Force the interrupt"
|
|
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "No effect,Force the interrupt"
|
|
newline
|
|
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "No effect,Force the interrupt"
|
|
line.word 0x14 "EQEP_QEPSTS,"
|
|
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "No unit position event detected,Unit position event detected"
|
|
bitfld.word 0x14 6. "FDF,Direction on the first index marker" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on the.."
|
|
newline
|
|
bitfld.word 0x14 5. "QDF,Quadrature direction flag" "Counter-clockwise rotation (or reverse movement),Clockwise rotation (or forward movement)"
|
|
bitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on.."
|
|
newline
|
|
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "Sticky bit cleared by writing 1,Overflow occurred in eQEP Capture timer (QEPCTMR)"
|
|
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "Sticky bit cleared by writing 1,Direction change occurred between the capture.."
|
|
newline
|
|
bitfld.word 0x14 1. "FIMF,First index marker flag" "Sticky bit cleared by writing 1,Set by first occurrence of index pulse"
|
|
bitfld.word 0x14 0. "PCEF,Position counter error flag" "No error occurred during the last index transition,Position counter error"
|
|
line.word 0x16 "EQEP_QCTMR,"
|
|
line.word 0x18 "EQEP_QCPRD,"
|
|
line.word 0x1A "EQEP_QCTMRLAT,"
|
|
line.word 0x1C "EQEP_QCPRDLAT,"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "EQEP_REVID,"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "GPIO"
|
|
repeat 2. (list 0. 1.)(list ad:0x2603000 ad:0x260A000)
|
|
tree "GPIO_$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "GPIO_PID,"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPIO_BINTEN,"
|
|
hexmask.long.word 0x00 0.--8. 1. "EN,Enables GPIO pins in each bank as interrupt sources to the CPU"
|
|
group.long 0x10++0xC7
|
|
line.long 0x00 "GPIO_DIR01,"
|
|
line.long 0x04 "GPIO_OUT_DATA01,"
|
|
line.long 0x08 "GPIO_SET_DATA01,"
|
|
line.long 0x0C "GPIO_CLR_DATA01,"
|
|
line.long 0x10 "GPIO_IN_DATA01,"
|
|
line.long 0x14 "GPIO_SET_RIS_TRIG01,"
|
|
line.long 0x18 "GPIO_CLR_RIS_TRIG01,"
|
|
line.long 0x1C "GPIO_SET_FAL_TRIG01,"
|
|
line.long 0x20 "GPIO_CLR_FAL_TRIG01,"
|
|
line.long 0x24 "GPIO_INTSTAT01,"
|
|
line.long 0x28 "GPIO_DIR23,"
|
|
line.long 0x2C "GPIO_OUT_DATA23,"
|
|
line.long 0x30 "GPIO_SET_DATA23,"
|
|
line.long 0x34 "GPIO_CLR_DATA23,"
|
|
line.long 0x38 "GPIO_IN_DATA23,"
|
|
line.long 0x3C "GPIO_SET_RIS_TRIG23,"
|
|
line.long 0x40 "GPIO_CLR_RIS_TRIG23,"
|
|
line.long 0x44 "GPIO_SET_FAL_TRIG23,"
|
|
line.long 0x48 "GPIO_CLR_FAL_TRIG23,"
|
|
line.long 0x4C "GPIO_INTSTAT23,"
|
|
line.long 0x50 "GPIO_DIR45,"
|
|
line.long 0x54 "GPIO_OUT_DATA45,"
|
|
line.long 0x58 "GPIO_SET_DATA45,"
|
|
line.long 0x5C "GPIO_CLR_DATA45,"
|
|
line.long 0x60 "GPIO_IN_DATA45,"
|
|
line.long 0x64 "GPIO_SET_RIS_TRIG45,"
|
|
line.long 0x68 "GPIO_CLR_RIS_TRIG45,"
|
|
line.long 0x6C "GPIO_SET_FAL_TRIG45,"
|
|
line.long 0x70 "GPIO_CLR_FAL_TRIG45,"
|
|
line.long 0x74 "GPIO_INTSTAT45,"
|
|
line.long 0x78 "GPIO_DIR67,"
|
|
line.long 0x7C "GPIO_OUT_DATA67,"
|
|
line.long 0x80 "GPIO_SET_DATA67,"
|
|
line.long 0x84 "GPIO_CLR_DATA67,"
|
|
line.long 0x88 "GPIO_IN_DATA67,"
|
|
line.long 0x8C "GPIO_SET_RIS_TRIG67,"
|
|
line.long 0x90 "GPIO_CLR_RIS_TRIG67,"
|
|
line.long 0x94 "GPIO_SET_FAL_TRIG67,"
|
|
line.long 0x98 "GPIO_CLR_FAL_TRIG67,"
|
|
line.long 0x9C "GPIO_INTSTAT67,"
|
|
line.long 0xA0 "GPIO_DIR8,"
|
|
hexmask.long.word 0xA0 0.--15. 1. "DIR,Controls the direction of the GPIOj pin j = 129 to 144"
|
|
line.long 0xA4 "GPIO_OUT_DATA8,"
|
|
hexmask.long.word 0xA4 0.--15. 1. "OUT,Controls the drive state of the corresponding GPIOj pin j = 129 to 144"
|
|
line.long 0xA8 "GPIO_SET_DATA8,"
|
|
hexmask.long.word 0xA8 0.--15. 1. "SET,Writing 1 sets the corresponding bit in the Output Data 8 register"
|
|
line.long 0xAC "GPIO_CLR_DATA8,"
|
|
hexmask.long.word 0xAC 0.--15. 1. "CLR,Writing 1 clears the corresponding bit in the Output Data 8 register"
|
|
line.long 0xB0 "GPIO_IN_DATA8,"
|
|
hexmask.long.word 0xB0 0.--15. 1. "IN,Returns the status of the corresponding GPIOj pin j = 129 to 144"
|
|
line.long 0xB4 "GPIO_SET_RIS_TRIG8,"
|
|
hexmask.long.word 0xB4 0.--15. 1. "SETRIS,Writing a 1 enables the rising edge detection for the corresponding GPIOj pin j = 129 to 144"
|
|
line.long 0xB8 "GPIO_CLR_RIS_TRIG8,"
|
|
hexmask.long.word 0xB8 0.--15. 1. "CLRRIS,Writing a 1 disables the rising edge detection for the corresponding GPIOj pin j = 129 to 144"
|
|
line.long 0xBC "GPIO_SET_FAL_TRIG8,"
|
|
hexmask.long.word 0xBC 0.--15. 1. "SETFAL,Writing a 1 enables the falling edge detection for the corresponding GPIOj pin j = 129 to 144"
|
|
line.long 0xC0 "GPIO_CLR_FAL_TRIG8,"
|
|
hexmask.long.word 0xC0 0.--15. 1. "CLRFAL,Writing a 1 disables the falling edge detection for the corresponding GPIOj pin j = 129 to 144"
|
|
line.long 0xC4 "GPIO_INTSTAT8,"
|
|
hexmask.long.word 0xC4 0.--15. 1. "STAT,Status of GPIO bank 8 interrupts"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "GPMC"
|
|
base ad:0x21818000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "GPMC_REVISION,"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "GPMC_SYSCONFIG,"
|
|
bitfld.long 0x00 3.--4. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
|
|
newline
|
|
bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running" "AUTOIDLE_0,AUTOIDLE_1"
|
|
line.long 0x04 "GPMC_SYSSTATUS,"
|
|
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing" "RESETDONE_0,RESETDONE_1"
|
|
line.long 0x08 "GPMC_IRQSTATUS,"
|
|
bitfld.long 0x08 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interruptWrite" "WAIT1EDGEDETECTIONSTATUS bit is unchanged,WAIT1EDGEDETECTIONSTATUS bit is reset.Read"
|
|
newline
|
|
bitfld.long 0x08 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interruptWrite" "WAIT0EDGEDETECTIONSTATUS bit is unchanged,WAIT0EDGEDETECTIONSTATUS bit is reset.Read"
|
|
newline
|
|
bitfld.long 0x08 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interruptWrite" "TERMINALCOUNTSTATUS bit is unchanged,TERMINALCOUNTSTATUS bit is reset.Read"
|
|
newline
|
|
bitfld.long 0x08 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interruptWrite" "FIFOEVENTSTATUS bit is unchanged,FIFOEVENTSTATUS bit is reset.Read"
|
|
line.long 0x0C "GPMC_IRQENABLE,"
|
|
bitfld.long 0x0C 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt 0h (R/W) = Wait1EdgeDetection interrupt is masked" "WAIT1EDGEDETECTIONENABLE_0,WAIT1EDGEDETECTIONENABLE_1"
|
|
newline
|
|
bitfld.long 0x0C 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt 0h (R/W) = Wait0EdgeDetection interrupt is masked" "WAIT0EDGEDETECTIONENABLE_0,WAIT0EDGEDETECTIONENABLE_1"
|
|
newline
|
|
bitfld.long 0x0C 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode 0h (R/W) = TerminalCountEvent interrupt is masked" "TERMINALCOUNTEVENTENABLE_0,TERMINALCOUNTEVENTENABLE_1"
|
|
newline
|
|
bitfld.long 0x0C 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt 0h (R/W) = FIFOEvent interrupt is masked" "FIFOEVENTENABLE_0,FIFOEVENTENABLE_1"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "GPMC_TIMEOUT_CONTROL,"
|
|
hexmask.long.word 0x00 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter"
|
|
newline
|
|
bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature 0h (R/W) = TimeOut feature is disabled" "TIMEOUTENABLE_0,TIMEOUTENABLE_1"
|
|
line.long 0x04 "GPMC_ERR_ADDRESS,"
|
|
hexmask.long 0x04 0.--30. 1. "ILLEGALADD,Address of illegal access"
|
|
line.long 0x08 "GPMC_ERR_TYPE,"
|
|
rbitfld.long 0x08 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "ILLEGALMCMD_0,ILLEGALMCMD_1,ILLEGALMCMD_2,ILLEGALMCMD_3,ILLEGALMCMD_4,ILLEGALMCMD_5,ILLEGALMCMD_6,ILLEGALMCMD_7"
|
|
newline
|
|
rbitfld.long 0x08 4. "ERRORNOTSUPPADD,Not supported address error 0h (R) = No error occurs" "ERRORNOTSUPPADD_0,ERRORNOTSUPPADD_1"
|
|
newline
|
|
rbitfld.long 0x08 3. "ERRORNOTSUPPMCMD,Not supported command error 0h (R) = No error occurs" "ERRORNOTSUPPMCMD_0,ERRORNOTSUPPMCMD_1"
|
|
newline
|
|
rbitfld.long 0x08 2. "ERRORTIMEOUT,Time-out error 0h (R) = No error occurs" "ERRORTIMEOUT_0,ERRORTIMEOUT_1"
|
|
newline
|
|
bitfld.long 0x08 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction 0h (R/W) = All error fields no longer valid 1h (R/W) = Error detected and logged in the other error fields" "ERRORVALID_0,ERRORVALID_1"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "GPMC_CONFIG,"
|
|
bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1 0h (R/W) = WAIT1 active low 1h (R/W) = WAIT1 active high" "WAIT1PINPOLARITY_0,WAIT1PINPOLARITY_1"
|
|
newline
|
|
bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0 0h (R/W) = WAIT0 active low 1h (R/W) = WAIT0 active high" "WAIT0PINPOLARITY_0,WAIT0PINPOLARITY_1"
|
|
newline
|
|
bitfld.long 0x00 4. "WRITEPROTECT,Controls the WP output pin level 0h (R/W) = nWP output pin is low 1h (R/W) = nWP output pin is high" "WRITEPROTECT_0,WRITEPROTECT_1"
|
|
newline
|
|
bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location 0h (R/W) = Disables Force Posted Write 1h (R/W) = Enables Force Posted" "NANDFORCEPOSTEDWRITE_0,NANDFORCEPOSTEDWRITE_1"
|
|
line.long 0x04 "GPMC_STATUS,"
|
|
bitfld.long 0x04 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "WAIT1STATUS_0,WAIT1STATUS_1"
|
|
newline
|
|
bitfld.long 0x04 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "WAIT0STATUS_0,WAIT0STATUS_1"
|
|
newline
|
|
bitfld.long 0x04 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer 0h (R) = Write buffer is not empty" "EMPTYWRITEBUFFERSTATUS_0,EMPTYWRITEBUFFERSTATUS_1"
|
|
group.long 0x1E0++0x07
|
|
line.long 0x00 "GPMC_PREFETCH_CONFIG1,"
|
|
bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "CYCLEOPTIMIZATION_0,CYCLEOPTIMIZATION_1,CYCLEOPTIMIZATION_2,CYCLEOPTIMIZATION_3,CYCLEOPTIMIZATION_4,CYCLEOPTIMIZATION_5,CYCLEOPTIMIZATION_6,CYCLEOPTIMIZATION_7"
|
|
newline
|
|
bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization 0h (R/W) = Access cycle optimization is disabled" "ENABLEOPTIMIZEDACCESS_0,ENABLEOPTIMIZEDACCESS_1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "ENGINECSSELECTOR_0,ENGINECSSELECTOR_1,ENGINECSSELECTOR_2,ENGINECSSELECTOR_3,ENGINECSSELECTOR_4,ENGINECSSELECTOR_5,ENGINECSSELECTOR_6,ENGINECSSELECTOR_7"
|
|
newline
|
|
bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration 0h (R/W) = Prefetch Postwrite engine round robin arbitration is disabled" "PFPWENROUNDROBIN_0,PFPWENROUNDROBIN_1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced" "PFPWWEIGHTEDPRIO_0,PFPWWEIGHTEDPRIO_1,PFPWWEIGHTEDPRIO_2,PFPWWEIGHTEDPRIO_3,PFPWWEIGHTEDPRIO_4,PFPWWEIGHTEDPRIO_5,PFPWWEIGHTEDPRIO_6,PFPWWEIGHTEDPRIO_7,PFPWWEIGHTEDPRIO_8,PFPWWEIGHTEDPRIO_9,PFPWWEIGHTEDPRIO_10,PFPWWEIGHTEDPRIO_11,PFPWWEIGHTEDPRIO_12,PFPWWEIGHTEDPRIO_13,PFPWWEIGHTEDPRIO_14,PFPWWEIGHTEDPRIO_15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request"
|
|
newline
|
|
bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine 0h (R/W) = Prefetch Postwrite engine is disabled" "ENABLEENGINE_0,ENABLEENGINE_1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode 0h (R/W) = Selects Wait0 EdgeDetection 1h (R/W) = Selects Wait1 EdgeDetection2h " "WAITPINSELECTOR_0,WAITPINSELECTOR_1,WAITPINSELECTOR_2,WAITPINSELECTOR_3"
|
|
newline
|
|
bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to chip-select 0h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set 1h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set AND wait to nonwait.." "SYNCHROMODE_0,SYNCHROMODE_1"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization 0h (R/W) = Interrupt synchronization is enabled" "DMAMODE_0,DMAMODE_1"
|
|
newline
|
|
bitfld.long 0x00 0. "ACCESSMODE,Selects prefetch read or write-posting accesses 0h (R/W) = Prefetch read mode 1h (R/W) = Write-posting mode" "ACCESSMODE_0,ACCESSMODE_1"
|
|
line.long 0x04 "GPMC_PREFETCH_CONFIG2,"
|
|
hexmask.long.word 0x04 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select"
|
|
group.long 0x1EC++0x13
|
|
line.long 0x00 "GPMC_PREFETCH_CONTROL,"
|
|
bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engineWrite" "Stops the engine,Resets the FIFO pointer to 0h in prefetch mode.."
|
|
line.long 0x04 "GPMC_PREFETCH_STATUS,"
|
|
hexmask.long.byte 0x04 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written"
|
|
newline
|
|
bitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value 0h (R) = FIFOPointer smaller or equal to FIFOThreshold" "FIFOTHRESHOLDSTATUS_0,FIFOTHRESHOLDSTATUS_1"
|
|
newline
|
|
hexmask.long.word 0x04 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value"
|
|
line.long 0x08 "GPMC_ECC_CONFIG,"
|
|
bitfld.long 0x08 16. "ECCALGORITHM,ECC algorithm used 0h (R/W) = Hamming code 1h (R/W) = BCH code" "ECCALGORITHM_0,ECCALGORITHM_1"
|
|
newline
|
|
bitfld.long 0x08 12.--13. "ECCBCHTSEL,Error correction capability used for BCH 0h (R/W) = Up to 4 bits error correction (t = 4) 1h (R/W) = Up to 8 bits error correction (t = 8) 2h (R/W) = Up to 16 bits error correction (t = 16) 3h (R/W) = Reserved" "ECCBCHTSEL_0,ECCBCHTSEL_1,ECCBCHTSEL_2,ECCBCHTSEL_3"
|
|
newline
|
|
bitfld.long 0x08 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "ECCWRAPMODE_0,ECCWRAPMODE_1,ECCWRAPMODE_2,ECCWRAPMODE_3,ECCWRAPMODE_4,ECCWRAPMODE_5,ECCWRAPMODE_6,ECCWRAPMODE_7,ECCWRAPMODE_8,ECCWRAPMODE_9,ECCWRAPMODE_10,ECCWRAPMODE_11,ECCWRAPMODE_12,ECCWRAPMODE_13,ECCWRAPMODE_14,ECCWRAPMODE_15"
|
|
newline
|
|
bitfld.long 0x08 7. "ECC16B,Selects an ECC calculated on 16 columns 0h (R/W) = ECC calculated on 8 columns 1h (R/W) = ECC calculated on 16 columns" "ECC16B_0,ECC16B_1"
|
|
newline
|
|
bitfld.long 0x08 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH" "ECCTOPSECTOR_0,ECCTOPSECTOR_1,ECCTOPSECTOR_2,ECCTOPSECTOR_3,ECCTOPSECTOR_4,ECCTOPSECTOR_5,ECCTOPSECTOR_6,ECCTOPSECTOR_7"
|
|
newline
|
|
bitfld.long 0x08 1.--3. "ECCCS,Selects the CS where ECC is computed 0h (R/W) = CS0 1h (R/W) = CS1 2h (R/W) = CS2 3h (R/W) =" "ECCCS_0,ECCCS_1,ECCCS_2,ECCCS_3,ECCCS_4,ECCCS_5,ECCCS_6,ECCCS_7"
|
|
newline
|
|
bitfld.long 0x08 0. "ECCENABLE,Enables the ECC feature 0h (R/W) = ECC disabled 1h (R/W) = ECC enabled" "ECCENABLE_0,ECCENABLE_1"
|
|
line.long 0x0C "GPMC_ECC_CONTROL,"
|
|
bitfld.long 0x0C 8. "ECCCLEAR,Clear all ECC result registers" "ECCCLEAR_0,ECCCLEAR_1"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Writing other values disables the ECC engine.." "ECCPOINTER_0,ECCPOINTER_1,ECCPOINTER_2,ECCPOINTER_3,ECCPOINTER_4,ECCPOINTER_5,ECCPOINTER_6,ECCPOINTER_7,ECCPOINTER_8,ECCPOINTER_9,ECCPOINTER_10,ECCPOINTER_11,ECCPOINTER_12,ECCPOINTER_13,ECCPOINTER_14,ECCPOINTER_15"
|
|
line.long 0x10 "GPMC_ECC_SIZE_CONFIG,"
|
|
hexmask.long.byte 0x10 22.--29. 1. "ECCSIZE1,Defines Hamming code ECC size 1 in bytes"
|
|
newline
|
|
hexmask.long.byte 0x10 12.--19. 1. "ECCSIZE0,Defines Hamming code ECC size 0 in bytes"
|
|
newline
|
|
bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC9RESULTSIZE_0,ECC9RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC8RESULTSIZE_0,ECC8RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC7RESULTSIZE_0,ECC7RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC6RESULTSIZE_0,ECC6RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC5RESULTSIZE_0,ECC5RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC4RESULTSIZE_0,ECC4RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC3RESULTSIZE_0,ECC3RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC2RESULTSIZE_0,ECC2RESULTSIZE_1"
|
|
newline
|
|
bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC1RESULTSIZE_0,ECC1RESULTSIZE_1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I2C"
|
|
repeat 3. (list 0. 1. 2.)(list ad:0x2530000 ad:0x2530400 ad:0x2530800)
|
|
tree "I2C_$1"
|
|
base $2
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "I2C_ICOAR,"
|
|
hexmask.long.word 0x00 0.--9. 1. "OADDR,Value = 0-3FFhOwn slave address"
|
|
line.long 0x04 "I2C_ICIMR,"
|
|
bitfld.long 0x04 6. "AAS,Address-as-slave interrupt enable bit" "0,1"
|
|
bitfld.long 0x04 5. "SCD,Stop condition detected interrupt enable bit" "0,1"
|
|
bitfld.long 0x04 4. "ICXRDY,Transmit-data-ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x04 3. "ICRDRDY,Receive-data-ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x04 2. "ARDY,Register-access-ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x04 1. "NACK,No-acknowledgment interrupt enable bit" "0,1"
|
|
bitfld.long 0x04 0. "AL,Arbitration-lost interrupt enable bit" "0,1"
|
|
line.long 0x08 "I2C_ICSTR,"
|
|
bitfld.long 0x08 14. "SDIR,Slave direction bit" "0,1"
|
|
bitfld.long 0x08 13. "NACKSNT,No-acknowledgment sent bit" "0,1"
|
|
bitfld.long 0x08 12. "BB,Bus busy bit" "0,1"
|
|
rbitfld.long 0x08 11. "RSFULL,Receive shift register full bit" "0,1"
|
|
bitfld.long 0x08 10. "XSMT,Underflow occurs when the transmit shift register ICXSR is empty but the data transmit register" "0,1"
|
|
rbitfld.long 0x08 9. "AAS,Addressed-as-slave bit" "0,1"
|
|
rbitfld.long 0x08 8. "AD0,Address 0 bit" "0,1"
|
|
bitfld.long 0x08 5. "SCD,Stop condition detected bit" "0,1"
|
|
bitfld.long 0x08 4. "ICXRDY,Transmit-data-ready interrupt flag bit" "0,1"
|
|
bitfld.long 0x08 3. "ICRDRDY,Receive-data-ready interrupt flag bit" "0,1"
|
|
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit (only applicable when the I" "0,1"
|
|
bitfld.long 0x08 1. "NACK,No-acknowledgment interrupt flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "AL,Arbitration-lost interrupt flag bit (only applicable when the I When AL is set to 1 the MST and STP bits of" "0,1"
|
|
line.long 0x0C "I2C_ICCLKL,"
|
|
hexmask.long.word 0x0C 0.--15. 1. "ICCL,Value = 0-FFFFhClock low-time divide-down value of 1-65536"
|
|
line.long 0x10 "I2C_ICCLKH,"
|
|
hexmask.long.word 0x10 0.--15. 1. "ICCH,Value = 0-FFFFhClock high-time divide-down value of 1-65536"
|
|
line.long 0x14 "I2C_ICCNT,"
|
|
hexmask.long.word 0x14 0.--15. 1. "ICDC,Value = 0-FFFFhData count value"
|
|
line.long 0x18 "I2C_ICDRR,"
|
|
hexmask.long.byte 0x18 0.--7. 1. "D,Value = 0-FFhReceive data"
|
|
line.long 0x1C "I2C_ICSAR,"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SADDR,Value = 0-3FFhSlave address"
|
|
line.long 0x20 "I2C_ICDXR,"
|
|
hexmask.long.byte 0x20 0.--7. 1. "D,Value = 0-FFhTransmit data"
|
|
line.long 0x24 "I2C_ICMDR,"
|
|
bitfld.long 0x24 15. "NACKMOD,No-acknowledge (NACK) mode bit (only applicable when the I" "0,1"
|
|
bitfld.long 0x24 14. "FREE,This emulation mode bit is used to determine the state of the I" "0,1"
|
|
bitfld.long 0x24 13. "STT,START condition bit (only applicable when the I" "0,1"
|
|
bitfld.long 0x24 11. "STP,STOP condition bit (only applicable when the I" "0,1"
|
|
bitfld.long 0x24 10. "MST,Master mode bit" "0,1"
|
|
bitfld.long 0x24 9. "TRX,Transmitter mode bit" "0,1"
|
|
bitfld.long 0x24 8. "XA,Expanded address enable bit" "0,1"
|
|
bitfld.long 0x24 7. "RM,Repeat mode bit (only applicable when the I" "0,1"
|
|
bitfld.long 0x24 6. "DLB,Digital loopback mode bit (only applicable when the In = ((I The transmit clock is also the receive clock. The address transmitted on the SDA pin is the address in" "0,1"
|
|
bitfld.long 0x24 5. "IRS,I" "0,1"
|
|
bitfld.long 0x24 4. "STB,START byte mode bit (only applicable when the I 1. A START condition 2. A START byte (0000 0001b) 3. A dummy acknowledge clock pulse 4. A repeated START conditionThe I" "0,1"
|
|
bitfld.long 0x24 3. "FDF,Free data format mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0.--2. "BC,Bit count bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "I2C_ICIVR,"
|
|
bitfld.long 0x28 0.--2. "INTCODE,Value = 0-7hInterrupt code bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "I2C_ICEMDR,"
|
|
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode" "0,1"
|
|
bitfld.long 0x2C 0. "BCM,Backward compatibility mode bit" "0,1"
|
|
line.long 0x30 "I2C_ICPSC,"
|
|
hexmask.long.byte 0x30 0.--7. 1. "IPSC,Value = 0-FFh Note: IPSC must be initialized while the I"
|
|
line.long 0x34 "I2C_ICPID1,"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "I2C_ICPID2,"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "MPU"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.)(list ad:0x2360000 ad:0x2368000 ad:0x2370000 ad:0x2378000 ad:0x2380000 ad:0x2388000 ad:0x2388400 ad:0x2388800 ad:0x2388C00 ad:0x2389000 ad:0x2389400 ad:0x2389800 ad:0x2389C00 ad:0x238A000 ad:0x238A400 ad:0x238A800)
|
|
tree "MPU_$1"
|
|
base $2
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MPU_REVID,"
|
|
line.long 0x04 "MPU_CONFIG,"
|
|
abitfld.long 0x04 24.--31. "ADDR_WIDTH,Address alignment for range checking" "0x00=1 KB alignment,0x01=2 KB alignment,0x06=64 KB alignment"
|
|
bitfld.long 0x04 20.--23. "NUM_FIXED,Shows the number of fixed address ranges supproted by the corresponding MPU" "0 fixed address ranges supproted,1 fixed address range supproted,2 fixed address ranges supproted,?..."
|
|
bitfld.long 0x04 16.--19. "NUM_PROG,Shows the number of programmable address ranges supproted by the corresponding MPU" "16 programmable address ranges,1 programmable address range,2 programmable address ranges,3 programmable address ranges,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. "NUM_AIDS,Shows the number of supported AIDs" "16 supported AIDs,1 supported AID,2 supported AIDs,3 supported AIDs,?..."
|
|
bitfld.long 0x04 0. "ASSUME_ALLOWED,Assume allowed bit" "Assume disallowed,Assume allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "MPU_IRAWSTAT,"
|
|
bitfld.long 0x00 1. "ADDR_ERR,Addressing violation error" "0,1"
|
|
bitfld.long 0x00 0. "PROT_ERR,Protection violation error" "0,1"
|
|
line.long 0x04 "MPU_IENSTAT,"
|
|
bitfld.long 0x04 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
|
|
bitfld.long 0x04 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
|
|
line.long 0x08 "MPU_IENSET,"
|
|
bitfld.long 0x08 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
|
|
bitfld.long 0x08 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
|
|
line.long 0x0C "MPU_IENCLR,"
|
|
bitfld.long 0x0C 1. "ADDR_ERR_EN_CLR,Addressing violation error enable" "0,1"
|
|
bitfld.long 0x0C 0. "PROT_ERR_EN_CLR,Protection violation error enable" "0,1"
|
|
line.long 0x10 "MPU_EOI,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,MPU_EOI vector value"
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "MPU_FLTADDRR,"
|
|
line.long 0x04 "MPU_FLTSTAT,"
|
|
hexmask.long.byte 0x04 16.--23. 1. "MSTID,Master ID of fault transfer"
|
|
bitfld.long 0x04 9.--12. "PRIVID,Privilege ID of fault transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 7. "NS,Security level of fault transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "TYPE,Fault type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "MPU_FLTCLR,"
|
|
bitfld.long 0x08 0. "CLEAR,Command to clear the current fault" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree "MPU_16"
|
|
base ad:0x238AC00
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MPU_REVID,"
|
|
line.long 0x04 "MPU_CONFIG,"
|
|
abitfld.long 0x04 24.--31. "ADDR_WIDTH,Address alignment for range checking" "0x00=1 KB alignment,0x01=2 KB alignment,0x06=64 KB alignment"
|
|
bitfld.long 0x04 20.--23. "NUM_FIXED,Shows the number of fixed address ranges supproted by the corresponding MPU" "0 fixed address ranges supproted,1 fixed address range supproted,2 fixed address ranges supproted,?..."
|
|
bitfld.long 0x04 16.--19. "NUM_PROG,Shows the number of programmable address ranges supproted by the corresponding MPU" "16 programmable address ranges,1 programmable address range,2 programmable address ranges,3 programmable address ranges,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. "NUM_AIDS,Shows the number of supported AIDs" "16 supported AIDs,1 supported AID,2 supported AIDs,3 supported AIDs,?..."
|
|
bitfld.long 0x04 0. "ASSUME_ALLOWED,Assume allowed bit" "Assume disallowed,Assume allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "MPU_IRAWSTAT,"
|
|
bitfld.long 0x00 1. "ADDR_ERR,Addressing violation error" "0,1"
|
|
bitfld.long 0x00 0. "PROT_ERR,Protection violation error" "0,1"
|
|
line.long 0x04 "MPU_IENSTAT,"
|
|
bitfld.long 0x04 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
|
|
bitfld.long 0x04 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
|
|
line.long 0x08 "MPU_IENSET,"
|
|
bitfld.long 0x08 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
|
|
bitfld.long 0x08 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
|
|
line.long 0x0C "MPU_IENCLR,"
|
|
bitfld.long 0x0C 1. "ADDR_ERR_EN_CLR,Addressing violation error enable" "0,1"
|
|
bitfld.long 0x0C 0. "PROT_ERR_EN_CLR,Protection violation error enable" "0,1"
|
|
line.long 0x10 "MPU_EOI,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,MPU_EOI vector value"
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "MPU_FLTADDRR,"
|
|
line.long 0x04 "MPU_FLTSTAT,"
|
|
hexmask.long.byte 0x04 16.--23. 1. "MSTID,Master ID of fault transfer"
|
|
bitfld.long 0x04 9.--12. "PRIVID,Privilege ID of fault transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 7. "NS,Security level of fault transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "TYPE,Fault type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "MPU_FLTCLR,"
|
|
bitfld.long 0x08 0. "CLEAR,Command to clear the current fault" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "MSMC"
|
|
tree "MSMC"
|
|
base ad:0xBC00000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MSMC_PID,"
|
|
rgroup.long 0x08++0x23
|
|
line.long 0x00 "MSMC_SMCERRAR,"
|
|
line.long 0x04 "MSMC_SMCERRXR,"
|
|
hexmask.long.byte 0x04 16.--23. 1. "ESYN,Value = 0-FFh Logs the syndrome value that identifies the erroneous bit in the data"
|
|
bitfld.long 0x04 8. "SER," "0,1"
|
|
bitfld.long 0x04 4.--7. "SEPID,Value = 0-Fh The PrivID associated with the access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "SEEADDR,Value = 0-Fh The upper 4 bits of the 36 bit address used in the accessing the corrupted location is stored here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "MSMC_SMEDCC,"
|
|
bitfld.long 0x08 31. "SEN,Scrubbing Engine Enable" "0,1"
|
|
bitfld.long 0x08 30. "ECM,Error Correction Mode" "0,1"
|
|
bitfld.long 0x08 26. "PRR,The PRR (Parity RAM Ready) bit shows the status of Parity RAM" "0,1"
|
|
hexmask.long.byte 0x08 0.--7. 1. "REFDEL,Value = 0-FFhControls the number of MSMC clock cycles between each scrub burst"
|
|
line.long 0x0C "MSMC_SMCEA,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "ESYN,Value = 0-FFh Logs the syndrome value that identifies the erroneous bit in the data"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. "SECA,Value = 0-FF FFFFh Scrubbing Error Correctable Address"
|
|
line.long 0x10 "MSMC_SMSECC,"
|
|
hexmask.long.word 0x10 16.--31. 1. "SNCEC,Value = 0-FFFFh Increments the counter on detection of a non-correctable two-bit error"
|
|
hexmask.long.word 0x10 0.--15. 1. "SCEC,Value = 0-FFFFh Increments the counter on detection of a correctable one-bit error"
|
|
line.long 0x14 "MSMC_SMPFAR,"
|
|
line.long 0x18 "MSMC_SMPFXR,"
|
|
bitfld.long 0x18 0. "NM," "0,1"
|
|
line.long 0x1C "MSMC_SMPFR,"
|
|
bitfld.long 0x1C 8.--11. "FPID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "FMSTID,"
|
|
line.long 0x20 "MSMC_SMPFCR,"
|
|
bitfld.long 0x20 0. "CLR," "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MSMC_SBNDC0,"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SCNTCE,Value = 0-FFh Reload value (pre-scaled by 16) for the starvation counter for DSP requests at the EMIF arbiter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCNTCM,Value = 0-FFh Reload value for the starvation counters for DSP requests at the RAM bank arbiter"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "MSMC_SBNDM,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCNTMM,Value = 0-FFh Reload value for the starvation counters for SMS requests at the RAM bank arbiter"
|
|
line.long 0x04 "MSMC_SBNDE,"
|
|
hexmask.long.byte 0x04 16.--23. 1. "SCNTEE,Value = 0-FFh Reload value (prescaled by 16) for the starvation counter for SES requests at the EMIF arbiter"
|
|
hexmask.long.byte 0x04 0.--7. 1. "SCNTEM,Value = 0-FFh Reload value for the starvation counters for SES requests at the RAM bank arbiter"
|
|
group.long 0x5C++0x37
|
|
line.long 0x00 "MSMC_CFGLCK,"
|
|
hexmask.long.word 0x00 16.--31. 1. "MGCID,"
|
|
bitfld.long 0x00 0. "WLCK," "0,1"
|
|
line.long 0x04 "MSMC_CFGULCK,"
|
|
hexmask.long.word 0x04 16.--31. 1. "MGCID,"
|
|
bitfld.long 0x04 0. "WEN," "0,1"
|
|
line.long 0x08 "MSMC_CFGLCKSTAT,"
|
|
bitfld.long 0x08 0. "WSTAT,Indicates the lock's current status" "0,1"
|
|
line.long 0x0C "MSMC_SMS_MPAX_LCK,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "MGCID,Value = 2CD1h Writing this key value along with setting WLCK[n] to 1 locks the SMS MPAX registers for PrivID n"
|
|
hexmask.long.word 0x0C 0.--15. 1. "WLCK,Value = 0-FFFFh Bit n denotes lock bit for PrivID n"
|
|
line.long 0x10 "MSMC_SMS_MPAX_ULCK,"
|
|
hexmask.long.word 0x10 16.--31. 1. "MGCID,Value = 2CD1hWriting this key value along with setting WEN[n] to 1 unlocks the SMS MPAX registers for PrivID n"
|
|
hexmask.long.word 0x10 0.--15. 1. "WEN,Value = 0-FFFFh Bit n denotes unlock bit for PrivID n"
|
|
line.long 0x14 "MSMC_SMS_MPAX_LCKSTAT,"
|
|
hexmask.long.word 0x14 0.--15. 1. "WSTAT,Value = 0-FFFFh Bit n indicates the lock's current status for PrivID n"
|
|
line.long 0x18 "MSMC_SES_MPAX_LCK,"
|
|
hexmask.long.word 0x18 16.--31. 1. "MGCID,Value = 2CD2h Writing this key value along with setting WLCK[n] to 1 locks the SES MPAX registers for PrivID n"
|
|
hexmask.long.word 0x18 0.--15. 1. "WLCK,Value = 0-FFFFh Bit n denotes lock bit for PrivID n"
|
|
line.long 0x1C "MSMC_SES_MPAX_ULCK,"
|
|
hexmask.long.word 0x1C 16.--31. 1. "MGCID,Value = 2CD2h Writing this key value along with setting WEN[n] to 1 unlocks the SES MPAX registers for PrivID n"
|
|
hexmask.long.word 0x1C 0.--15. 1. "WEN,Value = 0-FFFFh Bit n denotes unlock bit for PrivID n"
|
|
line.long 0x20 "MSMC_SES_MPAX_LCKSTAT,"
|
|
hexmask.long.word 0x20 0.--15. 1. "WSTAT,"
|
|
line.long 0x24 "MSMC_SMESTAT,"
|
|
hexmask.long.word 0x24 16.--31. 1. "PFESTAT,"
|
|
bitfld.long 0x24 3. "CEES," "0,1"
|
|
bitfld.long 0x24 2. "NCEES," "0,1"
|
|
bitfld.long 0x24 1. "CSES," "0,1"
|
|
bitfld.long 0x24 0. "NCSES," "0,1"
|
|
line.long 0x28 "MSMC_SMIRSTAT,"
|
|
hexmask.long.word 0x28 16.--31. 1. "PFISTAT,"
|
|
bitfld.long 0x28 3. "CEI," "0,1"
|
|
bitfld.long 0x28 2. "NCEI," "0,1"
|
|
bitfld.long 0x28 1. "CSI," "0,1"
|
|
bitfld.long 0x28 0. "NCSI," "0,1"
|
|
line.long 0x2C "MSMC_SMIRC,"
|
|
hexmask.long.word 0x2C 16.--31. 1. "PFIC,"
|
|
bitfld.long 0x2C 3. "CEC," "0,1"
|
|
bitfld.long 0x2C 2. "NCEC," "0,1"
|
|
bitfld.long 0x2C 1. "CSC," "0,1"
|
|
bitfld.long 0x2C 0. "NCSC," "0,1"
|
|
line.long 0x30 "MSMC_SMIESTAT,"
|
|
hexmask.long.word 0x30 16.--31. 1. "PFIESTAT,"
|
|
bitfld.long 0x30 3. "CEIE," "0,1"
|
|
bitfld.long 0x30 2. "NCEIE," "0,1"
|
|
bitfld.long 0x30 1. "CSIE," "0,1"
|
|
bitfld.long 0x30 0. "NCSIE," "0,1"
|
|
line.long 0x34 "MSMC_SMIEC,"
|
|
hexmask.long.word 0x34 16.--31. 1. "PFIEC,"
|
|
bitfld.long 0x34 3. "CEEC," "0,1"
|
|
bitfld.long 0x34 2. "NCEEC," "0,1"
|
|
bitfld.long 0x34 1. "CSEC," "0,1"
|
|
bitfld.long 0x34 0. "NCSEC," "0,1"
|
|
rgroup.long 0xC4++0x0B
|
|
line.long 0x00 "MSMC_SMNCERRAR,"
|
|
line.long 0x04 "MSMC_SMNCERRXR,"
|
|
bitfld.long 0x04 8. "SER," "0,1"
|
|
bitfld.long 0x04 4.--7. "SEPID,Value = 0-Fh The PrivID associated with the access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "SEEADDR,Value = 0-Fh The upper 4 bits of the 36 bit address used in the accessing the corrupted location is stored here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "MSMC_SMNCEA,"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "SENCA,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "NSS"
|
|
tree "NSS_0_CFG__cppidma0_tx_scheduler"
|
|
base ad:0x4010100
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_0,"
|
|
bitfld.long 0x00 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x04 "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_1,"
|
|
bitfld.long 0x04 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x08 "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_2,"
|
|
bitfld.long 0x08 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x0C "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_3,"
|
|
bitfld.long 0x0C 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x10 "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_4,"
|
|
bitfld.long 0x10 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x14 "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_5,"
|
|
bitfld.long 0x14 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x18 "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_6,"
|
|
bitfld.long 0x18 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
line.long 0x1C "CDMA_TX_CHANNEL_SCHEDULER_CONFIG_REG_7,"
|
|
bitfld.long 0x1C 0.--1. "PRIORITY,Tx scheduling priority" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_ALE"
|
|
base ad:0x423E000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "ALE_IDVER,"
|
|
line.long 0x04 "ALE_STATUS,"
|
|
hexmask.long.byte 0x04 8.--15. 1. "POLICERS_DIV_8,This is the number of policers the ALE implements divided by 8 (a value of 4 indicates 32 policers total)"
|
|
bitfld.long 0x04 6. "_32_ENTRIES,When set indicates that there are 32 entries in the ALE table" "0,1"
|
|
bitfld.long 0x04 0.--4. "ENTRIES_DIV_1024,This is the number of table entries total divided by 1024" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ALE_CONTROL,"
|
|
bitfld.long 0x08 31. "ENABLE,Enable ALE" "0,1"
|
|
bitfld.long 0x08 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1"
|
|
bitfld.long 0x08 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1"
|
|
bitfld.long 0x08 21.--23. "UPD_BW_CTL,The upd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - when set this will prevent source addresses of unknown VLANIDs from being automatically added into the look up table if learning is enabled" "0,1"
|
|
bitfld.long 0x08 8. "UNI_FLOOD_TO_HOST,Enable Port 0 Unicast Flood" "0,1"
|
|
bitfld.long 0x08 7. "LEARN_NO_VID,Learn No VID" "0,1"
|
|
bitfld.long 0x08 6. "EN_VID0_MODE,Enable VLAN ID = 0 Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode" "0,1"
|
|
bitfld.long 0x08 4. "BYPASS,ALE Bypass" "0,1"
|
|
bitfld.long 0x08 3. "RATE_LIMIT_TX,Rate Limit Transmit Mode" "0,1"
|
|
bitfld.long 0x08 2. "VLAN_AWARE,ALE VLAN Aware" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "0,1"
|
|
bitfld.long 0x08 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "0,1"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "ALE_PRESCALE,"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters"
|
|
line.long 0x04 "ALE_AGING_TIMER,"
|
|
bitfld.long 0x04 31. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable: When set removes 1 000 from the auto aging multiplier" "0,1"
|
|
bitfld.long 0x04 30. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable: When set removes 1 000 from the auto aging multiplier" "0,1"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "AGING_TIMER,ALE Aging Timer: When non-zero auto-aging is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALE_TABLE_CONTROL,"
|
|
bitfld.long 0x00 31. "WRITE_RDZ,Write Bit - This bit is always" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. "ENTRY_POINTER,Table Entry Pointer - The ENTRY_POINTER contains the table entry value that will be read/written with accesses to the table word registers"
|
|
group.long 0x34++0x27
|
|
line.long 0x00 "ALE_TABLE_WORD2,"
|
|
hexmask.long.byte 0x00 0.--6. 1. "ENTRY_70_64,Table entry bits 70 down to 64"
|
|
line.long 0x04 "ALE_TABLE_WORD1,"
|
|
line.long 0x08 "ALE_TABLE_WORD0,"
|
|
line.long 0x0C "ALE_PORT_CONTROL_0,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x0C 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x0C 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x0C 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x0C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x0C 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
line.long 0x10 "ALE_PORT_CONTROL_1,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x10 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x10 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x10 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x10 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x10 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x10 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
line.long 0x14 "ALE_PORT_CONTROL_2,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x14 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x14 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x14 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x14 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x14 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x14 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
line.long 0x18 "ALE_PORT_CONTROL_3,"
|
|
hexmask.long.byte 0x18 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x18 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x18 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x18 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x18 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x18 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
line.long 0x1C "ALE_PORT_CONTROL_4,"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x1C 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x1C 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x1C 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x1C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x1C 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
line.long 0x20 "ALE_PORT_CONTROL_5,"
|
|
hexmask.long.byte 0x20 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x20 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x20 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x20 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x20 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x20 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x20 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
line.long 0x24 "ALE_PORT_CONTROL_6,"
|
|
hexmask.long.byte 0x24 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit Each prescale pulse loads this field into the port broadcast rate limit counter"
|
|
hexmask.long.byte 0x24 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter"
|
|
bitfld.long 0x24 12. "DISABLE_AUTH_MODE,Disable MAC Authorization Mode When set this bit disables MAC authorization mode for this port (when enable_auth_mode in ALE_Control is set)" "0,1"
|
|
bitfld.long 0x24 5. "NO_SA_UPDATE,No Source Address Update When set an ingress packet on this port will not cause a matching source address entry port number to be changed (to this port)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "NO_LEARN,No Learn Mode When set the port is disabled from learning source addresses" "0,1"
|
|
bitfld.long 0x24 3. "VID_INGRESS_CHECK,VLAN ID Ingress Check If VLAN found and the receive port is not a VLAN member then drop the packet" "0,1"
|
|
bitfld.long 0x24 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1"
|
|
bitfld.long 0x24 0.--1. "PORT_STATE,Port State" "0,1,2,3"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "ALE_UNKNOWN_VLAN,"
|
|
bitfld.long 0x00 0.--1. "LIST,Unknown VLAN Member List" "0,1,2,3"
|
|
line.long 0x04 "ALE_UNKNOWN_UREG_MCAST_FLOOD,"
|
|
bitfld.long 0x04 0.--1. "MASK,Unknown VLAN Multicast Flood Mask" "0,1,2,3"
|
|
line.long 0x08 "ALE_UNKNOWN_REG_MCAST_FLOOD,"
|
|
bitfld.long 0x08 0.--1. "MASK,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3"
|
|
line.long 0x0C "ALE_FORCE_UNTAGGED_EGRESS,"
|
|
bitfld.long 0x0C 0.--1. "MASK,Force Untagged Egress Mask" "0,1,2,3"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "ALE_VLAN_MASK_MUX_0,"
|
|
bitfld.long 0x00 0.--1. "MASK,Force Untagged Egress Mask" "0,1,2,3"
|
|
line.long 0x04 "ALE_VLAN_MASK_MUX_1,"
|
|
bitfld.long 0x04 0.--1. "MASK,Force Untagged Egress Mask" "0,1,2,3"
|
|
line.long 0x08 "ALE_VLAN_MASK_MUX_2,"
|
|
bitfld.long 0x08 0.--1. "MASK,Force Untagged Egress Mask" "0,1,2,3"
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "ALE_POLICER_PORT_OUI,"
|
|
bitfld.long 0x00 31. "PORT_MEN,Enabled port match for the selected policing/classifier entry" "0,1"
|
|
bitfld.long 0x00 25.--28. "PORT_NUM,If enabled specifies the port address to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "PRI_MEN,Enabled frame priority match for the selected policing/classifier entry" "0,1"
|
|
bitfld.long 0x00 16.--18. "PRI_VAL,If enabled specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "OUI_MEN,Enabled frame OUI address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. "OUI_INDEX,If enabled specifies the ALE OUI address lookup table index to match for the selected policing/classifier entry"
|
|
line.long 0x04 "ALE_POLICER_DA_SA,"
|
|
bitfld.long 0x04 31. "DST_MEN,Enabled frame L2 destination address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x04 16.--28. 1. "DST_INDEX,If enabled specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry"
|
|
bitfld.long 0x04 15. "SRC_MEN,Enabled frame L2 source address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x04 0.--12. 1. "SRC_INDEX,If enabled specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry"
|
|
line.long 0x08 "ALE_POLICER_VLAN,"
|
|
bitfld.long 0x08 31. "OVLAN_MEN,Enabled frame Outer VLAN address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x08 16.--28. 1. "OVLAN_INDEX,If enabled specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry"
|
|
bitfld.long 0x08 15. "IVLAN_MEN,Enabled frame Inner VLAN address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x08 0.--12. 1. "IVLAN_INDEX,If enabled specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry"
|
|
line.long 0x0C "ALE_POLICER_ETHERTYPE_IPSA,"
|
|
bitfld.long 0x0C 31. "ETHERTYPE_MEN,Enabled frame Ether Type match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x0C 16.--28. 1. "ETHERTYPE_INDEX,If enabled specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry"
|
|
bitfld.long 0x0C 15. "IPSRC_MEN,Enabled frame IP Source address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x0C 0.--12. 1. "IPSRC_INDEX,If enabled specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry"
|
|
line.long 0x10 "ALE_POLICER_IPDA,"
|
|
bitfld.long 0x10 31. "IPDST_MEN,Enabled frame IP Destination address match for the selected policing/classifier entry" "0,1"
|
|
hexmask.long.word 0x10 16.--28. 1. "IPDST_INDEX,If enabled specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ALE_POLICER_TBL_CTL,"
|
|
bitfld.long 0x00 31. "WRITE_ENABLE,Setting this bit will write the POLICER_CFG0-7 to the pol_tbl_index selected policing/classifier entry" "0,1"
|
|
bitfld.long 0x00 0.--4. "POL_TBL_INDEX,This field specifies the policing/classifier entry to be read or written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x134++0x0B
|
|
line.long 0x00 "ALE_THREAD_DEF,"
|
|
bitfld.long 0x00 15. "ENABLE,This field is the read or written enable for the Default Thread ID" "0,1"
|
|
bitfld.long 0x00 0.--5. "VALUE,This field is the read or written default thread ID value that is used for host traffic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "ALE_THREAD_CTL,"
|
|
bitfld.long 0x04 0.--4. "ENTRY_PTR,Policer Thread Entry Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ALE_THREAD_VAL,"
|
|
bitfld.long 0x08 15. "ENABLE,This field is the read or written enable for the Thread ID" "0,1"
|
|
bitfld.long 0x08 0.--5. "VALUE,This field is the read or written thread ID value that is used to map a classifier hit to thread ID for host traffic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_CPPIDMA0_CONFIG"
|
|
base ad:0x4010000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "CDMA_REVISION_REG,"
|
|
line.long 0x04 "CDMA_PERF_CONTROL_REG,"
|
|
bitfld.long 0x04 16.--21. "WARB_FIFO_DEPTH,This field sets the depth of the write arbitration FIFO which stores write transaction information between the command arbiter and write data arbiters in the Bus Interface Unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles"
|
|
line.long 0x08 "CDMA_EMULATION_CONTROL_REG,"
|
|
bitfld.long 0x08 31. "LOOPBACK_EN,Streaming Interface loopback enable" "0,1"
|
|
bitfld.long 0x08 1. "SOFT,Soft" "0,1"
|
|
bitfld.long 0x08 0. "FREE,Free" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CDMA_PRIORITY_CONTROL_REG,"
|
|
bitfld.long 0x00 16.--18. "RX_PRIORITY,Rx priority: This field contains the 3-bit value which will be output on the mem_cpriority and mem_cepriority outputs during all Rx transactions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TX_PRIORITY,Tx priority: This field contains the 3-bit value which will be output on the mem_cpriority and mem_cepriority outputs during all Tx transactions" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CDMA_QM_BASE_ADDRESS_REG_0,"
|
|
line.long 0x04 "CDMA_QM_BASE_ADDRESS_REG_1,"
|
|
line.long 0x08 "CDMA_QM_BASE_ADDRESS_REG_2,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_CPSW"
|
|
base ad:0x4220000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CPSW_IDVER,"
|
|
line.long 0x04 "CPSW_CONTROL,"
|
|
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
|
|
bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
|
|
bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
|
|
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
|
|
newline
|
|
bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
|
|
bitfld.long 0x04 12. "P0_TX_CRC_TYPE,Port 0 Transmit CRC Type - The type of CRC on all Port 0 transmit packet (egress) regardless of the CRC type of in ingress Ethernet port" "0,1"
|
|
bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
|
|
bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
|
|
bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CPSW_EM_CONTROL,"
|
|
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
|
|
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
|
|
line.long 0x04 "CPSW_STAT_PORT_EN,"
|
|
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
|
|
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CPSW_SOFT_IDLE,"
|
|
bitfld.long 0x00 0. "SOFT_IDLE,Software Idle" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CPSW_EEE_PRESCALE,"
|
|
hexmask.long.word 0x00 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value - This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero"
|
|
group.long 0x1004++0x07
|
|
line.long 0x00 "CPSW_P0_CONTROL,"
|
|
bitfld.long 0x00 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
|
|
bitfld.long 0x00 1. "DSCP_IPV4_EN,Port 0 IPv4 DSCP enable" "0,1"
|
|
line.long 0x04 "CPSW_P0_FLOW_ID_OFFSET,"
|
|
hexmask.long.byte 0x04 0.--7. 1. "FLOW_ID_OFFSET,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
|
|
rgroup.long 0x1010++0x07
|
|
line.long 0x00 "CPSW_P0_BLK_CNT,"
|
|
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. "RX_BLK_CNT,Port 0 Receive Block Count Usage - This value is the number of blocks allocated in the receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CPSW_P0_PORT_VLAN,"
|
|
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
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hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
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group.long 0x101C++0x0B
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line.long 0x00 "CPSW_P0_PRI_CTL,"
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bitfld.long 0x00 8. "RX_PTYPE,Receive Priority Type" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "RX_RLIM,Receive Rate Limit Enable"
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line.long 0x04 "CPSW_P0_RX_PRI_MAP,"
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bitfld.long 0x04 28.--30. "PRI7,Priority 7 - A packet pri of 0x7 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 24.--26. "PRI6,Priority 6 - A packet pri of 0x6 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 20.--22. "PRI5,Priority 5 - A packet pri of 0x5 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 16.--18. "PRI4,Priority 4 - A packet pri of 0x4 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x04 12.--14. "PRI3,Priority 3 - A packet pri of 0x3 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 8.--10. "PRI2,Priority 2 - A packet pri of 0x2 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 4.--6. "PRI1,Priority 1 - A packet pri of 0x1 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--2. "PRI0,Priority 0 - A packet pri of 0x0 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
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line.long 0x08 "CPSW_P0_RX_MAXLEN,"
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hexmask.long.word 0x08 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length - This field determines the maximum length of a received frame"
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group.long 0x1030++0x0B
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line.long 0x00 "CPSW_P0_IDLE2LPI,"
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hexmask.long.tbyte 0x00 0.--23. 1. "IDLE2LPI,Port 0 EEE Idle to LPI counter load value - After EEE_CLKSTOP_REQ is asserted this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit or receive is not idle"
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line.long 0x04 "CPSW_P0_LPI2WAKE,"
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hexmask.long.tbyte 0x04 0.--23. 1. "LPI2WAKE,Port 0 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the EEE_CLKSTOP_REQ signal is deasserted this value is loaded into the port 0 LPI to wake counter"
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line.long 0x08 "CPSW_P0_EEE_STATUS,"
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bitfld.long 0x08 6. "TX_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1"
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bitfld.long 0x08 5. "RX_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1"
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bitfld.long 0x08 4. "TX_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
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bitfld.long 0x08 3. "TX_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
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newline
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bitfld.long 0x08 2. "TX_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
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bitfld.long 0x08 1. "RX_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
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bitfld.long 0x08 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
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group.long 0x1120++0x1B
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line.long 0x00 "CPSW_P0_RX_DSCP_MAP_0,"
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bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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line.long 0x04 "CPSW_P0_RX_DSCP_MAP_1,"
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bitfld.long 0x04 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x04 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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line.long 0x08 "CPSW_P0_RX_DSCP_MAP_2,"
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bitfld.long 0x08 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x08 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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line.long 0x0C "CPSW_P0_RX_DSCP_MAP_3,"
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bitfld.long 0x0C 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0C 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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line.long 0x10 "CPSW_P0_RX_DSCP_MAP_4,"
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bitfld.long 0x10 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x10 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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line.long 0x14 "CPSW_P0_RX_DSCP_MAP_5,"
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bitfld.long 0x14 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x14 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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line.long 0x18 "CPSW_P0_RX_DSCP_MAP_6,"
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bitfld.long 0x18 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x18 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
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group.long 0x1140++0x1B
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line.long 0x00 "CPSW_P0_PRI_SEND_0,"
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hexmask.long.tbyte 0x00 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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line.long 0x04 "CPSW_P0_PRI_SEND_1,"
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hexmask.long.tbyte 0x04 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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line.long 0x08 "CPSW_P0_PRI_SEND_2,"
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hexmask.long.tbyte 0x08 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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line.long 0x0C "CPSW_P0_PRI_SEND_3,"
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hexmask.long.tbyte 0x0C 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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line.long 0x10 "CPSW_P0_PRI_SEND_4,"
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hexmask.long.tbyte 0x10 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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line.long 0x14 "CPSW_P0_PRI_SEND_5,"
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hexmask.long.tbyte 0x14 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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line.long 0x18 "CPSW_P0_PRI_SEND_6,"
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hexmask.long.tbyte 0x18 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
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group.long 0x1160++0x1B
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line.long 0x00 "CPSW_P0_PRI_IDLE_0,"
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hexmask.long.tbyte 0x00 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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line.long 0x04 "CPSW_P0_PRI_IDLE_1,"
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hexmask.long.tbyte 0x04 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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line.long 0x08 "CPSW_P0_PRI_IDLE_2,"
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hexmask.long.tbyte 0x08 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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line.long 0x0C "CPSW_P0_PRI_IDLE_3,"
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hexmask.long.tbyte 0x0C 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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line.long 0x10 "CPSW_P0_PRI_IDLE_4,"
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hexmask.long.tbyte 0x10 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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line.long 0x14 "CPSW_P0_PRI_IDLE_5,"
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hexmask.long.tbyte 0x14 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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line.long 0x18 "CPSW_P0_PRI_IDLE_6,"
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hexmask.long.tbyte 0x18 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
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group.long 0x1300++0x03
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line.long 0x00 "CPSW_P0_SRC_ID_A,"
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hexmask.long.byte 0x00 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
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hgroup.long 0x2000++0x03
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hide.long 0x00 "CPSW_P1_RESERVED,"
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group.long 0x2004++0x07
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line.long 0x00 "CPSW_P1_CONTROL,"
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bitfld.long 0x00 12. "TX_LPI_CLKSTOP_EN,Transmit LPI clockstop enable" "0,1"
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bitfld.long 0x00 2. "DSCP_IPV6_EN,IPv6 DSCP enable" "0,1"
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bitfld.long 0x00 1. "DSCP_IPV4_EN,IPv4 DSCP enable" "0,1"
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line.long 0x04 "CPSW_P1_MAX_BLKS,"
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bitfld.long 0x04 8.--11. "TX_MAX_BLKS,Transmit FIFO maximum blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "RX_MAX_BLKS,Receive FIFO maximum blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x2010++0x07
|
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line.long 0x00 "CPSW_P1_BLK_CNT,"
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bitfld.long 0x00 8.--11. "TX_BLK_CNT,Transmit Block Count Usage - This value is the number of blocks allocated to the port's FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "RX_BLK_CNT,Receive Block Count Usage - This value is the number of blocks allocated to the port's FIFO receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "CPSW_P1_PORT_VLAN,"
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bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
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hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
|
|
group.long 0x201C++0x0B
|
|
line.long 0x00 "CPSW_P1_PRI_CTL,"
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bitfld.long 0x00 12.--15. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "CPSW_P1_RX_PRI_MAP,"
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bitfld.long 0x04 28.--30. "PRI7,Priority 7 - A packet pri of 0x7 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x04 24.--26. "PRI6,Priority 6 - A packet pri of 0x6 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x04 20.--22. "PRI5,Priority 5 - A packet pri of 0x5 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. "PRI4,Priority 4 - A packet pri of 0x4 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "PRI3,Priority 3 - A packet pri of 0x3 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. "PRI2,Priority 2 - A packet pri of 0x2 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. "PRI1,Priority 1 - A packet pri of 0x1 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. "PRI0,Priority 0 - A packet pri of 0x0 is mapped (changed) to this header packet pri" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CPSW_P1_RX_MAXLEN,"
|
|
hexmask.long.word 0x08 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length - This field determines the maximum length of a received frame"
|
|
group.long 0x2030++0x0B
|
|
line.long 0x00 "CPSW_P1_IDLE2LPI,"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "IDLE2LPI,EEE Idle to LPI counter load value- After EEE_CLKSTOP_REQ is asserted this value is loaded into the port idle to LPI counter on each clock that the port transmit is not idle"
|
|
line.long 0x04 "CPSW_P1_LPI2WAKE,"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "LPI2WAKE,EEE LPI to wake counter load value - When the port is in the transmit LPI state and the EEE_CLKSTOP_REQ signal is deasserted this value is loaded into the LPI to wake counter"
|
|
line.long 0x08 "CPSW_P1_EEE_STATUS,"
|
|
bitfld.long 0x08 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1"
|
|
bitfld.long 0x08 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1"
|
|
bitfld.long 0x08 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
|
|
bitfld.long 0x08 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
|
|
bitfld.long 0x08 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
|
|
bitfld.long 0x08 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
|
|
group.long 0x2120++0x1B
|
|
line.long 0x00 "CPSW_P1_RX_DSCP_MAP_0,"
|
|
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CPSW_P1_RX_DSCP_MAP_1,"
|
|
bitfld.long 0x04 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CPSW_P1_RX_DSCP_MAP_2,"
|
|
bitfld.long 0x08 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "CPSW_P1_RX_DSCP_MAP_3,"
|
|
bitfld.long 0x0C 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0C 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CPSW_P1_RX_DSCP_MAP_4,"
|
|
bitfld.long 0x10 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CPSW_P1_RX_DSCP_MAP_5,"
|
|
bitfld.long 0x14 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CPSW_P1_RX_DSCP_MAP_6,"
|
|
bitfld.long 0x18 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority where N = 0 to 7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2140++0x1B
|
|
line.long 0x00 "CPSW_P1_PRI_SEND_0,"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
line.long 0x04 "CPSW_P1_PRI_SEND_1,"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
line.long 0x08 "CPSW_P1_PRI_SEND_2,"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
line.long 0x0C "CPSW_P1_PRI_SEND_3,"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
line.long 0x10 "CPSW_P1_PRI_SEND_4,"
|
|
hexmask.long.tbyte 0x10 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
line.long 0x14 "CPSW_P1_PRI_SEND_5,"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
line.long 0x18 "CPSW_P1_PRI_SEND_6,"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. "COUNT,Priority N send count where N = 0 to 7"
|
|
group.long 0x2160++0x1B
|
|
line.long 0x00 "CPSW_P1_PRI_IDLE_0,"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
line.long 0x04 "CPSW_P1_PRI_IDLE_1,"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
line.long 0x08 "CPSW_P1_PRI_IDLE_2,"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
line.long 0x0C "CPSW_P1_PRI_IDLE_3,"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
line.long 0x10 "CPSW_P1_PRI_IDLE_4,"
|
|
hexmask.long.tbyte 0x10 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
line.long 0x14 "CPSW_P1_PRI_IDLE_5,"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
line.long 0x18 "CPSW_P1_PRI_IDLE_6,"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. "COUNT,Priority N idle count where N = 0 to 7"
|
|
group.long 0x2308++0x1B
|
|
line.long 0x00 "CPSW_P1_SA_L,"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)"
|
|
line.long 0x04 "CPSW_P1_SA_H,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)"
|
|
hexmask.long.byte 0x04 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24 (byte 3)"
|
|
hexmask.long.byte 0x04 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)"
|
|
hexmask.long.byte 0x04 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)"
|
|
line.long 0x08 "CPSW_P1_TS_CTL,"
|
|
hexmask.long.word 0x08 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)"
|
|
bitfld.long 0x08 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
|
|
bitfld.long 0x08 10. "TS_TX_ANNEX_E_EN,Time Sync Transmit Annex E Enable" "0,1"
|
|
bitfld.long 0x08 9. "TS_RX_ANNEX_E_EN,Time Sync Receive Annex E Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable (Transmit and Receive)" "0,1"
|
|
bitfld.long 0x08 7. "TS_TX_ANNEX_D_EN,Time Sync Transmit Annex D Enable" "0,1"
|
|
bitfld.long 0x08 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
|
|
bitfld.long 0x08 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "TS_TX_ANNEX_F_EN,Time Sync Transmit Annex F Enable" "0,1"
|
|
bitfld.long 0x08 3. "TS_RX_ANNEX_D_EN,Time Sync Receive Annex D Enable" "0,1"
|
|
bitfld.long 0x08 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
|
|
bitfld.long 0x08 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "TS_RX_ANNEX_F_EN,Time Sync Receive Annex F Enable" "0,1"
|
|
line.long 0x0C "CPSW_P1_TS_SEQ_LTYPE,"
|
|
bitfld.long 0x0C 16.--21. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x0C 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
|
|
line.long 0x10 "CPSW_P1_TS_VLAN_LTYPE,"
|
|
hexmask.long.word 0x10 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
|
|
hexmask.long.word 0x10 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
|
|
line.long 0x14 "CPSW_P1_TS_CTL_LTYPE2,"
|
|
bitfld.long 0x14 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
|
|
bitfld.long 0x14 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
|
|
bitfld.long 0x14 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
|
|
bitfld.long 0x14 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
|
|
bitfld.long 0x14 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
|
|
bitfld.long 0x14 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
|
|
bitfld.long 0x14 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
|
|
hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
|
|
line.long 0x18 "CPSW_P1_TS_CTL2,"
|
|
bitfld.long 0x18 16.--21. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x18 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
|
|
group.long 0x2330++0x13
|
|
line.long 0x00 "CPSW_P1_MAC_CONTROL,"
|
|
bitfld.long 0x00 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory" "0,1"
|
|
bitfld.long 0x00 23. "RX_CSF_EN,Enables frames or fragments shorter than 64 bytes to be copied to memory" "0,1"
|
|
bitfld.long 0x00 22. "RX_CEF_EN,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory" "0,1"
|
|
bitfld.long 0x00 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable Enables the tx_flow_en to be selected from the EXT_TX_FLOW_EN input signal and not from the TX_FLOW_EN bit in this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable - Enables the rx_flow_en to be selected from the EXT_RX_FLOW_EN input signal and not from the RX_FLOW_EN bit in this register" "0,1"
|
|
bitfld.long 0x00 18. "CTL_EN,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the fullduplex and gig bits in this register" "0,1"
|
|
bitfld.long 0x00 17. "GIG_FORCE,Gigabit Mode Force - This bit is used to force the Enet Mac into gigabit mode if the input GMII_MTCLK has been stopped by the PHY" "0,1"
|
|
bitfld.long 0x00 16. "IFCTL_B,Interface Control B" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IFCTL_A,Interface Control A.Determines the RMII speed" "0,1"
|
|
bitfld.long 0x00 12. "CRC_TYPE,Port CRC Type" "0,1"
|
|
bitfld.long 0x00 11. "CMD_IDLE,Command Idle" "0,1"
|
|
bitfld.long 0x00 7. "GIG,Gigabit Mode The GIG_OUT output is the value of this bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TX_PACE,Transmit Pacing Enable" "0,1"
|
|
bitfld.long 0x00 5. "GMII_EN,GMII Enable" "0,1"
|
|
bitfld.long 0x00 4. "TX_FLOW_EN,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode" "0,1"
|
|
bitfld.long 0x00 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MTEST,Manufacturing Test Mode - This bit must be set to allow writes to the BACKOFF_TEST and PAUSETIMER registers" "0,1"
|
|
bitfld.long 0x00 1. "LOOPBACK,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the fullduplex bit is set or not" "0,1"
|
|
bitfld.long 0x00 0. "FULLDUPLEX,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the fullduplex bit is set or not" "0,1"
|
|
line.long 0x04 "CPSW_P1_MAC_STATUS,"
|
|
bitfld.long 0x04 31. "IDLE,Enet IDLE - The Ethernet port is in the idle state (valid after an idle command)" "0,1"
|
|
bitfld.long 0x04 6. "EXT_RX_FLOW_EN,External Receive Flow Control Enable - This is the value of the EXT_RX_FLOW_EN input bit" "0,1"
|
|
bitfld.long 0x04 5. "EXT_TX_FLOW_EN,External Receive Flow Control Enable - This is the value of the EXT_TX_FLOW_EN input bit" "0,1"
|
|
bitfld.long 0x04 4. "EXT_GIG,External GIG mode - This is the value of the EXT_GIG input bit" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "EXT_FULLDUPLEX,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit" "0,1"
|
|
bitfld.long 0x04 1. "RX_FLOW_ACT,Receive Flow Control Active - When asserted indicates that receive flow control is enabled and triggered" "0,1"
|
|
bitfld.long 0x04 0. "TX_FLOW_ACT,Transmit Flow Control Active When asserted this bit indicates that the pause time period is being observed for a received pause frame" "0,1"
|
|
line.long 0x08 "CPSW_P1_MAC_SOFT_RESET,"
|
|
bitfld.long 0x08 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the Ethernet Mac logic to be reset" "0,1"
|
|
line.long 0x0C "CPSW_P1_MAC_BOFFTEST,"
|
|
bitfld.long 0x0C 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 16.--25. 1. "RNDNUM,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only)"
|
|
rbitfld.long 0x0C 12.--15. "COLL_COUNT,Collision Count - The number of collisions the current frame has experienced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x0C 0.--9. 1. "TX_BACKOFF,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes"
|
|
line.long 0x10 "CPSW_P1_MAC_RX_PAUSETIMER,"
|
|
hexmask.long.word 0x10 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode)"
|
|
group.long 0x2370++0x03
|
|
line.long 0x00 "CPSW_P1_MAC_TX_PAUSETIMER,"
|
|
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,802.3 Tx Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode)"
|
|
group.long 0x23A0++0x07
|
|
line.long 0x00 "CPSW_P1_MAC_EMCONTROL,"
|
|
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
|
|
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
|
|
line.long 0x04 "CPSW_P1_MAC_TX_GAP,"
|
|
hexmask.long.word 0x04 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap This is the default gap value and only bits 8:0 are used"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_CPTS"
|
|
base ad:0x423D000
|
|
rgroup.long 0x00++0x4B
|
|
line.long 0x00 "CPTS_IDVER,"
|
|
line.long 0x04 "CPTS_CONTROL,"
|
|
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
|
|
bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
|
|
bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
|
|
bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
|
|
bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
|
|
bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
|
|
bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
|
|
bitfld.long 0x04 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "0,1"
|
|
bitfld.long 0x04 5. "_64_BIT_MODE,64-Bit Mode" "0,1"
|
|
bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
|
|
bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
|
|
bitfld.long 0x04 1. "INT_TEST,Interrupt test - When set this bit allows the raw interrupt to be written to facilitate interrupt test" "0,1"
|
|
bitfld.long 0x04 0. "CPTS_EN,Time sync enable - When disabled (cleared to zero) the RCLK domain is held in reset" "0,1"
|
|
line.long 0x08 "CPTS_RFTCLK_SEL,"
|
|
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select: This RFTCLK_SEL value can be written only when the CPTS_EN bit and the TSTAMP_EN bit are cleared to zero in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "CPTS_TS_PUSH,"
|
|
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO" "0,1"
|
|
line.long 0x10 "CPTS_TS_LOAD_LOW_VAL,"
|
|
line.long 0x14 "CPTS_TS_LOAD_EN,"
|
|
bitfld.long 0x14 0. "TS_LOAD_EN,Time stamp load enable - Writing a one to this bit enables the time stamp value to be written with the value in TS_LOAD_VAL[63:0]" "0,1"
|
|
line.long 0x18 "CPTS_TS_COMP_LOW_VAL,"
|
|
line.long 0x1C "CPTS_TS_COMP_LEN,"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "TS_COMP_LENGTH,Time stamp comparison length - Writing a non-zero value to this field enables the time stamp comparison event and output"
|
|
line.long 0x20 "CPTS_INTSTAT_RAW,"
|
|
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
|
|
line.long 0x24 "CPTS_INTSTAT_MASKED,"
|
|
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
|
|
line.long 0x28 "CPTS_INT_ENABLE,"
|
|
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
|
|
line.long 0x2C "CPTS_TS_COMP_NUDGE,"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "TS_COMP_NUDGE,Timestamp Comparison Nudge Value"
|
|
line.long 0x30 "CPTS_EVENT_POP,"
|
|
bitfld.long 0x30 0. "EVENT_POP,Event pop - When a logic high is written to this bit an event is popped off the event FIFO" "0,1"
|
|
line.long 0x34 "CPTS_EVENT_0,"
|
|
line.long 0x38 "CPTS_EVENT_1,"
|
|
bitfld.long 0x38 24.--28. "PORT_NUMBER,Port number - indicates the port number (encoded) of an Ethernet event or the encoded hardware timestamp number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x38 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message type - The message type value that was contained in an Ethernet transmit or receive time sync packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence ID - The 16-bit sequence id is the value that was contained in an Ethernet transmit or receive time sync packet"
|
|
line.long 0x3C "CPTS_EVENT_2,"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,Domain - The 8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet"
|
|
line.long 0x40 "CPTS_EVENT_3,"
|
|
line.long 0x44 "CPTS_TS_LOAD_HIGH_VAL,"
|
|
line.long 0x48 "CPTS_TS_COMP_HIGH_VAL,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_EMAC"
|
|
base ad:0x4200000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SS_IDVER,"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SS_CONTROL,"
|
|
bitfld.long 0x00 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode" "0,1"
|
|
bitfld.long 0x00 0. "EEE_EN,Energy Efficient Ethernet Enable" "0,1"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "SS_RGMII_STATUS,"
|
|
bitfld.long 0x00 3. "FULLDUPLEX,Rgmii full dulex" "0,1"
|
|
bitfld.long 0x00 1.--2. "SPEED,Rgmii speed" "0,1,2,3"
|
|
bitfld.long 0x00 0. "LINK,Rgmii link indicator" "0,1"
|
|
line.long 0x04 "SS_SUBSSYSTEM_STATUS,"
|
|
bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW_2U" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_INTD"
|
|
base ad:0x4001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTD_REVISION_REG,"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "INTD_CONTROL_REG,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INTD_EOI_REG,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "INTD_INTR_VECTOR_REG,"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "INTD_STATUS_REG0,"
|
|
rbitfld.long 0x00 9. "STATUS_HOST_INT09SA_UL_PKA_IN_INTR,Status for INT09SA_UL_PKA_IN_INTR" "0,1"
|
|
rbitfld.long 0x00 8. "STATUS_HOST_INT08SA_UL_TRNG_IN_INTR,Status for INT08SA_UL_TRNG_IN_INTR" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "STATUS_HOST_INT07MDIO_USER1_IN_INTR,Status for INT07MDIO_USER1_IN_INTR" "0,1"
|
|
rbitfld.long 0x00 6. "STATUS_HOST_INT06MDIO_USER0_IN_INTR,Status for INT06MDIO_USER0_IN_INTR" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "STATUS_HOST_INT05MDIO_LINK1_IN_INTR,Status for INT05MDIO_LINK1_IN_INTR" "0,1"
|
|
rbitfld.long 0x00 4. "STATUS_HOST_INT04MDIO_LINK0_IN_INTR,Status for INT04MDIO_LINK0_IN_INTR" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "STATUS_HOST_INT03ESW_EVNT_PEND_IN_INTR,Status for INT03ESW_EVNT_PEND_IN_INTR" "0,1"
|
|
rbitfld.long 0x00 2. "STATUS_HOST_INT02ESW_STAT_PEND1_IN_INTR,Status for INT02ESW_STAT_PEND1_IN_INTR" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "STATUS_HOST_INT01ESW_STAT_PEND0_IN_INTR,Status for INT01ESW_STAT_PEND0_IN_INTR" "0,1"
|
|
bitfld.long 0x00 0. "STATUS_HOST_INT00CDMA0_STARVE_INTR_INT,Status (write 1 to set) for INT00CDMA0_STARVE_INTR_INT" "0,1"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "INTD_STATUS_CLR_REG0,"
|
|
bitfld.long 0x00 0. "STATUS_HOST_INT00CDMA0_STARVE_INTR_INT_CLR,Status (write 1 to clear) for INT00CDMA0_STARVE_INTR_INT" "0,1"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "INTD_INTCNT_REG0,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INTCNT_HOST_CNT_INT00CDMA0_STARVE_INTR_INT,Interrupt Count for HOST_CNT_INT00CDMA0_STARVE_INTR_INT (write to decrement)"
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "INTD_INTR_VECTOR_REG_HOST,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_MDIO"
|
|
base ad:0x4200F00
|
|
rgroup.long 0x00++0x17
|
|
line.long 0x00 "MDIO_VERSION,"
|
|
line.long 0x04 "MDIO_CONTROL,"
|
|
bitfld.long 0x04 31. "IDLE,MDIO state machine idle indicator" "State machine is running,State machine is in idle state"
|
|
newline
|
|
bitfld.long 0x04 30. "ENABLE,Enable control" "Disables the MDIO state machine,Enable the MDIO state machine"
|
|
newline
|
|
bitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "channel 0 only,channels 0 and 1 and so on,?..."
|
|
newline
|
|
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "Standard MDIO preamble is used,Disables this device from sending MDIO frame.."
|
|
newline
|
|
bitfld.long 0x04 19. "FAULT,Fault indicator" "No failure,Physical layer fault; the.."
|
|
newline
|
|
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "Disables the physical layer fault detection,Enables the physical layer fault detection"
|
|
newline
|
|
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "Interrupt bits are not set,Enables the host to set the USERINT and LINKINT.."
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
|
|
line.long 0x08 "MDIO_ALIVE,"
|
|
line.long 0x0C "MDIO_LINK,"
|
|
line.long 0x10 "MDIO_LINK_INT_RAW,"
|
|
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
|
|
line.long 0x14 "MDIO_LINK_INT_MASKED,"
|
|
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "MDIO_USER_INT_RAW,"
|
|
bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for the MDIO_USERACCESS register" "0,1,2,3"
|
|
line.long 0x04 "MDIO_USER_INT_MASKED,"
|
|
bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for the MDIO_USERACCESS register" "0,1,2,3"
|
|
line.long 0x08 "MDIO_USER_INT_MASK_SET,"
|
|
bitfld.long 0x08 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED" "0,1,2,3"
|
|
line.long 0x0C "MDIO_USER_INT_MASK_CLEAR,"
|
|
bitfld.long 0x0C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for USERINTMASKED" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_NAVSS_CFG"
|
|
base ad:0x4000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVISION_REGISTER,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_EMAC_ECC"
|
|
base ad:0x423F000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "ECC_VECTOR,"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status indicating that the serial VBUS read is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Trigger a read operation to the specified read address that requires a serial VBUS access" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,ECC RAM ID to select which ECC RAM to control or read status from"
|
|
line.long 0x04 "ECC_MISC_STATUS,"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of ECC RAMs serviced by the aggregator"
|
|
line.long 0x08 "ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "ECC_CONTROL,"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the force_sec/force_ded will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec or force_ded is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where force_sec or force_ded needs to be applied"
|
|
line.long 0x14 "ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when force_ded is set"
|
|
line.long 0x18 "ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,1 indicates a pending successive single-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
bitfld.long 0x18 2. "ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,1 indicates a double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "ECC_SEC,1 indicates a single-bit error" "0,1"
|
|
line.long 0x1C "ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the data bit that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "ECC_EOI,"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "ECC_INT_STATUS_0,"
|
|
line.long 0x08 "ECC_INT_STATUS_1,"
|
|
line.long 0x0C "ECC_INT_STATUS_2,"
|
|
line.long 0x10 "ECC_INT_STATUS_3,"
|
|
line.long 0x14 "ECC_INT_STATUS_4,"
|
|
line.long 0x18 "ECC_INT_STATUS_5,"
|
|
line.long 0x1C "ECC_INT_STATUS_6,"
|
|
line.long 0x20 "ECC_INT_STATUS_7,"
|
|
line.long 0x24 "ECC_INT_STATUS_8,"
|
|
line.long 0x28 "ECC_INT_STATUS_9,"
|
|
line.long 0x2C "ECC_INT_STATUS_10,"
|
|
line.long 0x30 "ECC_INT_STATUS_11,"
|
|
line.long 0x34 "ECC_INT_STATUS_12,"
|
|
line.long 0x38 "ECC_INT_STATUS_13,"
|
|
line.long 0x3C "ECC_INT_STATUS_14,"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "ECC_INT_ENABLE_0,"
|
|
line.long 0x04 "ECC_INT_ENABLE_1,"
|
|
line.long 0x08 "ECC_INT_ENABLE_2,"
|
|
line.long 0x0C "ECC_INT_ENABLE_3,"
|
|
line.long 0x10 "ECC_INT_ENABLE_4,"
|
|
line.long 0x14 "ECC_INT_ENABLE_5,"
|
|
line.long 0x18 "ECC_INT_ENABLE_6,"
|
|
line.long 0x1C "ECC_INT_ENABLE_7,"
|
|
line.long 0x20 "ECC_INT_ENABLE_8,"
|
|
line.long 0x24 "ECC_INT_ENABLE_9,"
|
|
line.long 0x28 "ECC_INT_ENABLE_10,"
|
|
line.long 0x2C "ECC_INT_ENABLE_11,"
|
|
line.long 0x30 "ECC_INT_ENABLE_12,"
|
|
line.long 0x34 "ECC_INT_ENABLE_13,"
|
|
line.long 0x38 "ECC_INT_ENABLE_14,"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "ECC_INT_CLEAR_0,"
|
|
line.long 0x04 "ECC_INT_CLEAR_1,"
|
|
line.long 0x08 "ECC_INT_CLEAR_2,"
|
|
line.long 0x0C "ECC_INT_CLEAR_3,"
|
|
line.long 0x10 "ECC_INT_CLEAR_4,"
|
|
line.long 0x14 "ECC_INT_CLEAR_5,"
|
|
line.long 0x18 "ECC_INT_CLEAR_6,"
|
|
line.long 0x1C "ECC_INT_CLEAR_7,"
|
|
line.long 0x20 "ECC_INT_CLEAR_8,"
|
|
line.long 0x24 "ECC_INT_CLEAR_9,"
|
|
line.long 0x28 "ECC_INT_CLEAR_10,"
|
|
line.long 0x2C "ECC_INT_CLEAR_11,"
|
|
line.long 0x30 "ECC_INT_CLEAR_12,"
|
|
line.long 0x34 "ECC_INT_CLEAR_13,"
|
|
line.long 0x38 "ECC_INT_CLEAR_14,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_NAVSS_ECC"
|
|
base ad:0x4000800
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "ECC_VECTOR,"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status indicating that the serial VBUS read is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Trigger a read operation to the specified read address that requires a serial VBUS access" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,ECC RAM ID to select which ECC RAM to control or read status from"
|
|
line.long 0x04 "ECC_MISC_STATUS,"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of ECC RAMs serviced by the aggregator"
|
|
line.long 0x08 "ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "ECC_CONTROL,"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the force_sec/force_ded will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec or force_ded is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where force_sec or force_ded needs to be applied"
|
|
line.long 0x14 "ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when force_ded is set"
|
|
line.long 0x18 "ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,1 indicates a pending successive single-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
bitfld.long 0x18 2. "ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,1 indicates a double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "ECC_SEC,1 indicates a single-bit error" "0,1"
|
|
line.long 0x1C "ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the data bit that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "ECC_EOI,"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "ECC_INT_STATUS_0,"
|
|
line.long 0x08 "ECC_INT_STATUS_1,"
|
|
line.long 0x0C "ECC_INT_STATUS_2,"
|
|
line.long 0x10 "ECC_INT_STATUS_3,"
|
|
line.long 0x14 "ECC_INT_STATUS_4,"
|
|
line.long 0x18 "ECC_INT_STATUS_5,"
|
|
line.long 0x1C "ECC_INT_STATUS_6,"
|
|
line.long 0x20 "ECC_INT_STATUS_7,"
|
|
line.long 0x24 "ECC_INT_STATUS_8,"
|
|
line.long 0x28 "ECC_INT_STATUS_9,"
|
|
line.long 0x2C "ECC_INT_STATUS_10,"
|
|
line.long 0x30 "ECC_INT_STATUS_11,"
|
|
line.long 0x34 "ECC_INT_STATUS_12,"
|
|
line.long 0x38 "ECC_INT_STATUS_13,"
|
|
line.long 0x3C "ECC_INT_STATUS_14,"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "ECC_INT_ENABLE_0,"
|
|
line.long 0x04 "ECC_INT_ENABLE_1,"
|
|
line.long 0x08 "ECC_INT_ENABLE_2,"
|
|
line.long 0x0C "ECC_INT_ENABLE_3,"
|
|
line.long 0x10 "ECC_INT_ENABLE_4,"
|
|
line.long 0x14 "ECC_INT_ENABLE_5,"
|
|
line.long 0x18 "ECC_INT_ENABLE_6,"
|
|
line.long 0x1C "ECC_INT_ENABLE_7,"
|
|
line.long 0x20 "ECC_INT_ENABLE_8,"
|
|
line.long 0x24 "ECC_INT_ENABLE_9,"
|
|
line.long 0x28 "ECC_INT_ENABLE_10,"
|
|
line.long 0x2C "ECC_INT_ENABLE_11,"
|
|
line.long 0x30 "ECC_INT_ENABLE_12,"
|
|
line.long 0x34 "ECC_INT_ENABLE_13,"
|
|
line.long 0x38 "ECC_INT_ENABLE_14,"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "ECC_INT_CLEAR_0,"
|
|
line.long 0x04 "ECC_INT_CLEAR_1,"
|
|
line.long 0x08 "ECC_INT_CLEAR_2,"
|
|
line.long 0x0C "ECC_INT_CLEAR_3,"
|
|
line.long 0x10 "ECC_INT_CLEAR_4,"
|
|
line.long 0x14 "ECC_INT_CLEAR_5,"
|
|
line.long 0x18 "ECC_INT_CLEAR_6,"
|
|
line.long 0x1C "ECC_INT_CLEAR_7,"
|
|
line.long 0x20 "ECC_INT_CLEAR_8,"
|
|
line.long 0x24 "ECC_INT_CLEAR_9,"
|
|
line.long 0x28 "ECC_INT_CLEAR_10,"
|
|
line.long 0x2C "ECC_INT_CLEAR_11,"
|
|
line.long 0x30 "ECC_INT_CLEAR_12,"
|
|
line.long 0x34 "ECC_INT_CLEAR_13,"
|
|
line.long 0x38 "ECC_INT_CLEAR_14,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NSS_0_CFG_QMGR0_CFG"
|
|
base ad:0x4040000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "QM_REVISION_REG,"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "QM_QUEUE_DIVERSION_REG,"
|
|
bitfld.long 0x00 31. "HEAD_TAIL,Indicates whether queue contents should be merged on to head or tail of destination queue" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. "DEST_QNUM,Destination queue number"
|
|
hexmask.long.word 0x00 0.--13. 1. "SOURCE_QNUM,Source queue number"
|
|
line.long 0x04 "QM_LINKING_RAM_REGION_0_BASE_ADDRESS_REG,"
|
|
hexmask.long 0x04 2.--31. 1. "REGION0_BASE,This field stores the base address for the first region of the linking RAM"
|
|
line.long 0x08 "QM_LINKING_RAM_REGION_0_SIZE_REG,"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. "REGION0_SIZE,This field indicates the number of entries that are contained in the linking RAM region 0"
|
|
line.long 0x0C "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_0,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
group.long 0x14++0x3B
|
|
line.long 0x00 "QM_LINKING_RAM_REGION_1_BASE_ADDRESS_REG,"
|
|
hexmask.long 0x00 2.--31. 1. "REGION1_BASE,This field stores the base address for the first region of the linking RAM"
|
|
line.long 0x04 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x04 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x04 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x04 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x08 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_2,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x08 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x08 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x08 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x0C "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_3,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x10 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_4,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x10 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x10 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x14 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_5,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x14 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x14 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x14 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x18 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_6,"
|
|
hexmask.long.byte 0x18 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x18 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x18 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x1C "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_7,"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x20 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_8,"
|
|
hexmask.long.byte 0x20 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x20 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x20 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x20 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x24 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_9,"
|
|
hexmask.long.byte 0x24 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x24 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x24 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x24 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x28 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_10,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x28 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x28 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x28 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x2C "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_11,"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x30 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_12,"
|
|
hexmask.long.byte 0x30 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x30 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x30 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x30 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x34 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_13,"
|
|
hexmask.long.byte 0x34 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x34 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x34 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x34 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
line.long 0x38 "QM_FREE_DESCRIPTOR_STARVE_COUNT_REG_14,"
|
|
hexmask.long.byte 0x38 24.--31. 1. "FDBQ3_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x38 16.--23. 1. "FDBQ2_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) +"
|
|
hexmask.long.byte 0x38 8.--15. 1. "FDBQ1_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4)"
|
|
hexmask.long.byte 0x38 0.--7. 1. "FDBQ0_STARVE_CNT,This field increments each time the Free Descriptor/Buffer Queue \[(N*4) \]==0 is read while it is empty"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_0_ECC_CFG"
|
|
base ad:0x2330400
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PCIE_ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "PCIE_ECC_VECTOR,"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status indicating that the serial VBUS read is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Trigger a read operation to the specified read address that requires a serial VBUS access" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,ECC RAM ID to select which ECC RAM to control or read status from"
|
|
line.long 0x04 "PCIE_ECC_MISC_STATUS,"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of ECC RAMs serviced by the aggregator"
|
|
line.long 0x08 "PCIE_ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "PCIE_ECC_CONTROL,"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the force_sec/force_ded will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "PCIE_ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "PCIE_ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "PCIE_ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "PCIE_ECC_BIT1,Data bit that needs to be flipped when force_sec or force_ded is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "PCIE_ECC_ROW,Row address where force_sec or force_ded needs to be applied"
|
|
line.long 0x14 "PCIE_ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 0.--15. 1. "PCIE_ECC_BIT2,Data bit that needs to be flipped when force_ded is set"
|
|
line.long 0x18 "PCIE_ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "PCIE_ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
bitfld.long 0x18 10. "CLR_PCIE_ECC_OTHER,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_PCIE_ECC_DED,1 indicates a pending successive single-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_PCIE_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
bitfld.long 0x18 2. "PCIE_ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "PCIE_ECC_DED,1 indicates a double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "PCIE_ECC_SEC,1 indicates a single-bit error" "0,1"
|
|
line.long 0x1C "PCIE_ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 0.--15. 1. "PCIE_ECC_BIT1,Indicates the data bit that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "PCIE_ECC_EOI,"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "PCIE_ECC_INT_STATUS_0,"
|
|
line.long 0x08 "PCIE_ECC_INT_STATUS_1,"
|
|
line.long 0x0C "PCIE_ECC_INT_STATUS_2,"
|
|
line.long 0x10 "PCIE_ECC_INT_STATUS_3,"
|
|
line.long 0x14 "PCIE_ECC_INT_STATUS_4,"
|
|
line.long 0x18 "PCIE_ECC_INT_STATUS_5,"
|
|
line.long 0x1C "PCIE_ECC_INT_STATUS_6,"
|
|
line.long 0x20 "PCIE_ECC_INT_STATUS_7,"
|
|
line.long 0x24 "PCIE_ECC_INT_STATUS_8,"
|
|
line.long 0x28 "PCIE_ECC_INT_STATUS_9,"
|
|
line.long 0x2C "PCIE_ECC_INT_STATUS_10,"
|
|
line.long 0x30 "PCIE_ECC_INT_STATUS_11,"
|
|
line.long 0x34 "PCIE_ECC_INT_STATUS_12,"
|
|
line.long 0x38 "PCIE_ECC_INT_STATUS_13,"
|
|
line.long 0x3C "PCIE_ECC_INT_STATUS_14,"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "PCIE_ECC_INT_ENABLE_0,"
|
|
line.long 0x04 "PCIE_ECC_INT_ENABLE_1,"
|
|
line.long 0x08 "PCIE_ECC_INT_ENABLE_2,"
|
|
line.long 0x0C "PCIE_ECC_INT_ENABLE_3,"
|
|
line.long 0x10 "PCIE_ECC_INT_ENABLE_4,"
|
|
line.long 0x14 "PCIE_ECC_INT_ENABLE_5,"
|
|
line.long 0x18 "PCIE_ECC_INT_ENABLE_6,"
|
|
line.long 0x1C "PCIE_ECC_INT_ENABLE_7,"
|
|
line.long 0x20 "PCIE_ECC_INT_ENABLE_8,"
|
|
line.long 0x24 "PCIE_ECC_INT_ENABLE_9,"
|
|
line.long 0x28 "PCIE_ECC_INT_ENABLE_10,"
|
|
line.long 0x2C "PCIE_ECC_INT_ENABLE_11,"
|
|
line.long 0x30 "PCIE_ECC_INT_ENABLE_12,"
|
|
line.long 0x34 "PCIE_ECC_INT_ENABLE_13,"
|
|
line.long 0x38 "PCIE_ECC_INT_ENABLE_14,"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "PCIE_ECC_INT_CLEAR_0,"
|
|
line.long 0x04 "PCIE_ECC_INT_CLEAR_1,"
|
|
line.long 0x08 "PCIE_ECC_INT_CLEAR_2,"
|
|
line.long 0x0C "PCIE_ECC_INT_CLEAR_3,"
|
|
line.long 0x10 "PCIE_ECC_INT_CLEAR_4,"
|
|
line.long 0x14 "PCIE_ECC_INT_CLEAR_5,"
|
|
line.long 0x18 "PCIE_ECC_INT_CLEAR_6,"
|
|
line.long 0x1C "PCIE_ECC_INT_CLEAR_7,"
|
|
line.long 0x20 "PCIE_ECC_INT_CLEAR_8,"
|
|
line.long 0x24 "PCIE_ECC_INT_CLEAR_9,"
|
|
line.long 0x28 "PCIE_ECC_INT_CLEAR_10,"
|
|
line.long 0x2C "PCIE_ECC_INT_CLEAR_11,"
|
|
line.long 0x30 "PCIE_ECC_INT_CLEAR_12,"
|
|
line.long 0x34 "PCIE_ECC_INT_CLEAR_13,"
|
|
line.long 0x38 "PCIE_ECC_INT_CLEAR_14,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_0_PHY_CFG"
|
|
base ad:0x2321FC0
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCIE_PHY_LANExCTL_STS,"
|
|
bitfld.long 0x00 31. "TX0_ENABLE_OVL,The Tx Enable Overlay bit when set allows the Tx Enable Value to override the CFGTX Enable input" "0,1"
|
|
bitfld.long 0x00 29.--30. "TX0_ENABLE_VAL,The Tx Enable Value when used allows the Tx lane to be placed in" "0,1,2,3"
|
|
bitfld.long 0x00 28. "TX0_RATE_OVL,The Tx Rate Overlay bit when set allows the Tx Rate Value to override the CFGTX Rate input" "0,1"
|
|
bitfld.long 0x00 26.--27. "TX0_RATE_VAL,The Tx Rate Value when used allows the Tx lane to be placed into" "0,1,2,3"
|
|
bitfld.long 0x00 25. "TX0_IDLE_OVL,The Tx Idle Overlay bit when set allows the Tx Idle Value to override the CFGTX.Idle input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "TX0_IDLE_VAL,The Tx Idle Value when used allows the Tx lane to be placed electrical Idle state in non PCIE mode" "0,1"
|
|
bitfld.long 0x00 23. "TX0_WIDTH_OVL,The Tx Width Overlay bit when set allows the Tx Width Value to override the CFGTX.Width input" "0,1"
|
|
bitfld.long 0x00 21.--22. "TX0_WIDTH_VAL,The Tx Width Value when used allows the Tx lane to be placed into" "0,1,2,3"
|
|
rbitfld.long 0x00 16.--20. "Reserved,Reserved - writes are ignored always reads zeros" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "RX0_ENABLE_OVL,The Rx Enable Overlay bit when set allows the Rx Enable Value to override the CFGRX Enable input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "RX0_ENABLE_VAL,The Rx Enable Value when used allows the Rx lane to be placed in" "0,1,2,3"
|
|
bitfld.long 0x00 12. "RX0_RATE_OVL,The Rx Rate Overlay bit when set allows the Rx Rate Value to override the CFGRX Rate input" "0,1"
|
|
bitfld.long 0x00 10.--11. "RX0_RATE_VAL,The Rx Rate Value when used allows the Rx lane to be placed into" "0,1,2,3"
|
|
bitfld.long 0x00 9. "RX0_POLARITY_OVL,The Rx Polarity Overlay bit when set allows the Rx Polarity Value to override the CFGRX.Polarity input" "0,1"
|
|
bitfld.long 0x00 8. "RX0_POLARITY_VAL,The Rx Polarity Value when used allows the lane Rx Polarity to be inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RX0_ALIGN_OVL,The Rx Align Overlay bit when set allows the Rx Align Value to override the CFGRX.Align input" "0,1"
|
|
bitfld.long 0x00 6. "RX0_ALIGN_VAL,The Rx Align Value when used allows the Rx lane to align to K28.1 K28.5 and K28.7 characters otherwise known as Comma Characters" "0,1"
|
|
bitfld.long 0x00 5. "RX0_WIDTH_OVL,The Rx Width Overlay bit when set allows the Rx Width Value to override the CFGRX Width input" "0,1"
|
|
bitfld.long 0x00 3.--4. "RX0_WIDTH_VAL,The Rx Width Value when used allows the Rx lane to be placed into" "0,1,2,3"
|
|
rbitfld.long 0x00 2. "Reserved,Reserved - writes are ignored always reads zeros" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "RX0_OK,The Rx OK indicate that the lane is in a functional state" "0,1"
|
|
rbitfld.long 0x00 0. "RX0_LOSS,The Rx Signal Loss Indicates that the data has not been detected or the CDR is not locked" "0,1"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "PCIE_PHY_PLL_CTRL,"
|
|
bitfld.long 0x00 31. "PLL_ENABLE_OVL,The PLL Enable Overlay bit when set allows the PLL Enable Value to override the CFGPLL.Enable input" "0,1"
|
|
bitfld.long 0x00 29.--30. "PLL_ENABLE_VAL,The PLL Enable Value when used allows the PLL to be placed in" "0,1,2,3"
|
|
rbitfld.long 0x00 28. "PLL_OK,The PLL Ok indicate that the transmit clocks are valid and the PLL circuits are ready for use" "0,1"
|
|
hexmask.long.word 0x00 18.--27. 1. "Reserved,Reserved - writes are ignored always reads zeros"
|
|
bitfld.long 0x00 17. "LN_WAFTER_OK,The LN_WAFTER_OK field will cause the lane OK indication to be Blocked until the LNX_CONT_OK is set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "LN_WAFTER_SD,The LN_WAFTER_SD field will cause the Rx signal indication to be Blocked until the LNX_CONT_SD is set" "0,1"
|
|
rbitfld.long 0x00 13.--15. "Reserved,Reserved - writes are ignored always reads zeros" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "LN0_CONT_OK,The LN0_CONT_OK allows the Blocked lane OK for lane 0 to now pass to the controlling PCS IP" "0,1"
|
|
rbitfld.long 0x00 9.--11. "Reserved,Reserved - writes are ignored always reads zeros" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8. "LN0_OK_STATE,The LN0_OK_STATE indicate the current state of the lane OK signal for lane 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "Reserved,Reserved - writes are ignored always reads zeros" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "LN0_CONT_SD,The LN0_CONT_SD allows the Blocked signal detect for lane 0 to now pass to the controlling PCS IP" "0,1"
|
|
rbitfld.long 0x00 1.--3. "Reserved,Reserved - writes are ignored always reads zeros" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0. "LN0_SD_STATE,The LN0_SD_STATE indicate the current state of the signal detect signal for lane 0" "0,1"
|
|
line.long 0x04 "PCIE_PHY_COMMA_LINK_DELAY,"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "Reserved,Reserved - writes are ignored always reads zeros"
|
|
hexmask.long.byte 0x04 0.--7. 1. "LANE0_CDELAY,Defines the number of network bits the comma aligner has added to the fixed delay of the PCS/PMA layer for lane 0"
|
|
line.long 0x08 "PCIE_PHY_CMU_WAIT,"
|
|
hexmask.long.word 0x08 17.--31. 1. "Reserved,Reserved - writes are ignored always reads zeros"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. "WAIT_VAL,Defines the number of clock cycles between writing to the CMU Reset register and CMU_RESET_I activation"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_APPLICATION"
|
|
base ad:0x21800000
|
|
rgroup.long 0x00++0x17
|
|
line.long 0x00 "PCIE_PID,"
|
|
line.long 0x04 "PCIE_CMD_STATUS,"
|
|
bitfld.long 0x04 5. "DBI_CS2,Set to enable writing to BAR mask registers that are overlaid on BAR registers" "0,1"
|
|
bitfld.long 0x04 4. "APP_RETRY_EN,Application request retry enable" "0,1"
|
|
bitfld.long 0x04 3. "POSTED_WR_EN,Posted write enable" "0,1"
|
|
bitfld.long 0x04 2. "IB_XLT_EN,Inbound address translation enable" "0,1"
|
|
bitfld.long 0x04 1. "OB_XLT_EN,Outbound address translation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "LTSSM_EN,Link training enable" "0,1"
|
|
line.long 0x08 "PCIE_CFG_SETUP,"
|
|
bitfld.long 0x08 24. "CFG_TYPE,Configuration type for outbound configuration accesses" "0,1"
|
|
hexmask.long.byte 0x08 16.--23. 1. "CFG_BUS,PCIe bus number for outbound configuration accesses (value = 0-FFh)"
|
|
bitfld.long 0x08 8.--12. "CFG_DEVICE,PCIe device number for outbound configuration accesses (value = 0-1Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--2. "CFG_FUNC,PCIe function number for outbound configuration accesses (value = 0-7h)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PCIE_IOBASE,"
|
|
hexmask.long.tbyte 0x0C 12.--31. 1. "IOBASE,Bits [31-12] of outgoing IO TLP (value = 0-FFFFFh)"
|
|
line.long 0x10 "PCIE_TLPCFG,"
|
|
bitfld.long 0x10 1. "RELAXED,Enable relaxed ordering for all outgoing TLPs" "0,1"
|
|
bitfld.long 0x10 0. "NO_SNOOP,Enable No Snoop attribute on all outgoing TLPs" "0,1"
|
|
line.long 0x14 "PCIE_RSTCMD,"
|
|
rbitfld.long 0x14 16. "FLUSH_N,Bridge flush status" "0,1"
|
|
bitfld.long 0x14 0. "INIT_RST,Write 1 to initiate a downstream hot reset sequence on downstream" "0,1"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "PCIE_PMCMD,"
|
|
bitfld.long 0x00 1. "PM_XMT_TURNOFF,Write 1 to transmit a PM_TURNOFF message" "0,1"
|
|
bitfld.long 0x00 0. "PM_XMT_PME,Write 1 to transmit a PM_PME message" "0,1"
|
|
line.long 0x04 "PCIE_PMCFG,"
|
|
bitfld.long 0x04 0. "ENTR_L23,Write 1 to enable entry to L2/L3 ready state" "0,1"
|
|
line.long 0x08 "PCIE_ACT_STATUS,"
|
|
bitfld.long 0x08 1. "OB_NOT_EMPTY," "0,1"
|
|
bitfld.long 0x08 0. "IB_NOT_EMPTY," "0,1"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "PCIE_OB_SIZE,"
|
|
bitfld.long 0x00 0.--2. "OB_SIZE,Set each outbound translation window size" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PCIE_DIAG_CTRL,"
|
|
bitfld.long 0x04 1. "INV_ECRC,Write 1 to force inversion of LSB of ECRC for the next one packet" "0,1"
|
|
bitfld.long 0x04 0. "INV_LCRC,Write 1 to force inversion of LSB of LCRC for the next one packet" "0,1"
|
|
line.long 0x08 "PCIE_ENDIAN,"
|
|
bitfld.long 0x08 0.--1. "ENDIAN_MODE,Endian mode" "0,1,2,3"
|
|
line.long 0x0C "PCIE_PRIORITY,"
|
|
bitfld.long 0x0C 16. "MST_PRIV,Master transaction mode" "0,1"
|
|
rbitfld.long 0x0C 8.--11. "MST_PRIVID,Master PRIVID value on master transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--2. "MST_PRIORITY,Priority level for each inbound transaction on the internal bus master port" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "PCIE_IRQ_EOI,"
|
|
bitfld.long 0x00 0.--3. "EOI,EOI for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PCIE_MSI_IRQ,"
|
|
group.long 0x64++0x1B
|
|
line.long 0x00 "PCIE_EP_IRQ_SET,"
|
|
bitfld.long 0x00 0. "EP_IRQ_SET,Write 1 to generate assert interrupt message" "0,1"
|
|
line.long 0x04 "PCIE_EP_IRQ_CLR,"
|
|
bitfld.long 0x04 0. "EP_IRQ_CLR,Write 1 to generate deassert interrupt message" "0,1"
|
|
line.long 0x08 "PCIE_EP_IRQ_STATUS,"
|
|
bitfld.long 0x08 0. "EP_IRQ_STATUS,Indicates whether interrupt for function 0 is asserted or not" "0,1"
|
|
line.long 0x0C "PCIE_GPR0,"
|
|
line.long 0x10 "PCIE_GPR1,"
|
|
line.long 0x14 "PCIE_GPR2,"
|
|
line.long 0x18 "PCIE_GPR3,"
|
|
group.long 0x100++0xDF
|
|
line.long 0x00 "PCIE_MSI0_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x00 0.--3. "MSI0_RAW_STATUS,Each bit indicates raw status of MSI vectors (24 16 8 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PCIE_MSI0_IRQ_STATUS,"
|
|
bitfld.long 0x04 0.--3. "MSI0_IRQ_STATUS,Each bit indicates status of MSI vector (24 16 8 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PCIE_MSI0_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x08 0.--3. "MSI0_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (24 16 8 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "PCIE_MSI0_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x0C 0.--3. "MSI0_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (24 16 8 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "PCIE_MSI1_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x10 0.--3. "MSI1_RAW_STATUS,Each bit indicates raw status of MSI vectors (25 17 9 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "PCIE_MSI1_IRQ_STATUS,"
|
|
bitfld.long 0x14 0.--3. "MSI1_IRQ_STATUS,Each bit indicates status of MSI vector (25 17 9 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "PCIE_MSI1_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x18 0.--3. "MSI1_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (25 17 9 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "PCIE_MSI1_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x1C 0.--3. "MSI1_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (25 17 9 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "PCIE_MSI2_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x20 0.--3. "MSI2_RAW_STATUS,Each bit indicates raw status of MSI vectors (26 18 10 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "PCIE_MSI2_IRQ_STATUS,"
|
|
bitfld.long 0x24 0.--3. "MSI2_IRQ_STATUS,Each bit indicates status of MSI vector (26 18 10 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "PCIE_MSI2_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x28 0.--3. "MSI2_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (26 18 10 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "PCIE_MSI2_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x2C 0.--3. "MSI2_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (26 18 10 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "PCIE_MSI3_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x30 0.--3. "MSI3_RAW_STATUS,Each bit indicates raw status of MSI vectors (27 19 11 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "PCIE_MSI3_IRQ_STATUS,"
|
|
bitfld.long 0x34 0.--3. "MSI3_IRQ_STATUS,Each bit indicates status of MSI vector (27 19 11 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "PCIE_MSI3_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x38 0.--3. "MSI3_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (27 19 11 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "PCIE_MSI3_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x3C 0.--3. "MSI3_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (27 19 11 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "PCIE_MSI4_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x40 0.--3. "MSI4_RAW_STATUS,Each bit indicates raw status of MSI vectors (28 20 12 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "PCIE_MSI4_IRQ_STATUS,"
|
|
bitfld.long 0x44 0.--3. "MSI4_IRQ_STATUS,Each bit indicates status of MSI vector (28 20 12 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "PCIE_MSI4_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x48 0.--3. "MSI4_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (28 20 12 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "PCIE_MSI4_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x4C 0.--3. "MSI4_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (28 20 12 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x50 "PCIE_MSI5_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x50 0.--3. "MSI5_RAW_STATUS,Each bit indicates raw status of MSI vectors (29 21 13 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x54 "PCIE_MSI5_IRQ_STATUS,"
|
|
bitfld.long 0x54 0.--3. "MSI5_IRQ_STATUS,Each bit indicates status of MSI vector (29 21 13 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x58 "PCIE_MSI5_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x58 0.--3. "MSI5_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (29 21 13 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x5C "PCIE_MSI5_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x5C 0.--3. "MSI5_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (29 21 13 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x60 "PCIE_MSI6_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x60 0.--3. "MSI6_RAW_STATUS,Each bit indicates raw status of MSI vectors (30 22 14 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x64 "PCIE_MSI6_IRQ_STATUS,"
|
|
bitfld.long 0x64 0.--3. "MSI6_IRQ_STATUS,Each bit indicates status of MSI vector (30 22 14 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x68 "PCIE_MSI6_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x68 0.--3. "MSI6_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (30 22 14 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x6C "PCIE_MSI6_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x6C 0.--3. "MSI6_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (30 22 14 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x70 "PCIE_MSI7_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x70 0.--3. "MSI7_RAW_STATUS,Each bit indicates raw status of MSI vectors (31 23 15 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x74 "PCIE_MSI7_IRQ_STATUS,"
|
|
bitfld.long 0x74 0.--3. "MSI7_IRQ_STATUS,Each bit indicates status of MSI vector (31 23 15 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x78 "PCIE_MSI7_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x78 0.--3. "MSI7_IRQ_EN_SET,Each bit when written to enables the MSI interrupt (31 23 15 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x7C "PCIE_MSI7_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x7C 0.--3. "MSI7_IRQ_EN_CLR,Each bit when written to disables the MSI interrupt (31 23 15 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x80 "PCIE_LEGACY_A_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x80 0. "INTA,Legacy Interrupt A raw status" "0,1"
|
|
line.long 0x84 "PCIE_LEGACY_A_IRQ_STATUS,"
|
|
bitfld.long 0x84 0. "INTA,Legacy Interrupt A status" "0,1"
|
|
line.long 0x88 "PCIE_LEGACY_A_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x88 0. "INTA,Legacy Interrupt A enable" "0,1"
|
|
line.long 0x8C "PCIE_LEGACY_A_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x8C 0. "INTA,Legacy Interrupt A disable" "0,1"
|
|
line.long 0x90 "PCIE_LEGACY_B_IRQ_STATUS_RAW,"
|
|
bitfld.long 0x90 0. "INTB,Legacy Interrupt B raw status" "0,1"
|
|
line.long 0x94 "PCIE_LEGACY_B_IRQ_STATUS,"
|
|
bitfld.long 0x94 0. "INTB,Legacy Interrupt B status" "0,1"
|
|
line.long 0x98 "PCIE_LEGACY_B_IRQ_ENABLE_SET,"
|
|
bitfld.long 0x98 0. "INTB,Legacy Interrupt B enable" "0,1"
|
|
line.long 0x9C "PCIE_LEGACY_B_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0x9C 0. "INTB,Legacy Interrupt B disable" "0,1"
|
|
line.long 0xA0 "PCIE_LEGACY_C_IRQ_STATUS_RAW,"
|
|
bitfld.long 0xA0 0. "INTC,Legacy Interrupt C raw status" "0,1"
|
|
line.long 0xA4 "PCIE_LEGACY_C_IRQ_STATUS,"
|
|
bitfld.long 0xA4 0. "INTC,Legacy Interrupt C status" "0,1"
|
|
line.long 0xA8 "PCIE_LEGACY_C_IRQ_ENABLE_SET,"
|
|
bitfld.long 0xA8 0. "INTC,Legacy Interrupt C enable" "0,1"
|
|
line.long 0xAC "PCIE_LEGACY_C_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0xAC 0. "INTC,Legacy Interrupt C disable" "0,1"
|
|
line.long 0xB0 "PCIE_LEGACY_D_IRQ_STATUS_RAW,"
|
|
bitfld.long 0xB0 0. "INTD,Legacy Interrupt D raw status" "0,1"
|
|
line.long 0xB4 "PCIE_LEGACY_D_IRQ_STATUS,"
|
|
bitfld.long 0xB4 0. "INTD,Legacy Interrupt D status" "0,1"
|
|
line.long 0xB8 "PCIE_LEGACY_D_IRQ_ENABLE_SET,"
|
|
bitfld.long 0xB8 0. "INTD,Legacy Interrupt D enable" "0,1"
|
|
line.long 0xBC "PCIE_LEGACY_D_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0xBC 0. "INTD,Legacy Interrupt D disable" "0,1"
|
|
line.long 0xC0 "PCIE_ERR_IRQ_STATUS_RAW,"
|
|
bitfld.long 0xC0 5. "ERR_AER,ECRC error raw status" "0,1"
|
|
bitfld.long 0xC0 4. "ERR_AXI,AXI tag lookup fatal error raw status" "0,1"
|
|
bitfld.long 0xC0 3. "ERR_CORR,Correctable error raw status" "0,1"
|
|
bitfld.long 0xC0 2. "ERR_NONFATAL,Nonfatal error raw status" "0,1"
|
|
bitfld.long 0xC0 1. "ERR_FATAL,Fatal error raw status" "0,1"
|
|
newline
|
|
bitfld.long 0xC0 0. "ERR_SYS,System error (fatal nonfatal or correctable error) raw status" "0,1"
|
|
line.long 0xC4 "PCIE_ERR_IRQ_STATUS,"
|
|
bitfld.long 0xC4 5. "ERR_AER,ECRC error status" "0,1"
|
|
bitfld.long 0xC4 4. "ERR_AXI,AXI tag lookup fatal error" "0,1"
|
|
bitfld.long 0xC4 3. "ERR_CORR,Correctable error status" "0,1"
|
|
bitfld.long 0xC4 2. "ERR_NONFATAL,Nonfatal error status" "0,1"
|
|
bitfld.long 0xC4 1. "ERR_FATAL,Fatal error status" "0,1"
|
|
newline
|
|
bitfld.long 0xC4 0. "ERR_SYS,System Error (fatal nonfatal or correctable error)" "0,1"
|
|
line.long 0xC8 "PCIE_ERR_IRQ_ENABLE_SET,"
|
|
bitfld.long 0xC8 5. "ERR_AER,ECRC error interrupt enable" "0,1"
|
|
bitfld.long 0xC8 4. "ERR_AXI,AXI tag lookup fatal error interrupt enable" "0,1"
|
|
bitfld.long 0xC8 3. "ERR_CORR,Correctable error interrupt enable" "0,1"
|
|
bitfld.long 0xC8 2. "ERR_NONFATAL,Nonfatal error interrupt enable" "0,1"
|
|
bitfld.long 0xC8 1. "ERR_FATAL,Fatal error interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC8 0. "ERR_SYS,System Error (fatal nonfatal or correctable error) interrupt enable" "0,1"
|
|
line.long 0xCC "PCIE_ERR_IRQ_ENABLE_CLR,"
|
|
bitfld.long 0xCC 5. "ERR_AER,ECRC error interrupt disable" "0,1"
|
|
bitfld.long 0xCC 4. "ERR_AXI,AXI tag lookup fatal error interrupt disable" "0,1"
|
|
bitfld.long 0xCC 3. "ERR_CORR,Correctable error interrupt disable" "0,1"
|
|
bitfld.long 0xCC 2. "ERR_NONFATAL,Nonfatal error interrupt disable" "0,1"
|
|
bitfld.long 0xCC 1. "ERR_FATAL,Fatal error interrupt disable" "0,1"
|
|
newline
|
|
bitfld.long 0xCC 0. "ERR_SYS,System error (fatal nonfatal or correctable error) interrupt disable" "0,1"
|
|
line.long 0xD0 "PCIE_PMRST_IRQ_STATUS_RAW,"
|
|
bitfld.long 0xD0 3. "LINK_RST_REQ,Link Request Reset interrupt raw status" "0,1"
|
|
bitfld.long 0xD0 2. "PM_PME,Power management PME message received interrupt raw status" "0,1"
|
|
bitfld.long 0xD0 1. "PM_TO_ACK,Power management ACK received interrupt raw status" "0,1"
|
|
bitfld.long 0xD0 0. "PM_TURNOFF,Power management turnoff message received raw status" "0,1"
|
|
line.long 0xD4 "PCIE_PMRST_IRQ_STATUS,"
|
|
bitfld.long 0xD4 3. "LINK_RST_REQ,Link request reset interrupt status" "0,1"
|
|
bitfld.long 0xD4 2. "PM_PME,Power management PME message received interrupt status" "0,1"
|
|
bitfld.long 0xD4 1. "PM_TO_ACK,Power management ACK received interrupt status" "0,1"
|
|
bitfld.long 0xD4 0. "PM_TURNOFF,Power management turnoff message received status" "0,1"
|
|
line.long 0xD8 "PCIE_PMRST_ENABLE_SET,"
|
|
bitfld.long 0xD8 3. "LINK_RST_REQ,Link request reset interrupt enable" "0,1"
|
|
bitfld.long 0xD8 2. "PM_PME,Power management PME message received interrupt enable" "0,1"
|
|
bitfld.long 0xD8 1. "PM_TO_ACK,Power management ACK received interrupt enable" "0,1"
|
|
bitfld.long 0xD8 0. "PM_TURNOFF,Power management turnoff message received enable" "0,1"
|
|
line.long 0xDC "PCIE_PMRST_ENABLE_CLR,"
|
|
bitfld.long 0xDC 3. "LINK_RST_REQ,Link Request Reset interrupt disable" "0,1"
|
|
bitfld.long 0xDC 2. "PM_PME,Power management PME message received interrupt disable" "0,1"
|
|
bitfld.long 0xDC 1. "PM_TO_ACK,Power management ACK received interrupt disable" "0,1"
|
|
bitfld.long 0xDC 0. "PM_TURNOFF,Power management Turnoff message received disable" "0,1"
|
|
group.long 0x300++0x3F
|
|
line.long 0x00 "PCIE_IB_BAR0,"
|
|
bitfld.long 0x00 0.--2. "IB_BAR0,BAR number to match for inbound translation region 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PCIE_IB_START0_LO,"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "IB_START0_LO,Start address bits [31-8] for inbound translation region 0"
|
|
line.long 0x08 "PCIE_IB_START0_HI,"
|
|
line.long 0x0C "PCIE_IB_OFFSET0,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "IB_OFFSET0,Offset address bits [31-8] for inbound translation region 0"
|
|
line.long 0x10 "PCIE_IB_BAR1,"
|
|
bitfld.long 0x10 0.--2. "IB_BAR1,BAR number to match for inbound translation region 1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "PCIE_IB_START1_LO,"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "IB_START1_LO,Start address bits [31-8] for inbound translation region 1"
|
|
line.long 0x18 "PCIE_IB_START1_HI,"
|
|
line.long 0x1C "PCIE_IB_OFFSET1,"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "IB_OFFSET1,Offset address bits [31-8] for inbound translation region 1"
|
|
line.long 0x20 "PCIE_IB_BAR2,"
|
|
bitfld.long 0x20 0.--2. "IB_BAR2,BAR number to match for inbound translation region 2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "PCIE_IB_START2_LO,"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "IB_START2_LO,Start address bits [31-8] for inbound translation region 2"
|
|
line.long 0x28 "PCIE_IB_START2_HI,"
|
|
line.long 0x2C "PCIE_IB_OFFSET2,"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "IB_OFFSET2,Offset address bits [31-8] for inbound translation region 2"
|
|
line.long 0x30 "PCIE_IB_BAR3,"
|
|
bitfld.long 0x30 0.--2. "IB_BAR3,BAR number to match for inbound translation region 3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "PCIE_IB_START3_LO,"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "IB_START3_LO,Start address bits [31-8] for inbound translation region 3"
|
|
line.long 0x38 "PCIE_IB_START3_HI,"
|
|
line.long 0x3C "PCIE_IB_OFFSET3,"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "IB_OFFSET3,Offset address bits [31-8] for inbound translation region 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_CAP_EXT_REGS"
|
|
base ad:0x21800000
|
|
rgroup.long 0x1100++0x37
|
|
line.long 0x00 "PCIE_EXTCAP,"
|
|
hexmask.long.word 0x00 20.--31. 1. "NEXT_CAP,Next Capability Pointer"
|
|
bitfld.long 0x00 16.--19. "EXT_CAP_VER,Extended Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "EXT_CAP_ID,PCIe Extended Capability ID"
|
|
line.long 0x04 "PCIE_UNCERR,"
|
|
bitfld.long 0x04 20. "UR_ERR_ST,Unsupported Request Error Status" "0,1"
|
|
bitfld.long 0x04 19. "ECRC_ERR_ST,ECRC Error Status" "0,1"
|
|
bitfld.long 0x04 18. "MTLP_ERR_ST,Malformed TLP Status" "0,1"
|
|
bitfld.long 0x04 17. "RCVR_OF_ST,Receiver Overflow Status" "0,1"
|
|
bitfld.long 0x04 16. "UCMP_ST,Unexpected Completion Status" "0,1"
|
|
bitfld.long 0x04 15. "CMPL_ABRT_ST,Completer Abort Status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 14. "CMPL_TMOT_ST,Completion Timeout Status" "0,1"
|
|
bitfld.long 0x04 13. "FCP_ERR_ST,Flow Control Protocol Error Status" "0,1"
|
|
bitfld.long 0x04 12. "PSND_TLP_ST,Poisoned TLP Status" "0,1"
|
|
rbitfld.long 0x04 5. "SRPS_DN_ST,Surprise Down Error Status" "0,1"
|
|
bitfld.long 0x04 4. "DLP_ERR_ST,Data Link Protocol Error Status" "0,1"
|
|
line.long 0x08 "PCIE_UNCERR_MASK,"
|
|
bitfld.long 0x08 20. "UR_ERR_MSK,Unsupported Request Error Mask" "0,1"
|
|
bitfld.long 0x08 19. "ECRC_ERR_MSK,ECRC Error Mask" "0,1"
|
|
bitfld.long 0x08 18. "MTLP_ERR_MSK,Malformed TLP Mask" "0,1"
|
|
bitfld.long 0x08 17. "RCVR_OF_MSK,Receiver Overflow Mask" "0,1"
|
|
bitfld.long 0x08 16. "UCMP_MSK,Unexpected Completion Mask" "0,1"
|
|
bitfld.long 0x08 15. "CMPL_ABRT_MSK,Completer Abort Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x08 14. "CMPL_TMOT_MSK,Completion Timeout Mask" "0,1"
|
|
bitfld.long 0x08 13. "FCP_ERR_MSK,Flow Control Protocol Error Mask" "0,1"
|
|
bitfld.long 0x08 12. "PSND_TLP_MSK,Poisoned TLP Mask" "0,1"
|
|
rbitfld.long 0x08 5. "SRPS_DN_MSK,Surprise Down Error Mask" "0,1"
|
|
bitfld.long 0x08 4. "DLP_ERR_MSK,Data Link Protocol Error Mask" "0,1"
|
|
line.long 0x0C "PCIE_UNCERR_SVRTY,"
|
|
bitfld.long 0x0C 20. "UR_ERR_SVRTY,Unsupported Request Error Severity" "0,1"
|
|
bitfld.long 0x0C 19. "ECRC_ERR_SVRTY,ECRC Error Severity" "0,1"
|
|
bitfld.long 0x0C 18. "MTLP_ERR_SVRTY,Malformed TLP Severity" "0,1"
|
|
bitfld.long 0x0C 17. "RCVR_OF_SVRTY,Receiver Overflow Severity" "0,1"
|
|
bitfld.long 0x0C 16. "UCMP_SVRTY,Unexpected Completion Severity" "0,1"
|
|
bitfld.long 0x0C 15. "CMPL_ABRT_SVRTY,Completer Abort Severity" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 14. "CMPL_TMOT_SVRTY,Completion Timeout Severity" "0,1"
|
|
bitfld.long 0x0C 13. "FCP_ERR_SVRTY,Flow Control Protocol Error Severity" "0,1"
|
|
bitfld.long 0x0C 12. "PSND_TLP_SVRTY,Poisoned TLP Severity" "0,1"
|
|
rbitfld.long 0x0C 5. "SRPS_DN_SVRTY,Surprise Down Error Severity" "0,1"
|
|
bitfld.long 0x0C 4. "DLP_ERR_SVRTY,Data Link Protocol Error Severity" "0,1"
|
|
line.long 0x10 "PCIE_CERR,"
|
|
bitfld.long 0x10 13. "ADV_NFERR_ST,Advisory Non-Fatal Error Status" "0,1"
|
|
bitfld.long 0x10 12. "RPLY_TMR_ST,Replay Timer Timeout Status" "0,1"
|
|
bitfld.long 0x10 8. "RPLT_RO_ST,REPLAY_NUM Rollover Status" "0,1"
|
|
bitfld.long 0x10 7. "BAD_DLLP_ST,Bad DLLP Status" "0,1"
|
|
bitfld.long 0x10 6. "BAD_TLP_ST,Bad TLP Status" "0,1"
|
|
bitfld.long 0x10 0. "RCVR_ERR_ST,Receiver Error Status" "0,1"
|
|
line.long 0x14 "PCIE_CERR_MASK,"
|
|
bitfld.long 0x14 13. "ADV_NFERR_MSK,Advisory Non Fatal Error MaskThis bit is Set by default to enable compatibility with software that does not comprehend Role-Based Error Reporting" "0,1"
|
|
bitfld.long 0x14 12. "RPLY_TMR_MSK,Reply Timer Timeout Mask" "0,1"
|
|
bitfld.long 0x14 8. "RPLT_RO_MSK,REPLAY_NUM Rollover Mask" "0,1"
|
|
bitfld.long 0x14 7. "BAD_DLLP_MSK,Bad DLLP Mask" "0,1"
|
|
bitfld.long 0x14 6. "BAD_TLP_MSK,Bad TLP Mask" "0,1"
|
|
bitfld.long 0x14 0. "RCVR_ERR_MSK,Receiver Error Mask" "0,1"
|
|
line.long 0x18 "PCIE_ACCR,"
|
|
bitfld.long 0x18 8. "ECRC_CHK_EN,ECRC Check Enable" "0,1"
|
|
rbitfld.long 0x18 7. "ECRC_CHK_CAP,ECRC Check Capable" "0,1"
|
|
bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable" "0,1"
|
|
rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capability" "0,1"
|
|
rbitfld.long 0x18 0.--4. "FRST_ERR_PTR,First Error PointerThe First Error Pointer is a field that identifies the bit position of the first error reported in the Uncorrectable Error Status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "PCIE_HDR_LOG0,"
|
|
line.long 0x20 "PCIE_HDR_LOG1,"
|
|
line.long 0x24 "PCIE_HDR_LOG2,"
|
|
line.long 0x28 "PCIE_HDR_LOG3,"
|
|
line.long 0x2C "PCIE_RC_ERR_CMD,"
|
|
bitfld.long 0x2C 2. "FERR_RPT_EN,Fatal Error Reporting Enable" "0,1"
|
|
bitfld.long 0x2C 1. "NFERR_RPT_EN,Nonfatal Error Reporting Enable" "0,1"
|
|
bitfld.long 0x2C 0. "CERR_RPT_EN,Correctable Error Reporting Enable" "0,1"
|
|
line.long 0x30 "PCIE_RC_ERR_ST,"
|
|
rbitfld.long 0x30 27.--31. "AER_INT_MSG,AER Interrupt Message Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x30 6. "FERR_RCV,Fatal Error Messages Received" "0,1"
|
|
bitfld.long 0x30 5. "NFERR,Non-Fatal Error Messages Received" "0,1"
|
|
bitfld.long 0x30 4. "UNCOR_FATAL,First Uncorrectable Fatal Received" "0,1"
|
|
bitfld.long 0x30 3. "MULT_FNF,Multiple Uncorrectable Error (ERR_FATAL/NONFATAL) Received" "0,1"
|
|
bitfld.long 0x30 2. "ERR_FNF,Uncorrectable Error (ERR_FATAL/NONFATAL) Received" "0,1"
|
|
newline
|
|
bitfld.long 0x30 1. "MULT_COR,Multiple Correctable Error (ERR_COR) Received" "0,1"
|
|
bitfld.long 0x30 0. "CORR_ERR,Correctable Error (ERR_COR) Received" "0,1"
|
|
line.long 0x34 "PCIE_ERR_SRC_ID,"
|
|
hexmask.long.word 0x34 16.--31. 1. "FNF_SRC_ID,Fatal or Non-Fatal error source identification"
|
|
hexmask.long.word 0x34 0.--15. 1. "CORR_SRC_ID,Correctable error source identification"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_CAP_REGS"
|
|
base ad:0x21800000
|
|
rgroup.long 0x1070++0x2B
|
|
line.long 0x00 "PCIE_CAP,"
|
|
bitfld.long 0x00 25.--29. "INT_MSG,Interrupt Message Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. "SLT_IMPL_N,Slot Implemented" "0,1"
|
|
bitfld.long 0x00 20.--23. "DPORT_TYPE,Device Port Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PCIE_CAP,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAP,Next capability pointer"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,PCIe Capability ID"
|
|
line.long 0x04 "PCIE_DEVICE_CAP,"
|
|
bitfld.long 0x04 26.--27. "PWR_LIMIT_SCALE,Captured Slot Power Limit Scale" "0,1,2,3"
|
|
hexmask.long.byte 0x04 18.--25. 1. "PWR_LIMIT_VALUE,Captured Slot Power Limit Value"
|
|
bitfld.long 0x04 15. "ERR_RPT,Role-based Error Reporting" "0,1"
|
|
bitfld.long 0x04 9.--11. "L1_LATENCY,Endpoint L1 Acceptable Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--8. "L0_LATENCY,Endpoint L0s Acceptable Latency" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 5. "EXT_TAG_FLD,Extended Tag Field Supported" "0,1"
|
|
bitfld.long 0x04 3.--4. "PHANTOM_FLD,Phantom Field Supported" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. "MAX_PAYLD_SZ,Maximum Payload size supported" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "PCIE_DEV_STAT_CTRL,"
|
|
rbitfld.long 0x08 21. "TPEND,Transaction Pending" "0,1"
|
|
rbitfld.long 0x08 20. "AUX_PWR,Auxiliary Power Detected" "0,1"
|
|
bitfld.long 0x08 19. "UNSUP_RQ_DET,Unsupported Request Detected" "0,1"
|
|
bitfld.long 0x08 18. "FATAL_ERR,Fatal Error Detected" "0,1"
|
|
bitfld.long 0x08 17. "NFATAL_ERR,Non-fatal Error Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. "CORR_ERR,Correctable Error Detected" "0,1"
|
|
bitfld.long 0x08 12.--14. "MAX_REQ_SZ,Maximum Read Request Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 11. "NO_SNOOP,Enable no snoop" "0,1"
|
|
bitfld.long 0x08 10. "AUX_PWR_PM_EN,AUX Power PM Enable" "0,1"
|
|
bitfld.long 0x08 9. "PHANTOM_EN,Phantom Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "XTAG_FIELD_EN,Extended Tag Field Enable" "0,1"
|
|
bitfld.long 0x08 5.--7. "MAX_PAYLD,Maximum Payload Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 4. "RELAXED,Enable Relaxed Ordering" "0,1"
|
|
bitfld.long 0x08 3. "UNSUP_REQ_RP,Enable Unsupported Request Reporting" "0,1"
|
|
bitfld.long 0x08 2. "FATAL_ERR_RP,Fatal Error Reporting Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "NFATAL_ERR_RP,Non-fatal Error Reporting Enable" "0,1"
|
|
bitfld.long 0x08 0. "CORR_ERR_RP,Correctable Error Reporting Enable" "0,1"
|
|
line.long 0x0C "PCIE_LINK_CAP,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number"
|
|
bitfld.long 0x0C 21. "BW_NOTIFY_CAP,Link Bandwidth Notification Capable" "0,1"
|
|
bitfld.long 0x0C 20. "DLL_REP_CAP,Data Link Layer Active Reporting Capable" "0,1"
|
|
bitfld.long 0x0C 19. "DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable" "0,1"
|
|
bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency when common clock is used" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 12.--14. "LOS_EXIT_LAT,L0s Exit Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 10.--11. "AS_LINK_PM,Active State Link Power Management Support" "0,1,2,3"
|
|
bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Maximum Link Width (xN - corresponding to N Lanes)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 0.--3. "MAX_LINK_SPEED,Maximum Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "PCIE_LINK_STAT_CTRL,"
|
|
bitfld.long 0x10 31. "LINK_BW_STATUS,Link Autonomous Bandwidth Status.This bit is Set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to correct.." "0,1"
|
|
bitfld.long 0x10 30. "LINK_BW_MGMT_STATUS,Link Bandwidth Management Status.This bit is Set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: A Link retraining has completed following a write of 1b to.." "0,1"
|
|
rbitfld.long 0x10 29. "DLL_ACTIVE,Data Link Layer ActiveThis bit indicates the status of the Data Link Control and Management State Machine" "0,1"
|
|
rbitfld.long 0x10 28. "SLOT_CLK_CFG,Slot Clock Configuration" "0,1"
|
|
rbitfld.long 0x10 27. "LINK_TRAINING,Link Training" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 20.--25. "NEGOTIATED_LINK_WD,Negotiated Link Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x10 11. "LINK_BW_INT_EN,Link Autonomous Bandwidth Interrupt Enable" "0,1"
|
|
rbitfld.long 0x10 10. "LINK_BW_MGMT_INT_EN,Link Bandwidth Management Interrupt Enable" "0,1"
|
|
rbitfld.long 0x10 9. "HW_AUTO_WIDTH_DIS,Hardware Autonomous Width Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "CLK_PWR_MGMT_EN,Enable Clock Power Management" "0,1"
|
|
bitfld.long 0x10 7. "EXT_SYNC,Extended Synchronization" "0,1"
|
|
bitfld.long 0x10 6. "COMMON_CLK_CFG,Common Clock Configuration" "0,1"
|
|
bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1"
|
|
bitfld.long 0x10 4. "LINK_DISABLE,This bit disables the link by directing the LTSSM to the Disabled state when set" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 3. "RCB,Read Completion Boundary" "0,1"
|
|
bitfld.long 0x10 0.--1. "ACTIVE_LINK_PM,Active State Link Power Management Control" "0,1,2,3"
|
|
line.long 0x14 "PCIE_SLOT_CAP,"
|
|
hexmask.long.word 0x14 19.--31. 1. "SLOT_NUM,Physical Slot Number"
|
|
bitfld.long 0x14 18. "CMD_COMP_SUPP,No Command Complete Support" "0,1"
|
|
bitfld.long 0x14 17. "EML_PRESENT,Electromechanical Interlock Present" "0,1"
|
|
bitfld.long 0x14 15.--16. "PWR_LMT_SCALE,Slot Power Limit Scale" "0,1,2,3"
|
|
hexmask.long.byte 0x14 7.--14. 1. "PWR_LMT_VALUE,Slow Power Limit Value"
|
|
newline
|
|
bitfld.long 0x14 6. "HP_CAP,Hot Plug Capable" "0,1"
|
|
bitfld.long 0x14 5. "HP_SURPRISE,Hot Plug Surprise" "0,1"
|
|
bitfld.long 0x14 4. "PWR_IND,Power Indicator Present" "0,1"
|
|
bitfld.long 0x14 3. "ATTN_IND,Attention Indicator Present" "0,1"
|
|
bitfld.long 0x14 2. "MRL_SENSOR,MRL Sensor Present" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "PWR_CTL,Power Controller Present" "0,1"
|
|
bitfld.long 0x14 0. "ATTN_BUTTON,Attention Indicator Present" "0,1"
|
|
line.long 0x18 "PCIE_SLOT_STAT_CTRL,"
|
|
bitfld.long 0x18 24. "DLL_STATE,Data Link Layer State Changed" "0,1"
|
|
rbitfld.long 0x18 23. "EM_LOCK,Electromechanical Lock Status" "0,1"
|
|
rbitfld.long 0x18 22. "PRESENCE_DET,Presence Detect State" "0,1"
|
|
rbitfld.long 0x18 21. "MRL_STATE,MRL Sensor State" "0,1"
|
|
bitfld.long 0x18 20. "CMD_COMLETE,Command Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "PRESENCE_CHG,Presence Detect Changed" "0,1"
|
|
bitfld.long 0x18 18. "MRL_CHANGE,MRL Sensor Changed" "0,1"
|
|
bitfld.long 0x18 17. "PWR_FAULT,Power Fault Detected" "0,1"
|
|
bitfld.long 0x18 16. "ATTN_PRESSED,Attention Button Pressed" "0,1"
|
|
bitfld.long 0x18 12. "DLL_CHG_EN,Data Link Layer State Changed Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "EM_LOCK_CTL,Electromechanical Interlock Control" "0,1"
|
|
bitfld.long 0x18 10. "PM_CTL,Power Controller Control" "0,1"
|
|
bitfld.long 0x18 8.--9. "PM_IND_CTL,Power Indicator Control" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "ATTN_IND_CTL,Attention Indicator Control" "0,1,2,3"
|
|
bitfld.long 0x18 5. "HP_INT_EN,Hot Plug Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "CMD_CMP_INT_EN,Command Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 3. "PRS_DET_CHG_EN,Presence Detect Changed Enable" "0,1"
|
|
bitfld.long 0x18 2. "MRL_CHG_EN,MRL Sensor Changed Enable" "0,1"
|
|
bitfld.long 0x18 1. "PWR_FLT_DET_EN,Power Fault Detected Enable" "0,1"
|
|
bitfld.long 0x18 0. "ATTN_BUTT_EN,Attention Button Pressed Enable" "0,1"
|
|
line.long 0x1C "PCIE_ROOT_CTRL_CAP,"
|
|
rbitfld.long 0x1C 16. "CRS_SW,CRS Software Visibility" "0,1"
|
|
rbitfld.long 0x1C 4. "CRS_SW_EN,CRS Software Visibility Enable" "0,1"
|
|
bitfld.long 0x1C 3. "PME_INT_EN,PME Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 2. "SERR_FATAL_ERR,System Error on Fatal Error Enable" "0,1"
|
|
bitfld.long 0x1C 1. "SERR_NFATAL_ERR,System Error on Non-fatal Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "SERR_EN,System Error on Correctable Error Enable" "0,1"
|
|
line.long 0x20 "PCIE_ROOT_STATUS,"
|
|
rbitfld.long 0x20 17. "PME_PEND,Indicates that another PME is pending when the PME Status bit is Set" "0,1"
|
|
bitfld.long 0x20 16. "PME_STATUS,Indicates that PME was asserted by the PME Requester" "0,1"
|
|
hexmask.long.word 0x20 0.--15. 1. "PME_REQ_ID,ID of the last PME Requester.This field is only valid when the PME Status bit is Set"
|
|
line.long 0x24 "PCIE_DEV_CAP2,"
|
|
bitfld.long 0x24 4. "CMPL_TO_DIS_SUPP,Completion timeout disable supported" "0,1"
|
|
bitfld.long 0x24 0.--3. "CMPL_TO_EN,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "PCIE_DEV_STAT_CTRL2,"
|
|
bitfld.long 0x28 4. "CMPL_TO_DIS,Completion timeout disable" "0,1"
|
|
bitfld.long 0x28 0.--3. "CMPL_TO,Completion timeout value.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PCIE_LINK_CTRL2,"
|
|
rbitfld.long 0x00 16. "DE_EMPH,Current De-emphasis level" "0,1"
|
|
bitfld.long 0x00 12. "POLL_DEEMPH,De-emphasis level in polling-compliance stateThis bit sets the de-emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1" "0,1"
|
|
bitfld.long 0x00 11. "CMPL_SOS,Compliance SOS.When this bit is set to 1 the LTSSM is required to send SKP Ordered Sets periodically in between the modified compliance patterns" "0,1"
|
|
bitfld.long 0x00 10. "ENTR_MOD_COMPL,Enter modified compliance.When this bit is set to 1 the device transmits Modified Compliance Pattern if the LTSSM enters Polling Compliance substate" "0,1"
|
|
bitfld.long 0x00 7.--9. "TX_MARGIN,Value of non-de-emphasized voltage level at transmitter pins" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6. "SEL_DEEMPH,Selectable De-emphasis.When the Link is operating at 5.0 GT/s speed this bit selects the level of de-emphasis for an upstream component" "0,1"
|
|
bitfld.long 0x00 5. "HW_AUTO_SPEED_DIS,Hardware Autonomous Speed Disable" "0,1"
|
|
bitfld.long 0x00 4. "ENTR_COMPL,Enter Compliance.Software is permitted to force a Link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1 in both components on a Link and then initiating a hot reset on the Link" "0,1"
|
|
bitfld.long 0x00 0.--3. "TGT_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_CFG"
|
|
base ad:0x21800000
|
|
rgroup.long 0x1000++0x0B
|
|
line.long 0x00 "PCIE_VENDOR_DEVICE_ID,"
|
|
line.long 0x04 "PCIE_STATUS_COMMAND,"
|
|
bitfld.long 0x04 31. "PARITY_ERROR,Set if function receives poisoned TLP" "0,1"
|
|
bitfld.long 0x04 30. "SIG_SYS_ERROR,Set if function sends an ERR_FATAL or ERR_NONFATAL message and SERR enable bit is set to one" "0,1"
|
|
bitfld.long 0x04 29. "RX_MST_ABORT,Set when a requester receives a completion with unsupported request completion status" "0,1"
|
|
bitfld.long 0x04 28. "RX_TGT_ABORT,Set when a requester receives a completion with completer abort status" "0,1"
|
|
bitfld.long 0x04 27. "SIG_TGT_ABORT,Set when a function acting as a completer terminates a request by issuing completer abort completion status to the requester" "0,1"
|
|
bitfld.long 0x04 24. "DAT_PAR_ERROR,This bit is set by a requester if the Parity Error Enable bit is set in its Command register and either the condition that the requester receives a poisoned completion or the condition that the requester poisons a write request is true" "0,1"
|
|
rbitfld.long 0x04 20. "CAP_LIST,For PCIe this field must be set to 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 19. "INT_STAT,Indicates that the function has received an interrupt" "0,1"
|
|
bitfld.long 0x04 10. "INTX_DIS,Setting this bit disables generation of INTx messages" "0,1"
|
|
bitfld.long 0x04 8. "SERR_EN,When set it enables generation of the appropriate PCI Express error messages to the Root Complex" "0,1"
|
|
bitfld.long 0x04 6. "PAR_ERR_RESP,This bit controls whether or not the device responds to detected parity errors (poisoned TLP)" "0,1"
|
|
bitfld.long 0x04 2. "BUS_MS,Enables mastership of the bus" "0,1"
|
|
bitfld.long 0x04 1. "MEM_SP,This bit is set to enable the device to respond to memory accesses" "0,1"
|
|
bitfld.long 0x04 0. "IO_SP,This bit is set to enable the device to respond to I/O accesses" "0,1"
|
|
line.long 0x08 "PCIE_CLASSCODE_REVID,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_CFG_TYPE0"
|
|
base ad:0x21800000
|
|
group.long 0x100C++0x07
|
|
line.long 0x00 "PCIE_BIST_HEADER,"
|
|
rbitfld.long 0x00 31. "BIST_CAP,Returns a one for BIST capability and zero otherwise" "0,1"
|
|
rbitfld.long 0x00 30. "START_BIST,Write a one to start BIST" "0,1"
|
|
rbitfld.long 0x00 24.--27. "COMP_CODE,Completion code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 23. "MULFUN_DEV,Returns 1 if it is a multi-function device" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "HDR_TYPE,Configuration header format"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LAT_TMR,Not applicable in PCIe"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CACHELN_SIZ,Not applicable in PCIe"
|
|
line.long 0x04 "PCIE_BAR0,"
|
|
hexmask.long 0x04 4.--31. 1. "BASE_ADDR,Base Address"
|
|
rbitfld.long 0x04 3. "PREFETCH,For memory BARs it indicates whether the region is prefetchable" "0,1"
|
|
rbitfld.long 0x04 1.--2. "TYPE,For memory BARs they determine the BAR type" "0,1,2,3"
|
|
rbitfld.long 0x04 0. "MEM_SPACE,Writable from internal bus interface" "0,1"
|
|
group.long 0x1010++0x07
|
|
line.long 0x00 "PCIE_BAR0_MASK,"
|
|
hexmask.long 0x00 1.--31. 1. "BAR_MASK,Indicates whichPCIE_BAR0 bits to mask (non-writeable) from host which determines the size of the BAR"
|
|
bitfld.long 0x00 0. "BAR_ENABLED,PCIE_BAR0 Enable" "0,1"
|
|
line.long 0x04 "PCIE_BAR1,"
|
|
hexmask.long 0x04 4.--31. 1. "BASE_ADDR,Base Address"
|
|
rbitfld.long 0x04 3. "PREFETCH,For memory BARs it indicates whether the region is prefetchable" "0,1"
|
|
rbitfld.long 0x04 1.--2. "TYPE,For memory BARs they determine the BAR type" "0,1,2,3"
|
|
rbitfld.long 0x04 0. "MEM_SPACE,Writable from internal bus interface" "0,1"
|
|
group.long 0x1014++0x07
|
|
line.long 0x00 "PCIE_BAR1_MASK,"
|
|
hexmask.long 0x00 1.--31. 1. "BAR_MASK,Indicates whichPCIE_BAR1 bits to mask (non-writeable) from host which determines the size of the BAR"
|
|
bitfld.long 0x00 0. "BAR_ENABLED,PCIE_BAR1 Enable" "0,1"
|
|
line.long 0x04 "PCIE_BAR2,"
|
|
hexmask.long 0x04 4.--31. 1. "BASE_ADDR,Base Address"
|
|
rbitfld.long 0x04 3. "PREFETCH,For memory BARs it indicates whether the region is prefetchable" "0,1"
|
|
rbitfld.long 0x04 1.--2. "TYPE,For memory BARs they determine the BAR type" "0,1,2,3"
|
|
rbitfld.long 0x04 0. "MEM_SPACE,Writable from internal bus interface" "0,1"
|
|
group.long 0x1018++0x07
|
|
line.long 0x00 "PCIE_BAR2_MASK,"
|
|
hexmask.long 0x00 1.--31. 1. "BAR_MASK,Indicates whichPCIE_BAR2 bits to mask (non-writeable) from host which determines the size of the BAR"
|
|
bitfld.long 0x00 0. "BAR_ENABLED,PCIE_BAR2 Enable" "0,1"
|
|
line.long 0x04 "PCIE_BAR3,"
|
|
hexmask.long 0x04 4.--31. 1. "BASE_ADDR,Base Address"
|
|
rbitfld.long 0x04 3. "PREFETCH,For memory BARs it indicates whether the region is prefetchable" "0,1"
|
|
rbitfld.long 0x04 1.--2. "TYPE,For memory BARs they determine the BAR type" "0,1,2,3"
|
|
rbitfld.long 0x04 0. "MEM_SPACE,Writable from internal bus interface" "0,1"
|
|
group.long 0x101C++0x07
|
|
line.long 0x00 "PCIE_BAR3_MASK,"
|
|
hexmask.long 0x00 1.--31. 1. "BAR_MASK,Indicates whichPCIE_BAR3 bits to mask (non-writeable) from host which determines the size of the BAR"
|
|
bitfld.long 0x00 0. "BAR_ENABLED,PCIE_BAR3 Enable" "0,1"
|
|
line.long 0x04 "PCIE_BAR4,"
|
|
hexmask.long 0x04 4.--31. 1. "BASE_ADDR,Base Address"
|
|
rbitfld.long 0x04 3. "PREFETCH,For memory BARs it indicates whether the region is prefetchable" "0,1"
|
|
rbitfld.long 0x04 1.--2. "TYPE,For memory BARs they determine the BAR type" "0,1,2,3"
|
|
rbitfld.long 0x04 0. "MEM_SPACE,Writable from internal bus interface" "0,1"
|
|
group.long 0x1020++0x07
|
|
line.long 0x00 "PCIE_BAR4_MASK,"
|
|
hexmask.long 0x00 1.--31. 1. "BAR_MASK,Indicates whichPCIE_BAR4 bits to mask (non-writeable) from host which determines the size of the BAR"
|
|
bitfld.long 0x00 0. "BAR_ENABLED,PCIE_BAR4 Enable" "0,1"
|
|
line.long 0x04 "PCIE_BAR5,"
|
|
hexmask.long 0x04 4.--31. 1. "BASE_ADDR,Base Address"
|
|
rbitfld.long 0x04 3. "PREFETCH,For memory BARs it indicates whether the region is prefetchable" "0,1"
|
|
rbitfld.long 0x04 1.--2. "TYPE,For memory BARs they determine the BAR type" "0,1,2,3"
|
|
rbitfld.long 0x04 0. "MEM_SPACE,Writable from internal bus interface" "0,1"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "PCIE_BAR5_MASK,"
|
|
hexmask.long 0x00 1.--31. 1. "BAR_MASK,Indicates whichPCIE_BAR5 bits to mask (non-writeable) from host which determines the size of the BAR"
|
|
bitfld.long 0x00 0. "BAR_ENABLED,PCIE_BAR5 Enable" "0,1"
|
|
rgroup.long 0x102C++0x0B
|
|
line.long 0x00 "PCIE_SUBSYS_VNDR_ID,"
|
|
line.long 0x04 "PCIE_EXPNSN_ROM,"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "EXP_ROM_BASE_ADDR,Address of Expansion ROM"
|
|
bitfld.long 0x04 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1"
|
|
line.long 0x08 "PCIE_CAP_PTR,"
|
|
hexmask.long.byte 0x08 0.--7. 1. "CAP_PTR,First Capability Pointer"
|
|
group.long 0x103C++0x03
|
|
line.long 0x00 "PCIE_INT_PIN,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAX_LATENCY,Not applicable to PCI Express"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MIN_GRANT,Not applicable to PCI Express"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INT_LINE,Interrupt Line"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_CFG_TYPE1"
|
|
base ad:0x21800000
|
|
group.long 0x1018++0x1B
|
|
line.long 0x00 "PCIE_BUSNUM,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SEC_LAT_TMR,Secondary Latency Timer"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SUB_BUS_NUM,Subordinate Bus Number"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_BUS_NUM,Primary Bus Number"
|
|
line.long 0x04 "PCIE_SECSTAT,"
|
|
bitfld.long 0x04 31. "DTCT_PERROR,Detected Parity Error" "0,1"
|
|
bitfld.long 0x04 30. "RX_SYS_ERROR,Received System Error" "0,1"
|
|
bitfld.long 0x04 29. "RX_MST_ABORT,Received Master Abort" "0,1"
|
|
bitfld.long 0x04 28. "RX_TGT_ABORT,Received Target Abort" "0,1"
|
|
bitfld.long 0x04 27. "TX_TGT_ABORT,Signaled Target Abort" "0,1"
|
|
bitfld.long 0x04 24. "MST_DPERR,Master Data Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12.--15. "IO_LIMIT,Upper 4 bits of 16bit IO Space Limit Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 8. "IO_LIMIT_ADDR,Indicates addressing for IO Limit Address" "0,1"
|
|
bitfld.long 0x04 4.--7. "IO_BASE,Upper 4 bits of 16bit IO Space Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 0. "IO_BASE_ADDR,Indicates addressing for the IO Base Address" "0,1"
|
|
line.long 0x08 "PCIE_MEMSPACE,"
|
|
hexmask.long.word 0x08 20.--31. 1. "MEM_LIMIT,Upper 12 bits of 32bit Memory Limit Address"
|
|
hexmask.long.word 0x08 4.--15. 1. "MEM_BASE,Upper 12 bits of 32bit Memory Base Address"
|
|
line.long 0x0C "PCIE_PREFETCH_MEM,"
|
|
hexmask.long.word 0x0C 20.--31. 1. "PREFETCH_LIMIT,Upper 12 bits of 32bit prefetchable memory limit address (end address)"
|
|
rbitfld.long 0x0C 16. "PRE_LIMIT_ADDR,Indicates addressing for prefetchable memory limit address (end address)" "0,1"
|
|
hexmask.long.word 0x0C 4.--15. 1. "PREFETCH_BASE,Upper 12 bits of 32bit prefetchable memory base address (start address)"
|
|
rbitfld.long 0x0C 0. "PRE_BASE_ADDR,Indicates addressing for the prefetchable memory base address (start address)" "0,1"
|
|
line.long 0x10 "PCIE_PREFETCH_BASE,"
|
|
line.long 0x14 "PCIE_PREFETCH_LIMIT,"
|
|
line.long 0x18 "PCIE_IOSPACE,"
|
|
hexmask.long.word 0x18 16.--31. 1. "IOBASE,Upper 16 bits of IO Base Address"
|
|
hexmask.long.word 0x18 0.--15. 1. "IOLIMIT,Upper 16 bits of IO Limit Address"
|
|
group.long 0x103C++0x03
|
|
line.long 0x00 "PCIE_BRIDGE_INT,"
|
|
rbitfld.long 0x00 27. "SERREN_STATUS,Discard Timer SERR Enable Status" "0,1"
|
|
rbitfld.long 0x00 26. "TIMER_STATUS,Discard Timer Status" "0,1"
|
|
rbitfld.long 0x00 25. "SEC_TIMER,Secondary Discard Timer" "0,1"
|
|
rbitfld.long 0x00 24. "PRI_TIMER,Primary Discard Timer" "0,1"
|
|
rbitfld.long 0x00 23. "B2B_EN,Fast Back to Back Transactions Enable" "0,1"
|
|
bitfld.long 0x00 22. "SEC_BUS_RST,Secondary Bus Reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 21. "MST_ABORT_MODE,Master Abort Mode" "0,1"
|
|
bitfld.long 0x00 20. "VGA_DECODE,VGA 16 bit Decode" "0,1"
|
|
bitfld.long 0x00 19. "VGA_EN,VGA Enable" "0,1"
|
|
bitfld.long 0x00 18. "ISA_EN,ISA Enable" "0,1"
|
|
bitfld.long 0x00 17. "SERR_EN,SERR Enable" "0,1"
|
|
bitfld.long 0x00 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INT_LINE,Interrupt Line"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_MSG_IRQ_REGS"
|
|
base ad:0x21800000
|
|
group.long 0x1050++0x0F
|
|
line.long 0x00 "PCIE_MSI_CAP,"
|
|
rbitfld.long 0x00 23. "_64BIT_EN,64-bit addressing enabled" "0,1"
|
|
bitfld.long 0x00 20.--22. "MULT_MSG_EN,Multiple message enabled" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 17.--19. "MULT_MSG_CAP,Multiple message capable" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "MSI_EN,MSI Enabled" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAP,Next capability pointer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,MSI Capability ID"
|
|
line.long 0x04 "PCIE_MSI_LOW32,"
|
|
line.long 0x08 "PCIE_MSI_UP32,"
|
|
line.long 0x0C "PCIE_MSI_DATA,"
|
|
hexmask.long.word 0x0C 0.--15. 1. "MSI_DATA,MSI Data"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_PORT_LOGIC_REGS"
|
|
base ad:0x21800000
|
|
group.long 0x1700++0x23
|
|
line.long 0x00 "PCIE_PL_ACKTIMER,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RPLY_LIMT,Replay Time Limit"
|
|
hexmask.long.word 0x00 0.--15. 1. "RND_TRP_LMT,Round Trip Latency Time Limit"
|
|
line.long 0x04 "PCIE_PL_OMSG,"
|
|
line.long 0x08 "PCIE_PL_FORCE_LINK,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "LPE_CNT,Low Power Entrance Count"
|
|
bitfld.long 0x08 16.--21. "LINK_STATE,Link State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 15. "FORCE_LINK,Force Link" "0,1"
|
|
hexmask.long.byte 0x08 0.--7. 1. "LINK_NUM,Link Number"
|
|
line.long 0x0C "PCIE_ACK_FREQ,"
|
|
bitfld.long 0x0C 30. "ASPM_L1,Set to allow entering ASPM L1 even when link partner did not to L0s" "0,1"
|
|
bitfld.long 0x0C 27.--29. "L1_ENTRY_LATENCY,L1 entrance latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 24.--26. "L0S_ENTRY_LATENCY,L0s entrance latency" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "COMM_NFTS,Number of fast training sequences when common clock is used and when transitioning from L0s to L0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "NFTS,Number of fast training sequences to be transmitted when transitioning from L0s to L0"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "ACK_FREQ,Ack Frequency"
|
|
line.long 0x10 "PCIE_PL_LINK_CTRL,"
|
|
bitfld.long 0x10 16.--21. "LNK_MODE,Link Mode Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 8.--11. "LINK_RATE,Default link rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 7. "FLNK_MODE,Fast link mode" "0,1"
|
|
bitfld.long 0x10 5. "DLL_EN,DLL Link Enable" "0,1"
|
|
bitfld.long 0x10 3. "RST_ASRT,Reset assert" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "LPBK_EN,Loopback Enable" "0,1"
|
|
bitfld.long 0x10 1. "SCRM_DIS,Scramble Disable" "0,1"
|
|
bitfld.long 0x10 0. "OMSG_REQ,Other message request" "0,1"
|
|
line.long 0x14 "PCIE_LANE_SKEW,"
|
|
bitfld.long 0x14 31. "L2L_DESKEW,Disable Lane to Lane Deskew" "0,1"
|
|
bitfld.long 0x14 25. "ACK_DISABLE,Disable Ack and Nak DLLP transmission" "0,1"
|
|
bitfld.long 0x14 24. "FC_DISABLE,Flow Control Disable" "0,1"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "LANE_SKEW,Insert Lane Skew for Transmit"
|
|
line.long 0x18 "PCIE_SYM_NUM,"
|
|
bitfld.long 0x18 29.--31. "MAX_FUNC,Configuration requests targeted at function numbers above this value will result in UR response" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 24.--28. "FCWATCH_TIMER,Timer Modifier for Flow Control Watchdog Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 19.--23. "ACK_LATENCY_TIMER,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 14.--18. "REPLAY_TIMER,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 8.--10. "SKP_COUNT,Number of SKP Symbols" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 4.--7. "NUM_TS2_SYMBOLS,Number of TS2 Symbols" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. "TS_COUNT,Number of TS Symbols" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "PCIE_SYMTIMER_FLTMASK,"
|
|
bitfld.long 0x1C 31. "F1_CFG_DROP,Set to allow CFG TLPs on RC" "0,1"
|
|
bitfld.long 0x1C 30. "F1_IO_DROP,Set to allow IO TLPs on RC" "0,1"
|
|
bitfld.long 0x1C 29. "F1_MSG_DROP,Set to allow MSG TLPs on RC" "0,1"
|
|
bitfld.long 0x1C 28. "F1_CPL_ECRC_DROP,Set to allow Completion TLPs with ECRC to pass up" "0,1"
|
|
bitfld.long 0x1C 27. "F1_ECRC_DROP,Set to allow TLPs with ECRC error to pass up" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 26. "F1_CPL_LEN_TEST,Set to mask length match for received completion TLPs" "0,1"
|
|
bitfld.long 0x1C 25. "F1_CPL_ATTR_TEST,Set to mask attribute match on received completion TLPs" "0,1"
|
|
bitfld.long 0x1C 24. "F1_CPL_TC_TEST,Set to mask traffic match on received completion TLPs" "0,1"
|
|
bitfld.long 0x1C 23. "F1_CPL_FUNC_TEST,Set to mask function match on received completion TLPs" "0,1"
|
|
bitfld.long 0x1C 22. "F1_CPL_REQID_TEST,Set to mask request ID match on received completion TLPs" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 21. "F1_CPL_TAGERR_TEST,Set to mask tag error rules for received completion TLPs" "0,1"
|
|
bitfld.long 0x1C 20. "F1_LOCKED_RD_AS_UR,Set to treat locked read TLPs as supported for EP UR for RC" "0,1"
|
|
bitfld.long 0x1C 19. "F1_CFG1_RE_AS_US,Set to treat type 1 CFG TLPs as supported for EP UR for RC" "0,1"
|
|
bitfld.long 0x1C 18. "F1_UR_OUT_OF_BAR,Set to treat out-of-BAR TLPs as supported requests" "0,1"
|
|
bitfld.long 0x1C 17. "F1_UR_POISON,Set to treat poisoned TLPs as supported requests" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 16. "F1_UR_FUN_MISMATCH,Set to treat function mismatched TLPs as supported requests" "0,1"
|
|
bitfld.long 0x1C 15. "FC_WDOG_DISABLE,Set to disable FC watchdog timer" "0,1"
|
|
hexmask.long.word 0x1C 0.--10. 1. "SKP_VALUE,Number of symbol times to wait between transmitting SKP ordered sets"
|
|
line.long 0x20 "PCIE_FLT_MASK2,"
|
|
bitfld.long 0x20 3. "FLUSH_REQ,Set to enable the filter to handle flush request" "0,1"
|
|
bitfld.long 0x20 2. "DLLP_ABORT,Set to disable DLLP abort for unexpected CPL" "0,1"
|
|
bitfld.long 0x20 1. "VMSG1_DROP,Set to disable dropping of Vendor MSG Type 1" "0,1"
|
|
bitfld.long 0x20 0. "VMSG0_DROP,Set to disable dropping of Vendor MSG Type 0 with UR reporting" "0,1"
|
|
rgroup.long 0x1728++0x07
|
|
line.long 0x00 "PCIE_DEBUG0,"
|
|
bitfld.long 0x00 28.--31. "TS_LINK_CTRL,Link control bits advertised by link partner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "TS_LANE_K237,Currently receiving k237 (PAD) in place of lane number" "0,1"
|
|
bitfld.long 0x00 26. "TS_LINK_K237,Currently receiving k237 (PAD) in place of link number" "0,1"
|
|
bitfld.long 0x00 25. "RCVD_IDLE0,Receiver is receiving logical idle" "0,1"
|
|
bitfld.long 0x00 24. "RCVD_IDLE1,2nd symbol is also idle (16bit PHY interface only)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 8.--23. 1. "PIPE_TXDATA,PIPE Transmit data"
|
|
bitfld.long 0x00 6.--7. "PIPE_TXDATAK,PIPE transmit K indication" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TXB_SKIP_TX,A skip ordered set has been transmitted" "0,1"
|
|
bitfld.long 0x00 0.--4. "LTSSM_STATE,LTSSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "PCIE_DEBUG1,"
|
|
bitfld.long 0x04 31. "SCRAMBLER_DISABLE,Scrambling disabled for the link" "0,1"
|
|
bitfld.long 0x04 30. "LINK_DISABLE,LTSSM in DISABLE state" "0,1"
|
|
bitfld.long 0x04 29. "LINK_IN_TRAINING,LTSSM performing link training" "0,1"
|
|
bitfld.long 0x04 28. "RCVR_REVRS_POL_EN,LTSSM testing for polarity reversal" "0,1"
|
|
bitfld.long 0x04 27. "TRAINING_RST_N,LTSSM-negotiated link reset" "0,1"
|
|
newline
|
|
bitfld.long 0x04 22. "PIPE_TXDETECTRX_LB,PIPE receiver detect/loopback request" "0,1"
|
|
bitfld.long 0x04 21. "PIPE_TXELECIDLE,PIPE transmit electrical idle request" "0,1"
|
|
bitfld.long 0x04 20. "PIPE_TXCOMPLIANCE,PIPE transmit compliance request" "0,1"
|
|
bitfld.long 0x04 19. "APP_INIT_RST,Application request to initiate training reset" "0,1"
|
|
hexmask.long.byte 0x04 8.--15. 1. "RMLH_TS_LINK_NUM,Link number advertised/confirmed by link partner"
|
|
newline
|
|
bitfld.long 0x04 4. "XMLH_LINK_UP,LTSSM reports PHY link up" "0,1"
|
|
bitfld.long 0x04 3. "RMLH_INSKIP_RCV,Receiver reports skip reception" "0,1"
|
|
bitfld.long 0x04 2. "RMLH_TS1_RCVD,TS1 training sequence received (pulse)" "0,1"
|
|
bitfld.long 0x04 1. "RMLH_TS2_RCVD,TS2 training sequence received (pulse)" "0,1"
|
|
bitfld.long 0x04 0. "RMLH_RCVD_LANE_REV,Receiver detected lane reversal" "0,1"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "PCIE_PL_GEN2,"
|
|
bitfld.long 0x00 20. "DEEMPH,Set de-emphasis level for upstream ports (EP ports)" "0,1"
|
|
bitfld.long 0x00 19. "CFG_TX_CMPL,Configure TX compliance receive bit" "0,1"
|
|
bitfld.long 0x00 18. "CFG_TX_SWING,Configure PHY TX Swing" "0,1"
|
|
bitfld.long 0x00 17. "DIR_SPD,Directed Speed Change" "0,1"
|
|
hexmask.long.word 0x00 8.--16. 1. "LN_EN,Lane Enable"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "NUM_FTS,Number of fast training sequences"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIE_PWR_REGS"
|
|
base ad:0x21800000
|
|
rgroup.long 0x1040++0x07
|
|
line.long 0x00 "PCIE_PMCAP,"
|
|
bitfld.long 0x00 27.--31. "PME_SUPP_N,PME Support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "D2_SUPP_N,D2 Support" "0,1"
|
|
bitfld.long 0x00 25. "D1_SUPP_N,D1 Support" "0,1"
|
|
bitfld.long 0x00 22.--24. "AUX_CURR_N,Auxiliary Current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "DSI_N,Device Specific Initialization" "0,1"
|
|
bitfld.long 0x00 19. "PME_CLK,PME Clock" "0,1"
|
|
bitfld.long 0x00 16.--18. "PME_SPEC_VER,Power Management Specification Version" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PM_NEXT_PTR,Next capability pointer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PM_CAP_ID,Power Management Capability ID"
|
|
line.long 0x04 "PCIE_PM_CTL_STAT,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "DATA_REG,Data register for additional information"
|
|
rbitfld.long 0x04 23. "CLK_CTRL_EN,Bus Power/Clock Control Enable" "0,1"
|
|
rbitfld.long 0x04 22. "B2_B3_SUPPORT,B2 and B3 support" "0,1"
|
|
bitfld.long 0x04 15. "PME_STATUS,PME Status" "0,1"
|
|
rbitfld.long 0x04 13.--14. "DATA_SCALE,Data Scale" "0,1,2,3"
|
|
rbitfld.long 0x04 9.--12. "DATA_SELECT,Data Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8. "PME_EN,PME Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 3. "NO_SOFT_RST,No Soft Reset" "0,1"
|
|
bitfld.long 0x04 0.--1. "PWR_STATE,Power State" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PSC"
|
|
base ad:0x2350000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PID,"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PTCMD,"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "PTSTAT,"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "PDSTAT16,"
|
|
bitfld.long 0x00 0.--1. "STATE,Power domain status" "0,1,2,3"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "PDCTL16,"
|
|
bitfld.long 0x00 0. "NEXT,Default value after reset: ON domain -1; OFF domains -0" "0,1"
|
|
repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0xA40)++0x03
|
|
line.long 0x00 "MDCTL$1,"
|
|
bitfld.long 0x00 12. "RESETISO,Reset isolation" "0,1"
|
|
bitfld.long 0x00 8. "LRST,Module local reset control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "NEXT,Default value after reset: DSP domain and Never-Gated domain -0x3; other domains -0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xA00)++0x03
|
|
line.long 0x00 "MDCTL$1,"
|
|
bitfld.long 0x00 12. "RESETISO,Reset isolation" "0,1"
|
|
bitfld.long 0x00 8. "LRST,Module local reset control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "NEXT,Default value after reset: DSP domain and Never-Gated domain -0x3; other domains -0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
rgroup.long ($2+0x840)++0x03
|
|
line.long 0x00 "MDSTAT$1,"
|
|
bitfld.long 0x00 12. "MCKOUT,Default value after reset: DSP domain and Never-Gated domain -1; other domains -0" "0,1"
|
|
bitfld.long 0x00 11. "MRSTDONE,Module reset done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "MRST,Module reset status" "0,1"
|
|
bitfld.long 0x00 9. "LRSTDONE,Default value after reset: DSP domain -0; other domains -1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "LRST,Module local reset status" "0,1"
|
|
bitfld.long 0x00 0.--5. "STATE,Default value after reset: DSP domain and Never-Gated domain -0x3; other domains -0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x800)++0x03
|
|
line.long 0x00 "MDSTAT$1,"
|
|
bitfld.long 0x00 12. "MCKOUT,Default value after reset: DSP domain and Never-Gated domain -1; other domains -0" "0,1"
|
|
bitfld.long 0x00 11. "MRSTDONE,Module reset done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "MRST,Module reset status" "0,1"
|
|
bitfld.long 0x00 9. "LRSTDONE,Default value after reset: DSP domain -0; other domains -1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "LRST,Module local reset status" "0,1"
|
|
bitfld.long 0x00 0.--5. "STATE,Default value after reset: DSP domain and Never-Gated domain -0x3; other domains -0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "PDCTL$1,"
|
|
bitfld.long 0x00 0. "NEXT,Default value after reset: ON domain -1; OFF domains -0" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x200)++0x03
|
|
line.long 0x00 "PDSTAT$1,"
|
|
bitfld.long 0x00 0.--1. "STATE,Power domain status" "0,1,2,3"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "QSPI"
|
|
base ad:0x2940000
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "QSPI_CONFIG_REG,"
|
|
rbitfld.long 0x00 31. "QSPI_IDLE_FLD,Serial interface and QSPI pipeline is IDLE" "0,1"
|
|
bitfld.long 0x00 19.--22. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor (2 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately" "0,1"
|
|
bitfld.long 0x00 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping (Direct Access Mode Only)" "0,1"
|
|
bitfld.long 0x00 10.--13. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines:else ss[3:0] directly drives n_ss_out[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode" "0,1"
|
|
bitfld.long 0x00 8. "ENB_LEGACY_IP_MODE_FLD,Legacy QSPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller" "0,1"
|
|
bitfld.long 0x00 2. "SEL_CLK_PHASE_FLD,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word" "0,1"
|
|
bitfld.long 0x00 0. "ENB_QSPI_FLD,QSPI Enable" "0,1"
|
|
line.long 0x04 "QSPI_DEV_INSTR_RD_CONFIG_REG,"
|
|
bitfld.long 0x04 24.--28. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes" "0,1,2,3"
|
|
bitfld.long 0x04 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 8.--9. "INSTR_TYPE_FLD,Instruction Type" "0,1,2,3"
|
|
hexmask.long.byte 0x04 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode"
|
|
line.long 0x08 "QSPI_DEV_INSTR_WR_CONFIG_REG,"
|
|
bitfld.long 0x08 24.--28. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes" "0,1,2,3"
|
|
hexmask.long.byte 0x08 0.--7. 1. "WR_OPCODE_FLD,Write Opcode"
|
|
line.long 0x0C "QSPI_DEV_DELAY_REG,"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out"
|
|
line.long 0x10 "QSPI_RD_DATA_CAPTURE_REG,"
|
|
bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection (of the flash memory data outputs)" "0,1"
|
|
bitfld.long 0x10 1.--4. "DELAY_FLD,Read Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 0. "BYPASS_FLD,Bypass" "0,1"
|
|
line.long 0x14 "QSPI_DEV_SIZE_CONFIG_REG,"
|
|
bitfld.long 0x14 16.--20. "BYTES_PER_SUBSECTOR_FLD,Number of Bytes per Block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of Bytes per Device Page"
|
|
newline
|
|
bitfld.long 0x14 0.--3. "NUM_ADDR_BYTES_FLD,Number of address Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "QSPI_SRAM_PARTITION_CFG_REG,"
|
|
hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size"
|
|
line.long 0x1C "QSPI_IND_AHB_ADDR_TRIGGER_REG,"
|
|
group.long 0x24++0x23
|
|
line.long 0x00 "QSPI_REMAP_ADDR_REG,"
|
|
line.long 0x04 "QSPI_MODE_BIT_CONFIG_REG,"
|
|
hexmask.long.byte 0x04 0.--7. 1. "MODE_FLD,Mode Bits"
|
|
line.long 0x08 "QSPI_SRAM_FILL_REG,"
|
|
hexmask.long.word 0x08 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level (Indirect Write Partition)"
|
|
hexmask.long.word 0x08 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level (Indirect Read Partition)"
|
|
line.long 0x0C "QSPI_TX_THRESH_REG,"
|
|
bitfld.long 0x0C 0.--3. "LEVEL_FLD,Level TX FIFO not full" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSPI_RX_THRESH_REG,"
|
|
bitfld.long 0x10 0.--3. "LEVEL_FLD,Level RX FIFO not empty" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "QSPI_WRITE_COMPLETION_CTRL_REG,"
|
|
hexmask.long.byte 0x14 16.--23. 1. "POLL_COUNT_FLD,Polling Count"
|
|
bitfld.long 0x14 14. "DISABLE_POLLING_FLD,Disable Polling" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "POLLING_POLARITY_FLD,Polling Polarity" "0,1"
|
|
bitfld.long 0x14 8.--10. "POLLING_BIT_INDEX_FLD,Polling Bit Index" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "OPCODE_FLD,Opcode"
|
|
line.long 0x18 "QSPI_NO_OF_POLLS_BEF_EXP_REG,"
|
|
line.long 0x1C "QSPI_IRQ_STATUS_REG,"
|
|
bitfld.long 0x1C 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow" "0,1"
|
|
bitfld.long 0x1C 11. "RX_FIFO_FULL_FLD,Small RX FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty" "0,1"
|
|
bitfld.long 0x1C 9. "TX_FIFO_FULL_FLD,Small TX FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full" "0,1"
|
|
bitfld.long 0x1C 7. "RECV_OVERFLOW_FLD,Receive Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Transfer Watermark Breach" "0,1"
|
|
bitfld.long 0x1C 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB Access Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "PROT_WR_ATTEMPT_FLD,Protected Area Write Attempt" "0,1"
|
|
bitfld.long 0x1C 3. "INDIRECT_READ_REJECT_FLD,Indirect Read Reject" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete" "0,1"
|
|
bitfld.long 0x1C 1. "UNDERFLOW_DET_FLD,Underflow Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "MODE_M_FAIL_FLD,Mode M Failure" "0,1"
|
|
line.long 0x20 "QSPI_IRQ_MASK_REG,"
|
|
bitfld.long 0x20 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1"
|
|
bitfld.long 0x20 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1"
|
|
bitfld.long 0x20 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1"
|
|
bitfld.long 0x20 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1"
|
|
bitfld.long 0x20 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1"
|
|
bitfld.long 0x20 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1"
|
|
bitfld.long 0x20 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "QSPI_LOWER_WR_PROT_REG,"
|
|
line.long 0x04 "QSPI_UPPER_WR_PROT_REG,"
|
|
line.long 0x08 "QSPI_WR_PROT_CTRL_REG,"
|
|
bitfld.long 0x08 1. "ENB_FLD,Write Protection Enable Bit" "0,1"
|
|
bitfld.long 0x08 0. "INV_FLD,Write Protection Inversion Bit" "0,1"
|
|
group.long 0x60++0x1F
|
|
line.long 0x00 "QSPI_INDIRECT_READ_XFER_CTRL_REG,"
|
|
rbitfld.long 0x00 6.--7. "NUM_IND_OPS_DONE_FLD,Completed Indirect Operations" "0,1,2,3"
|
|
bitfld.long 0x00 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "RD_QUEUED_FLD,Queued Indirect Read Operations" "0,1"
|
|
bitfld.long 0x00 3. "SRAM_FULL_FLD,SRAM Full" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2. "RD_STATUS_FLD,Indirect Read Status" "0,1"
|
|
bitfld.long 0x00 1. "CANCEL_FLD,Cancel Indirect Read" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "START_FLD,Start Indirect Read" "0,1"
|
|
line.long 0x04 "QSPI_INDIRECT_READ_XFER_WATERMARK_REG,"
|
|
line.long 0x08 "QSPI_INDIRECT_READ_XFER_START_REG,"
|
|
line.long 0x0C "QSPI_INDIRECT_READ_XFER_NUM_BYTES_REG,"
|
|
line.long 0x10 "QSPI_INDIRECT_WRITE_XFER_CTRL_REG,"
|
|
rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,Completed Indirect Operations" "0,1,2,3"
|
|
bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 4. "WR_QUEUED_FLD,Queued Indirect Write Operations" "0,1"
|
|
rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write" "0,1"
|
|
bitfld.long 0x10 0. "START_FLD,Start Indirect Write" "0,1"
|
|
line.long 0x14 "QSPI_INDIRECT_WRITE_XFER_WATERMARK_REG,"
|
|
line.long 0x18 "QSPI_INDIRECT_WRITE_XFER_START_REG,"
|
|
line.long 0x1C "QSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG,"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "QSPI_FLASH_CMD_CTRL_REG,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode"
|
|
bitfld.long 0x00 23. "ENB_READ_DATA_FLD,Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19. "ENB_COMD_ADDR_FLD,Command Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "ENB_MODE_BIT_FLD,Mode Bit Enable" "0,1"
|
|
bitfld.long 0x00 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 15. "ENB_WRITE_DATA_FLD,Write Data Enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7.--11. "NUM_DUMMY_BYTES_FLD,Number of Dummy Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. "CMD_EXEC_STATUS_FLD,Command Execution Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CMD_EXEC_FLD,Execute Command" "0,1"
|
|
line.long 0x04 "QSPI_FLASH_CMD_ADDR_REG,"
|
|
group.long 0xA0++0x13
|
|
line.long 0x00 "QSPI_FLASH_RD_DATA_LOWER_REG,"
|
|
line.long 0x04 "QSPI_FLASH_RD_DATA_UPPER_REG,"
|
|
line.long 0x08 "QSPI_FLASH_WR_DATA_LOWER_REG,"
|
|
line.long 0x0C "QSPI_FLASH_WR_DATA_UPPER_REG,"
|
|
line.long 0x10 "QSPI_POLLING_FLASH_STATUS_REG,"
|
|
bitfld.long 0x10 8. "DEVICE_STATUS_VALID_FLD,Polling Status Valid: This bit is set when value in" "0,1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DEVICE_STATUS_FLD,Flash Status: Defines actual Status Register of Device"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "QSPI_MODULE_ID_REG,"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE_FLD,Module ID number"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "QSPI_ECC_REVISION,"
|
|
group.long 0x408++0x1F
|
|
line.long 0x00 "QSPI_ECC_VECTOR,"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status indicating that the read is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
newline
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Trigger a read operation to the specified read address" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,ECC RAM ID to select which ECC RAM to control or read status from"
|
|
line.long 0x04 "QSPI_ECC_MISC_STATUS,"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of ECC RAMs serviced by the aggregator"
|
|
line.long 0x08 "QSPI_ECC_WRAPPER_REVISION,"
|
|
bitfld.long 0x08 30.--31. "SCHEME,Scheme that this register is compliant with" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--27. 1. "MODID,Module ID"
|
|
newline
|
|
bitfld.long 0x08 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 6.--7. "REVCUSTOM,Custom revision" "0,1,2,3"
|
|
bitfld.long 0x08 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "QSPI_ECC_CONTROL,"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/FORCE_DED will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "QSPI_ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where FORCE_SEC or FORCE_DED needs to be applied"
|
|
line.long 0x14 "QSPI_ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when FORCE_DED is set"
|
|
line.long 0x18 "QSPI_ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,'1' indicates a successive single-bit error" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,'1' indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,'1' indicates a pending single-bit error" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "ECC_OTHER,'1' - Indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,'1' - Indicates pending double-bit error status Since the double-bit error from the ECC logic is a pulsed interrupt this is also a status set register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "ECC_SEC,'1' - Indicates pending single-bit error status Since the single-bit error from the ECC logic is a pulsed interrupt this is also a status set register" "0,1"
|
|
line.long 0x1C "QSPI_ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the bit position in the ram data that is in error"
|
|
group.long 0x43C++0x3F
|
|
line.long 0x00 "QSPI_ECC_EOI,"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "QSPI_ECC_INT_STATUS_0,"
|
|
line.long 0x08 "QSPI_ECC_INT_STATUS_1,"
|
|
line.long 0x0C "QSPI_ECC_INT_STATUS_2,"
|
|
line.long 0x10 "QSPI_ECC_INT_STATUS_3,"
|
|
line.long 0x14 "QSPI_ECC_INT_STATUS_4,"
|
|
line.long 0x18 "QSPI_ECC_INT_STATUS_5,"
|
|
line.long 0x1C "QSPI_ECC_INT_STATUS_6,"
|
|
line.long 0x20 "QSPI_ECC_INT_STATUS_7,"
|
|
line.long 0x24 "QSPI_ECC_INT_STATUS_8,"
|
|
line.long 0x28 "QSPI_ECC_INT_STATUS_9,"
|
|
line.long 0x2C "QSPI_ECC_INT_STATUS_10,"
|
|
line.long 0x30 "QSPI_ECC_INT_STATUS_11,"
|
|
line.long 0x34 "QSPI_ECC_INT_STATUS_12,"
|
|
line.long 0x38 "QSPI_ECC_INT_STATUS_13,"
|
|
line.long 0x3C "QSPI_ECC_INT_STATUS_14,"
|
|
group.long 0x480++0x3B
|
|
line.long 0x00 "QSPI_ECC_INT_ENABLE_0,"
|
|
line.long 0x04 "QSPI_ECC_INT_ENABLE_1,"
|
|
line.long 0x08 "QSPI_ECC_INT_ENABLE_2,"
|
|
line.long 0x0C "QSPI_ECC_INT_ENABLE_3,"
|
|
line.long 0x10 "QSPI_ECC_INT_ENABLE_4,"
|
|
line.long 0x14 "QSPI_ECC_INT_ENABLE_5,"
|
|
line.long 0x18 "QSPI_ECC_INT_ENABLE_6,"
|
|
line.long 0x1C "QSPI_ECC_INT_ENABLE_7,"
|
|
line.long 0x20 "QSPI_ECC_INT_ENABLE_8,"
|
|
line.long 0x24 "QSPI_ECC_INT_ENABLE_9,"
|
|
line.long 0x28 "QSPI_ECC_INT_ENABLE_10,"
|
|
line.long 0x2C "QSPI_ECC_INT_ENABLE_11,"
|
|
line.long 0x30 "QSPI_ECC_INT_ENABLE_12,"
|
|
line.long 0x34 "QSPI_ECC_INT_ENABLE_13,"
|
|
line.long 0x38 "QSPI_ECC_INT_ENABLE_14,"
|
|
group.long 0x4C0++0x3B
|
|
line.long 0x00 "QSPI_ECC_INT_CLEAR_0,"
|
|
line.long 0x04 "QSPI_ECC_INT_CLEAR_1,"
|
|
line.long 0x08 "QSPI_ECC_INT_CLEAR_2,"
|
|
line.long 0x0C "QSPI_ECC_INT_CLEAR_3,"
|
|
line.long 0x10 "QSPI_ECC_INT_CLEAR_4,"
|
|
line.long 0x14 "QSPI_ECC_INT_CLEAR_5,"
|
|
line.long 0x18 "QSPI_ECC_INT_CLEAR_6,"
|
|
line.long 0x1C "QSPI_ECC_INT_CLEAR_7,"
|
|
line.long 0x20 "QSPI_ECC_INT_CLEAR_8,"
|
|
line.long 0x24 "QSPI_ECC_INT_CLEAR_9,"
|
|
line.long 0x28 "QSPI_ECC_INT_CLEAR_10,"
|
|
line.long 0x2C "QSPI_ECC_INT_CLEAR_11,"
|
|
line.long 0x30 "QSPI_ECC_INT_CLEAR_12,"
|
|
line.long 0x34 "QSPI_ECC_INT_CLEAR_13,"
|
|
line.long 0x38 "QSPI_ECC_INT_CLEAR_14,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SEMAPHORE"
|
|
base ad:0x2640000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SEM_PID,"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SEM_RST_RUN,"
|
|
bitfld.long 0x00 0. "RESET,Reset bit 0h (R) = Module is not ready" "0,1"
|
|
line.long 0x04 "SEM_EOI,"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EOI,Interrupt End of Interrupt 0h (W) = Re-arm SEM_INT0"
|
|
group.long 0x100++0xFB
|
|
line.long 0x00 "SEM_0,"
|
|
abitfld.long 0x00 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x00 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x04 "SEM_1,"
|
|
abitfld.long 0x04 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x04 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x08 "SEM_2,"
|
|
abitfld.long 0x08 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x08 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x0C "SEM_3,"
|
|
abitfld.long 0x0C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x0C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x10 "SEM_4,"
|
|
abitfld.long 0x10 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x10 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x14 "SEM_5,"
|
|
abitfld.long 0x14 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x14 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x18 "SEM_6,"
|
|
abitfld.long 0x18 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x18 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x1C "SEM_7,"
|
|
abitfld.long 0x1C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x1C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x20 "SEM_8,"
|
|
abitfld.long 0x20 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x20 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x24 "SEM_9,"
|
|
abitfld.long 0x24 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x24 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x28 "SEM_10,"
|
|
abitfld.long 0x28 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x28 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x2C "SEM_11,"
|
|
abitfld.long 0x2C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x2C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x30 "SEM_12,"
|
|
abitfld.long 0x30 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x30 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x34 "SEM_13,"
|
|
abitfld.long 0x34 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x34 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x38 "SEM_14,"
|
|
abitfld.long 0x38 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x38 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x3C "SEM_15,"
|
|
abitfld.long 0x3C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x3C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x40 "SEM_16,"
|
|
abitfld.long 0x40 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x40 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x44 "SEM_17,"
|
|
abitfld.long 0x44 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x44 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x48 "SEM_18,"
|
|
abitfld.long 0x48 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x48 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x4C "SEM_19,"
|
|
abitfld.long 0x4C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x4C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x50 "SEM_20,"
|
|
abitfld.long 0x50 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x50 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x54 "SEM_21,"
|
|
abitfld.long 0x54 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x54 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x58 "SEM_22,"
|
|
abitfld.long 0x58 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x58 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x5C "SEM_23,"
|
|
abitfld.long 0x5C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x5C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x60 "SEM_24,"
|
|
abitfld.long 0x60 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x60 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x64 "SEM_25,"
|
|
abitfld.long 0x64 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x64 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x68 "SEM_26,"
|
|
abitfld.long 0x68 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x68 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x6C "SEM_27,"
|
|
abitfld.long 0x6C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x6C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x70 "SEM_28,"
|
|
abitfld.long 0x70 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x70 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x74 "SEM_29,"
|
|
abitfld.long 0x74 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x74 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x78 "SEM_30,"
|
|
abitfld.long 0x78 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x78 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x7C "SEM_31,"
|
|
abitfld.long 0x7C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x7C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x80 "SEM_32,"
|
|
abitfld.long 0x80 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x80 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x84 "SEM_33,"
|
|
abitfld.long 0x84 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x84 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x88 "SEM_34,"
|
|
abitfld.long 0x88 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x88 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x8C "SEM_35,"
|
|
abitfld.long 0x8C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x8C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x90 "SEM_36,"
|
|
abitfld.long 0x90 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x90 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x94 "SEM_37,"
|
|
abitfld.long 0x94 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x94 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x98 "SEM_38,"
|
|
abitfld.long 0x98 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x98 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0x9C "SEM_39,"
|
|
abitfld.long 0x9C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x9C 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xA0 "SEM_40,"
|
|
abitfld.long 0xA0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA0 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xA4 "SEM_41,"
|
|
abitfld.long 0xA4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA4 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xA8 "SEM_42,"
|
|
abitfld.long 0xA8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA8 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xAC "SEM_43,"
|
|
abitfld.long 0xAC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xAC 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xB0 "SEM_44,"
|
|
abitfld.long 0xB0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB0 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xB4 "SEM_45,"
|
|
abitfld.long 0xB4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB4 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xB8 "SEM_46,"
|
|
abitfld.long 0xB8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB8 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xBC "SEM_47,"
|
|
abitfld.long 0xBC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xBC 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xC0 "SEM_48,"
|
|
abitfld.long 0xC0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC0 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xC4 "SEM_49,"
|
|
abitfld.long 0xC4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC4 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xC8 "SEM_50,"
|
|
abitfld.long 0xC8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC8 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xCC "SEM_51,"
|
|
abitfld.long 0xCC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xCC 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xD0 "SEM_52,"
|
|
abitfld.long 0xD0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD0 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xD4 "SEM_53,"
|
|
abitfld.long 0xD4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD4 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xD8 "SEM_54,"
|
|
abitfld.long 0xD8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD8 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xDC "SEM_55,"
|
|
abitfld.long 0xDC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xDC 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xE0 "SEM_56,"
|
|
abitfld.long 0xE0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE0 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xE4 "SEM_57,"
|
|
abitfld.long 0xE4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE4 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xE8 "SEM_58,"
|
|
abitfld.long 0xE8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE8 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xEC "SEM_59,"
|
|
abitfld.long 0xEC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xEC 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xF0 "SEM_60,"
|
|
abitfld.long 0xF0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF0 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xF4 "SEM_61,"
|
|
abitfld.long 0xF4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF4 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
line.long 0xF8 "SEM_62,"
|
|
abitfld.long 0xF8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF8 0. "FREE0,Direct Semaphore flag control read/write action 0h (R) = Semaphore is not granted" "0,1"
|
|
group.long 0x200++0xFB
|
|
line.long 0x00 "ISEM_0,"
|
|
abitfld.long 0x00 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x00 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x04 "ISEM_1,"
|
|
abitfld.long 0x04 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x04 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x08 "ISEM_2,"
|
|
abitfld.long 0x08 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x08 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x0C "ISEM_3,"
|
|
abitfld.long 0x0C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x0C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x10 "ISEM_4,"
|
|
abitfld.long 0x10 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x10 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x14 "ISEM_5,"
|
|
abitfld.long 0x14 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x14 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x18 "ISEM_6,"
|
|
abitfld.long 0x18 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x18 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x1C "ISEM_7,"
|
|
abitfld.long 0x1C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x1C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x20 "ISEM_8,"
|
|
abitfld.long 0x20 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x20 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x24 "ISEM_9,"
|
|
abitfld.long 0x24 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x24 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x28 "ISEM_10,"
|
|
abitfld.long 0x28 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x28 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x2C "ISEM_11,"
|
|
abitfld.long 0x2C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x2C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x30 "ISEM_12,"
|
|
abitfld.long 0x30 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x30 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x34 "ISEM_13,"
|
|
abitfld.long 0x34 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x34 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x38 "ISEM_14,"
|
|
abitfld.long 0x38 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x38 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x3C "ISEM_15,"
|
|
abitfld.long 0x3C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x3C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x40 "ISEM_16,"
|
|
abitfld.long 0x40 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x40 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x44 "ISEM_17,"
|
|
abitfld.long 0x44 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x44 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x48 "ISEM_18,"
|
|
abitfld.long 0x48 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x48 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x4C "ISEM_19,"
|
|
abitfld.long 0x4C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x4C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x50 "ISEM_20,"
|
|
abitfld.long 0x50 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x50 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x54 "ISEM_21,"
|
|
abitfld.long 0x54 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x54 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x58 "ISEM_22,"
|
|
abitfld.long 0x58 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x58 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x5C "ISEM_23,"
|
|
abitfld.long 0x5C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x5C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x60 "ISEM_24,"
|
|
abitfld.long 0x60 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x60 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x64 "ISEM_25,"
|
|
abitfld.long 0x64 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x64 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x68 "ISEM_26,"
|
|
abitfld.long 0x68 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x68 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x6C "ISEM_27,"
|
|
abitfld.long 0x6C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x6C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x70 "ISEM_28,"
|
|
abitfld.long 0x70 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x70 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x74 "ISEM_29,"
|
|
abitfld.long 0x74 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x74 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x78 "ISEM_30,"
|
|
abitfld.long 0x78 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x78 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x7C "ISEM_31,"
|
|
abitfld.long 0x7C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x7C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x80 "ISEM_32,"
|
|
abitfld.long 0x80 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x80 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x84 "ISEM_33,"
|
|
abitfld.long 0x84 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x84 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x88 "ISEM_34,"
|
|
abitfld.long 0x88 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x88 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x8C "ISEM_35,"
|
|
abitfld.long 0x8C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x8C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x90 "ISEM_36,"
|
|
abitfld.long 0x90 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x90 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x94 "ISEM_37,"
|
|
abitfld.long 0x94 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x94 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x98 "ISEM_38,"
|
|
abitfld.long 0x98 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x98 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0x9C "ISEM_39,"
|
|
abitfld.long 0x9C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x9C 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xA0 "ISEM_40,"
|
|
abitfld.long 0xA0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA0 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xA4 "ISEM_41,"
|
|
abitfld.long 0xA4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA4 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xA8 "ISEM_42,"
|
|
abitfld.long 0xA8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA8 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xAC "ISEM_43,"
|
|
abitfld.long 0xAC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xAC 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xB0 "ISEM_44,"
|
|
abitfld.long 0xB0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB0 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xB4 "ISEM_45,"
|
|
abitfld.long 0xB4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB4 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xB8 "ISEM_46,"
|
|
abitfld.long 0xB8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB8 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xBC "ISEM_47,"
|
|
abitfld.long 0xBC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xBC 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xC0 "ISEM_48,"
|
|
abitfld.long 0xC0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC0 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xC4 "ISEM_49,"
|
|
abitfld.long 0xC4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC4 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xC8 "ISEM_50,"
|
|
abitfld.long 0xC8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC8 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xCC "ISEM_51,"
|
|
abitfld.long 0xCC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xCC 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xD0 "ISEM_52,"
|
|
abitfld.long 0xD0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD0 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xD4 "ISEM_53,"
|
|
abitfld.long 0xD4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD4 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xD8 "ISEM_54,"
|
|
abitfld.long 0xD8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD8 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xDC "ISEM_55,"
|
|
abitfld.long 0xDC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xDC 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xE0 "ISEM_56,"
|
|
abitfld.long 0xE0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE0 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xE4 "ISEM_57,"
|
|
abitfld.long 0xE4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE4 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xE8 "ISEM_58,"
|
|
abitfld.long 0xE8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE8 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xEC "ISEM_59,"
|
|
abitfld.long 0xEC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xEC 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xF0 "ISEM_60,"
|
|
abitfld.long 0xF0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF0 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xF4 "ISEM_61,"
|
|
abitfld.long 0xF4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF4 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
line.long 0xF8 "ISEM_62,"
|
|
abitfld.long 0xF8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF8 0. "FREE0,Indirect Semaphore flag control read/write action 0h (R) = Semaphore is not granted request posted to queue" "0,1"
|
|
group.long 0x300++0xFB
|
|
line.long 0x00 "QSEM_0,"
|
|
abitfld.long 0x00 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x00 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x04 "QSEM_1,"
|
|
abitfld.long 0x04 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x04 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x08 "QSEM_2,"
|
|
abitfld.long 0x08 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x08 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x0C "QSEM_3,"
|
|
abitfld.long 0x0C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x0C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x10 "QSEM_4,"
|
|
abitfld.long 0x10 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x10 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x14 "QSEM_5,"
|
|
abitfld.long 0x14 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x14 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x18 "QSEM_6,"
|
|
abitfld.long 0x18 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x18 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x1C "QSEM_7,"
|
|
abitfld.long 0x1C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x1C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x20 "QSEM_8,"
|
|
abitfld.long 0x20 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x20 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x24 "QSEM_9,"
|
|
abitfld.long 0x24 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x24 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x28 "QSEM_10,"
|
|
abitfld.long 0x28 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x28 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x2C "QSEM_11,"
|
|
abitfld.long 0x2C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x2C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x30 "QSEM_12,"
|
|
abitfld.long 0x30 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x30 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x34 "QSEM_13,"
|
|
abitfld.long 0x34 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x34 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x38 "QSEM_14,"
|
|
abitfld.long 0x38 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x38 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x3C "QSEM_15,"
|
|
abitfld.long 0x3C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x3C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x40 "QSEM_16,"
|
|
abitfld.long 0x40 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x40 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x44 "QSEM_17,"
|
|
abitfld.long 0x44 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x44 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x48 "QSEM_18,"
|
|
abitfld.long 0x48 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x48 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x4C "QSEM_19,"
|
|
abitfld.long 0x4C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x4C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x50 "QSEM_20,"
|
|
abitfld.long 0x50 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x50 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x54 "QSEM_21,"
|
|
abitfld.long 0x54 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x54 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x58 "QSEM_22,"
|
|
abitfld.long 0x58 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x58 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x5C "QSEM_23,"
|
|
abitfld.long 0x5C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x5C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x60 "QSEM_24,"
|
|
abitfld.long 0x60 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x60 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x64 "QSEM_25,"
|
|
abitfld.long 0x64 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x64 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x68 "QSEM_26,"
|
|
abitfld.long 0x68 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x68 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x6C "QSEM_27,"
|
|
abitfld.long 0x6C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x6C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x70 "QSEM_28,"
|
|
abitfld.long 0x70 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x70 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x74 "QSEM_29,"
|
|
abitfld.long 0x74 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x74 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x78 "QSEM_30,"
|
|
abitfld.long 0x78 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x78 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x7C "QSEM_31,"
|
|
abitfld.long 0x7C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x7C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x80 "QSEM_32,"
|
|
abitfld.long 0x80 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x80 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x84 "QSEM_33,"
|
|
abitfld.long 0x84 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x84 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x88 "QSEM_34,"
|
|
abitfld.long 0x88 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x88 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x8C "QSEM_35,"
|
|
abitfld.long 0x8C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x8C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x90 "QSEM_36,"
|
|
abitfld.long 0x90 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x90 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x94 "QSEM_37,"
|
|
abitfld.long 0x94 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x94 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x98 "QSEM_38,"
|
|
abitfld.long 0x98 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x98 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0x9C "QSEM_39,"
|
|
abitfld.long 0x9C 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0x9C 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xA0 "QSEM_40,"
|
|
abitfld.long 0xA0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA0 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xA4 "QSEM_41,"
|
|
abitfld.long 0xA4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA4 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xA8 "QSEM_42,"
|
|
abitfld.long 0xA8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xA8 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xAC "QSEM_43,"
|
|
abitfld.long 0xAC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xAC 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xB0 "QSEM_44,"
|
|
abitfld.long 0xB0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB0 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xB4 "QSEM_45,"
|
|
abitfld.long 0xB4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB4 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xB8 "QSEM_46,"
|
|
abitfld.long 0xB8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xB8 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xBC "QSEM_47,"
|
|
abitfld.long 0xBC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xBC 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xC0 "QSEM_48,"
|
|
abitfld.long 0xC0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC0 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xC4 "QSEM_49,"
|
|
abitfld.long 0xC4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC4 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xC8 "QSEM_50,"
|
|
abitfld.long 0xC8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xC8 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xCC "QSEM_51,"
|
|
abitfld.long 0xCC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xCC 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xD0 "QSEM_52,"
|
|
abitfld.long 0xD0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD0 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xD4 "QSEM_53,"
|
|
abitfld.long 0xD4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD4 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xD8 "QSEM_54,"
|
|
abitfld.long 0xD8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xD8 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xDC "QSEM_55,"
|
|
abitfld.long 0xDC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xDC 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xE0 "QSEM_56,"
|
|
abitfld.long 0xE0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE0 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xE4 "QSEM_57,"
|
|
abitfld.long 0xE4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE4 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xE8 "QSEM_58,"
|
|
abitfld.long 0xE8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xE8 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xEC "QSEM_59,"
|
|
abitfld.long 0xEC 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xEC 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xF0 "QSEM_60,"
|
|
abitfld.long 0xF0 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF0 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xF4 "QSEM_61,"
|
|
abitfld.long 0xF4 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF4 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
line.long 0xF8 "QSEM_62,"
|
|
abitfld.long 0xF8 8.--15. "FREE8_15,Semaphore resource owner FREE0 =" "0x00=Read returns Core ID of current owner FREE0 =,0x01=Read returns 0h"
|
|
bitfld.long 0xF8 0. "FREE0,Semaphore flag query and control read/write action 0h (R) = Semaphore is not available" "0,1"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "SEMFLAGL_0,"
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_0,"
|
|
line.long 0x04 "SEMFLAGL_1,"
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_1,"
|
|
line.long 0x04 "SEMFLAGL_2,"
|
|
group.long 0x408++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_2,"
|
|
line.long 0x04 "SEMFLAGL_3,"
|
|
group.long 0x40C++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_3,"
|
|
line.long 0x04 "SEMFLAGL_4,"
|
|
group.long 0x410++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_4,"
|
|
line.long 0x04 "SEMFLAGL_5,"
|
|
group.long 0x414++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_5,"
|
|
line.long 0x04 "SEMFLAGL_6,"
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_6,"
|
|
line.long 0x04 "SEMFLAGL_7,"
|
|
group.long 0x41C++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_7,"
|
|
line.long 0x04 "SEMFLAGL_8,"
|
|
group.long 0x420++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_8,"
|
|
line.long 0x04 "SEMFLAGL_9,"
|
|
group.long 0x424++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_9,"
|
|
line.long 0x04 "SEMFLAGL_10,"
|
|
group.long 0x428++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_10,"
|
|
line.long 0x04 "SEMFLAGL_11,"
|
|
group.long 0x42C++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_11,"
|
|
line.long 0x04 "SEMFLAGL_12,"
|
|
group.long 0x430++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_12,"
|
|
line.long 0x04 "SEMFLAGL_13,"
|
|
group.long 0x434++0x07
|
|
line.long 0x00 "SEMFLAGL_CLEAR_13,"
|
|
line.long 0x04 "SEMFLAGL_14,"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SEMFLAGL_CLEAR_14,"
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SEMFLAGH_0,"
|
|
group.long 0x440++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_0,"
|
|
line.long 0x04 "SEMFLAGH_1,"
|
|
group.long 0x444++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_1,"
|
|
line.long 0x04 "SEMFLAGH_2,"
|
|
group.long 0x448++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_2,"
|
|
line.long 0x04 "SEMFLAGH_3,"
|
|
group.long 0x44C++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_3,"
|
|
line.long 0x04 "SEMFLAGH_4,"
|
|
group.long 0x450++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_4,"
|
|
line.long 0x04 "SEMFLAGH_5,"
|
|
group.long 0x454++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_5,"
|
|
line.long 0x04 "SEMFLAGH_6,"
|
|
group.long 0x458++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_6,"
|
|
line.long 0x04 "SEMFLAGH_7,"
|
|
group.long 0x45C++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_7,"
|
|
line.long 0x04 "SEMFLAGH_8,"
|
|
group.long 0x460++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_8,"
|
|
line.long 0x04 "SEMFLAGH_9,"
|
|
group.long 0x464++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_9,"
|
|
line.long 0x04 "SEMFLAGH_10,"
|
|
group.long 0x468++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_10,"
|
|
line.long 0x04 "SEMFLAGH_11,"
|
|
group.long 0x46C++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_11,"
|
|
line.long 0x04 "SEMFLAGH_12,"
|
|
group.long 0x470++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_12,"
|
|
line.long 0x04 "SEMFLAGH_13,"
|
|
group.long 0x474++0x07
|
|
line.long 0x00 "SEMFLAGH_CLEAR_13,"
|
|
line.long 0x04 "SEMFLAGH_14,"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SEMFLAGH_CLEAR_14,"
|
|
group.long 0x480++0x3B
|
|
line.long 0x00 "SEMFLAGL_SET_0,"
|
|
line.long 0x04 "SEMFLAGL_SET_1,"
|
|
line.long 0x08 "SEMFLAGL_SET_2,"
|
|
line.long 0x0C "SEMFLAGL_SET_3,"
|
|
line.long 0x10 "SEMFLAGL_SET_4,"
|
|
line.long 0x14 "SEMFLAGL_SET_5,"
|
|
line.long 0x18 "SEMFLAGL_SET_6,"
|
|
line.long 0x1C "SEMFLAGL_SET_7,"
|
|
line.long 0x20 "SEMFLAGL_SET_8,"
|
|
line.long 0x24 "SEMFLAGL_SET_9,"
|
|
line.long 0x28 "SEMFLAGL_SET_10,"
|
|
line.long 0x2C "SEMFLAGL_SET_11,"
|
|
line.long 0x30 "SEMFLAGL_SET_12,"
|
|
line.long 0x34 "SEMFLAGL_SET_13,"
|
|
line.long 0x38 "SEMFLAGL_SET_14,"
|
|
group.long 0x4C0++0x3B
|
|
line.long 0x00 "SEMFLAGH_SET_0,"
|
|
line.long 0x04 "SEMFLAGH_SET_1,"
|
|
line.long 0x08 "SEMFLAGH_SET_2,"
|
|
line.long 0x0C "SEMFLAGH_SET_3,"
|
|
line.long 0x10 "SEMFLAGH_SET_4,"
|
|
line.long 0x14 "SEMFLAGH_SET_5,"
|
|
line.long 0x18 "SEMFLAGH_SET_6,"
|
|
line.long 0x1C "SEMFLAGH_SET_7,"
|
|
line.long 0x20 "SEMFLAGH_SET_8,"
|
|
line.long 0x24 "SEMFLAGH_SET_9,"
|
|
line.long 0x28 "SEMFLAGH_SET_10,"
|
|
line.long 0x2C "SEMFLAGH_SET_11,"
|
|
line.long 0x30 "SEMFLAGH_SET_12,"
|
|
line.long 0x34 "SEMFLAGH_SET_13,"
|
|
line.long 0x38 "SEMFLAGH_SET_14,"
|
|
rgroup.long 0x500++0x0B
|
|
line.long 0x00 "SEMERR,"
|
|
hexmask.long.byte 0x00 9.--15. 1. "FAULTID,Master that caused the error Read returns ID of the core that is responsible for the error (0h-Fh)"
|
|
bitfld.long 0x00 3.--8. "SEMNUM,Semaphore Number Read returns Semaphore number associated with error (0h-3Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. "ERR,Semaphore Error Code 0h (R) = No Error" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SEMERR_CLEAR,"
|
|
bitfld.long 0x04 0. "CLRERR,Clear Semaphore Error 0h (W) = No effect" "0,1"
|
|
line.long 0x08 "SEMERR_SET,"
|
|
hexmask.long.byte 0x08 9.--15. 1. "FAULTID,Set Master that caused the error ID of the core that will be responsible for the error (0h-Fh)"
|
|
bitfld.long 0x08 3.--8. "SEMNUM,Set Semaphore Number Semaphore number associated with error (0h-3Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--2. "ERR,Set Semaphore error code 0h (W) = No Error" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PLL"
|
|
base ad:0x2130000
|
|
rgroup.long 0xE4++0x0F
|
|
line.long 0x00 "RSTYPE,"
|
|
bitfld.long 0x00 28. "EMU_RST,Reset initiated by emulation" "0,1"
|
|
bitfld.long 0x00 9. "WDRST,Reset initiated by Watchdog Timer(s)" "0,1"
|
|
bitfld.long 0x00 2. "PLLCTRLRST,Reset initiated by PLL Controller (software reset)" "0,1"
|
|
bitfld.long 0x00 1. "RESET,RESET pin reset" "0,1"
|
|
bitfld.long 0x00 0. "POR,Power-on reset" "0,1"
|
|
line.long 0x04 "RSCTRL,"
|
|
bitfld.long 0x04 16. "SWRST,Software reset" "0,1"
|
|
hexmask.long.word 0x04 0.--15. 1. "KEY,Key used to enable writes toRSCTRL and RSCFG"
|
|
line.long 0x08 "RSCFG,"
|
|
bitfld.long 0x08 17. "WDBLOCK,Block Watchdog timers reset" "0,1"
|
|
bitfld.long 0x08 13. "PLLCTLRSTTYPE,PLL Controller initiates a software driven reset of type" "0,1"
|
|
bitfld.long 0x08 12. "RESETTYPE,RESET pin initiates a reset of type" "0,1"
|
|
bitfld.long 0x08 1. "WDTYPE,Watchdog Timers initiate a reset of type" "0,1"
|
|
line.long 0x0C "RSISO,"
|
|
hexmask.long 0x0C 0.--27. 1. "MOD_ISO_N,Isolate Module domain[N]"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PLLCTL,"
|
|
rbitfld.long 0x00 5. "PLLENSRC,PLL enable source bit" "0,1"
|
|
bitfld.long 0x00 3. "PLLRST,PLL reset bit" "0,1"
|
|
bitfld.long 0x00 1. "PLLPWRDN,PLL power-down mode select bit" "0,1"
|
|
bitfld.long 0x00 0. "PLLEN,PLL enable bit" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SECCTL,"
|
|
bitfld.long 0x00 23. "BYPASS,PLL Bypass Enable" "0,1"
|
|
bitfld.long 0x00 19.--22. "OUTPUT_DIVIDE,Output Divider ratio bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PLLM,"
|
|
bitfld.long 0x00 0.--5. "PLLM,PLL multiplier bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x138++0x0F
|
|
line.long 0x00 "PLLCMD,"
|
|
bitfld.long 0x00 0. "GOSET,GO operation command for SYSCLK rate change and phase alignment" "0,1"
|
|
line.long 0x04 "PLLSTAT,"
|
|
bitfld.long 0x04 0. "GOSTAT,GO operation status" "0,1"
|
|
line.long 0x08 "ALNCTL,"
|
|
bitfld.long 0x08 3. "ALN4,SYSCLK4 alignment" "0,1"
|
|
bitfld.long 0x08 2. "ALN3,SYSCLK3 alignment" "0,1"
|
|
bitfld.long 0x08 1. "ALN2,SYSCLK2 alignment" "0,1"
|
|
bitfld.long 0x08 0. "ALN1,SYSCLK1 alignment" "0,1"
|
|
line.long 0x0C "DCHANGE,"
|
|
bitfld.long 0x0C 3. "SYS4,Identifies when the SYSCLK4 divide ratio has been modified" "0,1"
|
|
bitfld.long 0x0C 2. "SYS3,Identifies when the SYSCLK3 divide ratio has been modified" "0,1"
|
|
bitfld.long 0x0C 1. "SYS2,Identifies when the SYSCLK2 divide ratio has been modified" "0,1"
|
|
bitfld.long 0x0C 0. "SYS1,Identifies when the SYSCLK1 divide ratio has been modified" "0,1"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SYSTAT,"
|
|
bitfld.long 0x00 3. "SYS4ON,SYSCLK4 on status" "0,1"
|
|
bitfld.long 0x00 2. "SYS3ON,SYSCLK3 on status" "0,1"
|
|
bitfld.long 0x00 1. "SYS2ON,SYSCLK2 on status" "0,1"
|
|
bitfld.long 0x00 0. "SYS1ON,SYSCLK1 on status" "0,1"
|
|
repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x48 )
|
|
group.long ($2+0x118)++0x03
|
|
line.long 0x00 "PLLDIV$1,"
|
|
bitfld.long 0x00 15. "EN,Divider Denable bit" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RATIO,Divider ratio bits"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "CIC"
|
|
base ad:0x2600000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CIC_REVISION_REG,"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CIC_GLOBAL_ENABLE_HINT_REG,"
|
|
bitfld.long 0x00 0. "ENABLE,This field enables or disables all the host interrupts at once" "0,1"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "CIC_STATUS_SET_INDEX_REG,"
|
|
hexmask.long.word 0x00 0.--9. 1. "INDEX,This field allows setting the status of an interrupt"
|
|
line.long 0x04 "CIC_STATUS_CLR_INDEX_REG,"
|
|
hexmask.long.word 0x04 0.--9. 1. "INDEX,This field allows clearing the status of an interrupt"
|
|
line.long 0x08 "CIC_ENABLE_SET_INDEX_REG,"
|
|
hexmask.long.word 0x08 0.--9. 1. "INDEX,This field allows enabling an interrupt"
|
|
line.long 0x0C "CIC_ENABLE_CLR_INDEX_REG,"
|
|
hexmask.long.word 0x0C 0.--9. 1. "INDEX,This field allows disabling an interrupt"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "CIC_HINT_ENABLE_SET_INDEX_REG,"
|
|
hexmask.long.word 0x00 0.--9. 1. "INDEX,This field allows enabling a host interrupt output"
|
|
line.long 0x04 "CIC_HINT_ENABLE_CLR_INDEX_REG,"
|
|
hexmask.long.word 0x04 0.--9. 1. "INDEX,This field allows disabling a host interrupt output"
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x1500)++0x03
|
|
line.long 0x00 "CIC_ENABLE_HINT_REG$1,"
|
|
repeat.end
|
|
repeat 9. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
|
|
rgroup.long ($2+0x840)++0x03
|
|
line.long 0x00 "CIC_HINT_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HINT3_MAP,Set the host interrupt for channel N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HINT2_MAP,Set the host interrupt for channel N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HINT1_MAP,Set the host interrupt for channel N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "HINT0_MAP,Set the host interrupt for channel N"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x800)++0x03
|
|
line.long 0x00 "CIC_HINT_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HINT3_MAP,Set the host interrupt for channel N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HINT2_MAP,Set the host interrupt for channel N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HINT1_MAP,Set the host interrupt for channel N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "HINT0_MAP,Set the host interrupt for channel N"
|
|
repeat.end
|
|
repeat 7. (list 96. 97. 98. 99. 100. 101. 102. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x580)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x540)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x500)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x4C0)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x440)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "CIC_CH_MAP_REG$1,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CH3_MAP,Set the channel for the system interrupt N + 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CH2_MAP,Set the channel for the system interrupt N + 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CH1_MAP,Set the channel for the system interrupt N + 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CH0_MAP,Set the channel for the system interrupt N"
|
|
repeat.end
|
|
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "CIC_ENABLE_CLR_REG$1,"
|
|
repeat.end
|
|
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "CIC_ENABLE_REG$1,"
|
|
repeat.end
|
|
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "CIC_ENA_STATUS_REG$1,"
|
|
repeat.end
|
|
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "CIC_RAW_STATUS_REG$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "McASP"
|
|
tree "MCASP_0__CFG"
|
|
base ad:0x2340000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MCASP_REV,"
|
|
line.long 0x04 "MCASP_PWRIDLESYSCONFIG,"
|
|
bitfld.long 0x04 2.--5. "OTHER,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode" "0,1,2,3"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "MCASP_PFUNC,"
|
|
bitfld.long 0x00 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x00 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO" "ACLKR_0,ACLKR_1"
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bitfld.long 0x00 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO" "AFSX_0,AFSX_1"
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bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO" "AHCLKX_0,AHCLKX_1"
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bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO" "ACLKX_0,ACLKX_1"
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|
newline
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bitfld.long 0x00 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO" "AMUTE_0,AMUTE_1"
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bitfld.long 0x00 0.--3. "AXR,Determines if AXRn pin functions as McASP or GPIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "MCASP_PDIR,"
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bitfld.long 0x04 31. "AFSR,Determines if AFSR pin functions as an input or output" "AFSR_0,AFSR_1"
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bitfld.long 0x04 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output" "AHCLKR_0,AHCLKR_1"
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|
bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin functions as an input or output" "ACLKR_0,ACLKR_1"
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bitfld.long 0x04 28. "AFSX,Determines if AFSX pin functions as an input or output" "AFSX_0,AFSX_1"
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bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output" "AHCLKX_0,AHCLKX_1"
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bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin functions as an input or output" "ACLKX_0,ACLKX_1"
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|
newline
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bitfld.long 0x04 25. "AMUTE,Determines if AMUTE pin functions as an input or output" "AMUTE_0,AMUTE_1"
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bitfld.long 0x04 0.--3. "AXR,Determines if AXRn pin functions as an input or output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "MCASP_PDOUT,"
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bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the corresponding 0h (R/W) = Pin drives low" "AFSR_0,AFSR_1"
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bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding 0h (R/W) = Pin drives low" "AHCLKR_0,AHCLKR_1"
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bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding 0h (R/W) = Pin drives low" "ACLKR_0,ACLKR_1"
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bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the corresponding 0h (R/W) = Pin drives low" "AFSX_0,AFSX_1"
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|
bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding 0h (R/W) = Pin drives low" "AHCLKX_0,AHCLKX_1"
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bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding 0h (R/W) = Pin drives low" "ACLKX_0,ACLKX_1"
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newline
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bitfld.long 0x08 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding 0h (R/W) = Pin drives low" "AMUTE_0,AMUTE_1"
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bitfld.long 0x08 0.--3. "AXR,Determines drive on AXR[n] output pin when the corresponding 0h (R/W) = Pin drives low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "MCASP_PDIN,"
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bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin" "AFSR_0,AFSR_1"
|
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bitfld.long 0x0C 30. "AHCLKR,Logic level on AHCLKR pin" "AHCLKR_0,AHCLKR_1"
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bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin" "ACLKR_0,ACLKR_1"
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bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin" "AFSX_0,AFSX_1"
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bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin" "AHCLKX_0,AHCLKX_1"
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bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin" "ACLKX_0,ACLKX_1"
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newline
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bitfld.long 0x0C 25. "AMUTE,Logic level on AMUTE pin" "AMUTE_0,AMUTE_1"
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bitfld.long 0x0C 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x1C++0x07
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line.long 0x00 "MCASP_PDSET,"
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bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin" "AFSR_0,AFSR_1"
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bitfld.long 0x00 30. "AHCLKR,Logic level on AHCLKR pin" "AHCLKR_0,AHCLKR_1"
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bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin" "ACLKR_0,ACLKR_1"
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bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin" "AFSX_0,AFSX_1"
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bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin" "AHCLKX_0,AHCLKX_1"
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bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin" "ACLKX_0,ACLKX_1"
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newline
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bitfld.long 0x00 25. "AMUTE,Logic level on AMUTE pin" "AMUTE_0,AMUTE_1"
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bitfld.long 0x00 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "MCASP_PDCLR,"
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bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit in 0h (R/W) = No effect" "AFSR_0,AFSR_1"
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bitfld.long 0x04 30. "AHCLKR,Allows the corresponding AHCLKR bit in 0h (R/W) = No effect" "AHCLKR_0,AHCLKR_1"
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bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit in 0h (R/W) = No effect" "ACLKR_0,ACLKR_1"
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bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit in 0h (R/W) = No effect" "AFSX_0,AFSX_1"
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bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit in 0h (R/W) = No effect" "AHCLKX_0,AHCLKX_1"
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bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit in 0h (R/W) = No effect" "ACLKX_0,ACLKX_1"
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newline
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bitfld.long 0x04 25. "AMUTE,Allows the corresponding AMUTE bit in 0h (R/W) = No effect" "AMUTE_0,AMUTE_1"
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bitfld.long 0x04 0.--3. "AXR,Allows the corresponding AXR[n] bit in 0h (R/W) = No effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x44++0x0F
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line.long 0x00 "MCASP_GBLCTL,"
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bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "XFRST_0,XFRST_1"
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bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "XSMRST_0,XSMRST_1"
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bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1"
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bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1"
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bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1"
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bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1"
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|
newline
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bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1"
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bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1"
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bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1"
|
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bitfld.long 0x00 0. "RCLKRST,Receive high-frequency clock divider reset enable bit" "RCLKRST_0,RCLKRST_1"
|
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line.long 0x04 "MCASP_AMUTE,"
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bitfld.long 0x04 12. "XDMAERR,If transmit DMA error (XDMAERR) drive 0h (R/W) = Drive is disabled" "XDMAERR_0,XDMAERR_1"
|
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bitfld.long 0x04 11. "RDMAERR,If receive DMA error (RDMAERR) drive 0h (R/W) = Drive is disabled" "RDMAERR_0,RDMAERR_1"
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bitfld.long 0x04 10. "XCKFAIL,If transmit clock failure (XCKFAIL) drive 0h (R/W) = Drive is disabled" "XCKFAIL_0,XCKFAIL_1"
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bitfld.long 0x04 9. "RCKFAIL,If receive clock failure (RCKFAIL) drive 0h (R/W) = Drive is disabled" "RCKFAIL_0,RCKFAIL_1"
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bitfld.long 0x04 8. "XSYNCERR,If unexpected transmit frame sync error (XSYNCERR) drive 0h (R/W) = Drive is disabled" "XSYNCERR_0,XSYNCERR_1"
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bitfld.long 0x04 7. "RSYNCERR,If unexpected receive frame sync error (RSYNCERR) drive 0h (R/W) = Drive is disabled" "RSYNCERR_0,RSYNCERR_1"
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newline
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bitfld.long 0x04 6. "XUNDRN,If transmit underrun error (XUNDRN) drive 0h (R/W) = Drive is disabled" "XUNDRN_0,XUNDRN_1"
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bitfld.long 0x04 5. "ROVRN,If receiver overrun error (ROVRN) drive 0h (R/W) = Drive is disabled" "ROVRN_0,ROVRN_1"
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rbitfld.long 0x04 4. "INSTAT,Determines drive on AXRn pin when 0h (R/W) = AMUTEIN pin is inactive" "INSTAT_0,INSTAT_1"
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bitfld.long 0x04 3. "INEN,Drive 0h (R/W) = Drive is disabled" "INEN_0,INEN_1"
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bitfld.long 0x04 2. "INPOL,Audio mute in (AMUTEIN) polarity select bit" "INPOL_0,INPOL_1"
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bitfld.long 0x04 0.--1. "MUTEN,0h (R/W) = 1h (R/W) = 2h (R/W) = 3h (R/W) = Reserved" "MUTEN_0,MUTEN_1,MUTEN_2,MUTEN_3"
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line.long 0x08 "MCASP_DLBCTL,"
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bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits" "0,1,2,3"
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bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "0,1"
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bitfld.long 0x08 0. "DLBEN,Loopback mode enable bit" "0,1"
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line.long 0x0C "MCASP_DITCTL,"
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bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "0,1"
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bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "0,1"
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bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "0,1"
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group.long 0x60++0x2F
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line.long 0x00 "MCASP_RGBLCTL,"
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rbitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
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rbitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
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rbitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
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rbitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
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bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
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newline
|
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bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
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bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
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bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
|
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bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
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line.long 0x04 "MCASP_RMASK,"
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line.long 0x08 "MCASP_RFMT,"
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bitfld.long 0x08 16.--17. "RDATDLY,Receive bit delay" "0,1,2,3"
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bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "0,1"
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bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "0,1,2,3"
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bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU or DMA from 0h (R/W) = Pad with bit 0 value. 1h (R/W) = Pad with bit 1 to bit 31 value from 1h to 1Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 4.--7. "RSSZ,Receive slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "0,1"
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newline
|
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bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "0,1,2,3,4,5,6,7"
|
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line.long 0x0C "MCASP_AFSRCTL,"
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hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select bits"
|
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bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "0,1"
|
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bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "0,1"
|
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bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "0,1"
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line.long 0x10 "MCASP_ACLKRCTL,"
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bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1"
|
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bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1"
|
|
bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,CLKRDIV_2,CLKRDIV_3,CLKRDIV_4,CLKRDIV_5,CLKRDIV_6,CLKRDIV_7,CLKRDIV_8,CLKRDIV_9,CLKRDIV_10,CLKRDIV_11,CLKRDIV_12,CLKRDIV_13,CLKRDIV_14,CLKRDIV_15,CLKRDIV_16,CLKRDIV_17,CLKRDIV_18,CLKRDIV_19,CLKRDIV_20,CLKRDIV_21,CLKRDIV_22,CLKRDIV_23,CLKRDIV_24,CLKRDIV_25,CLKRDIV_26,CLKRDIV_27,CLKRDIV_28,CLKRDIV_29,CLKRDIV_30,CLKRDIV_31"
|
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line.long 0x14 "MCASP_AHCLKRCTL,"
|
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bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit" "HCLKRM_0,HCLKRM_1"
|
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bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1"
|
|
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
|
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line.long 0x18 "MCASP_RTDM,"
|
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line.long 0x1C "MCASP_RINTCTL,"
|
|
bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "0,1"
|
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bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "0,1"
|
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bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit" "0,1"
|
|
newline
|
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bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "0,1"
|
|
line.long 0x20 "MCASP_RSTAT,"
|
|
bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "0,1"
|
|
bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "0,1"
|
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bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "0,1"
|
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bitfld.long 0x20 5. "RDATA,Receive data ready flag" "0,1"
|
|
bitfld.long 0x20 4. "RLAST,Receive last slot flag" "0,1"
|
|
rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of 0h (R/W) = Current TDM time slot is odd" "0,1"
|
|
newline
|
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bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "0,1"
|
|
bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "0,1"
|
|
bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "0,1"
|
|
line.long 0x24 "MCASP_RSLOT,"
|
|
hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT,"
|
|
line.long 0x28 "MCASP_RCLKCHK,"
|
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hexmask.long.byte 0x28 24.--31. 1. "RCNT,Receive clock count value (from previous measurement)"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RMAX,Receive clock maximum boundary"
|
|
hexmask.long.byte 0x28 8.--15. 1. "RMIN,Receive clock minimum boundary"
|
|
bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "MCASP_REVTCTL,"
|
|
bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1"
|
|
group.long 0xA0++0x2F
|
|
line.long 0x00 "MCASP_XGBLCTL,"
|
|
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
|
|
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
|
|
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
|
|
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
|
|
rbitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
|
|
rbitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
|
|
line.long 0x04 "MCASP_XMASK,"
|
|
line.long 0x08 "MCASP_XFMT,"
|
|
bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "0,1,2,3"
|
|
bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "0,1"
|
|
bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by 0h (R/W) = Pad extra bits with 0" "0,1,2,3"
|
|
bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to 0h (R/W) = Pad with bit 0 value. 1h (R/W) = Pad with bit 1 to bit 31 value from 1h to 1Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "0,1"
|
|
newline
|
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bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "MCASP_AFSXCTL,"
|
|
hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame sync mode select bits"
|
|
bitfld.long 0x0C 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period" "0,1"
|
|
bitfld.long 0x0C 1. "FSXM,Transmit frame sync generation select bit" "0,1"
|
|
bitfld.long 0x0C 0. "FSXP,Transmit frame sync polarity select bit" "0,1"
|
|
line.long 0x10 "MCASP_ACLKXCTL,"
|
|
bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1"
|
|
bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit" "ASYNC_0,ASYNC_1"
|
|
bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1"
|
|
bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31"
|
|
line.long 0x14 "MCASP_AHCLKXCTL,"
|
|
bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1"
|
|
bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1"
|
|
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
|
|
line.long 0x18 "MCASP_XTDM,"
|
|
line.long 0x1C "MCASP_XINTCTL,"
|
|
bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "0,1"
|
|
line.long 0x20 "MCASP_XSTAT,"
|
|
bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "0,1"
|
|
bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "0,1"
|
|
bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "0,1"
|
|
bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "0,1"
|
|
bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "0,1"
|
|
rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of 0h (R/W) = Current TDM time slot is odd" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "0,1"
|
|
bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag" "0,1"
|
|
bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "0,1"
|
|
line.long 0x24 "MCASP_XSLOT,"
|
|
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current transmit time slot count"
|
|
line.long 0x28 "MCASP_XCLKCHK,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)"
|
|
hexmask.long.byte 0x28 16.--23. 1. "XMAX,Transmit clock maximum boundary"
|
|
hexmask.long.byte 0x28 8.--15. 1. "XMIN,Transmit clock minimum boundary"
|
|
bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "MCASP_XEVTCTL,"
|
|
bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "MCASP_RBUF$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "MCASP_XBUF$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "MCASP_SRCTL$1,"
|
|
rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "0,1"
|
|
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "0,1,2,3"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x148)++0x03
|
|
line.long 0x00 "MCASP_DITUDRB$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x130)++0x03
|
|
line.long 0x00 "MCASP_DITUDRA$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x118)++0x03
|
|
line.long 0x00 "MCASP_DITCSRB$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "MCASP_DITCSRA$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_1__CFG"
|
|
base ad:0x2342000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MCASP_REV,"
|
|
line.long 0x04 "MCASP_PWRIDLESYSCONFIG,"
|
|
bitfld.long 0x04 2.--5. "OTHER,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode" "0,1,2,3"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "MCASP_PFUNC,"
|
|
bitfld.long 0x00 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x00 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x00 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x00 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x00 0.--3. "AXR,Determines if AXRn pin functions as McASP or GPIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MCASP_PDIR,"
|
|
bitfld.long 0x04 31. "AFSR,Determines if AFSR pin functions as an input or output" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x04 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin functions as an input or output" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x04 28. "AFSX,Determines if AFSX pin functions as an input or output" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin functions as an input or output" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x04 25. "AMUTE,Determines if AMUTE pin functions as an input or output" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x04 0.--3. "AXR,Determines if AXRn pin functions as an input or output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "MCASP_PDOUT,"
|
|
bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the corresponding 0h (R/W) = Pin drives low" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding 0h (R/W) = Pin drives low" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding 0h (R/W) = Pin drives low" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the corresponding 0h (R/W) = Pin drives low" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding 0h (R/W) = Pin drives low" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding 0h (R/W) = Pin drives low" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x08 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding 0h (R/W) = Pin drives low" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x08 0.--3. "AXR,Determines drive on AXR[n] output pin when the corresponding 0h (R/W) = Pin drives low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "MCASP_PDIN,"
|
|
bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x0C 30. "AHCLKR,Logic level on AHCLKR pin" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x0C 25. "AMUTE,Logic level on AMUTE pin" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x0C 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "MCASP_PDSET,"
|
|
bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x00 30. "AHCLKR,Logic level on AHCLKR pin" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x00 25. "AMUTE,Logic level on AMUTE pin" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x00 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MCASP_PDCLR,"
|
|
bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit in 0h (R/W) = No effect" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x04 30. "AHCLKR,Allows the corresponding AHCLKR bit in 0h (R/W) = No effect" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit in 0h (R/W) = No effect" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit in 0h (R/W) = No effect" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit in 0h (R/W) = No effect" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit in 0h (R/W) = No effect" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x04 25. "AMUTE,Allows the corresponding AMUTE bit in 0h (R/W) = No effect" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x04 0.--3. "AXR,Allows the corresponding AXR[n] bit in 0h (R/W) = No effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x0F
|
|
line.long 0x00 "MCASP_GBLCTL,"
|
|
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "XFRST_0,XFRST_1"
|
|
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "XSMRST_0,XSMRST_1"
|
|
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1"
|
|
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1"
|
|
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1"
|
|
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1"
|
|
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1"
|
|
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1"
|
|
bitfld.long 0x00 0. "RCLKRST,Receive high-frequency clock divider reset enable bit" "RCLKRST_0,RCLKRST_1"
|
|
line.long 0x04 "MCASP_AMUTE,"
|
|
bitfld.long 0x04 12. "XDMAERR,If transmit DMA error (XDMAERR) drive 0h (R/W) = Drive is disabled" "XDMAERR_0,XDMAERR_1"
|
|
bitfld.long 0x04 11. "RDMAERR,If receive DMA error (RDMAERR) drive 0h (R/W) = Drive is disabled" "RDMAERR_0,RDMAERR_1"
|
|
bitfld.long 0x04 10. "XCKFAIL,If transmit clock failure (XCKFAIL) drive 0h (R/W) = Drive is disabled" "XCKFAIL_0,XCKFAIL_1"
|
|
bitfld.long 0x04 9. "RCKFAIL,If receive clock failure (RCKFAIL) drive 0h (R/W) = Drive is disabled" "RCKFAIL_0,RCKFAIL_1"
|
|
bitfld.long 0x04 8. "XSYNCERR,If unexpected transmit frame sync error (XSYNCERR) drive 0h (R/W) = Drive is disabled" "XSYNCERR_0,XSYNCERR_1"
|
|
bitfld.long 0x04 7. "RSYNCERR,If unexpected receive frame sync error (RSYNCERR) drive 0h (R/W) = Drive is disabled" "RSYNCERR_0,RSYNCERR_1"
|
|
newline
|
|
bitfld.long 0x04 6. "XUNDRN,If transmit underrun error (XUNDRN) drive 0h (R/W) = Drive is disabled" "XUNDRN_0,XUNDRN_1"
|
|
bitfld.long 0x04 5. "ROVRN,If receiver overrun error (ROVRN) drive 0h (R/W) = Drive is disabled" "ROVRN_0,ROVRN_1"
|
|
rbitfld.long 0x04 4. "INSTAT,Determines drive on AXRn pin when 0h (R/W) = AMUTEIN pin is inactive" "INSTAT_0,INSTAT_1"
|
|
bitfld.long 0x04 3. "INEN,Drive 0h (R/W) = Drive is disabled" "INEN_0,INEN_1"
|
|
bitfld.long 0x04 2. "INPOL,Audio mute in (AMUTEIN) polarity select bit" "INPOL_0,INPOL_1"
|
|
bitfld.long 0x04 0.--1. "MUTEN,0h (R/W) = 1h (R/W) = 2h (R/W) = 3h (R/W) = Reserved" "MUTEN_0,MUTEN_1,MUTEN_2,MUTEN_3"
|
|
line.long 0x08 "MCASP_DLBCTL,"
|
|
bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits" "0,1,2,3"
|
|
bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "0,1"
|
|
bitfld.long 0x08 0. "DLBEN,Loopback mode enable bit" "0,1"
|
|
line.long 0x0C "MCASP_DITCTL,"
|
|
bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "0,1"
|
|
bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "0,1"
|
|
bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "0,1"
|
|
group.long 0x60++0x2F
|
|
line.long 0x00 "MCASP_RGBLCTL,"
|
|
rbitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
|
|
rbitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
|
|
rbitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
|
|
rbitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
|
|
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
|
|
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
|
|
line.long 0x04 "MCASP_RMASK,"
|
|
line.long 0x08 "MCASP_RFMT,"
|
|
bitfld.long 0x08 16.--17. "RDATDLY,Receive bit delay" "0,1,2,3"
|
|
bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "0,1"
|
|
bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "0,1,2,3"
|
|
bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU or DMA from 0h (R/W) = Pad with bit 0 value. 1h (R/W) = Pad with bit 1 to bit 31 value from 1h to 1Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. "RSSZ,Receive slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "MCASP_AFSRCTL,"
|
|
hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select bits"
|
|
bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "0,1"
|
|
bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "0,1"
|
|
bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "0,1"
|
|
line.long 0x10 "MCASP_ACLKRCTL,"
|
|
bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1"
|
|
bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1"
|
|
bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,CLKRDIV_2,CLKRDIV_3,CLKRDIV_4,CLKRDIV_5,CLKRDIV_6,CLKRDIV_7,CLKRDIV_8,CLKRDIV_9,CLKRDIV_10,CLKRDIV_11,CLKRDIV_12,CLKRDIV_13,CLKRDIV_14,CLKRDIV_15,CLKRDIV_16,CLKRDIV_17,CLKRDIV_18,CLKRDIV_19,CLKRDIV_20,CLKRDIV_21,CLKRDIV_22,CLKRDIV_23,CLKRDIV_24,CLKRDIV_25,CLKRDIV_26,CLKRDIV_27,CLKRDIV_28,CLKRDIV_29,CLKRDIV_30,CLKRDIV_31"
|
|
line.long 0x14 "MCASP_AHCLKRCTL,"
|
|
bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit" "HCLKRM_0,HCLKRM_1"
|
|
bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1"
|
|
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
|
|
line.long 0x18 "MCASP_RTDM,"
|
|
line.long 0x1C "MCASP_RINTCTL,"
|
|
bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "0,1"
|
|
line.long 0x20 "MCASP_RSTAT,"
|
|
bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "0,1"
|
|
bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "0,1"
|
|
bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "0,1"
|
|
bitfld.long 0x20 5. "RDATA,Receive data ready flag" "0,1"
|
|
bitfld.long 0x20 4. "RLAST,Receive last slot flag" "0,1"
|
|
rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of 0h (R/W) = Current TDM time slot is odd" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "0,1"
|
|
bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "0,1"
|
|
bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "0,1"
|
|
line.long 0x24 "MCASP_RSLOT,"
|
|
hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT,"
|
|
line.long 0x28 "MCASP_RCLKCHK,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "RCNT,Receive clock count value (from previous measurement)"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RMAX,Receive clock maximum boundary"
|
|
hexmask.long.byte 0x28 8.--15. 1. "RMIN,Receive clock minimum boundary"
|
|
bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "MCASP_REVTCTL,"
|
|
bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1"
|
|
group.long 0xA0++0x2F
|
|
line.long 0x00 "MCASP_XGBLCTL,"
|
|
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
|
|
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
|
|
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
|
|
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
|
|
rbitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
|
|
rbitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
|
|
line.long 0x04 "MCASP_XMASK,"
|
|
line.long 0x08 "MCASP_XFMT,"
|
|
bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "0,1,2,3"
|
|
bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "0,1"
|
|
bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by 0h (R/W) = Pad extra bits with 0" "0,1,2,3"
|
|
bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to 0h (R/W) = Pad with bit 0 value. 1h (R/W) = Pad with bit 1 to bit 31 value from 1h to 1Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "MCASP_AFSXCTL,"
|
|
hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame sync mode select bits"
|
|
bitfld.long 0x0C 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period" "0,1"
|
|
bitfld.long 0x0C 1. "FSXM,Transmit frame sync generation select bit" "0,1"
|
|
bitfld.long 0x0C 0. "FSXP,Transmit frame sync polarity select bit" "0,1"
|
|
line.long 0x10 "MCASP_ACLKXCTL,"
|
|
bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1"
|
|
bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit" "ASYNC_0,ASYNC_1"
|
|
bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1"
|
|
bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31"
|
|
line.long 0x14 "MCASP_AHCLKXCTL,"
|
|
bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1"
|
|
bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1"
|
|
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
|
|
line.long 0x18 "MCASP_XTDM,"
|
|
line.long 0x1C "MCASP_XINTCTL,"
|
|
bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "0,1"
|
|
line.long 0x20 "MCASP_XSTAT,"
|
|
bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "0,1"
|
|
bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "0,1"
|
|
bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "0,1"
|
|
bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "0,1"
|
|
bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "0,1"
|
|
rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of 0h (R/W) = Current TDM time slot is odd" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "0,1"
|
|
bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag" "0,1"
|
|
bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "0,1"
|
|
line.long 0x24 "MCASP_XSLOT,"
|
|
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current transmit time slot count"
|
|
line.long 0x28 "MCASP_XCLKCHK,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)"
|
|
hexmask.long.byte 0x28 16.--23. 1. "XMAX,Transmit clock maximum boundary"
|
|
hexmask.long.byte 0x28 8.--15. 1. "XMIN,Transmit clock minimum boundary"
|
|
bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "MCASP_XEVTCTL,"
|
|
bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "MCASP_RBUF$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "MCASP_XBUF$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "MCASP_SRCTL$1,"
|
|
rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "0,1"
|
|
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "0,1,2,3"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x148)++0x03
|
|
line.long 0x00 "MCASP_DITUDRB$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x130)++0x03
|
|
line.long 0x00 "MCASP_DITUDRA$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x118)++0x03
|
|
line.long 0x00 "MCASP_DITCSRB$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "MCASP_DITCSRA$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_2__CFG"
|
|
base ad:0x2344000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MCASP_REV,"
|
|
line.long 0x04 "MCASP_PWRIDLESYSCONFIG,"
|
|
bitfld.long 0x04 2.--5. "OTHER,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode" "0,1,2,3"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "MCASP_PFUNC,"
|
|
bitfld.long 0x00 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x00 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x00 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x00 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x00 0.--3. "AXR,Determines if AXRn pin functions as McASP or GPIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MCASP_PDIR,"
|
|
bitfld.long 0x04 31. "AFSR,Determines if AFSR pin functions as an input or output" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x04 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin functions as an input or output" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x04 28. "AFSX,Determines if AFSX pin functions as an input or output" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin functions as an input or output" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x04 25. "AMUTE,Determines if AMUTE pin functions as an input or output" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x04 0.--3. "AXR,Determines if AXRn pin functions as an input or output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "MCASP_PDOUT,"
|
|
bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the corresponding 0h (R/W) = Pin drives low" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding 0h (R/W) = Pin drives low" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding 0h (R/W) = Pin drives low" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the corresponding 0h (R/W) = Pin drives low" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding 0h (R/W) = Pin drives low" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding 0h (R/W) = Pin drives low" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x08 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding 0h (R/W) = Pin drives low" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x08 0.--3. "AXR,Determines drive on AXR[n] output pin when the corresponding 0h (R/W) = Pin drives low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "MCASP_PDIN,"
|
|
bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x0C 30. "AHCLKR,Logic level on AHCLKR pin" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x0C 25. "AMUTE,Logic level on AMUTE pin" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x0C 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "MCASP_PDSET,"
|
|
bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x00 30. "AHCLKR,Logic level on AHCLKR pin" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x00 25. "AMUTE,Logic level on AMUTE pin" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x00 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MCASP_PDCLR,"
|
|
bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit in 0h (R/W) = No effect" "AFSR_0,AFSR_1"
|
|
bitfld.long 0x04 30. "AHCLKR,Allows the corresponding AHCLKR bit in 0h (R/W) = No effect" "AHCLKR_0,AHCLKR_1"
|
|
bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit in 0h (R/W) = No effect" "ACLKR_0,ACLKR_1"
|
|
bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit in 0h (R/W) = No effect" "AFSX_0,AFSX_1"
|
|
bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit in 0h (R/W) = No effect" "AHCLKX_0,AHCLKX_1"
|
|
bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit in 0h (R/W) = No effect" "ACLKX_0,ACLKX_1"
|
|
newline
|
|
bitfld.long 0x04 25. "AMUTE,Allows the corresponding AMUTE bit in 0h (R/W) = No effect" "AMUTE_0,AMUTE_1"
|
|
bitfld.long 0x04 0.--3. "AXR,Allows the corresponding AXR[n] bit in 0h (R/W) = No effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x0F
|
|
line.long 0x00 "MCASP_GBLCTL,"
|
|
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "XFRST_0,XFRST_1"
|
|
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "XSMRST_0,XSMRST_1"
|
|
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1"
|
|
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1"
|
|
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1"
|
|
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1"
|
|
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1"
|
|
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1"
|
|
bitfld.long 0x00 0. "RCLKRST,Receive high-frequency clock divider reset enable bit" "RCLKRST_0,RCLKRST_1"
|
|
line.long 0x04 "MCASP_AMUTE,"
|
|
bitfld.long 0x04 12. "XDMAERR,If transmit DMA error (XDMAERR) drive 0h (R/W) = Drive is disabled" "XDMAERR_0,XDMAERR_1"
|
|
bitfld.long 0x04 11. "RDMAERR,If receive DMA error (RDMAERR) drive 0h (R/W) = Drive is disabled" "RDMAERR_0,RDMAERR_1"
|
|
bitfld.long 0x04 10. "XCKFAIL,If transmit clock failure (XCKFAIL) drive 0h (R/W) = Drive is disabled" "XCKFAIL_0,XCKFAIL_1"
|
|
bitfld.long 0x04 9. "RCKFAIL,If receive clock failure (RCKFAIL) drive 0h (R/W) = Drive is disabled" "RCKFAIL_0,RCKFAIL_1"
|
|
bitfld.long 0x04 8. "XSYNCERR,If unexpected transmit frame sync error (XSYNCERR) drive 0h (R/W) = Drive is disabled" "XSYNCERR_0,XSYNCERR_1"
|
|
bitfld.long 0x04 7. "RSYNCERR,If unexpected receive frame sync error (RSYNCERR) drive 0h (R/W) = Drive is disabled" "RSYNCERR_0,RSYNCERR_1"
|
|
newline
|
|
bitfld.long 0x04 6. "XUNDRN,If transmit underrun error (XUNDRN) drive 0h (R/W) = Drive is disabled" "XUNDRN_0,XUNDRN_1"
|
|
bitfld.long 0x04 5. "ROVRN,If receiver overrun error (ROVRN) drive 0h (R/W) = Drive is disabled" "ROVRN_0,ROVRN_1"
|
|
rbitfld.long 0x04 4. "INSTAT,Determines drive on AXRn pin when 0h (R/W) = AMUTEIN pin is inactive" "INSTAT_0,INSTAT_1"
|
|
bitfld.long 0x04 3. "INEN,Drive 0h (R/W) = Drive is disabled" "INEN_0,INEN_1"
|
|
bitfld.long 0x04 2. "INPOL,Audio mute in (AMUTEIN) polarity select bit" "INPOL_0,INPOL_1"
|
|
bitfld.long 0x04 0.--1. "MUTEN,0h (R/W) = 1h (R/W) = 2h (R/W) = 3h (R/W) = Reserved" "MUTEN_0,MUTEN_1,MUTEN_2,MUTEN_3"
|
|
line.long 0x08 "MCASP_DLBCTL,"
|
|
bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits" "0,1,2,3"
|
|
bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "0,1"
|
|
bitfld.long 0x08 0. "DLBEN,Loopback mode enable bit" "0,1"
|
|
line.long 0x0C "MCASP_DITCTL,"
|
|
bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "0,1"
|
|
bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "0,1"
|
|
bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "0,1"
|
|
group.long 0x60++0x2F
|
|
line.long 0x00 "MCASP_RGBLCTL,"
|
|
rbitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
|
|
rbitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
|
|
rbitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
|
|
rbitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
|
|
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
|
|
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
|
|
line.long 0x04 "MCASP_RMASK,"
|
|
line.long 0x08 "MCASP_RFMT,"
|
|
bitfld.long 0x08 16.--17. "RDATDLY,Receive bit delay" "0,1,2,3"
|
|
bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "0,1"
|
|
bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "0,1,2,3"
|
|
bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU or DMA from 0h (R/W) = Pad with bit 0 value. 1h (R/W) = Pad with bit 1 to bit 31 value from 1h to 1Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. "RSSZ,Receive slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "MCASP_AFSRCTL,"
|
|
hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select bits"
|
|
bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "0,1"
|
|
bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "0,1"
|
|
bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "0,1"
|
|
line.long 0x10 "MCASP_ACLKRCTL,"
|
|
bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1"
|
|
bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1"
|
|
bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,CLKRDIV_2,CLKRDIV_3,CLKRDIV_4,CLKRDIV_5,CLKRDIV_6,CLKRDIV_7,CLKRDIV_8,CLKRDIV_9,CLKRDIV_10,CLKRDIV_11,CLKRDIV_12,CLKRDIV_13,CLKRDIV_14,CLKRDIV_15,CLKRDIV_16,CLKRDIV_17,CLKRDIV_18,CLKRDIV_19,CLKRDIV_20,CLKRDIV_21,CLKRDIV_22,CLKRDIV_23,CLKRDIV_24,CLKRDIV_25,CLKRDIV_26,CLKRDIV_27,CLKRDIV_28,CLKRDIV_29,CLKRDIV_30,CLKRDIV_31"
|
|
line.long 0x14 "MCASP_AHCLKRCTL,"
|
|
bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit" "HCLKRM_0,HCLKRM_1"
|
|
bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1"
|
|
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
|
|
line.long 0x18 "MCASP_RTDM,"
|
|
line.long 0x1C "MCASP_RINTCTL,"
|
|
bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "0,1"
|
|
line.long 0x20 "MCASP_RSTAT,"
|
|
bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "0,1"
|
|
bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "0,1"
|
|
bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "0,1"
|
|
bitfld.long 0x20 5. "RDATA,Receive data ready flag" "0,1"
|
|
bitfld.long 0x20 4. "RLAST,Receive last slot flag" "0,1"
|
|
rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of 0h (R/W) = Current TDM time slot is odd" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "0,1"
|
|
bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "0,1"
|
|
bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "0,1"
|
|
line.long 0x24 "MCASP_RSLOT,"
|
|
hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT,"
|
|
line.long 0x28 "MCASP_RCLKCHK,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "RCNT,Receive clock count value (from previous measurement)"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RMAX,Receive clock maximum boundary"
|
|
hexmask.long.byte 0x28 8.--15. 1. "RMIN,Receive clock minimum boundary"
|
|
bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "MCASP_REVTCTL,"
|
|
bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1"
|
|
group.long 0xA0++0x2F
|
|
line.long 0x00 "MCASP_XGBLCTL,"
|
|
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
|
|
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
|
|
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
|
|
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
|
|
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
|
|
rbitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
|
|
rbitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
|
|
rbitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
|
|
line.long 0x04 "MCASP_XMASK,"
|
|
line.long 0x08 "MCASP_XFMT,"
|
|
bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "0,1,2,3"
|
|
bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "0,1"
|
|
bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by 0h (R/W) = Pad extra bits with 0" "0,1,2,3"
|
|
bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to 0h (R/W) = Pad with bit 0 value. 1h (R/W) = Pad with bit 1 to bit 31 value from 1h to 1Fh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "MCASP_AFSXCTL,"
|
|
hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame sync mode select bits"
|
|
bitfld.long 0x0C 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period" "0,1"
|
|
bitfld.long 0x0C 1. "FSXM,Transmit frame sync generation select bit" "0,1"
|
|
bitfld.long 0x0C 0. "FSXP,Transmit frame sync polarity select bit" "0,1"
|
|
line.long 0x10 "MCASP_ACLKXCTL,"
|
|
bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1"
|
|
bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit" "ASYNC_0,ASYNC_1"
|
|
bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1"
|
|
bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31"
|
|
line.long 0x14 "MCASP_AHCLKXCTL,"
|
|
bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1"
|
|
bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1"
|
|
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
|
|
line.long 0x18 "MCASP_XTDM,"
|
|
line.long 0x1C "MCASP_XINTCTL,"
|
|
bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "0,1"
|
|
line.long 0x20 "MCASP_XSTAT,"
|
|
bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "0,1"
|
|
bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "0,1"
|
|
bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "0,1"
|
|
bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "0,1"
|
|
bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "0,1"
|
|
rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of 0h (R/W) = Current TDM time slot is odd" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "0,1"
|
|
bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag" "0,1"
|
|
bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "0,1"
|
|
line.long 0x24 "MCASP_XSLOT,"
|
|
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current transmit time slot count"
|
|
line.long 0x28 "MCASP_XCLKCHK,"
|
|
hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)"
|
|
hexmask.long.byte 0x28 16.--23. 1. "XMAX,Transmit clock maximum boundary"
|
|
hexmask.long.byte 0x28 8.--15. 1. "XMIN,Transmit clock minimum boundary"
|
|
bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "MCASP_XEVTCTL,"
|
|
bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "MCASP_RBUF$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "MCASP_XBUF$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "MCASP_SRCTL$1,"
|
|
rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "0,1"
|
|
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "0,1,2,3"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x148)++0x03
|
|
line.long 0x00 "MCASP_DITUDRB$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x130)++0x03
|
|
line.long 0x00 "MCASP_DITUDRA$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x118)++0x03
|
|
line.long 0x00 "MCASP_DITCSRB$1,"
|
|
repeat.end
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "MCASP_DITCSRA$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_0__FIFO_CFG"
|
|
base ad:0x2340400
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "MCASP_WFIFOCTL,"
|
|
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
|
|
abitfld.long 0x00 8.--15. "WNUMEVT,Write word count per DMA event (32 bit)" "0x40=3 to 64 words from 3h to 40h,0xFF=Reserved from 41h to FFh"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer (32 bit words)"
|
|
line.long 0x04 "MCASP_WFIFOSTS,"
|
|
abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
|
|
line.long 0x08 "MCASP_RFIFOCTL,"
|
|
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
|
|
abitfld.long 0x08 8.--15. "RNUMEVT,Read word count per DMA event (32 bit)" "0x40=3 to 64 words from 3h to 40h,0x41=FFh,0xFF=Reserved from"
|
|
newline
|
|
abitfld.long 0x08 0.--7. "RNUMDMA,Read word count per transfer (32 bit words)" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
|
|
line.long 0x0C "MCASP_RFIFOSTS,"
|
|
abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_1__FIFO_CFG"
|
|
base ad:0x2342400
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "MCASP_WFIFOCTL,"
|
|
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
|
|
abitfld.long 0x00 8.--15. "WNUMEVT,Write word count per DMA event (32 bit)" "0x40=3 to 64 words from 3h to 40h,0xFF=Reserved from 41h to FFh"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer (32 bit words)"
|
|
line.long 0x04 "MCASP_WFIFOSTS,"
|
|
abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
|
|
line.long 0x08 "MCASP_RFIFOCTL,"
|
|
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
|
|
abitfld.long 0x08 8.--15. "RNUMEVT,Read word count per DMA event (32 bit)" "0x40=3 to 64 words from 3h to 40h,0x41=FFh,0xFF=Reserved from"
|
|
newline
|
|
abitfld.long 0x08 0.--7. "RNUMDMA,Read word count per transfer (32 bit words)" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
|
|
line.long 0x0C "MCASP_RFIFOSTS,"
|
|
abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_2__FIFO_CFG"
|
|
base ad:0x2344400
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "MCASP_WFIFOCTL,"
|
|
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
|
|
abitfld.long 0x00 8.--15. "WNUMEVT,Write word count per DMA event (32 bit)" "0x40=3 to 64 words from 3h to 40h,0xFF=Reserved from 41h to FFh"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer (32 bit words)"
|
|
line.long 0x04 "MCASP_WFIFOSTS,"
|
|
abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
|
|
line.long 0x08 "MCASP_RFIFOCTL,"
|
|
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
|
|
abitfld.long 0x08 8.--15. "RNUMEVT,Read word count per DMA event (32 bit)" "0x40=3 to 64 words from 3h to 40h,0x41=FFh,0xFF=Reserved from"
|
|
newline
|
|
abitfld.long 0x08 0.--7. "RNUMDMA,Read word count per transfer (32 bit words)" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
|
|
line.long 0x0C "MCASP_RFIFOSTS,"
|
|
abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_0_SLV"
|
|
base ad:0x21804000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MCASP_RBUF,"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCASP_XBUF,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_1_SLV"
|
|
base ad:0x21804400
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MCASP_RBUF,"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCASP_XBUF,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCASP_2_SLV"
|
|
base ad:0x21804800
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MCASP_RBUF,"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCASP_XBUF,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "MCBSP"
|
|
base ad:0x2346000
|
|
rgroup.long 0x00++0x3F
|
|
line.long 0x00 "MCBSP_DRR,"
|
|
line.long 0x04 "MCBSP_DXR,"
|
|
line.long 0x08 "MCBSP_SPCR,"
|
|
bitfld.long 0x08 25. "FREE,Free-running enable mode bit" "0,1"
|
|
bitfld.long 0x08 24. "SOFT,Soft bit enable mode bit" "0,1"
|
|
bitfld.long 0x08 23. "FRST,Frame-sync generator reset bit" "0,1"
|
|
bitfld.long 0x08 22. "GRST,Sample-rate generator reset bit" "0,1"
|
|
bitfld.long 0x08 20.--21. "XINTM,Transmit interrupt (XINT) mode bit" "0,1,2,3"
|
|
bitfld.long 0x08 19. "XSYNCERR,Transmit synchronization error bit" "0,1"
|
|
rbitfld.long 0x08 18. "XEMPTY,Transmit shift register empty bit" "0,1"
|
|
rbitfld.long 0x08 17. "XRDY,Transmitter ready bit" "0,1"
|
|
bitfld.long 0x08 16. "XRST,Transmitter reset bit resets or enables the transmitter" "0,1"
|
|
bitfld.long 0x08 15. "DLB,Digital loop back mode enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 13.--14. "RJUST,Receive sign-extension and justification mode bit" "0,1,2,3"
|
|
rbitfld.long 0x08 11.--12. "CLKSTP,Clock stop mode bit" "0,1,2,3"
|
|
bitfld.long 0x08 7. "DXENA,DX enabler bit" "0,1"
|
|
bitfld.long 0x08 4.--5. "RINTM,Receive interrupt (RINT) mode bit" "0,1,2,3"
|
|
bitfld.long 0x08 3. "RSYNCERR,Receive synchronization error bit" "0,1"
|
|
rbitfld.long 0x08 2. "RFULL,Receive shift register full bit" "0,1"
|
|
rbitfld.long 0x08 1. "RRDY,Receiver ready bit" "0,1"
|
|
bitfld.long 0x08 0. "RRST,Receiver reset bit resets or enables the receiver" "0,1"
|
|
line.long 0x0C "MCBSP_RCR,"
|
|
bitfld.long 0x0C 31. "RPHASE,Receive phases bit" "0,1"
|
|
hexmask.long.byte 0x0C 24.--30. 1. "RFRLEN2,Specifies the receive frame length (number of words) in phase 2"
|
|
bitfld.long 0x0C 21.--23. "RWDLEN2,Specifies the receive word length (number of bits) in phase 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 19.--20. "RCOMPAND,Receive companding mode bit" "0,1,2,3"
|
|
bitfld.long 0x0C 18. "RFIG,Receive frame ignore bit" "0,1"
|
|
bitfld.long 0x0C 16.--17. "RDATDLY,Receive data delay bit" "0,1,2,3"
|
|
hexmask.long.byte 0x0C 8.--14. 1. "RFRLEN1,Specifies the receive frame length (number of words) in phase 1"
|
|
bitfld.long 0x0C 5.--7. "RWDLEN1,Specifies the receive word length (number of bits) in phase 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 4. "RWDREVRS,Receive 32-bit reversal enable bit" "0,1"
|
|
line.long 0x10 "MCBSP_XCR,"
|
|
bitfld.long 0x10 31. "XPHASE,Transmit phases bit" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. "XFRLEN2,Specifies the transmit frame length (number of words) in phase 2"
|
|
bitfld.long 0x10 21.--23. "XWDLEN2,Specifies the transmit word length (number of bits) in phase 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 19.--20. "XCOMPAND,Transmit companding mode bit" "0,1,2,3"
|
|
bitfld.long 0x10 18. "XFIG,Transmit frame ignore bit" "0,1"
|
|
bitfld.long 0x10 16.--17. "XDATDLY,Transmit data delay bit" "0,1,2,3"
|
|
hexmask.long.byte 0x10 8.--14. 1. "XFRLEN1,Specifies the transmit frame length (number of words) in phase 1"
|
|
bitfld.long 0x10 5.--7. "XWDLEN1,Specifies the transmit word length (number of bits) in phase 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 4. "XWDREVRS,Transmit 32-bit reversal feature enable bit" "0,1"
|
|
line.long 0x14 "MCBSP_SRGR,"
|
|
bitfld.long 0x14 31. "GSYNC,Sample-rate generator clock synchronization bit is only used when CLKS drives the sample-rate generator clock (CLKSM = 0)" "0,1"
|
|
bitfld.long 0x14 30. "CLKSP,CLKS polarity clock edge select bit is only used when CLKS drives the sample-rate generator clock (CLKSM = 0)" "0,1"
|
|
bitfld.long 0x14 29. "CLKSM,Sample rate generator input clock mode bit" "0,1"
|
|
bitfld.long 0x14 28. "FSGM,Sample-rate generator transmit frame-synchronization mode bit is only used when FSXM = 1 inMCBSP_PCR" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "FPER,"
|
|
hexmask.long.byte 0x14 8.--15. 1. "FWID,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "CLKGDV,"
|
|
line.long 0x18 "MCBSP_MCR,"
|
|
bitfld.long 0x18 25. "XMCME,Transmit multichannel partition mode bit" "0,1"
|
|
bitfld.long 0x18 23.--24. "XPBBLK,Transmit partition B block bit.XPBBLK is only applicable if channels can be individually disabled/enabled and masked/unmasked (XMCM is nonzero) and the 2-partition mode is selected (XMCME = 0)" "0,1,2,3"
|
|
bitfld.long 0x18 21.--22. "XPABLK,Transmit partition A block bit.XPABLK is only applicable if channels can be individually disabled/enabled and masked/unmasked (XMCM is nonzero) and the 2-partition mode is selected (XMCME = 0)" "0,1,2,3"
|
|
rbitfld.long 0x18 18.--20. "XCBLK,Transmit current block indicator" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 16.--17. "XMCM,Transmit multichannel selection mode bit" "0,1,2,3"
|
|
bitfld.long 0x18 9. "RMCME,Receive multichannel partition mode bit" "0,1"
|
|
bitfld.long 0x18 7.--8. "RPBBLK,Receive partition B block bit.RPBBLK is only applicable if channels can be individually disabled/enabled (RMCM = 1) and the 2-partition mode is selected (RMCME = 0)" "0,1,2,3"
|
|
bitfld.long 0x18 5.--6. "RPABLK,Receive partition A block bit.RPABLK is only applicable if channels can be individually disabled/enabled (RMCM = 1) and the 2-partition mode is selected (RMCME = 0)" "0,1,2,3"
|
|
rbitfld.long 0x18 2.--4. "RCBLK,Receive current block indicator" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0. "RMCM,Receive multichannel selection mode bit" "0,1"
|
|
line.long 0x1C "MCBSP_RCERE0,"
|
|
bitfld.long 0x1C 31. "RCE31,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 30. "RCE30,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 29. "RCE29,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 28. "RCE28,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 27. "RCE27,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 26. "RCE26,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 25. "RCE25,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 24. "RCE24,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 23. "RCE23,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 22. "RCE22,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 21. "RCE21,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 20. "RCE20,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 19. "RCE19,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 18. "RCE18,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 17. "RCE17,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 16. "RCE16,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 15. "RCE15,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 14. "RCE14,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 13. "RCE13,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 12. "RCE12,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "RCE11,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 10. "RCE10,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 9. "RCE9,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 8. "RCE8,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 7. "RCE7,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 6. "RCE6,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "RCE5,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "RCE4,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "RCE3,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "RCE2,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "RCE1,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "RCE0,Receive channel enable bit" "0,1"
|
|
line.long 0x20 "MCBSP_XCERE0,"
|
|
bitfld.long 0x20 31. "XCE31,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 30. "XCE30,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 29. "XCE29,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 28. "XCE28,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 27. "XCE27,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 26. "XCE26,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 25. "XCE25,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 24. "XCE24,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 23. "XCE23,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 22. "XCE22,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 21. "XCE21,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 20. "XCE20,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 19. "XCE19,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 18. "XCE18,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 17. "XCE17,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 16. "XCE16,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 15. "XCE15,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 14. "XCE14,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 13. "XCE13,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 12. "XCE12,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 11. "XCE11,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 10. "XCE10,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 9. "XCE9,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 8. "XCE8,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 7. "XCE7,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 6. "XCE6,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 5. "XCE5,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 4. "XCE4,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 3. "XCE3,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 2. "XCE2,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "XCE1,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x20 0. "XCE0,Transmit channel enable bit" "0,1"
|
|
line.long 0x24 "MCBSP_PCR,"
|
|
bitfld.long 0x24 11. "FSXM,Transmit frame-synchronization mode bit" "0,1"
|
|
bitfld.long 0x24 10. "FSRM,Receive frame-synchronization mode bit" "0,1"
|
|
bitfld.long 0x24 9. "CLKXM,Transmit clock mode bit" "0,1"
|
|
bitfld.long 0x24 8. "CLKRM,Receive clock mode bit" "0,1"
|
|
bitfld.long 0x24 7. "SCLKME,Sample rate generator input clock mode bit" "0,1"
|
|
bitfld.long 0x24 3. "FSXP,Transmit frame-synchronization polarity bit" "0,1"
|
|
bitfld.long 0x24 2. "FSRP,Receive frame-synchronization polarity bit" "0,1"
|
|
bitfld.long 0x24 1. "CLKXP,Transmit clock polarity bit" "0,1"
|
|
bitfld.long 0x24 0. "CLKRP,Receive clock polarity bit" "0,1"
|
|
line.long 0x28 "MCBSP_RCERE1,"
|
|
bitfld.long 0x28 31. "RCE31,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 30. "RCE30,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 29. "RCE29,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 28. "RCE28,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 27. "RCE27,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 26. "RCE26,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 25. "RCE25,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 24. "RCE24,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 23. "RCE23,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 22. "RCE22,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "RCE21,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 20. "RCE20,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 19. "RCE19,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 18. "RCE18,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 17. "RCE17,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 16. "RCE16,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 15. "RCE15,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 14. "RCE14,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 13. "RCE13,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 12. "RCE12,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "RCE11,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 10. "RCE10,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 9. "RCE9,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 8. "RCE8,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 7. "RCE7,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 6. "RCE6,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 5. "RCE5,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 4. "RCE4,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 3. "RCE3,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 2. "RCE2,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "RCE1,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x28 0. "RCE0,Receive channel enable bit" "0,1"
|
|
line.long 0x2C "MCBSP_XCERE1,"
|
|
bitfld.long 0x2C 31. "XCE31,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 30. "XCE30,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 29. "XCE29,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 28. "XCE28,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 27. "XCE27,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 26. "XCE26,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 25. "XCE25,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 24. "XCE24,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 23. "XCE23,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 22. "XCE22,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 21. "XCE21,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 20. "XCE20,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 19. "XCE19,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 18. "XCE18,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 17. "XCE17,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 16. "XCE16,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 15. "XCE15,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 14. "XCE14,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 13. "XCE13,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 12. "XCE12,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 11. "XCE11,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 10. "XCE10,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 9. "XCE9,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 8. "XCE8,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 7. "XCE7,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 6. "XCE6,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 5. "XCE5,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 4. "XCE4,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 3. "XCE3,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 2. "XCE2,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 1. "XCE1,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x2C 0. "XCE0,Transmit channel enable bit" "0,1"
|
|
line.long 0x30 "MCBSP_RCERE2,"
|
|
bitfld.long 0x30 31. "RCE31,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 30. "RCE30,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 29. "RCE29,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 28. "RCE28,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 27. "RCE27,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 26. "RCE26,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 25. "RCE25,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 24. "RCE24,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 23. "RCE23,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 22. "RCE22,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x30 21. "RCE21,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 20. "RCE20,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 19. "RCE19,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 18. "RCE18,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 17. "RCE17,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 16. "RCE16,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 15. "RCE15,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 14. "RCE14,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 13. "RCE13,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 12. "RCE12,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x30 11. "RCE11,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 10. "RCE10,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 9. "RCE9,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 8. "RCE8,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 7. "RCE7,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 6. "RCE6,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 5. "RCE5,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 4. "RCE4,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 3. "RCE3,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 2. "RCE2,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x30 1. "RCE1,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x30 0. "RCE0,Receive channel enable bit" "0,1"
|
|
line.long 0x34 "MCBSP_XCERE2,"
|
|
bitfld.long 0x34 31. "XCE31,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 30. "XCE30,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 29. "XCE29,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 28. "XCE28,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 27. "XCE27,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 26. "XCE26,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 25. "XCE25,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 24. "XCE24,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 23. "XCE23,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 22. "XCE22,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 21. "XCE21,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 20. "XCE20,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 19. "XCE19,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 18. "XCE18,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 17. "XCE17,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 16. "XCE16,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 15. "XCE15,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 14. "XCE14,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 13. "XCE13,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 12. "XCE12,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 11. "XCE11,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 10. "XCE10,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 9. "XCE9,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 8. "XCE8,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 7. "XCE7,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 6. "XCE6,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 5. "XCE5,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 4. "XCE4,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 3. "XCE3,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 2. "XCE2,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "XCE1,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x34 0. "XCE0,Transmit channel enable bit" "0,1"
|
|
line.long 0x38 "MCBSP_RCERE3,"
|
|
bitfld.long 0x38 31. "RCE31,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 30. "RCE30,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 29. "RCE29,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 28. "RCE28,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 27. "RCE27,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 26. "RCE26,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 25. "RCE25,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 24. "RCE24,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 23. "RCE23,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 22. "RCE22,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 21. "RCE21,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 20. "RCE20,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 19. "RCE19,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 18. "RCE18,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 17. "RCE17,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 16. "RCE16,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 15. "RCE15,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 14. "RCE14,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 13. "RCE13,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 12. "RCE12,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 11. "RCE11,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 10. "RCE10,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 9. "RCE9,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 8. "RCE8,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 7. "RCE7,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 6. "RCE6,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 5. "RCE5,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 4. "RCE4,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 3. "RCE3,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 2. "RCE2,Receive channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 1. "RCE1,Receive channel enable bit" "0,1"
|
|
bitfld.long 0x38 0. "RCE0,Receive channel enable bit" "0,1"
|
|
line.long 0x3C "MCBSP_XCERE3,"
|
|
bitfld.long 0x3C 31. "XCE31,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 30. "XCE30,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 29. "XCE29,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 28. "XCE28,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 27. "XCE27,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 26. "XCE26,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 25. "XCE25,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 24. "XCE24,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 23. "XCE23,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 22. "XCE22,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 21. "XCE21,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 20. "XCE20,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 19. "XCE19,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 18. "XCE18,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 17. "XCE17,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 16. "XCE16,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 15. "XCE15,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 14. "XCE14,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 13. "XCE13,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 12. "XCE12,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 11. "XCE11,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 10. "XCE10,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 9. "XCE9,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 8. "XCE8,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 7. "XCE7,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 6. "XCE6,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 5. "XCE5,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 4. "XCE4,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 3. "XCE3,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 2. "XCE2,Transmit channel enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 1. "XCE1,Transmit channel enable bit" "0,1"
|
|
bitfld.long 0x3C 0. "XCE0,Transmit channel enable bit" "0,1"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "MCBSP_BFIFOREV,"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "MCBSP_WFIFOCTL,"
|
|
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer (32-bit words)"
|
|
line.long 0x04 "MCBSP_WFIFOSTS,"
|
|
hexmask.long.byte 0x04 0.--7. 1. "WLVL,Write level"
|
|
line.long 0x08 "MCBSP_RFIFOCTL,"
|
|
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
|
|
hexmask.long.byte 0x08 8.--15. 1. "RNUMEVT,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x08 0.--7. 1. "RNUMDMA,Read word count per transfer (32-bit words)"
|
|
line.long 0x0C "MCBSP_RFIFOSTS,"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "RLVL,Read level"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MLB"
|
|
base ad:0x21C6000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MLB_MLBSSREV,"
|
|
line.long 0x04 "MLB_MLBSSPWR,"
|
|
bitfld.long 0x04 0. "MSTANDBY,Value to be driven in the MStandby bus of the power management interface Writing a 1 to this bit asserts the MStandby output of MLBSS thereby initiating the clock disabling sequence for the MLBSS" "Mstandby output is deasserted,Mstandby output is asserted"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MLB_MLBSSPRF,"
|
|
bitfld.long 0x00 16. "WRNP,The WRNP bit controls whether the writes issued by the DMA interface are posted (no write response required to complete transaction) or non posted (write response required to complete transaction)" "Only posted writes are issued,Only non-posted writes are issued"
|
|
bitfld.long 0x00 12.--14. "ASYNC_PRI,ASYNC_PRI controls the priority carried in MREQINFO attribute of DMA interface when a asynchronous transaction is requested at the DMA interface" "Highest priority,?,?,?,?,?,?,Lowest priority"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "SYNC_PRI,SYNC_PRI controls the priority carried in MREQINFO attribute of DMA interface when a synchronous transaction is requested at the DMA interface" "Highest priority,?,?,?,?,?,?,Lowest priority"
|
|
bitfld.long 0x00 4.--5. "ASYNC_FLAG,ASYNC_FLAG controls the value carried in MFLAG attribute of DMA interface" "Lowest priority through on-chip network,Medium priority through on-chip network,Reserved,Highest priority through on-chip network"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SYNC_FLAG,SYNC_FLAG controls the value carried in MFLAG attribute of DMA interface" "Lowest priority through on-chip network,Medium priority through on-chip network,Reserved,Highest priority through on-chip network"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "MLB_MLBC0,"
|
|
bitfld.long 0x00 15.--17. "FCNT,The number of frames per sub-buffer for synchronous channels" "1 frame per sub-buffer (operation is the same as..,2 frames per sub-buffer,4 frames per sub-buffer,8 frames per sub-buffer,16 frames per sub-buffer,32 frames per sub-buffer,64 frames per sub-buffer,Reserved"
|
|
bitfld.long 0x00 14. "CTLRETRY,Control Tx packet retry" "Control packet is skipped,Control packet is re-transmitted"
|
|
newline
|
|
bitfld.long 0x00 12. "ASYRETRY,Asynchronous Tx packet retry" "Asynchronous packet is skipped,Asynchronous packet is re-transmitted"
|
|
bitfld.long 0x00 7. "MLBLK,MediaLB lock status" "MediaLB is unlocked,MediaLB is locked"
|
|
newline
|
|
bitfld.long 0x00 5. "MLBPEN,MediaLB 6-pin enable" "MediaLB 3-pin interface enabled,MediaLB 6-pin interface enabled"
|
|
bitfld.long 0x00 2.--4. "MLBCLK,MediaLB clock speed select" "256 -Fs (for MLBPEN = 0),512 -Fs (for MLBPEN = 0),1024 -Fs (for MLBPEN = 0),2048xFs (for MLBPEN = 1) 4h-7h: Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "MLBEN,MediaLB enable" "MediaLB disabled,MediaLB enabled"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "MLB_MS0,"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "MLB_MS1,"
|
|
group.long 0x420++0x07
|
|
line.long 0x00 "MLB_MSS,"
|
|
bitfld.long 0x00 5. "SERVREQ,Service request enabled" "Service request disabled (not detected),Service request enabled (detected)"
|
|
bitfld.long 0x00 4. "SWSYSCMD,Software system command detected (in the system quadlet)" "Software system command not detected,Software system command detected"
|
|
newline
|
|
bitfld.long 0x00 3. "CSSYSCMD,Channel scan system command detected (in the system quadlet)" "Channel scan system command not detected,Channel scan system command detected"
|
|
bitfld.long 0x00 2. "ULKSYSCMD,Network unlock system command detected (in the system quadlet)" "Unlock system command not detected,Unlock system command detected"
|
|
newline
|
|
bitfld.long 0x00 1. "LKSYSCMD,Network lock system command detected (in the system quadlet)" "Lock system not detected,Lock system detected"
|
|
bitfld.long 0x00 0. "RSTSYSCMD,Reset system command detected (in the system quadlet)" "Reset system command not detected,Reset system command detected"
|
|
line.long 0x04 "MLB_MSD,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "SD3,System data (byte 3)"
|
|
hexmask.long.byte 0x04 16.--23. 1. "SD2,System data (byte 2)"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "SD1,System data (byte 1)"
|
|
hexmask.long.byte 0x04 0.--7. 1. "SD0,System data (byte 0)"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "MLB_MIEN,"
|
|
bitfld.long 0x00 29. "CTX_BREAK,Control Tx break enable" "Control Tx break disabled,Control Tx break enabled"
|
|
bitfld.long 0x00 28. "CTX_PE,Control Tx protocol error enable" "Control Tx protocol error disabled,Control Tx protocol error enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "CTX_DONE,Control Tx packet done enable" "Control Tx packet done disabled,Control Tx packet done enabled"
|
|
bitfld.long 0x00 26. "CRX_BREAK,Control Rx break enable" "Control Rx break disabled,Control Rx break enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CRX_PE,Control Rx protocol error enable" "Control Rx protocol error disabled,Control Rx protocol error enabled"
|
|
bitfld.long 0x00 24. "CRX_DONE,Control Rx packet done enable" "Control Rx packet done disabled,Control Rx packet done enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "ATX_BREAK,Asynchronous Tx break enable" "Asynchronous Tx break disabled,Asynchronous Tx break enabled"
|
|
bitfld.long 0x00 21. "ATX_PE,Asynchronous Tx protocol error enable" "Asynchronous Tx protocol error disabled,Asynchronous Tx protocol error enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "ATX_DONE,Asynchronous Tx packet done enable" "Asynchronous Tx packet done disabled,Asynchronous Tx packet done enabled"
|
|
bitfld.long 0x00 19. "ARX_BREAK,Asynchronous Rx break enable" "Asynchronous Rx break disabled,Asynchronous Rx break enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "ARX_PE,Asynchronous Rx protocol error enable" "Asynchronous Rx protocol error disabled,Asynchronous Rx protocol error enabled"
|
|
bitfld.long 0x00 17. "ARX_DONE,Asynchronous Rx packet done enable" "Asynchronous Rx packet done disabled,Asynchronous Rx packet done enable"
|
|
newline
|
|
bitfld.long 0x00 16. "SYNC_PE,Synchronous protocol error enable" "Synchronous protocol error disabled,Synchronous protocol error enabled"
|
|
bitfld.long 0x00 1. "ISOC_BUFO,Isochronous Rx buffer overflow enable" "Buffer overflow disabled,Buffer overflow enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ISOC_PE,Isochronous Rx protocol error enable" "Isochronous Rx ProtocolError disabled,Isochronous Rx ProtocolError enabled"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "MLB_MLBC1,"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NDA,Node device address"
|
|
bitfld.long 0x00 7. "CLKMERR,MediaLB clock missing status" "MediaLB clock is toggling at the pins,MediaLB clock is not toggling at the pins"
|
|
newline
|
|
bitfld.long 0x00 6. "LOCKERR,MediaLB lock error status" "No MediaLB lock error,MediaLB lock error"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "MLB_DIENR,"
|
|
bitfld.long 0x00 15. "EN,DMA enable" "Disabled,Enabled"
|
|
group.long 0x488++0x07
|
|
line.long 0x00 "MLB_DICER0,"
|
|
line.long 0x04 "MLB_DICER1,"
|
|
group.long 0x4C0++0x27
|
|
line.long 0x00 "MLB_MDAT0,"
|
|
line.long 0x04 "MLB_MDAT1,"
|
|
line.long 0x08 "MLB_MDAT2,"
|
|
line.long 0x0C "MLB_MDAT3,"
|
|
line.long 0x10 "MLB_MDWE0,"
|
|
line.long 0x14 "MLB_MDWE1,"
|
|
line.long 0x18 "MLB_MDWE2,"
|
|
line.long 0x1C "MLB_MDWE3,"
|
|
line.long 0x20 "MLB_MCTL,"
|
|
bitfld.long 0x20 0. "XCMP,Transfer complete (write 0 to clear)" "Memory interface transfer not completed,Memory interface transfer is completed"
|
|
line.long 0x24 "MLB_MADR,"
|
|
bitfld.long 0x24 31. "WNR,Write-Not-Read selection" ","
|
|
hexmask.long.byte 0x24 0.--7. 1. "ADDR,CTR address of 128-bit entry"
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "MLB_DCTL,"
|
|
bitfld.long 0x00 4. "PKT_MODE,Packet mode for async/control packets" "Single packet mode,Multi Packet mode"
|
|
bitfld.long 0x00 2. "DMA_MODE,DMA mode" "DMA Mode 0 (Not supported),DMA Mode 1 (Use always this value)"
|
|
newline
|
|
bitfld.long 0x00 1. "SMX,DMA interrupt mux enable" ","
|
|
bitfld.long 0x00 0. "SCE,Software clear enable" "Hardware clears interrupt after,Software clears interrupt"
|
|
group.long 0x7D0++0x0F
|
|
line.long 0x00 "MLB_DCSR0,"
|
|
line.long 0x04 "MLB_DCSR1,"
|
|
line.long 0x08 "MLB_DCMR0,"
|
|
line.long 0x0C "MLB_DCMR1,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MMCSD"
|
|
repeat 2. (list 0. 1.)(list ad:0x23000000 ad:0x23100000)
|
|
tree "MMCSD_$1"
|
|
base $2
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "MMCHS_HL_REV,"
|
|
line.long 0x04 "MMCHS_HL_HWINFO,"
|
|
bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
|
|
bitfld.long 0x04 2.--5. "MEM_SIZE,Memory size for FIFO buffer 1h (R) = Memory of 512 bytes max block length is 512 bytes" "MEM_SIZE_0,MEM_SIZE_1,MEM_SIZE_2,MEM_SIZE_3,MEM_SIZE_4,MEM_SIZE_5,MEM_SIZE_6,MEM_SIZE_7,MEM_SIZE_8,MEM_SIZE_9,MEM_SIZE_10,MEM_SIZE_11,MEM_SIZE_12,MEM_SIZE_13,MEM_SIZE_14,MEM_SIZE_15"
|
|
bitfld.long 0x04 1. "MERGE_MEM,Memory merged for FIFO buffer This bit field defines the configuration of FIFO buffer architecture" "MERGE_MEM_0,MERGE_MEM_1"
|
|
bitfld.long 0x04 0. "MADMA_EN,Master DMA enabled generic parameter This bit defines the configuration of the controller to know if it supports the master DMA management called ADMA" "MADMA_EN_0,MADMA_EN_1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MMCHS_HL_SYSCONFIG,"
|
|
bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode By definition initiator may generate read/write transaction as long as it is out of STANDBY state" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3"
|
|
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
|
|
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal Functionality NOT implemented in MMC" "FREEEMU_0,FREEEMU_1"
|
|
bitfld.long 0x00 0. "SOFTRESET,Software reset (Optional)0h (W) = No action.1h (W) = Initiate software reset" "SOFTRESET_0,SOFTRESET_1"
|
|
group.long 0x110++0x07
|
|
line.long 0x00 "MMCHS_SYSCONFIG,"
|
|
bitfld.long 0x00 12.--13. "STANDBYMODE,Master interface Power Management standby/wait control The bit field is only useful when generic parameter 0h (R/W) = Force-standby" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3"
|
|
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity Bit8: Interface clock" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3"
|
|
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MMC acknowledges it unconditionally and goes in Inactive mode" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
|
|
bitfld.long 0x00 2. "ENAWAKEUP,Wakeup feature control 0h (R/W) = Wakeup capability is disabled" "ENAWAKEUP_0,ENAWAKEUP_1"
|
|
newline
|
|
bitfld.long 0x00 1. "SOFTRESET,Software reset The bit is automatically reset by the hardware" "SOFTRESET_0,SOFTRESET_1"
|
|
bitfld.long 0x00 0. "AUTOIDLE,Internal Clock gating strategy 0h (R/W) = Clocks are free-running" "AUTOIDLE_0,AUTOIDLE_1"
|
|
line.long 0x04 "MMCHS_SYSSTATUS,"
|
|
bitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring 0h (R) = Internal module reset is on-going" "RESETDONE_0,RESETDONE_1"
|
|
group.long 0x124++0x13
|
|
line.long 0x00 "MMCHS_CSRE,"
|
|
line.long 0x04 "MMCHS_SYSTEST,"
|
|
rbitfld.long 0x04 16. "OBI,Out-Of-Band Interrupt (OBI) data value 0h (R) = The Out-of-Band Interrupt pin is driven low" "OBI_0,OBI_1"
|
|
rbitfld.long 0x04 15. "SDCD,Card detect input signal (MMCi_SDCD) data value 0h (R) = The card detect pin is driven low" "SDCD_0,SDCD_1"
|
|
rbitfld.long 0x04 14. "SDWP,Write protect input signal (MMCi_SDWP) data value 0h (R) = The write protect pin MMCi_SDWP is driven low" "SDWP_0,SDWP_1"
|
|
bitfld.long 0x04 13. "WAKD,Wake request output signal data value0h (W) = The pin SWAKEUP is driven low.1h (W) = The pin SWAKEUP is driven high" "WAKD_0,WAKD_1"
|
|
newline
|
|
bitfld.long 0x04 12. "SSB,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (0h (W) = Clear this SSB bitfield. Writing 0 does not clear already set status bits.1h (W) = Force to 1 all status bits of the interrupt.." "SSB_0,SSB_1"
|
|
bitfld.long 0x04 11. "D7D,DAT7 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT7 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT7 line is driven high" "D7D_0,D7D_1"
|
|
bitfld.long 0x04 10. "D6D,DAT6 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT6 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT6 line is driven high" "D6D_0,D6D_1"
|
|
bitfld.long 0x04 9. "D5D,DAT5 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT5 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT5 line is driven high" "D5D_0,D5D_1"
|
|
newline
|
|
bitfld.long 0x04 8. "D4D,DAT4 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT4 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT4 line is driven high" "D4D_0,D4D_1"
|
|
bitfld.long 0x04 7. "D3D,DAT3 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT3 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT3 line is driven high" "D3D_0,D3D_1"
|
|
bitfld.long 0x04 6. "D2D,DAT2 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT2 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT2 line is driven high" "D2D_0,D2D_1"
|
|
bitfld.long 0x04 5. "D1D,DAT1 input/output signal data value 0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT1 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT1 line is driven high" "D1D_0,D1D_1"
|
|
newline
|
|
bitfld.long 0x04 4. "D0D,DAT0 input/output signal data value0h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT0 line is driven low.1h (W) = If SYSTEST[DDIR] = 0 (output mode direction) the DAT0 line is driven high" "D0D_0,D0D_1"
|
|
bitfld.long 0x04 3. "DDIR,Control of the DAT[7:0] pins direction0h (W) = The DAT lines are outputs (host to card)1h (W) = The DAT lines are inputs (card to host) 0h (R) = No action" "DDIR_0,DDIR_1"
|
|
bitfld.long 0x04 2. "CDAT,CMD input/output signal data value0h (W) = If SYSTEST[CDIR] = 0 (output mode direction) the CMD line is driven low.1h (W) = If SYSTEST[CDIR] = 0 (output mode direction) the CMD line is driven high" "CDAT_0,CDAT_1"
|
|
bitfld.long 0x04 1. "CDIR,Control of the CMD pin direction0h (W) = The CMD line is an output (host to card)1h (W) = The CMD line is an input (card to host) 0h (R) = No action" "CDIR_0,CDIR_1"
|
|
newline
|
|
bitfld.long 0x04 0. "MCKD,MMC clock output signal data value0h (W) = The output clock is driven low.1h (W) = The output clock is driven high" "MCKD_0,MCKD_1"
|
|
line.long 0x08 "MMCHS_CON,"
|
|
bitfld.long 0x08 21. "SDMA_LNE,Slave DMA Level/Edge Request The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to 0h (R/W) = Slave DMA edge sensitive Early DMA de-assertion" "SDMA_LNE_0,SDMA_LNE_1"
|
|
bitfld.long 0x08 20. "DMA_MNS,DMA Master or Slave selection When this bit is set and the controller is configured to use the DMA Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory)" "DMA_MNS_0,DMA_MNS_1"
|
|
bitfld.long 0x08 19. "DDR,Dual Data Rate mode When this bit field is set the controller uses both clock edge to emit or receive data" "DDR_0,DDR_1"
|
|
bitfld.long 0x08 18. "BOOT_CF0,Boot status supported This bit field is set when the CMD line need to be forced to '0' for a boot sequence" "BOOT_CF0_0,BOOT_CF0_1"
|
|
newline
|
|
bitfld.long 0x08 17. "BOOT_ACK,Book acknowledge received When this bit is set the controller should receive a boot status on DAT0 line after next command issued" "BOOT_ACK_0,BOOT_ACK_1"
|
|
bitfld.long 0x08 16. "CLKEXTFREE,External clock free running This bit field is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]" "CLKEXTFREE_0,CLKEXTFREE_1"
|
|
bitfld.long 0x08 15. "PADEN,Control Power for MMC Lines This bit field is only useful when MMC PADs contain power saving mechanism to minimize its leakage power" "PADEN_0,PADEN_1"
|
|
bitfld.long 0x08 14. "OBIE,Out-of-Band Interrupt Enable MMC cards only: 0h (R/W) = Out-of-Band interrupt detection disabled" "OBIE_0,OBIE_1"
|
|
newline
|
|
bitfld.long 0x08 13. "OBIP,Out-of-Band Interrupt Polarity MMC cards only: 0h (R/W) = Active high level" "OBIP_0,OBIP_1"
|
|
bitfld.long 0x08 12. "CEATA,CE-ATA control mode MMC cards compliant with CE-ATA: By default this bit is set to 0" "CEATA_0,CEATA_1"
|
|
bitfld.long 0x08 11. "CTPL,Control Power for DAT[1] line MMC and SD cards: 0h (R/W) = Disable all the input buffers outside of a transaction" "CTPL_0,CTPL_1"
|
|
bitfld.long 0x08 9.--10. "DVAL,Debounce filter value All cards: 0h (R/W) = 33 us debounce period" "DVAL_0,DVAL_1,DVAL_2,DVAL_3"
|
|
newline
|
|
bitfld.long 0x08 8. "WPP,Write protect polarity For SD and SDIO cards only: 0h (R/W) = Active high level" "WPP_0,WPP_1"
|
|
bitfld.long 0x08 7. "CDP,Card detect polarity All cards: 0h (R/W) = Active low level" "CDP_0,CDP_1"
|
|
bitfld.long 0x08 6. "MIT,MMC interrupt command Only for MMC cards: 0h (R/W) = Command timeout enabled" "MIT_0,MIT_1"
|
|
bitfld.long 0x08 5. "DW8,8-bit mode MMC select For SD/SDIO cards this bit must be set to 0" "DW8_0,DW8_1"
|
|
newline
|
|
bitfld.long 0x08 4. "MODE,Mode select All cards: 0h (R/W) = Functional mode" "MODE_0,MODE_1"
|
|
bitfld.long 0x08 3. "STR,Stream command Only for MMC cards: 0h (R/W) = Block oriented data transfer" "STR_0,STR_1"
|
|
bitfld.long 0x08 2. "HR,Broadcast host response Only for MMC cards: 0h (R/W) = The host does not generate a 48-bit response instead of a command" "HR_0,HR_1"
|
|
bitfld.long 0x08 1. "INIT,Send initialization stream All cards: 0h (R/W) = The host does not send an initialization sequence" "INIT_0,INIT_1"
|
|
newline
|
|
bitfld.long 0x08 0. "OD,Card open drain mode Only for MMC cards: 0h (R/W) = No Open Drain" "OD_0,OD_1"
|
|
line.long 0x0C "MMCHS_PWCNT,"
|
|
hexmask.long.word 0x0C 0.--15. 1. "PWRCNT,Power counter register This bit field is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued"
|
|
line.long 0x10 "MMCHS_DLL,"
|
|
bitfld.long 0x10 31. "DLL_SOFT_RESET,Soft reset for DLL active HIGH0h (W) = No action.1h (W) = Issue soft reset" "0,1"
|
|
bitfld.long 0x10 30. "LOCK_TIMER,Timer for the DLL_LOCK signal to be asserted after reset 0h (R/W) = 1024 cycles (equivalent to DLL fast mode lock)" "0,1"
|
|
hexmask.long.byte 0x10 22.--29. 1. "MAX_LOCK_DIFF,Maximum number of taps that the master DLL clock period measurement can deviate without resulting in the master DLL losing lock"
|
|
bitfld.long 0x10 21. "FORCE_SR_F,Forced fine delay value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "SWT,Software Tuning enable The bit shall be set to manage the tuning sequence fully in software" "0,1"
|
|
hexmask.long.byte 0x10 13.--19. 1. "FORCE_SR_C,Forced coarse delay value"
|
|
bitfld.long 0x10 12. "FORCE_VALUE,Put forced values to slave DLL ignoring master DLL output and ratio value 0h (R/W) = Do not put force value" "0,1"
|
|
bitfld.long 0x10 6.--11. "SLAVE_RATIO,Fraction of a clock cycle for the shift to be implemented in units of 256ths of a clock cycle 0h (R/W) = 0 degree delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 3. "DLL_UNLOCK_CLEAR,Clears the PHY_REG_STATUS_MDLL_UNLOCK_STICKY flags of the DLL 0h (R/W) = No effect" "0,1"
|
|
rbitfld.long 0x10 2. "DLL_UNLOCK_STICKY,Asserted when any single period measurement exceeds MAX_LOCK_DIFF" "0,1"
|
|
bitfld.long 0x10 1. "DLL_CALIB,Enables Slave DLL to update new delay values 0h (R/W) = Disabled" "0,1"
|
|
rbitfld.long 0x10 0. "DLL_LOCK,Master DLL lock status 0h (R) = DLL is not locked" "0,1"
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "MMCHS_SDMASA,"
|
|
line.long 0x04 "MMCHS_BLK,"
|
|
hexmask.long.word 0x04 16.--31. 1. "NBLK,Blocks count for current transfer This bit field is enabled when Block count Enable ( 0h (R/W) = Stop count. 1h (R/W) = 1 block. 2h (R/W) = 2 blocks. FFFFh (R/W) = 65535 blocks"
|
|
hexmask.long.word 0x04 0.--11. 1. "BLEN,Transfer Block Size This bit field specifies the block size for block data transfers"
|
|
line.long 0x08 "MMCHS_ARG,"
|
|
line.long 0x0C "MMCHS_CMD,"
|
|
bitfld.long 0x0C 24.--29. "INDX,Command index Binary encoded value from 0 to 63 specifying the command number send to card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 22.--23. "CMD_TYPE,Command type This bit field specifies three types of special command: Suspend Resume and Abort" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3"
|
|
bitfld.long 0x0C 21. "DP,Data present select This bit field indicates that data is present and DAT line shall be used" "DP_0,DP_1"
|
|
bitfld.long 0x0C 20. "CICE,Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command" "CICE_0,CICE_1"
|
|
newline
|
|
bitfld.long 0x0C 19. "CCCE,Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus" "CCCE_0,CCCE_1"
|
|
bitfld.long 0x0C 16.--17. "RSP_TYPE,Response type This bits defines the response type of the command" "RSP_TYPE_0,RSP_TYPE_1,RSP_TYPE_2,RSP_TYPE_3"
|
|
bitfld.long 0x0C 5. "MSBS,Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command" "MSBS_0,MSBS_1"
|
|
bitfld.long 0x0C 4. "DDIR,Data transfer Direction SelectThis bit defines either data transfer will be a read or a write 0h (R/W) = Data Write (host to card)" "DDIR_0,DDIR_1"
|
|
newline
|
|
bitfld.long 0x0C 2.--3. "ACEN,Auto CMD Enable - SD card only This field determines use of auto command functions" "ACEN_0,ACEN_1,?,?"
|
|
bitfld.long 0x0C 1. "BCE,Block Count Enable Multiple block transfers only" "BCE_0,BCE_1"
|
|
bitfld.long 0x0C 0. "DE,DMA EnableThis bit is used to enable DMA mode for host data access 0h (R/W) = DMA mode disable" "DE_0,DE_1"
|
|
group.long 0x220++0x2B
|
|
line.long 0x00 "MMCHS_DATA,"
|
|
line.long 0x04 "MMCHS_PSTATE,"
|
|
bitfld.long 0x04 24. "CLEV,CMD line signal level This status is used to check the CMD line level to recover from errors and for debugging" "CLEV_0,CLEV_1"
|
|
bitfld.long 0x04 20.--23. "DLEV,DAT[3:0] line signal level DAT[3] => bit 23" "DLEV_0,DLEV_1,DLEV_2,DLEV_3,DLEV_4,DLEV_5,DLEV_6,DLEV_7,DLEV_8,DLEV_9,DLEV_10,DLEV_11,DLEV_12,DLEV_13,DLEV_14,DLEV_15"
|
|
bitfld.long 0x04 19. "WP,Write protect switch pin level For SDIO cards only" "WP_0,WP_1"
|
|
bitfld.long 0x04 18. "CDPL,Card detect pin level This bit reflects the inverse value of the card detect input pin (MMCi_SDCD) debouncing is not performed on this bit and bit is valid only when Card State Stable 0h (R) = The value of the card detect input pin (MMCi_SDCD) is 1" "CDPL_0,CDPL_1"
|
|
newline
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bitfld.long 0x04 17. "CSS,Card State Stable This bit is used for testing" "CSS_0,CSS_1"
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bitfld.long 0x04 16. "CINS,Card inserted This bit is the debounced value of the card detect input pin (MMCi_SDCD)" "CINS_0,CINS_1"
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bitfld.long 0x04 11. "BRE,Buffer read enable This bit is used for non-DMA read transfers" "BRE_0,BRE_1"
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bitfld.long 0x04 10. "BWE,Buffer Write enable This status is used for non-DMA write transfers" "BWE_0,BWE_1"
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bitfld.long 0x04 9. "RTA,Read transfer active This status is used for detecting completion of a read transfer" "RTA_0,RTA_1"
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bitfld.long 0x04 8. "WTA,Write transfer active This status indicates a write transfer active" "WTA_0,WTA_1"
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bitfld.long 0x04 3. "RTR,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "0,1"
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bitfld.long 0x04 2. "DLA,DAT line active This status bit indicates whether one of the DAT line is in use" "DLA_0,DLA_1"
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bitfld.long 0x04 1. "DATI,Command inhibit (DAT) This status bit is generated if either DAT line is active ( 0h (R) = Issuing of command using the DAT lines is allowed. 1h (R) = Issuing of command using DAT lines is not allowed" "DATI_0,DATI_1"
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bitfld.long 0x04 0. "CMDI,Command inhibit (CMD) This status bit indicates that the CMD line is in use" "CMDI_0,CMDI_1"
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line.long 0x08 "MMCHS_HCTL,"
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bitfld.long 0x08 27. "OBWE,Wakeup event enable for 'Out-of-Band' Interrupt This bit enables wakeup events for 'Out-of-Band' assertion" "OBWE_0,OBWE_1"
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bitfld.long 0x08 26. "REM,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion" "REM_0,REM_1"
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bitfld.long 0x08 25. "INS,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion" "INS_0,INS_1"
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bitfld.long 0x08 24. "IWE,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion" "IWE_0,IWE_1"
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bitfld.long 0x08 19. "IBG,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer" "IBG_0,IBG_1"
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bitfld.long 0x08 18. "RWC,Read wait control The read wait function is optional only for SDIO cards" "RWC_0,RWC_1"
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bitfld.long 0x08 17. "CR,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap ( 0h (R/W) = No affect. 1h (R/W) = transfer restart" "CR_0,CR_1"
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bitfld.long 0x08 16. "SBGR,Stop at block gap request This bit is used to stop executing a transaction at the next block gap" "SBGR_0,SBGR_1"
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bitfld.long 0x08 9.--11. "SDVS,SD bus voltage select All cards" "SDVS_0,SDVS_1,SDVS_2,SDVS_3,SDVS_4,SDVS_5,SDVS_6,SDVS_7"
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bitfld.long 0x08 8. "SDBP,SD bus power Before setting this bit the host driver shall select the SD bus voltage ( 0h (R/W) = Power off. 1h (R/W) = Power on" "SDBP_0,SDBP_1"
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bitfld.long 0x08 7. "CDSS,Card Detect Signal Selection This bit selects source for the card detection" "CDSS_0,CDSS_1"
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bitfld.long 0x08 6. "CDTL,Card Detect Test Level This bit is enabled while 0h (R/W) = No Card" "CDTL_0,CDTL_1"
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bitfld.long 0x08 3.--4. "DMAS,DMA Select Mode One of supported DMA modes can be selected" "DMAS_0,DMAS_1,DMAS_2,DMAS_3"
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bitfld.long 0x08 2. "HSPE,High Speed Enable Before setting this bit the Host Driver shall check the 0h (R/W) = Normal speed mode" "HSPE_0,HSPE_1"
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bitfld.long 0x08 1. "DTW,Data transfer width For MMC card this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument" "DTW_0,DTW_1"
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rbitfld.long 0x08 0. "LED,Reserved bit LED control feature is not supported" "LED_0,LED_1"
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line.long 0x0C "MMCHS_SYSCTL,"
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bitfld.long 0x0C 26. "SRD,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed" "SRD_0,SRD_1"
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bitfld.long 0x0C 25. "SRC,Software reset for CMD line For more information about SRC bit manipulation see 0h (R/W) = Reset completed" "SRC_0,SRC_1"
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bitfld.long 0x0C 24. "SRA,Software reset for all This bit is set to 1 for reset and released to 0 when completed" "SRA_0,SRA_1"
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bitfld.long 0x0C 16.--19. "DTO,Data timeout counter value and busy timeout This value determines the interval by which DAT lines timeouts are detected" "DTO_0,DTO_1,DTO_2,DTO_3,DTO_4,DTO_5,DTO_6,DTO_7,DTO_8,DTO_9,DTO_10,DTO_11,DTO_12,DTO_13,DTO_14,DTO_15"
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hexmask.long.word 0x0C 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between MMC_CLK_ADPI and the output clock frequency on the CLK pin of either the memory card (MMC SD or SDIO)"
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rbitfld.long 0x0C 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit" "0,1"
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bitfld.long 0x0C 2. "CEN,Clock enable This bit controls if the clock is provided to the card or not" "CEN_0,CEN_1"
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rbitfld.long 0x0C 1. "ICS,Internal clock stable (status) This bit indicates either the internal clock is stable or not" "ICS_0,ICS_1"
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bitfld.long 0x0C 0. "ICE,Internal clock enable This bit field controls the internal clock activity" "ICE_0,ICE_1"
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line.long 0x10 "MMCHS_STAT,"
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bitfld.long 0x10 29. "BADA,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed:0h (W) = Status bit unchanged.1h (W) = Status is cleared" "BADA_0,BADA_1"
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bitfld.long 0x10 28. "CERR,Card error This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b" "CERR_0,CERR_1"
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bitfld.long 0x10 26. "TE,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select)" "0,1"
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bitfld.long 0x10 25. "ADMAE,ADMA Error This bit is set when the Host Controller detects errors during ADMA based data transfer" "ADMAE_0,ADMAE_1"
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bitfld.long 0x10 24. "ACE,Auto CMD error Auto CMD12 and Auto CMD23 use this error status" "ACE_0,ACE_1"
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bitfld.long 0x10 22. "DEB,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode.0h (W) = Status bit unchanged.1h (W) = Status is cleared" "DEB_0,DEB_1"
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bitfld.long 0x10 21. "DCRC,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command.0h (W) = Status.." "DCRC_0,DCRC_1"
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bitfld.long 0x10 20. "DTO,Data timeout error This bit is set automatically according to the following conditions:0h (W) = Status bit unchanged.1h (W) = Status is cleared" "DTO_0,DTO_1"
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bitfld.long 0x10 19. "CIE,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted" "CIE_0,CIE_1"
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bitfld.long 0x10 18. "CEB,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response.0h (W) = Status bit unchanged.1h (W) = Status is cleared" "CEB_0,CEB_1"
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bitfld.long 0x10 17. "CCRC,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in0h (W) = Status bit unchanged.1h (W) = Status is cleared" "CCRC_0,CCRC_1"
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bitfld.long 0x10 16. "CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command.0h (W) = Status bit unchanged.1h (W) = Status is cleared" "CTO_0,CTO_1"
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rbitfld.long 0x10 15. "ERRI,Error Interrupt If any of the bits in the Error Interrupt Status register ( 0h (R) = No Interrupt. 1h (R) = Error interrupt event(s) occurred" "ERRI_0,ERRI_1"
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bitfld.long 0x10 10. "BSR,Boot status received interrupt This bit is set automatically when0h (W) = Status bit unchanged.1h (W) = Status is cleared" "BSR_0,BSR_1"
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bitfld.long 0x10 9. "OBI,Out-Of-Band interrupt This bit is set automatically when0h (W) = Status bit unchanged.1h (W) = Status is cleared" "OBI_0,OBI_1"
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rbitfld.long 0x10 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards" "CIRQ_0,CIRQ_1"
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bitfld.long 0x10 7. "CREM,Card removal This bit is set automatically when0h (W) = Status bit unchanged.1h (W) = Status is cleared" "CREM_0,CREM_1"
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bitfld.long 0x10 6. "CINS,Card insertion This bit is set automatically when0h (W) = Status bit unchanged.1h (W) = Status is cleared" "CINS_0,CINS_1"
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bitfld.long 0x10 5. "BRR,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by0h (W) = Status bit unchanged.1h (W) = Status is cleared" "BRR_0,BRR_1"
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bitfld.long 0x10 4. "BWR,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by0h (W) = Status bit unchanged.1h (W) = Status is cleared" "BWR_0,BWR_1"
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bitfld.long 0x10 3. "DMA,DMA interrupt This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion.0h (W) = Status bit unchanged.1h (W) = Status is cleared" "DMA_0,DMA_1"
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bitfld.long 0x10 2. "BGE,Block gap event When a stop at block gap is requested (0h (W) = Status bit unchanged.1h (W) = Status is cleared. 0h (R) = No block gap event. 1h (R) = Transaction stopped at block gap" "BGE_0,BGE_1"
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bitfld.long 0x10 1. "TC,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (0h (W) = Status bit unchanged.1h (W) = Status is cleared. 0h (R) = No transfer.." "TC_0,TC_1"
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bitfld.long 0x10 0. "CC,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (0h (W) = Status bit unchanged.1h (W) = Status is cleared. 0h (R) = No Command complete. 1h (R) = Command complete" "CC_0,CC_1"
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line.long 0x14 "MMCHS_IE,"
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bitfld.long 0x14 29. "BADA_ENABLE,Bad access to data space Status Enable 0h (R/W) = Masked" "BADA_ENABLE_0,BADA_ENABLE_1"
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bitfld.long 0x14 28. "CERR_ENABLE,Card Error Status Enable 0h (R/W) = Masked" "CERR_ENABLE_0,CERR_ENABLE_1"
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bitfld.long 0x14 26. "TE_ENABLE,Tuning Error Status Enable 0h (R/W) = Masked" "0,1"
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bitfld.long 0x14 25. "ADMAE_ENABLE,ADMA Error Status Enable 0h (R/W) = Masked" "ADMAE_ENABLE_0,ADMAE_ENABLE_1"
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bitfld.long 0x14 24. "ACE_ENABLE,Auto CMD Error Status Enable 0h (R/W) = Masked" "ACE_ENABLE_0,ACE_ENABLE_1"
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bitfld.long 0x14 22. "DEB_ENABLE,Data End Bit Error Status Enable 0h (R/W) = Masked" "DEB_ENABLE_0,DEB_ENABLE_1"
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bitfld.long 0x14 21. "DCRC_ENABLE,Data CRC Error Status Enable 0h (R/W) = Masked" "DCRC_ENABLE_0,DCRC_ENABLE_1"
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bitfld.long 0x14 20. "DTO_ENABLE,Data Timeout Error Status Enable 0h (R/W) = The data timeout detection is deactivated" "DTO_ENABLE_0,DTO_ENABLE_1"
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bitfld.long 0x14 19. "CIE_ENABLE,Command Index Error Status Enable 0h (R/W) = Masked" "CIE_ENABLE_0,CIE_ENABLE_1"
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bitfld.long 0x14 18. "CEB_ENABLE,Command End Bit Error Status Enable 0h (R/W) = Masked" "CEB_ENABLE_0,CEB_ENABLE_1"
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bitfld.long 0x14 17. "CCRC_ENABLE,Command CRC Error Status Enable 0h (R/W) = Masked" "CCRC_ENABLE_0,CCRC_ENABLE_1"
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bitfld.long 0x14 16. "CTO_ENABLE,Command Timeout Error Status Enable 0h (R/W) = Masked" "CTO_ENABLE_0,CTO_ENABLE_1"
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rbitfld.long 0x14 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1"
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bitfld.long 0x14 10. "BSR_ENABLE,Boot Status Enable A write to this bit field when 0h (R/W) = Masked" "BSR_ENABLE_0,BSR_ENABLE_1"
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bitfld.long 0x14 9. "OBI_ENABLE,Out-of-Band Status Enable A write to this bit field when 0h (R/W) = Masked" "OBI_ENABLE_0,OBI_ENABLE_1"
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bitfld.long 0x14 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit" "CIRQ_ENABLE_0,CIRQ_ENABLE_1"
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bitfld.long 0x14 7. "CREM_ENABLE,Card Removal Status Enable 0h (R/W) = Masked" "CREM_ENABLE_0,CREM_ENABLE_1"
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bitfld.long 0x14 6. "CINS_ENABLE,Card Insertion Status Enable 0h (R/W) = Masked" "CINS_ENABLE_0,CINS_ENABLE_1"
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bitfld.long 0x14 5. "BRR_ENABLE,Buffer Read Ready Status Enable 0h (R/W) = Masked" "BRR_ENABLE_0,BRR_ENABLE_1"
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bitfld.long 0x14 4. "BWR_ENABLE,Buffer Write Ready Status Enable 0h (R/W) = Masked" "BWR_ENABLE_0,BWR_ENABLE_1"
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bitfld.long 0x14 3. "DMA_ENABLE,DMA Status Enable 0h (R/W) = Masked" "DMA_ENABLE_0,DMA_ENABLE_1"
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bitfld.long 0x14 2. "BGE_ENABLE,Block Gap Event Status Enable 0h (R/W) = Masked" "BGE_ENABLE_0,BGE_ENABLE_1"
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bitfld.long 0x14 1. "TC_ENABLE,Transfer Complete Status Enable 0h (R/W) = Masked" "TC_ENABLE_0,TC_ENABLE_1"
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bitfld.long 0x14 0. "CC_ENABLE,Command Complete Status Enable 0h (R/W) = Masked" "CC_ENABLE_0,CC_ENABLE_1"
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line.long 0x18 "MMCHS_ISE,"
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bitfld.long 0x18 29. "BADA_SIGEN,Bad access to data space Signal Enable 0h (R/W) = Masked" "BADA_SIGEN_0,BADA_SIGEN_1"
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bitfld.long 0x18 28. "CERR_SIGEN,Card Error Interrupt Signal Enable 0h (R/W) = Masked" "CERR_SIGEN_0,CERR_SIGEN_1"
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bitfld.long 0x18 26. "TE_SIGEN,Tuning Error Signal Enable 0h (R/W) = Masked" "0,1"
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bitfld.long 0x18 25. "ADMAE_SIGEN,ADMA Error Signal Enable 0h (R/W) = Masked" "ADMAE_SIGEN_0,ADMAE_SIGEN_1"
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bitfld.long 0x18 24. "ACE_SIGEN,Auto CMD Error Signal Enable 0h (R/W) = Masked" "ACE_SIGEN_0,ACE_SIGEN_1"
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bitfld.long 0x18 22. "DEB_SIGEN,Data End Bit Error Signal Enable 0h (R/W) = Masked" "DEB_SIGEN_0,DEB_SIGEN_1"
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bitfld.long 0x18 21. "DCRC_SIGEN,Data CRC Error Signal Enable 0h (R/W) = Masked" "DCRC_SIGEN_0,DCRC_SIGEN_1"
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bitfld.long 0x18 20. "DTO_SIGEN,Data Timeout Error Signal Enable 0h (R/W) = Masked" "DTO_SIGEN_0,DTO_SIGEN_1"
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bitfld.long 0x18 19. "CIE_SIGEN,Command Index Error Signal Enable 0h (R/W) = Masked" "CIE_SIGEN_0,CIE_SIGEN_1"
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bitfld.long 0x18 18. "CEB_SIGEN,Command End Bit Error Signal Enable 0h (R/W) = Masked" "CEB_SIGEN_0,CEB_SIGEN_1"
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bitfld.long 0x18 17. "CCRC_SIGEN,Command CRC Error Signal Enable 0h (R/W) = Masked" "CCRC_SIGEN_0,CCRC_SIGEN_1"
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bitfld.long 0x18 16. "CTO_SIGEN,Command timeout Error Signal Enable 0h (R/W) = Masked" "CTO_SIGEN_0,CTO_SIGEN_1"
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rbitfld.long 0x18 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1"
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bitfld.long 0x18 10. "BSR_SIGEN,Boot Status Signal Enable A write to this bit field when 0h (R/W) = Masked" "BSR_SIGEN_0,BSR_SIGEN_1"
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bitfld.long 0x18 9. "OBI_SIGEN,Out-Of-Band Interrupt Signal Enable A write to this bit field when 0h (R/W) = Masked" "OBI_SIGEN_0,OBI_SIGEN_1"
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bitfld.long 0x18 8. "CIRQ_SIGEN,Card Interrupt Signal Enable 0h (R/W) = Masked" "CIRQ_SIGEN_0,CIRQ_SIGEN_1"
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bitfld.long 0x18 7. "CREM_SIGEN,Card Removal Signal Enable 0h (R/W) = Masked" "CREM_SIGEN_0,CREM_SIGEN_1"
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bitfld.long 0x18 6. "CINS_SIGEN,Card Insertion Signal Enable 0h (R/W) = Masked" "CINS_SIGEN_0,CINS_SIGEN_1"
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bitfld.long 0x18 5. "BRR_SIGEN,Buffer Read Ready Signal Enable 0h (R/W) = Masked" "BRR_SIGEN_0,BRR_SIGEN_1"
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bitfld.long 0x18 4. "BWR_SIGEN,Buffer Write Ready Signal Enable 0h (R/W) = Masked" "BWR_SIGEN_0,BWR_SIGEN_1"
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bitfld.long 0x18 3. "DMA_SIGEN,DMA Interrupt Signal Enable 0h (R/W) = Masked" "DMA_SIGEN_0,DMA_SIGEN_1"
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bitfld.long 0x18 2. "BGE_SIGEN,Black Gap Event Signal Enable 0h (R/W) = Masked" "BGE_SIGEN_0,BGE_SIGEN_1"
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bitfld.long 0x18 1. "TC_SIGEN,Transfer Completed Status Enable 0h (R/W) = Masked" "TC_SIGEN_0,TC_SIGEN_1"
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bitfld.long 0x18 0. "CC_SIGEN,Command Complete Status Enable 0h (R/W) = Masked" "CC_SIGEN_0,CC_SIGEN_1"
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line.long 0x1C "MMCHS_AC12,"
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bitfld.long 0x1C 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit" "0,1"
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bitfld.long 0x1C 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and 0h (R/W) = Disabled" "0,1"
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bitfld.long 0x1C 23. "SCLK_SEL,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT" "0,1"
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bitfld.long 0x1C 22. "ET,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "0,1"
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bitfld.long 0x1C 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8 V signaling is selected by this bit" "0,1,2,3"
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bitfld.long 0x1C 19. "V1V8_SIGEN,1.8 V Signaling Enable This bit controls voltage regulator for I/O cell" "0,1"
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bitfld.long 0x1C 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8 V Signaling Enable is set to 1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x1C 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this bit field" "CNI_0,CNI_1"
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rbitfld.long 0x1C 4. "ACIE,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command" "ACIE_0,ACIE_1"
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rbitfld.long 0x1C 3. "ACEB,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0" "ACEB_0,ACEB_1"
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rbitfld.long 0x1C 2. "ACCE,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response" "ACCE_0,ACCE_1"
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rbitfld.long 0x1C 1. "ACTO,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command" "ACTO_0,ACTO_1"
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rbitfld.long 0x1C 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "ACNE_0,ACNE_1"
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line.long 0x20 "MMCHS_CAPA,"
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rbitfld.long 0x20 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "0,1"
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rbitfld.long 0x20 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus" "BIT64_0,BIT64_1"
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bitfld.long 0x20 26. "VS18,Voltage support 1.8 V Initialization of this bit field (via a write access to this bit field) depends on the system capabilities" "VS18_0,VS18_1"
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bitfld.long 0x20 25. "VS30,Voltage support 3.0 V Initialization of this bit field (via a write access to this bit field) depends on the system capabilities" "VS30_0,VS30_1"
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bitfld.long 0x20 24. "VS33,Voltage support 3.3 V Initialization of this bit field (via a write access to this bit field) depends on the system capabilities" "VS33_0,VS33_1"
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rbitfld.long 0x20 23. "SRS,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality" "SRS_0,SRS_1"
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rbitfld.long 0x20 22. "DS,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly" "DS_0,DS_1"
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rbitfld.long 0x20 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency" "HSS_0,HSS_1"
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rbitfld.long 0x20 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "AD2S_0,AD2S_1"
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rbitfld.long 0x20 16.--17. "MBL,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller" "MBL_0,MBL_1,MBL_2,MBL_3"
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|
hexmask.long.byte 0x20 8.--15. 1. "BCF,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock"
|
|
rbitfld.long 0x20 7. "TCU,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h (R) = KHz. 1h (R) = MHz" "TCU_0,TCU_1"
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|
newline
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rbitfld.long 0x20 0.--5. "TCF,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error ( 0h (R) = The timeout clock frequency depends on the frequency of the clock provided to the card. The value of the timeout clock frequency is not available in.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "MMCHS_CAPA2,"
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|
hexmask.long.byte 0x24 16.--23. 1. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator"
|
|
bitfld.long 0x24 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length" "0,1,2,3"
|
|
bitfld.long 0x24 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "0,1"
|
|
bitfld.long 0x24 8.--11. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x24 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling" "0,1"
|
|
bitfld.long 0x24 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling" "0,1"
|
|
bitfld.long 0x24 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling" "0,1"
|
|
bitfld.long 0x24 2. "DDR50,DDR50 Support 0h (R) = DDR50 is Not Supported" "0,1"
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|
newline
|
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bitfld.long 0x24 1. "SDR104,SDR104 Support SDR104 requires tuning" "0,1"
|
|
bitfld.long 0x24 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1" "0,1"
|
|
line.long 0x28 "MMCHS_CUR_CAPA,"
|
|
hexmask.long.byte 0x28 16.--23. 1. "CUR_1V8,Maximum current for 1.8 V 0h (R) = The maximum current capability for this voltage is not available"
|
|
hexmask.long.byte 0x28 8.--15. 1. "CUR_3V0,Maximum current for 3.0 V 0h (R) = The maximum current capability for this voltage is not available"
|
|
hexmask.long.byte 0x28 0.--7. 1. "CUR_3V3,Maximum current for 3.3 V 0h (R) = The maximum current capability for this voltage is not available"
|
|
group.long 0x250++0x0B
|
|
line.long 0x00 "MMCHS_FE,"
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bitfld.long 0x00 29. "FE_BADA,Force Event Bad access to data space 0h (W) = No effect No Interrupt" "FE_BADA_0,FE_BADA_1"
|
|
bitfld.long 0x00 28. "FE_CERR,Force Event Card error 0h (W) = No effect No Interrupt" "FE_CERR_0,FE_CERR_1"
|
|
bitfld.long 0x00 25. "FE_ADMAE,Force Event ADMA Error 0h (W) = No effect No Interrupt" "FE_ADMAE_0,FE_ADMAE_1"
|
|
bitfld.long 0x00 24. "FE_ACE,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23 0h (W) = No effect No Interrupt" "FE_ACE_0,FE_ACE_1"
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|
newline
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bitfld.long 0x00 22. "FE_DEB,Force Event Data End Bit error 0h (W) = No effect No Interrupt" "FE_DEB_0,FE_DEB_1"
|
|
bitfld.long 0x00 21. "FE_DCRC,Force Event Data CRC Error 0h (W) = No effect No Interrupt" "FE_DCRC_0,FE_DCRC_1"
|
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bitfld.long 0x00 20. "FE_DTO,Force Event Data Timeout Error 0h (W) = No effect No Interrupt" "FE_DTO_0,FE_DTO_1"
|
|
bitfld.long 0x00 19. "FE_CIE,Force Event Command Index Error 0h (W) = No effect No Interrupt" "FE_CIE_0,FE_CIE_1"
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newline
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bitfld.long 0x00 18. "FE_CEB,Force Event Command End Bit Error 0h (W) = No effect No Interrupt" "FE_CEB_0,FE_CEB_1"
|
|
bitfld.long 0x00 17. "FE_CCRC,Force Event Command CRC Error 0h (W) = No effect No Interrupt" "FE_CCRC_0,FE_CCRC_1"
|
|
bitfld.long 0x00 16. "FE_CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "FE_CTO_0,FE_CTO_1"
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bitfld.long 0x00 7. "FE_CNI,Force Event Command not issue by Auto CMD12 error 0h (W) = No effect No Interrupt" "FE_CNI_0,FE_CNI_1"
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newline
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bitfld.long 0x00 4. "FE_ACIE,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23 0h (W) = No effect No Interrupt" "FE_ACIE_0,FE_ACIE_1"
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bitfld.long 0x00 3. "FE_ACEB,Force Event Auto CMD End Bit Error 0h (W) = No effect No Interrupt" "FE_ACEB_0,FE_ACEB_1"
|
|
bitfld.long 0x00 2. "FE_ACCE,Force Event Auto CMD CRC Error 0h (W) = No effect No Interrupt" "FE_ACCE_0,FE_ACCE_1"
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bitfld.long 0x00 1. "FE_ACTO,Force Event Auto CMD Timeout Error 0h (W) = No effect No Interrupt" "FE_ACTO_0,FE_ACTO_1"
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newline
|
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bitfld.long 0x00 0. "FE_ACNE,Force Event Auto CMD12 Not Executed 0h (W) = No effect No Interrupt" "FE_ACNE_0,FE_ACNE_1"
|
|
line.long 0x04 "MMCHS_ADMAES,"
|
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bitfld.long 0x04 2. "LME,ADMA Length Mismatch Error 0h (R/W) = No Error" "LME_0,LME_1"
|
|
bitfld.long 0x04 0.--1. "AES,ADMA Error State his field indicates the state of ADMA when error is occurred during ADMA data transfer" "AES_0,AES_1,AES_2,AES_3"
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line.long 0x08 "MMCHS_ADMASAL,"
|
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rgroup.long 0x260++0x0F
|
|
line.long 0x00 "MMCHS_PVINITSD,"
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bitfld.long 0x00 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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|
bitfld.long 0x00 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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|
hexmask.long.word 0x00 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set"
|
|
bitfld.long 0x00 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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newline
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bitfld.long 0x00 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set"
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line.long 0x04 "MMCHS_PVHSSDR12,"
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bitfld.long 0x04 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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bitfld.long 0x04 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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hexmask.long.word 0x04 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set"
|
|
bitfld.long 0x04 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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newline
|
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bitfld.long 0x04 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
|
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hexmask.long.word 0x04 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set"
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line.long 0x08 "MMCHS_PVSDR25SDR50,"
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bitfld.long 0x08 30.--31. "SDR50DS_SEL,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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bitfld.long 0x08 26. "SDR50CLKGEN_SEL,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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hexmask.long.word 0x08 16.--25. 1. "SDR50SDCLK_SEL,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set"
|
|
bitfld.long 0x08 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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newline
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bitfld.long 0x08 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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hexmask.long.word 0x08 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set"
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line.long 0x0C "MMCHS_PVSDR104DDR50,"
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bitfld.long 0x0C 30.--31. "DDR50DS_SEL,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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bitfld.long 0x0C 26. "DDR50CLKGEN_SEL,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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hexmask.long.word 0x0C 16.--25. 1. "DDR50SDCLK_SEL,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set"
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|
bitfld.long 0x0C 14.--15. "SDR104DS_SEL,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8 V signaling bus speed modes" "0,1,2,3"
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newline
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bitfld.long 0x0C 10. "SDR104CLKGEN_SEL,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator" "0,1"
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hexmask.long.word 0x0C 0.--9. 1. "SDR104SDCLK_SEL,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set"
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rgroup.long 0x2FC++0x03
|
|
line.long 0x00 "MMCHS_REV,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "VREV,Vendor Version Number: MMC revision [7-4] Major revision"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec"
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|
bitfld.long 0x00 0. "SIS,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module" "SIS_0,SIS_1"
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|
repeat 4. (list 10. 32. 54. 76. )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0x210)++0x03
|
|
line.long 0x00 "MMCHS_RSP$1,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RSP1,Command Response [31:16]"
|
|
hexmask.long.word 0x00 0.--15. 1. "RSP0,Command Response [15:0]"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
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repeat.end
|
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tree.end
|
|
tree "PRU_ICSS"
|
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tree "PRU_ICSS_0_CFG"
|
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base ad:0x20AA6000
|
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rgroup.long 0x00++0x03
|
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line.long 0x00 "PRUSS_REVID,"
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|
group.long 0x08++0x0B
|
|
line.long 0x00 "PRUSS_GPCFG0,"
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|
rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 26.--29. "PR1_PRU0_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 25. "PRU0_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
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|
bitfld.long 0x00 20.--24. "PRU0_GPO_DIV1,Divisor value (divide by PRU0_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
|
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bitfld.long 0x00 15.--19. "PRU0_GPO_DIV0,Divisor value (divide by PRU0_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14. "PRU0_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x00 13. "PRU0_GPI_SB,Start Bit event for 28-bit shift mode" "0,1"
|
|
bitfld.long 0x00 8.--12. "PRU0_GPI_DIV1,Divisor value (divide by PRU0_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 3.--7. "PRU0_GPI_DIV0,Divisor value (divide by PRU0_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 2. "PRU0_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x00 0.--1. "PRU0_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_GPCFG1,"
|
|
rbitfld.long 0x04 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x04 26.--29. "PR1_PRU1_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 25. "PRU1_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x04 20.--24. "PRU1_GPO_DIV1,Divisor value (divide by PRU1_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 15.--19. "PRU1_GPO_DIV0,Divisor value (divide by PRU1_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. "PRU1_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x04 13. "PRU1_GPI_SB,28-bit shift mode Start Bit event" "0,1"
|
|
bitfld.long 0x04 8.--12. "PRU1_GPI_DIV1,Divisor value (divide by PRU1_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 3.--7. "PRU1_GPI_DIV0,Divisor value (divide by PRU1_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 2. "PRU1_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x04 0.--1. "PRU1_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_CGR,"
|
|
bitfld.long 0x08 31. "ICSS_STOP_ACK,Acknowledgement that ICSS clock can be stopped" "0,1"
|
|
rbitfld.long 0x08 30. "ICSS_STOP_REQ,ICSS request to stop clock" "0,1"
|
|
hexmask.long.word 0x08 18.--29. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 17. "IEP_CLK_EN,IEP clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 16. "IEP_CLK_STOP_ACK,Acknowledgement that IEP clock can be stopped" "0,1"
|
|
bitfld.long 0x08 15. "IEP_CLK_STOP_REQ,IEP request to stop clock" "0,1"
|
|
bitfld.long 0x08 14. "ECAP_CLK_EN,ECAP clock enable" "0,1"
|
|
rbitfld.long 0x08 13. "ECAP_CLK_STOP_ACK,Acknowledgement that ECAP clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "ECAP_CLK_STOP_REQ,ECAP request to stop clock" "0,1"
|
|
bitfld.long 0x08 11. "UART_CLK_EN,UART clock enable" "0,1"
|
|
rbitfld.long 0x08 10. "UART_CLK_STOP_ACK,Acknowledgement that UART clock can be stopped" "0,1"
|
|
bitfld.long 0x08 9. "UART_CLK_STOP_REQ,UART request to stop clock" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "PRUSS_INTC_CLK_EN,PRUSS_INTC clock enable" "0,1"
|
|
rbitfld.long 0x08 7. "PRUSS_INTC_CLK_STOP_ACK,Acknowledgement that PRUSS_INTC clock can be stopped" "0,1"
|
|
bitfld.long 0x08 6. "PRUSS_INTC_CLK_STOP_REQ,PRUSS_INTC request to stop clock" "0,1"
|
|
bitfld.long 0x08 5. "PRU1_CLK_EN,PRU1 clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 4. "PRU1_CLK_STOP_ACK,Acknowledgement that PRU1 clock can be stopped" "0,1"
|
|
bitfld.long 0x08 3. "PRU1_CLK_STOP_REQ,PRU1 request to stop clock" "0,1"
|
|
bitfld.long 0x08 2. "PRU0_CLK_EN,PRU0 clock enable" "0,1"
|
|
rbitfld.long 0x08 1. "PRU0_CLK_STOP_ACK,Acknowledgement that PRU0 clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PRU0_CLK_STOP_REQ,PRU0 request to stop clock" "0,1"
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "PRUSS_PMAO,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 1. "PMAO_PRU1,PRU1 Master Port Address Offset Enable" "0,1"
|
|
bitfld.long 0x00 0. "PMAO_PRU0,PRU0 Master Port Address Offset Enable" "0,1"
|
|
line.long 0x04 "PRUSS_MII_RT,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "MII_RT_EVENT_EN,Enables the MII_RT Events to the PRU-ICSS_INTC" "0,1"
|
|
line.long 0x08 "PRUSS_IEPCLK,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0. "OCP_EN,IEP clock source" "0,1"
|
|
line.long 0x0C "PRUSS_SPP,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 1. "XFR_SHIFT_EN,Enables XIN XOUT shift functionality" "0,1"
|
|
bitfld.long 0x0C 0. "PRU1_PAD_HP_EN,Defines which PRU wins write cycle arbitration to a common scratch pad bank" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PRUSS_PIN_MX,"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 10.--11. "PWM3_REMAP_EN,Remaps the eHRPWM3_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
bitfld.long 0x00 8.--9. "PWM0_REMAP_EN,Remaps the eHRPWM0_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED,Reserved"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_CFG"
|
|
base ad:0x20AE6000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PRUSS_REVID,"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PRUSS_GPCFG0,"
|
|
rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 26.--29. "PR1_PRU0_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 25. "PRU0_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x00 20.--24. "PRU0_GPO_DIV1,Divisor value (divide by PRU0_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15.--19. "PRU0_GPO_DIV0,Divisor value (divide by PRU0_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. "PRU0_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x00 13. "PRU0_GPI_SB,Start Bit event for 28-bit shift mode" "0,1"
|
|
bitfld.long 0x00 8.--12. "PRU0_GPI_DIV1,Divisor value (divide by PRU0_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "PRU0_GPI_DIV0,Divisor value (divide by PRU0_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 2. "PRU0_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x00 0.--1. "PRU0_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_GPCFG1,"
|
|
rbitfld.long 0x04 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x04 26.--29. "PR1_PRU1_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 25. "PRU1_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x04 20.--24. "PRU1_GPO_DIV1,Divisor value (divide by PRU1_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 15.--19. "PRU1_GPO_DIV0,Divisor value (divide by PRU1_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. "PRU1_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x04 13. "PRU1_GPI_SB,28-bit shift mode Start Bit event" "0,1"
|
|
bitfld.long 0x04 8.--12. "PRU1_GPI_DIV1,Divisor value (divide by PRU1_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 3.--7. "PRU1_GPI_DIV0,Divisor value (divide by PRU1_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 2. "PRU1_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x04 0.--1. "PRU1_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_CGR,"
|
|
bitfld.long 0x08 31. "ICSS_STOP_ACK,Acknowledgement that ICSS clock can be stopped" "0,1"
|
|
rbitfld.long 0x08 30. "ICSS_STOP_REQ,ICSS request to stop clock" "0,1"
|
|
hexmask.long.word 0x08 18.--29. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 17. "IEP_CLK_EN,IEP clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 16. "IEP_CLK_STOP_ACK,Acknowledgement that IEP clock can be stopped" "0,1"
|
|
bitfld.long 0x08 15. "IEP_CLK_STOP_REQ,IEP request to stop clock" "0,1"
|
|
bitfld.long 0x08 14. "ECAP_CLK_EN,ECAP clock enable" "0,1"
|
|
rbitfld.long 0x08 13. "ECAP_CLK_STOP_ACK,Acknowledgement that ECAP clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "ECAP_CLK_STOP_REQ,ECAP request to stop clock" "0,1"
|
|
bitfld.long 0x08 11. "UART_CLK_EN,UART clock enable" "0,1"
|
|
rbitfld.long 0x08 10. "UART_CLK_STOP_ACK,Acknowledgement that UART clock can be stopped" "0,1"
|
|
bitfld.long 0x08 9. "UART_CLK_STOP_REQ,UART request to stop clock" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "PRUSS_INTC_CLK_EN,PRUSS_INTC clock enable" "0,1"
|
|
rbitfld.long 0x08 7. "PRUSS_INTC_CLK_STOP_ACK,Acknowledgement that PRUSS_INTC clock can be stopped" "0,1"
|
|
bitfld.long 0x08 6. "PRUSS_INTC_CLK_STOP_REQ,PRUSS_INTC request to stop clock" "0,1"
|
|
bitfld.long 0x08 5. "PRU1_CLK_EN,PRU1 clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 4. "PRU1_CLK_STOP_ACK,Acknowledgement that PRU1 clock can be stopped" "0,1"
|
|
bitfld.long 0x08 3. "PRU1_CLK_STOP_REQ,PRU1 request to stop clock" "0,1"
|
|
bitfld.long 0x08 2. "PRU0_CLK_EN,PRU0 clock enable" "0,1"
|
|
rbitfld.long 0x08 1. "PRU0_CLK_STOP_ACK,Acknowledgement that PRU0 clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PRU0_CLK_STOP_REQ,PRU0 request to stop clock" "0,1"
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "PRUSS_PMAO,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 1. "PMAO_PRU1,PRU1 Master Port Address Offset Enable" "0,1"
|
|
bitfld.long 0x00 0. "PMAO_PRU0,PRU0 Master Port Address Offset Enable" "0,1"
|
|
line.long 0x04 "PRUSS_MII_RT,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "MII_RT_EVENT_EN,Enables the MII_RT Events to the PRU-ICSS_INTC" "0,1"
|
|
line.long 0x08 "PRUSS_IEPCLK,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0. "OCP_EN,IEP clock source" "0,1"
|
|
line.long 0x0C "PRUSS_SPP,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 1. "XFR_SHIFT_EN,Enables XIN XOUT shift functionality" "0,1"
|
|
bitfld.long 0x0C 0. "PRU1_PAD_HP_EN,Defines which PRU wins write cycle arbitration to a common scratch pad bank" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PRUSS_PIN_MX,"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 10.--11. "PWM3_REMAP_EN,Remaps the eHRPWM3_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
bitfld.long 0x00 8.--9. "PWM0_REMAP_EN,Remaps the eHRPWM0_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED,Reserved"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_ECAP"
|
|
base ad:0x20AB0000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_ECAP_TSCNT,"
|
|
line.long 0x04 "PRUSS_ECAP_CNTPHS,"
|
|
line.long 0x08 "PRUSS_ECAP_CAP1,"
|
|
line.long 0x0C "PRUSS_ECAP_CAP2,"
|
|
line.long 0x10 "PRUSS_ECAP_CAP3,"
|
|
line.long 0x14 "PRUSS_ECAP_CAP4,"
|
|
group.word 0x28++0x09
|
|
line.word 0x00 "PRUSS_ECAP_ECCTL1,"
|
|
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. "CAPLDEN,Enable Loading of" "0,1"
|
|
bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x02 "PRUSS_ECAP_ECCTL2,"
|
|
rbitfld.word 0x02 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 10. "APWMPOL," "0,1"
|
|
bitfld.word 0x02 9. "CAPAPWM," "0,1"
|
|
bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1"
|
|
bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3"
|
|
bitfld.word 0x02 5. "SYNCI_EN," "0,1"
|
|
bitfld.word 0x02 4. "TSCNTSTP," "0,1"
|
|
bitfld.word 0x02 3. "REARMRESET," "0,1"
|
|
bitfld.word 0x02 1.--2. "STOPVALUE," "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x02 0. "CONTONESHT," "0,1"
|
|
line.word 0x04 "PRUSS_ECAP_ECEINT,"
|
|
hexmask.word.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x04 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x04 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x04 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x04 4. "CEVT4," "0,1"
|
|
bitfld.word 0x04 3. "CEVT3," "0,1"
|
|
bitfld.word 0x04 2. "CEVT2," "0,1"
|
|
bitfld.word 0x04 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x04 0. "RESERVED,Reserved" "0,1"
|
|
line.word 0x06 "PRUSS_ECAP_ECFLG,"
|
|
hexmask.word.byte 0x06 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x06 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x06 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x06 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x06 4. "CEVT4," "0,1"
|
|
bitfld.word 0x06 3. "CEVT3," "0,1"
|
|
bitfld.word 0x06 2. "CEVT2," "0,1"
|
|
bitfld.word 0x06 1. "CEVT1," "0,1"
|
|
bitfld.word 0x06 0. "INT," "0,1"
|
|
line.word 0x08 "PRUSS_ECAP_ECCLR,"
|
|
hexmask.word.byte 0x08 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x08 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x08 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x08 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x08 4. "CEVT4," "0,1"
|
|
bitfld.word 0x08 3. "CEVT3," "0,1"
|
|
bitfld.word 0x08 2. "CEVT2," "0,1"
|
|
bitfld.word 0x08 1. "CEVT1," "0,1"
|
|
bitfld.word 0x08 0. "INT," "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PRUSS_ECAP_ECFRC,"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x00 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x00 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x00 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x00 4. "CEVT4," "0,1"
|
|
bitfld.word 0x00 3. "CEVT3," "0,1"
|
|
bitfld.word 0x00 2. "CEVT2," "0,1"
|
|
bitfld.word 0x00 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x00 0. "RESERVED,Reserved" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "PRUSS_ECAP_PID,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_ECAP"
|
|
base ad:0x20AF0000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_ECAP_TSCNT,"
|
|
line.long 0x04 "PRUSS_ECAP_CNTPHS,"
|
|
line.long 0x08 "PRUSS_ECAP_CAP1,"
|
|
line.long 0x0C "PRUSS_ECAP_CAP2,"
|
|
line.long 0x10 "PRUSS_ECAP_CAP3,"
|
|
line.long 0x14 "PRUSS_ECAP_CAP4,"
|
|
group.word 0x28++0x09
|
|
line.word 0x00 "PRUSS_ECAP_ECCTL1,"
|
|
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. "CAPLDEN,Enable Loading of" "0,1"
|
|
bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x02 "PRUSS_ECAP_ECCTL2,"
|
|
rbitfld.word 0x02 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 10. "APWMPOL," "0,1"
|
|
bitfld.word 0x02 9. "CAPAPWM," "0,1"
|
|
bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1"
|
|
bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3"
|
|
bitfld.word 0x02 5. "SYNCI_EN," "0,1"
|
|
bitfld.word 0x02 4. "TSCNTSTP," "0,1"
|
|
bitfld.word 0x02 3. "REARMRESET," "0,1"
|
|
bitfld.word 0x02 1.--2. "STOPVALUE," "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x02 0. "CONTONESHT," "0,1"
|
|
line.word 0x04 "PRUSS_ECAP_ECEINT,"
|
|
hexmask.word.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x04 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x04 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x04 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x04 4. "CEVT4," "0,1"
|
|
bitfld.word 0x04 3. "CEVT3," "0,1"
|
|
bitfld.word 0x04 2. "CEVT2," "0,1"
|
|
bitfld.word 0x04 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x04 0. "RESERVED,Reserved" "0,1"
|
|
line.word 0x06 "PRUSS_ECAP_ECFLG,"
|
|
hexmask.word.byte 0x06 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x06 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x06 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x06 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x06 4. "CEVT4," "0,1"
|
|
bitfld.word 0x06 3. "CEVT3," "0,1"
|
|
bitfld.word 0x06 2. "CEVT2," "0,1"
|
|
bitfld.word 0x06 1. "CEVT1," "0,1"
|
|
bitfld.word 0x06 0. "INT," "0,1"
|
|
line.word 0x08 "PRUSS_ECAP_ECCLR,"
|
|
hexmask.word.byte 0x08 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x08 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x08 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x08 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x08 4. "CEVT4," "0,1"
|
|
bitfld.word 0x08 3. "CEVT3," "0,1"
|
|
bitfld.word 0x08 2. "CEVT2," "0,1"
|
|
bitfld.word 0x08 1. "CEVT1," "0,1"
|
|
bitfld.word 0x08 0. "INT," "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PRUSS_ECAP_ECFRC,"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x00 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x00 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x00 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x00 4. "CEVT4," "0,1"
|
|
bitfld.word 0x00 3. "CEVT3," "0,1"
|
|
bitfld.word 0x00 2. "CEVT2," "0,1"
|
|
bitfld.word 0x00 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x00 0. "RESERVED,Reserved" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "PRUSS_ECAP_PID,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_ECC_CFG"
|
|
base ad:0x20AA7000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "ECC_VECTOR,"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status to indicate if read on the serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
rbitfld.long 0x00 11.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,Value written to select the corresponding ECC RAM for control or status"
|
|
line.long 0x04 "ECC_MISC_STATUS,"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
|
|
line.long 0x08 "ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "ECC_CONTROL,"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/ FORCE_DED will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Column/ Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where FORCE_SEC or FORCE_DED needs to be applied"
|
|
line.long 0x14 "ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when FORCE_DED is set"
|
|
line.long 0x18 "ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
rbitfld.long 0x18 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,1 indicates a successive single-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
rbitfld.long 0x18 3.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 2. "ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,1 indicates pending double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "ECC_SEC,1 indicates pending single-bit error status" "0,1"
|
|
line.long 0x1C "ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the bit position in the RAM data that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "ECC_EOI,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "ECC_INT_STATUS_0,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_STATUS_1,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_STATUS_2,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_STATUS_3,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_STATUS_4,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_STATUS_5,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_STATUS_6,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_STATUS_7,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_STATUS_8,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_STATUS_9,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_STATUS_10,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_STATUS_11,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_STATUS_12,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_STATUS_13,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x3C "ECC_INT_STATUS_14,"
|
|
hexmask.long 0x3C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x3C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "ECC_INT_ENABLE_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_ENABLE_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_ENABLE_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_ENABLE_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_ENABLE_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_ENABLE_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_ENABLE_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_ENABLE_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_ENABLE_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_ENABLE_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_ENABLE_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_ENABLE_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_ENABLE_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_ENABLE_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_ENABLE_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "ECC_INT_CLEAR_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_CLEAR_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_CLEAR_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_CLEAR_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_CLEAR_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_CLEAR_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_CLEAR_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_CLEAR_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_CLEAR_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_CLEAR_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_CLEAR_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_CLEAR_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_CLEAR_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_CLEAR_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_CLEAR_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_ECC_CFG"
|
|
base ad:0x20AE7000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "ECC_VECTOR,"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status to indicate if read on the serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
rbitfld.long 0x00 11.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,Value written to select the corresponding ECC RAM for control or status"
|
|
line.long 0x04 "ECC_MISC_STATUS,"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
|
|
line.long 0x08 "ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "ECC_CONTROL,"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/ FORCE_DED will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Column/ Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where FORCE_SEC or FORCE_DED needs to be applied"
|
|
line.long 0x14 "ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when FORCE_DED is set"
|
|
line.long 0x18 "ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
rbitfld.long 0x18 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,1 indicates a successive single-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
rbitfld.long 0x18 3.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 2. "ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,1 indicates pending double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "ECC_SEC,1 indicates pending single-bit error status" "0,1"
|
|
line.long 0x1C "ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the bit position in the RAM data that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "ECC_EOI,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "ECC_INT_STATUS_0,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_STATUS_1,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_STATUS_2,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_STATUS_3,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_STATUS_4,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_STATUS_5,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_STATUS_6,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_STATUS_7,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_STATUS_8,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_STATUS_9,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_STATUS_10,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_STATUS_11,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_STATUS_12,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_STATUS_13,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x3C "ECC_INT_STATUS_14,"
|
|
hexmask.long 0x3C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x3C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "ECC_INT_ENABLE_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_ENABLE_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_ENABLE_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_ENABLE_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_ENABLE_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_ENABLE_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_ENABLE_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_ENABLE_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_ENABLE_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_ENABLE_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_ENABLE_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_ENABLE_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_ENABLE_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_ENABLE_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_ENABLE_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "ECC_INT_CLEAR_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_CLEAR_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_CLEAR_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_CLEAR_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_CLEAR_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_CLEAR_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_CLEAR_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_CLEAR_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_CLEAR_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_CLEAR_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_CLEAR_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_CLEAR_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_CLEAR_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_CLEAR_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_CLEAR_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_IEP"
|
|
base ad:0x20AAE000
|
|
group.long 0x00++0x57
|
|
line.long 0x00 "PRUSS_IEP_GLOBAL_CFG,"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,Defines the increment value when compensation is active"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DEFAULT_INC,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "CNT_ENABLE,Counter enable" "Disables the counter,Enables the counter"
|
|
line.long 0x04 "PRUSS_IEP_STATUS,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CNT_OVF,Counter overflow status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_COMPENSATION,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "COMPEN_CNT,Compensation counter"
|
|
line.long 0x0C "PRUSS_IEP_SLOW_COMPENSATION,"
|
|
line.long 0x10 "PRUSS_IEP_LOW_COUNTER,"
|
|
line.long 0x14 "PRUSS_IEP_HIGH_COUNTER,"
|
|
line.long 0x18 "PRUSS_IEP_CAPTURE_CFG,"
|
|
hexmask.long.word 0x18 18.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x18 10.--17. "CAP_ASYNC_EN,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable" "0x00=Disable synchronization,0x01=Enable synchronization"
|
|
newline
|
|
bitfld.long 0x18 9. "CAP7F_1ST_EVENT_EN,Capture 1st Event Enable for CAP7F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 8. "CAP7R_1ST_EVENT_EN,Capture 1st Event Enable for CAP7R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 7. "CAP6F_1ST_EVENT_EN,Capture 1st Event Enable for CAP6F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 6. "CAP6R_1ST_EVENT_EN,Capture 1st Event Enable for CAP6R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 0.--5. "CAP_1ST_EVENT_EN,Capture 1st Event Enable for registers" "Continues mode,First Event mode,?..."
|
|
line.long 0x1C "PRUSS_IEP_CAPTURE_STATUS,"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x1C 16.--23. "CAP_RAW,Raw/Current status bit for each of the capture registers where CAP_RAW[n] maps to CAPR[n]" "0x00=Current state is low,0x01=Current state is high"
|
|
newline
|
|
bitfld.long 0x1C 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x1C 10. "CAP_VALID,Valid status for capture function" "No Hit for any capture event i.e,Hit for 1 or more captures events is pending i.e"
|
|
newline
|
|
bitfld.long 0x1C 9. "CAPF7_VALID,Valid status for CAPF7 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 8. "CAPR7_VALID,Valid status for CAPR7 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 7. "CAPF6_VALID,Valid status for CAPF6 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 6. "CAPR6_VALID,Valid status for CAPR6 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. "CAPR_VALID,Valid status bit for each compare register where CAPR_VALID[n] maps to CAPR[n] (rise)" "No Hit no capture event occurred,Hit capture event occurred,?..."
|
|
line.long 0x20 "PRUSS_IEP_CAPTURE_RISE00,"
|
|
line.long 0x24 "PRUSS_IEP_CAPTURE_RISE10,"
|
|
line.long 0x28 "PRUSS_IEP_CAPTURE_RISE01,"
|
|
line.long 0x2C "PRUSS_IEP_CAPTURE_RISE11,"
|
|
line.long 0x30 "PRUSS_IEP_CAPTURE_RISE02,"
|
|
line.long 0x34 "PRUSS_IEP_CAPTURE_RISE12,"
|
|
line.long 0x38 "PRUSS_IEP_CAPTURE_RISE03,"
|
|
line.long 0x3C "PRUSS_IEP_CAPTURE_RISE13,"
|
|
line.long 0x40 "PRUSS_IEP_CAPTURE_RISE04,"
|
|
line.long 0x44 "PRUSS_IEP_CAPTURE_RISE14,"
|
|
line.long 0x48 "PRUSS_IEP_CAPTURE_RISE05,"
|
|
line.long 0x4C "PRUSS_IEP_CAPTURE_RISE15,"
|
|
line.long 0x50 "PRUSS_IEP_CAPTURE_RISE06,"
|
|
line.long 0x54 "PRUSS_IEP_CAPTURE_RISE16,"
|
|
rgroup.long 0x60++0xAB
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_RISE07,"
|
|
line.long 0x04 "PRUSS_IEP_CAPTURE_RISE17,"
|
|
line.long 0x08 "PRUSS_IEP_CAPTURE_FALL07,"
|
|
line.long 0x0C "PRUSS_IEP_CAPTURE_FALL17,"
|
|
line.long 0x10 "PRUSS_IEP_COMPARE_CFG,"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x10 1.--16. 1. "CMP_EN,Enable bits for each of the compare registers"
|
|
newline
|
|
bitfld.long 0x10 0. "CMP0_RST_CNT_EN,Enable the reset of the counter" "0,1"
|
|
line.long 0x14 "PRUSS_IEP_COMPARE_STATUS,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP_HIT,Status bit for each of the compare registers"
|
|
line.long 0x18 "PRUSS_IEP_COMPARE00,"
|
|
line.long 0x1C "PRUSS_IEP_COMPARE10,"
|
|
line.long 0x20 "PRUSS_IEP_COMPARE01,"
|
|
line.long 0x24 "PRUSS_IEP_COMPARE11,"
|
|
line.long 0x28 "PRUSS_IEP_COMPARE02,"
|
|
line.long 0x2C "PRUSS_IEP_COMPARE12,"
|
|
line.long 0x30 "PRUSS_IEP_COMPARE03,"
|
|
line.long 0x34 "PRUSS_IEP_COMPARE13,"
|
|
line.long 0x38 "PRUSS_IEP_COMPARE04,"
|
|
line.long 0x3C "PRUSS_IEP_COMPARE14,"
|
|
line.long 0x40 "PRUSS_IEP_COMPARE05,"
|
|
line.long 0x44 "PRUSS_IEP_COMPARE15,"
|
|
line.long 0x48 "PRUSS_IEP_COMPARE06,"
|
|
line.long 0x4C "PRUSS_IEP_COMPARE16,"
|
|
line.long 0x50 "PRUSS_IEP_COMPARE07,"
|
|
line.long 0x54 "PRUSS_IEP_COMPARE17,"
|
|
line.long 0x58 "PRUSS_IEP_RXIPG0,"
|
|
hexmask.long.word 0x58 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x58 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x5C "PRUSS_IEP_RXIPG1,"
|
|
hexmask.long.word 0x5C 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x5C 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x60 "PRUSS_IEP_COMPARE08,"
|
|
line.long 0x64 "PRUSS_IEP_COMPARE18,"
|
|
line.long 0x68 "PRUSS_IEP_COMPARE09,"
|
|
line.long 0x6C "PRUSS_IEP_COMPARE19,"
|
|
line.long 0x70 "PRUSS_IEP_COMPARE010,"
|
|
line.long 0x74 "PRUSS_IEP_COMPARE110,"
|
|
line.long 0x78 "PRUSS_IEP_COMPARE011,"
|
|
line.long 0x7C "PRUSS_IEP_COMPARE111,"
|
|
line.long 0x80 "PRUSS_IEP_COMPARE012,"
|
|
line.long 0x84 "PRUSS_IEP_COMPARE112,"
|
|
line.long 0x88 "PRUSS_IEP_COMPARE013,"
|
|
line.long 0x8C "PRUSS_IEP_COMPARE113,"
|
|
line.long 0x90 "PRUSS_IEP_COMPARE014,"
|
|
line.long 0x94 "PRUSS_IEP_COMPARE114,"
|
|
line.long 0x98 "PRUSS_IEP_COMPARE015,"
|
|
line.long 0x9C "PRUSS_IEP_COMPARE115,"
|
|
line.long 0xA0 "PRUSS_IEP_LOW_COUNTER_RESET_VALUE,"
|
|
line.long 0xA4 "PRUSS_IEP_HIGH_COUNTER_RESET_VALUE,"
|
|
line.long 0xA8 "PRUSS_IEP_PWM,"
|
|
hexmask.long 0xA8 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0xA8 3. "PWM3_HIT,The raw status bit of eHRPWM3_SYNCO event" "No eHRPWM3_SYNCO event,eHRPWM3_SYNCO event occurred Write 1h to Clear"
|
|
newline
|
|
bitfld.long 0xA8 2. "PWM3_RST_CNT_EN,Enable the reset of the counter by a eHRPWM3_SYNCO event" "Disable,Enable the reset of.."
|
|
newline
|
|
bitfld.long 0xA8 1. "PWM0_HIT,The raw status bit of eHRPWM0_SYNCO event" "No eHRPWM0_SYNCO event,eHRPWM0_SYNCO event occurred Write 1 to Clear"
|
|
newline
|
|
bitfld.long 0xA8 0. "PWM0_RST_CNT_EN,Enable the reset of the counter by a eHRPWM0_SYNCO event" "Disable,Enable the reset of.."
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "PRUSS_IEP_SYNC_CTRL,"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SYNC1_IND_EN,SYNC1 independent mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SYNC1_ACK_EN,SYNC1 acknowledgement mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SYNC0_ACK_EN,SYNC0 acknowledgement mode enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SYNC1_EN,SYNC1 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNC0_EN,SYNC0 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SYNC_EN,SYNC generation enable" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_SYNC_FIRST_STAT,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "FIRST_SYNC1,SYNC1 First Event status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "FIRST_SYNC0,SYNC0 First Event status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_SYNC0_STAT,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "SYNC0_PEND,SYNC0 pending state" "0,1"
|
|
line.long 0x0C "PRUSS_IEP_SYNC1_STAT,"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "SYNC1_PEND,SYNC1 pending state" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_SYNC_PWIDTH,"
|
|
line.long 0x14 "PRUSS_IEP_SYNC0_PERIOD,"
|
|
line.long 0x18 "PRUSS_IEP_SYNC1_DELAY,"
|
|
line.long 0x1C "PRUSS_IEP_SYNC_START,"
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "PRUSS_IEP_WD_PREDIV,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,Defines the number of ICSS_IEP_CLK cycles per WD clock event"
|
|
line.long 0x04 "PRUSS_IEP_PDI_WD_TIM,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,Defines the number of WD ticks (or increments) for PDI WD that is the number of WD increments"
|
|
line.long 0x08 "PRUSS_IEP_PD_WD_TIM,"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,Defines the number of WD ticks (or increments) for PD WD that is the number of WD increments"
|
|
line.long 0x0C "PRUSS_IEP_WD_STATUS,"
|
|
hexmask.long.word 0x0C 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 16. "PDI_WD_STAT,WD PDI status" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "PD_WD_STAT,WD PD status (triggered by Sync Mangers status)" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_WD_EXP_CNT,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,WD PD expiration counter"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,WD PDI expiration counter"
|
|
line.long 0x14 "PRUSS_IEP_WD_CTRL,"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 16. "PDI_WD_EN,Watchdog PDI" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "PD_WD_EN,Watchdog PD" "0,1"
|
|
group.long 0x300++0x1B
|
|
line.long 0x00 "PRUSS_IEP_DIGIO_CTRL,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OUT_MODE,Defines events that triggers data out to be updated" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IN_MODE,Defines event that triggers data in to be sampled" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "WD_MODE,Defines Watchdog behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2. "BIDI_MODE,Defines the digital input/output direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUTVALID_MODE,Defines the outvalid mode behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "OUTVALID_POL,Defines OUTVALID polarity" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_DIGIO_STATUS,"
|
|
line.long 0x08 "PRUSS_IEP_DIGIO_DATA_IN,"
|
|
line.long 0x0C "PRUSS_IEP_DIGIO_DATA_IN_RAW,"
|
|
line.long 0x10 "PRUSS_IEP_DIGIO_DATA_OUT,"
|
|
line.long 0x14 "PRUSS_IEP_DIGIO_DATA_OUT_EN,"
|
|
line.long 0x18 "PRUSS_IEP_DIGIO_EXP,"
|
|
hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x18 13. "EOF_SEL,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "SOF_SEL,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "SOF_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 4.--7. "OUTVALID_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "SW_OUTVALID,PR<k>_EDIO_OUTVALID = SW_OUTVALID only if OUTVALID_OVR_EN is set" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "OUTVALID_OVR_EN,Software override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "SW_DATA_OUT_UPDATE,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1" "0,1"
|
|
repeat 2. (list 06. 16. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x58)++0x03
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_FALL$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_IEP"
|
|
base ad:0x20AEE000
|
|
group.long 0x00++0x57
|
|
line.long 0x00 "PRUSS_IEP_GLOBAL_CFG,"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,Defines the increment value when compensation is active"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DEFAULT_INC,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "CNT_ENABLE,Counter enable" "Disables the counter,Enables the counter"
|
|
line.long 0x04 "PRUSS_IEP_STATUS,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CNT_OVF,Counter overflow status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_COMPENSATION,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "COMPEN_CNT,Compensation counter"
|
|
line.long 0x0C "PRUSS_IEP_SLOW_COMPENSATION,"
|
|
line.long 0x10 "PRUSS_IEP_LOW_COUNTER,"
|
|
line.long 0x14 "PRUSS_IEP_HIGH_COUNTER,"
|
|
line.long 0x18 "PRUSS_IEP_CAPTURE_CFG,"
|
|
hexmask.long.word 0x18 18.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x18 10.--17. "CAP_ASYNC_EN,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable" "0x00=Disable synchronization,0x01=Enable synchronization"
|
|
newline
|
|
bitfld.long 0x18 9. "CAP7F_1ST_EVENT_EN,Capture 1st Event Enable for CAP7F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 8. "CAP7R_1ST_EVENT_EN,Capture 1st Event Enable for CAP7R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 7. "CAP6F_1ST_EVENT_EN,Capture 1st Event Enable for CAP6F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 6. "CAP6R_1ST_EVENT_EN,Capture 1st Event Enable for CAP6R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 0.--5. "CAP_1ST_EVENT_EN,Capture 1st Event Enable for registers" "Continues mode,First Event mode,?..."
|
|
line.long 0x1C "PRUSS_IEP_CAPTURE_STATUS,"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x1C 16.--23. "CAP_RAW,Raw/Current status bit for each of the capture registers where CAP_RAW[n] maps to CAPR[n]" "0x00=Current state is low,0x01=Current state is high"
|
|
newline
|
|
bitfld.long 0x1C 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x1C 10. "CAP_VALID,Valid status for capture function" "No Hit for any capture event i.e,Hit for 1 or more captures events is pending i.e"
|
|
newline
|
|
bitfld.long 0x1C 9. "CAPF7_VALID,Valid status for CAPF7 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 8. "CAPR7_VALID,Valid status for CAPR7 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 7. "CAPF6_VALID,Valid status for CAPF6 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 6. "CAPR6_VALID,Valid status for CAPR6 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. "CAPR_VALID,Valid status bit for each compare register where CAPR_VALID[n] maps to CAPR[n] (rise)" "No Hit no capture event occurred,Hit capture event occurred,?..."
|
|
line.long 0x20 "PRUSS_IEP_CAPTURE_RISE00,"
|
|
line.long 0x24 "PRUSS_IEP_CAPTURE_RISE10,"
|
|
line.long 0x28 "PRUSS_IEP_CAPTURE_RISE01,"
|
|
line.long 0x2C "PRUSS_IEP_CAPTURE_RISE11,"
|
|
line.long 0x30 "PRUSS_IEP_CAPTURE_RISE02,"
|
|
line.long 0x34 "PRUSS_IEP_CAPTURE_RISE12,"
|
|
line.long 0x38 "PRUSS_IEP_CAPTURE_RISE03,"
|
|
line.long 0x3C "PRUSS_IEP_CAPTURE_RISE13,"
|
|
line.long 0x40 "PRUSS_IEP_CAPTURE_RISE04,"
|
|
line.long 0x44 "PRUSS_IEP_CAPTURE_RISE14,"
|
|
line.long 0x48 "PRUSS_IEP_CAPTURE_RISE05,"
|
|
line.long 0x4C "PRUSS_IEP_CAPTURE_RISE15,"
|
|
line.long 0x50 "PRUSS_IEP_CAPTURE_RISE06,"
|
|
line.long 0x54 "PRUSS_IEP_CAPTURE_RISE16,"
|
|
rgroup.long 0x60++0xAB
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_RISE07,"
|
|
line.long 0x04 "PRUSS_IEP_CAPTURE_RISE17,"
|
|
line.long 0x08 "PRUSS_IEP_CAPTURE_FALL07,"
|
|
line.long 0x0C "PRUSS_IEP_CAPTURE_FALL17,"
|
|
line.long 0x10 "PRUSS_IEP_COMPARE_CFG,"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x10 1.--16. 1. "CMP_EN,Enable bits for each of the compare registers"
|
|
newline
|
|
bitfld.long 0x10 0. "CMP0_RST_CNT_EN,Enable the reset of the counter" "0,1"
|
|
line.long 0x14 "PRUSS_IEP_COMPARE_STATUS,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP_HIT,Status bit for each of the compare registers"
|
|
line.long 0x18 "PRUSS_IEP_COMPARE00,"
|
|
line.long 0x1C "PRUSS_IEP_COMPARE10,"
|
|
line.long 0x20 "PRUSS_IEP_COMPARE01,"
|
|
line.long 0x24 "PRUSS_IEP_COMPARE11,"
|
|
line.long 0x28 "PRUSS_IEP_COMPARE02,"
|
|
line.long 0x2C "PRUSS_IEP_COMPARE12,"
|
|
line.long 0x30 "PRUSS_IEP_COMPARE03,"
|
|
line.long 0x34 "PRUSS_IEP_COMPARE13,"
|
|
line.long 0x38 "PRUSS_IEP_COMPARE04,"
|
|
line.long 0x3C "PRUSS_IEP_COMPARE14,"
|
|
line.long 0x40 "PRUSS_IEP_COMPARE05,"
|
|
line.long 0x44 "PRUSS_IEP_COMPARE15,"
|
|
line.long 0x48 "PRUSS_IEP_COMPARE06,"
|
|
line.long 0x4C "PRUSS_IEP_COMPARE16,"
|
|
line.long 0x50 "PRUSS_IEP_COMPARE07,"
|
|
line.long 0x54 "PRUSS_IEP_COMPARE17,"
|
|
line.long 0x58 "PRUSS_IEP_RXIPG0,"
|
|
hexmask.long.word 0x58 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x58 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x5C "PRUSS_IEP_RXIPG1,"
|
|
hexmask.long.word 0x5C 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x5C 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x60 "PRUSS_IEP_COMPARE08,"
|
|
line.long 0x64 "PRUSS_IEP_COMPARE18,"
|
|
line.long 0x68 "PRUSS_IEP_COMPARE09,"
|
|
line.long 0x6C "PRUSS_IEP_COMPARE19,"
|
|
line.long 0x70 "PRUSS_IEP_COMPARE010,"
|
|
line.long 0x74 "PRUSS_IEP_COMPARE110,"
|
|
line.long 0x78 "PRUSS_IEP_COMPARE011,"
|
|
line.long 0x7C "PRUSS_IEP_COMPARE111,"
|
|
line.long 0x80 "PRUSS_IEP_COMPARE012,"
|
|
line.long 0x84 "PRUSS_IEP_COMPARE112,"
|
|
line.long 0x88 "PRUSS_IEP_COMPARE013,"
|
|
line.long 0x8C "PRUSS_IEP_COMPARE113,"
|
|
line.long 0x90 "PRUSS_IEP_COMPARE014,"
|
|
line.long 0x94 "PRUSS_IEP_COMPARE114,"
|
|
line.long 0x98 "PRUSS_IEP_COMPARE015,"
|
|
line.long 0x9C "PRUSS_IEP_COMPARE115,"
|
|
line.long 0xA0 "PRUSS_IEP_LOW_COUNTER_RESET_VALUE,"
|
|
line.long 0xA4 "PRUSS_IEP_HIGH_COUNTER_RESET_VALUE,"
|
|
line.long 0xA8 "PRUSS_IEP_PWM,"
|
|
hexmask.long 0xA8 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0xA8 3. "PWM3_HIT,The raw status bit of eHRPWM3_SYNCO event" "No eHRPWM3_SYNCO event,eHRPWM3_SYNCO event occurred Write 1h to Clear"
|
|
newline
|
|
bitfld.long 0xA8 2. "PWM3_RST_CNT_EN,Enable the reset of the counter by a eHRPWM3_SYNCO event" "Disable,Enable the reset of.."
|
|
newline
|
|
bitfld.long 0xA8 1. "PWM0_HIT,The raw status bit of eHRPWM0_SYNCO event" "No eHRPWM0_SYNCO event,eHRPWM0_SYNCO event occurred Write 1 to Clear"
|
|
newline
|
|
bitfld.long 0xA8 0. "PWM0_RST_CNT_EN,Enable the reset of the counter by a eHRPWM0_SYNCO event" "Disable,Enable the reset of.."
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "PRUSS_IEP_SYNC_CTRL,"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SYNC1_IND_EN,SYNC1 independent mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SYNC1_ACK_EN,SYNC1 acknowledgement mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SYNC0_ACK_EN,SYNC0 acknowledgement mode enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SYNC1_EN,SYNC1 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNC0_EN,SYNC0 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SYNC_EN,SYNC generation enable" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_SYNC_FIRST_STAT,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "FIRST_SYNC1,SYNC1 First Event status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "FIRST_SYNC0,SYNC0 First Event status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_SYNC0_STAT,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "SYNC0_PEND,SYNC0 pending state" "0,1"
|
|
line.long 0x0C "PRUSS_IEP_SYNC1_STAT,"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "SYNC1_PEND,SYNC1 pending state" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_SYNC_PWIDTH,"
|
|
line.long 0x14 "PRUSS_IEP_SYNC0_PERIOD,"
|
|
line.long 0x18 "PRUSS_IEP_SYNC1_DELAY,"
|
|
line.long 0x1C "PRUSS_IEP_SYNC_START,"
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "PRUSS_IEP_WD_PREDIV,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,Defines the number of ICSS_IEP_CLK cycles per WD clock event"
|
|
line.long 0x04 "PRUSS_IEP_PDI_WD_TIM,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,Defines the number of WD ticks (or increments) for PDI WD that is the number of WD increments"
|
|
line.long 0x08 "PRUSS_IEP_PD_WD_TIM,"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,Defines the number of WD ticks (or increments) for PD WD that is the number of WD increments"
|
|
line.long 0x0C "PRUSS_IEP_WD_STATUS,"
|
|
hexmask.long.word 0x0C 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 16. "PDI_WD_STAT,WD PDI status" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "PD_WD_STAT,WD PD status (triggered by Sync Mangers status)" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_WD_EXP_CNT,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,WD PD expiration counter"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,WD PDI expiration counter"
|
|
line.long 0x14 "PRUSS_IEP_WD_CTRL,"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 16. "PDI_WD_EN,Watchdog PDI" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "PD_WD_EN,Watchdog PD" "0,1"
|
|
group.long 0x300++0x1B
|
|
line.long 0x00 "PRUSS_IEP_DIGIO_CTRL,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OUT_MODE,Defines events that triggers data out to be updated" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IN_MODE,Defines event that triggers data in to be sampled" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "WD_MODE,Defines Watchdog behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2. "BIDI_MODE,Defines the digital input/output direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUTVALID_MODE,Defines the outvalid mode behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "OUTVALID_POL,Defines OUTVALID polarity" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_DIGIO_STATUS,"
|
|
line.long 0x08 "PRUSS_IEP_DIGIO_DATA_IN,"
|
|
line.long 0x0C "PRUSS_IEP_DIGIO_DATA_IN_RAW,"
|
|
line.long 0x10 "PRUSS_IEP_DIGIO_DATA_OUT,"
|
|
line.long 0x14 "PRUSS_IEP_DIGIO_DATA_OUT_EN,"
|
|
line.long 0x18 "PRUSS_IEP_DIGIO_EXP,"
|
|
hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x18 13. "EOF_SEL,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "SOF_SEL,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "SOF_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 4.--7. "OUTVALID_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "SW_OUTVALID,PR<k>_EDIO_OUTVALID = SW_OUTVALID only if OUTVALID_OVR_EN is set" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "OUTVALID_OVR_EN,Software override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "SW_DATA_OUT_UPDATE,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1" "0,1"
|
|
repeat 2. (list 06. 16. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x58)++0x03
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_FALL$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_INTC"
|
|
base ad:0x20AA0000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_INTC_REVID,"
|
|
line.long 0x04 "PRUSS_INTC_CR,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Reserved" "0,1"
|
|
bitfld.long 0x04 2.--3. "NEST_MODE,The nesting mode" "0,1,2,3"
|
|
bitfld.long 0x04 1. "WAKEUP_MODE,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 0. "RESERVED,Reserved" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRUSS_INTC_GER,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "ENABLE_HINT_ANY,The current global enable value when" "0,1"
|
|
group.long 0x1C++0x13
|
|
line.long 0x00 "PRUSS_INTC_GNLR,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Always read as 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,The current global nesting level (highest channel that is nested)"
|
|
line.long 0x04 "PRUSS_INTC_SISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Writes set the status of the interrupt given in the index value"
|
|
line.long 0x08 "PRUSS_INTC_SICR,"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Writes clear the status of the interrupt given in the index value"
|
|
line.long 0x0C "PRUSS_INTC_EISR,"
|
|
hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Writes set the enable of the interrupt given in the index value"
|
|
line.long 0x10 "PRUSS_INTC_EICR,"
|
|
hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Writes clear the enable of the interrupt given in the index value"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "PRUSS_INTC_HIEISR,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Writes set the enable of the host interrupt given in the index value"
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line.long 0x04 "PRUSS_INTC_HIDISR,"
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hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
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hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Writes clear the enable of the host interrupt given in the index value"
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rgroup.long 0x80++0x03
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line.long 0x00 "PRUSS_INTC_GPIR,"
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bitfld.long 0x00 31. "GLB_NONE,No Interrupt is pending" "0,1"
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hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,The currently highest priority interrupt index pending across all the host interrupts"
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group.long 0x200++0x07
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line.long 0x00 "PRUSS_INTC_SRSR0,"
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line.long 0x04 "PRUSS_INTC_SRSR1,"
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group.long 0x280++0x07
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line.long 0x00 "PRUSS_INTC_SECR0,"
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line.long 0x04 "PRUSS_INTC_SECR1,"
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group.long 0x300++0x07
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line.long 0x00 "PRUSS_INTC_ESR0,"
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line.long 0x04 "PRUSS_INTC_ERS1,"
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group.long 0x380++0x07
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line.long 0x00 "PRUSS_INTC_ECR0,"
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line.long 0x04 "PRUSS_INTC_ECR1,"
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group.long 0x400++0x3F
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line.long 0x00 "PRUSS_INTC_CMR_0,"
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rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "CH_MAP_3,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "CH_MAP_2,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "CH_MAP_1,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "CH_MAP_0,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "PRUSS_INTC_CMR_1,"
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rbitfld.long 0x04 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 24.--27. "CH_MAP_7,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "CH_MAP_6,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "CH_MAP_5,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "CH_MAP_4,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "PRUSS_INTC_CMR_2,"
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rbitfld.long 0x08 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 24.--27. "CH_MAP_11,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "CH_MAP_10,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x08 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "CH_MAP_9,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "CH_MAP_8,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "PRUSS_INTC_CMR_3,"
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rbitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 24.--27. "CH_MAP_15,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "CH_MAP_14,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x0C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. "CH_MAP_13,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "CH_MAP_12,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "PRUSS_INTC_CMR_4,"
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rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 24.--27. "CH_MAP_19,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "CH_MAP_18,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x10 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "CH_MAP_17,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--3. "CH_MAP_16,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x14 "PRUSS_INTC_CMR_5,"
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rbitfld.long 0x14 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 24.--27. "CH_MAP_23,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "CH_MAP_22,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x14 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "CH_MAP_21,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. "CH_MAP_20,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x18 "PRUSS_INTC_CMR_6,"
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rbitfld.long 0x18 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 24.--27. "CH_MAP_27,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "CH_MAP_26,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x18 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 8.--11. "CH_MAP_25,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 0.--3. "CH_MAP_24,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x1C "PRUSS_INTC_CMR_7,"
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rbitfld.long 0x1C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 24.--27. "CH_MAP_31,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "CH_MAP_30,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x1C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 8.--11. "CH_MAP_29,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 0.--3. "CH_MAP_28,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x20 "PRUSS_INTC_CMR_8,"
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rbitfld.long 0x20 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 24.--27. "CH_MAP_35,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "CH_MAP_34,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x20 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--11. "CH_MAP_33,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "CH_MAP_32,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "PRUSS_INTC_CMR_9,"
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rbitfld.long 0x24 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. "CH_MAP_39,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "CH_MAP_38,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x24 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 8.--11. "CH_MAP_37,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. "CH_MAP_36,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x28 "PRUSS_INTC_CMR_10,"
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rbitfld.long 0x28 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 24.--27. "CH_MAP_43,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. "CH_MAP_42,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x28 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--11. "CH_MAP_41,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "CH_MAP_40,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x2C "PRUSS_INTC_CMR_11,"
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rbitfld.long 0x2C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 24.--27. "CH_MAP_47,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--19. "CH_MAP_46,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x2C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 8.--11. "CH_MAP_45,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "CH_MAP_44,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x30 "PRUSS_INTC_CMR_12,"
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rbitfld.long 0x30 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 24.--27. "CH_MAP_51,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--19. "CH_MAP_50,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x30 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 8.--11. "CH_MAP_49,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "CH_MAP_48,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x34 "PRUSS_INTC_CMR_13,"
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rbitfld.long 0x34 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 24.--27. "CH_MAP_55,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 16.--19. "CH_MAP_54,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x34 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 8.--11. "CH_MAP_53,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x34 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 0.--3. "CH_MAP_52,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "PRUSS_INTC_CMR_14,"
|
|
rbitfld.long 0x38 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 24.--27. "CH_MAP_59,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x38 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 16.--19. "CH_MAP_58,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x38 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 8.--11. "CH_MAP_57,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x38 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 0.--3. "CH_MAP_56,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "PRUSS_INTC_CMR_15,"
|
|
rbitfld.long 0x3C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x3C 24.--27. "CH_MAP_63,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x3C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x3C 16.--19. "CH_MAP_62,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x3C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x3C 8.--11. "CH_MAP_61,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x3C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x3C 0.--3. "CH_MAP_60,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "PRUSS_INTC_HMR2,"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 8.--11. "HINT_MAP_9,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HINT_MAP_8,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x900++0x27
|
|
line.long 0x00 "PRUSS_INTC_HIPIR_0,"
|
|
bitfld.long 0x00 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x04 "PRUSS_INTC_HIPIR_1,"
|
|
bitfld.long 0x04 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x04 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x08 "PRUSS_INTC_HIPIR_2,"
|
|
bitfld.long 0x08 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x08 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x0C "PRUSS_INTC_HIPIR_3,"
|
|
bitfld.long 0x0C 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x0C 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x10 "PRUSS_INTC_HIPIR_4,"
|
|
bitfld.long 0x10 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x10 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x14 "PRUSS_INTC_HIPIR_5,"
|
|
bitfld.long 0x14 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x14 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x18 "PRUSS_INTC_HIPIR_6,"
|
|
bitfld.long 0x18 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x18 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x1C "PRUSS_INTC_HIPIR_7,"
|
|
bitfld.long 0x1C 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x1C 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x20 "PRUSS_INTC_HIPIR_8,"
|
|
bitfld.long 0x20 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x20 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x24 "PRUSS_INTC_HIPIR_9,"
|
|
bitfld.long 0x24 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x24 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
group.long 0xD00++0x07
|
|
line.long 0x00 "PRUSS_INTC_SIPR0,"
|
|
line.long 0x04 "PRUSS_INTC_SIPR1,"
|
|
group.long 0xD80++0x07
|
|
line.long 0x00 "PRUSS_INTC_SITR0,"
|
|
line.long 0x04 "PRUSS_INTC_SITR1,"
|
|
group.long 0x1100++0x27
|
|
line.long 0x00 "PRUSS_INTC_HINLR_0,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x04 "PRUSS_INTC_HINLR_1,"
|
|
bitfld.long 0x04 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x08 "PRUSS_INTC_HINLR_2,"
|
|
bitfld.long 0x08 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x08 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x0C "PRUSS_INTC_HINLR_3,"
|
|
bitfld.long 0x0C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x0C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x10 "PRUSS_INTC_HINLR_4,"
|
|
bitfld.long 0x10 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x10 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x14 "PRUSS_INTC_HINLR_5,"
|
|
bitfld.long 0x14 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x14 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x18 "PRUSS_INTC_HINLR_6,"
|
|
bitfld.long 0x18 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x18 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x1C "PRUSS_INTC_HINLR_7,"
|
|
bitfld.long 0x1C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x1C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x20 "PRUSS_INTC_HINLR_8,"
|
|
bitfld.long 0x20 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x20 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x24 "PRUSS_INTC_HINLR_9,"
|
|
bitfld.long 0x24 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x24 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "PRUSS_INTC_HIER,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "ENABLE_HINT,The enable of the host interrupts (one per bit)"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "PRUSS_INTC_HMR$1,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "HINT_MAP_3,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "HINT_MAP_2,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HINT_MAP_1,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HINT_MAP_0,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_INTC"
|
|
base ad:0x20AE0000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_INTC_REVID,"
|
|
line.long 0x04 "PRUSS_INTC_CR,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Reserved" "0,1"
|
|
bitfld.long 0x04 2.--3. "NEST_MODE,The nesting mode" "0,1,2,3"
|
|
bitfld.long 0x04 1. "WAKEUP_MODE,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 0. "RESERVED,Reserved" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRUSS_INTC_GER,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "ENABLE_HINT_ANY,The current global enable value when" "0,1"
|
|
group.long 0x1C++0x13
|
|
line.long 0x00 "PRUSS_INTC_GNLR,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Always read as 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,The current global nesting level (highest channel that is nested)"
|
|
line.long 0x04 "PRUSS_INTC_SISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Writes set the status of the interrupt given in the index value"
|
|
line.long 0x08 "PRUSS_INTC_SICR,"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Writes clear the status of the interrupt given in the index value"
|
|
line.long 0x0C "PRUSS_INTC_EISR,"
|
|
hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Writes set the enable of the interrupt given in the index value"
|
|
line.long 0x10 "PRUSS_INTC_EICR,"
|
|
hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Writes clear the enable of the interrupt given in the index value"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "PRUSS_INTC_HIEISR,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Writes set the enable of the host interrupt given in the index value"
|
|
line.long 0x04 "PRUSS_INTC_HIDISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Writes clear the enable of the host interrupt given in the index value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PRUSS_INTC_GPIR,"
|
|
bitfld.long 0x00 31. "GLB_NONE,No Interrupt is pending" "0,1"
|
|
hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,The currently highest priority interrupt index pending across all the host interrupts"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "PRUSS_INTC_SRSR0,"
|
|
line.long 0x04 "PRUSS_INTC_SRSR1,"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "PRUSS_INTC_SECR0,"
|
|
line.long 0x04 "PRUSS_INTC_SECR1,"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "PRUSS_INTC_ESR0,"
|
|
line.long 0x04 "PRUSS_INTC_ERS1,"
|
|
group.long 0x380++0x07
|
|
line.long 0x00 "PRUSS_INTC_ECR0,"
|
|
line.long 0x04 "PRUSS_INTC_ECR1,"
|
|
group.long 0x400++0x3F
|
|
line.long 0x00 "PRUSS_INTC_CMR_0,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "CH_MAP_3,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH_MAP_2,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH_MAP_1,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH_MAP_0,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PRUSS_INTC_CMR_1,"
|
|
rbitfld.long 0x04 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "CH_MAP_7,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "CH_MAP_6,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. "CH_MAP_5,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "CH_MAP_4,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PRUSS_INTC_CMR_2,"
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rbitfld.long 0x08 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 24.--27. "CH_MAP_11,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "CH_MAP_10,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x08 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "CH_MAP_9,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "CH_MAP_8,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "PRUSS_INTC_CMR_3,"
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rbitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 24.--27. "CH_MAP_15,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "CH_MAP_14,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x0C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. "CH_MAP_13,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "CH_MAP_12,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "PRUSS_INTC_CMR_4,"
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rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 24.--27. "CH_MAP_19,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "CH_MAP_18,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x10 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "CH_MAP_17,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--3. "CH_MAP_16,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x14 "PRUSS_INTC_CMR_5,"
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rbitfld.long 0x14 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 24.--27. "CH_MAP_23,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "CH_MAP_22,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x14 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "CH_MAP_21,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. "CH_MAP_20,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x18 "PRUSS_INTC_CMR_6,"
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rbitfld.long 0x18 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 24.--27. "CH_MAP_27,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "CH_MAP_26,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x18 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 8.--11. "CH_MAP_25,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 0.--3. "CH_MAP_24,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x1C "PRUSS_INTC_CMR_7,"
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rbitfld.long 0x1C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 24.--27. "CH_MAP_31,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "CH_MAP_30,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x1C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 8.--11. "CH_MAP_29,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 0.--3. "CH_MAP_28,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x20 "PRUSS_INTC_CMR_8,"
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rbitfld.long 0x20 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 24.--27. "CH_MAP_35,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "CH_MAP_34,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x20 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--11. "CH_MAP_33,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "CH_MAP_32,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "PRUSS_INTC_CMR_9,"
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rbitfld.long 0x24 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. "CH_MAP_39,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "CH_MAP_38,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x24 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 8.--11. "CH_MAP_37,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. "CH_MAP_36,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x28 "PRUSS_INTC_CMR_10,"
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rbitfld.long 0x28 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 24.--27. "CH_MAP_43,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. "CH_MAP_42,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x28 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--11. "CH_MAP_41,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "CH_MAP_40,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x2C "PRUSS_INTC_CMR_11,"
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rbitfld.long 0x2C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 24.--27. "CH_MAP_47,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--19. "CH_MAP_46,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x2C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 8.--11. "CH_MAP_45,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "CH_MAP_44,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x30 "PRUSS_INTC_CMR_12,"
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rbitfld.long 0x30 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 24.--27. "CH_MAP_51,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--19. "CH_MAP_50,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x30 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 8.--11. "CH_MAP_49,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "CH_MAP_48,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x34 "PRUSS_INTC_CMR_13,"
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rbitfld.long 0x34 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 24.--27. "CH_MAP_55,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 16.--19. "CH_MAP_54,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x34 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 8.--11. "CH_MAP_53,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 0.--3. "CH_MAP_52,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x38 "PRUSS_INTC_CMR_14,"
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rbitfld.long 0x38 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 24.--27. "CH_MAP_59,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x38 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "CH_MAP_58,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x38 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 8.--11. "CH_MAP_57,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x38 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 0.--3. "CH_MAP_56,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x3C "PRUSS_INTC_CMR_15,"
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rbitfld.long 0x3C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 24.--27. "CH_MAP_63,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x3C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 16.--19. "CH_MAP_62,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x3C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 8.--11. "CH_MAP_61,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x3C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0.--3. "CH_MAP_60,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x808++0x03
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line.long 0x00 "PRUSS_INTC_HMR2,"
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 8.--11. "HINT_MAP_9,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HINT_MAP_8,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x900++0x27
|
|
line.long 0x00 "PRUSS_INTC_HIPIR_0,"
|
|
bitfld.long 0x00 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x04 "PRUSS_INTC_HIPIR_1,"
|
|
bitfld.long 0x04 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x04 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x08 "PRUSS_INTC_HIPIR_2,"
|
|
bitfld.long 0x08 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x08 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x0C "PRUSS_INTC_HIPIR_3,"
|
|
bitfld.long 0x0C 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x0C 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x10 "PRUSS_INTC_HIPIR_4,"
|
|
bitfld.long 0x10 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x10 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x14 "PRUSS_INTC_HIPIR_5,"
|
|
bitfld.long 0x14 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x14 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x18 "PRUSS_INTC_HIPIR_6,"
|
|
bitfld.long 0x18 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x18 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x1C "PRUSS_INTC_HIPIR_7,"
|
|
bitfld.long 0x1C 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x1C 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x20 "PRUSS_INTC_HIPIR_8,"
|
|
bitfld.long 0x20 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x20 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x24 "PRUSS_INTC_HIPIR_9,"
|
|
bitfld.long 0x24 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x24 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
group.long 0xD00++0x07
|
|
line.long 0x00 "PRUSS_INTC_SIPR0,"
|
|
line.long 0x04 "PRUSS_INTC_SIPR1,"
|
|
group.long 0xD80++0x07
|
|
line.long 0x00 "PRUSS_INTC_SITR0,"
|
|
line.long 0x04 "PRUSS_INTC_SITR1,"
|
|
group.long 0x1100++0x27
|
|
line.long 0x00 "PRUSS_INTC_HINLR_0,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x04 "PRUSS_INTC_HINLR_1,"
|
|
bitfld.long 0x04 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x08 "PRUSS_INTC_HINLR_2,"
|
|
bitfld.long 0x08 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x08 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x0C "PRUSS_INTC_HINLR_3,"
|
|
bitfld.long 0x0C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x0C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x10 "PRUSS_INTC_HINLR_4,"
|
|
bitfld.long 0x10 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x10 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x14 "PRUSS_INTC_HINLR_5,"
|
|
bitfld.long 0x14 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x14 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x18 "PRUSS_INTC_HINLR_6,"
|
|
bitfld.long 0x18 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x18 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x1C "PRUSS_INTC_HINLR_7,"
|
|
bitfld.long 0x1C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x1C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x20 "PRUSS_INTC_HINLR_8,"
|
|
bitfld.long 0x20 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x20 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x24 "PRUSS_INTC_HINLR_9,"
|
|
bitfld.long 0x24 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x24 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "PRUSS_INTC_HIER,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "ENABLE_HINT,The enable of the host interrupts (one per bit)"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "PRUSS_INTC_HMR$1,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "HINT_MAP_3,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "HINT_MAP_2,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HINT_MAP_1,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HINT_MAP_0,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_MII_MDIO"
|
|
base ad:0x20AB2400
|
|
rgroup.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_MII_MDIO_VER,"
|
|
line.long 0x04 "PRUSS_MII_MDIO_CONTROL,"
|
|
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
|
|
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
|
|
rbitfld.long 0x04 29. "RESERVED,Reserved" "0,1"
|
|
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
|
|
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
|
|
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
|
|
rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1"
|
|
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
|
|
line.long 0x08 "PRUSS_MII_MDIO_ALIVE,"
|
|
line.long 0x0C "PRUSS_MII_MDIO_LINK,"
|
|
line.long 0x10 "PRUSS_MII_MDIO_LINKINTRAW,"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
|
|
line.long 0x14 "PRUSS_MII_MDIO_LINKINTMASKED,"
|
|
hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERINTRAW,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERINTMASKED,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERINTMASKSET,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--1. "USERINTMASKEDSET,MDIO user interrupt mask set for userintmasked[1:0] respectively" "0,1,2,3"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERINTMASKCLR,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--1. "USERINTMASKEDCLR,MDIO user command complete interrupt mask clear for userintmasked[1:0] respectively" "0,1,2,3"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERACCESS0,"
|
|
bitfld.long 0x00 31. "GO,Go" "0,1"
|
|
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x00 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERPHYSEL0,"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x04 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERACCESS1,"
|
|
bitfld.long 0x08 31. "GO,Go" "0,1"
|
|
bitfld.long 0x08 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x08 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x08 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,User data"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERPHYSEL1,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x0C 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x0C 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_MII_MDIO"
|
|
base ad:0x20AF2400
|
|
rgroup.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_MII_MDIO_VER,"
|
|
line.long 0x04 "PRUSS_MII_MDIO_CONTROL,"
|
|
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
|
|
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
|
|
rbitfld.long 0x04 29. "RESERVED,Reserved" "0,1"
|
|
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
|
|
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
|
|
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
|
|
rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1"
|
|
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
|
|
line.long 0x08 "PRUSS_MII_MDIO_ALIVE,"
|
|
line.long 0x0C "PRUSS_MII_MDIO_LINK,"
|
|
line.long 0x10 "PRUSS_MII_MDIO_LINKINTRAW,"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
|
|
line.long 0x14 "PRUSS_MII_MDIO_LINKINTMASKED,"
|
|
hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERINTRAW,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERINTMASKED,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERINTMASKSET,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--1. "USERINTMASKEDSET,MDIO user interrupt mask set for userintmasked[1:0] respectively" "0,1,2,3"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERINTMASKCLR,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--1. "USERINTMASKEDCLR,MDIO user command complete interrupt mask clear for userintmasked[1:0] respectively" "0,1,2,3"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERACCESS0,"
|
|
bitfld.long 0x00 31. "GO,Go" "0,1"
|
|
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x00 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERPHYSEL0,"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x04 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERACCESS1,"
|
|
bitfld.long 0x08 31. "GO,Go" "0,1"
|
|
bitfld.long 0x08 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x08 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x08 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,User data"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERPHYSEL1,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x0C 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x0C 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_MII_RT"
|
|
base ad:0x20AB2000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_MII_RT_RXCFG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "Disable,Enable it must.."
|
|
newline
|
|
bitfld.long 0x00 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3 Nibble2}..,R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1 Nibble0}.."
|
|
newline
|
|
bitfld.long 0x00 4. "RX_L2_EN,Enables RX L2 buffer" "Disable (RX L2..,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "RX_MUX_SEL,Selects receive data source" "MII RX Data from Port 0 (default for..,MII RX Data from Port 1 (default for.."
|
|
newline
|
|
bitfld.long 0x00 2. "RX_CUT_PREAMBLE,Removes received preamble" "All data from Ethernet PHY are passed on to PRU..,MII interface suppresses preamble and sync frame.."
|
|
newline
|
|
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "Disable,Enable"
|
|
line.long 0x04 "PRUSS_MII_RT_RXCFG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "RX_L2_EN,Enables RX L2 buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "RX_MUX_SEL,Selects receive data source" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "RX_CUT_PREAMBLE,Removes received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "0,1"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PRUSS_MII_RT_TX_IPG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x04 "PRUSS_MII_RT_TX_IPG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x08 "PRUSS_MII_RT_PRS0,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "MII_CRS,Read the current state of pr1_mii0_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "MII_COL,Read the current state of pr1_mii0_col" "0,1"
|
|
line.long 0x0C "PRUSS_MII_RT_PRS1,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "MII_CRS,Read the current state of pr1_mii1_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "MII_COL,Read the current state of pr1_mii1_col" "0,1"
|
|
line.long 0x10 "PRUSS_MII_RT_RX_FRMS0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
line.long 0x14 "PRUSS_MII_RT_RX_FRMS1,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_FIFO_LEVEL,Define the number of valid nibbles in the TX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL,Define the number of valid bytes in the RX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_ERR$1,"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 3. "RX_MAX_FRM_ERR,Error status of received frame is more than the value of RX_MAX_FRM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_MIN_FRM_ERR,Error status of received frame is less than the value of RX_MIN_FRM" "0,1"
|
|
bitfld.long 0x00 1. "RX_MAX_PCNT_ERR,Error status of received preamble nibble is more than the value of RX_MAX_PCNT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_MIN_PCNT_ERR,Error status of received preamble nibble is less than the value of RX_MIN_PCNT" "0,1"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_PCNT$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 4.--7. "RX_MAX_PCNT,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RX_MIN_PCNT,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred which is matched the value 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x20)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TX_CRC$1,"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXCFG$1,"
|
|
rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "TX_CLK_DELAY,In order to guarantee the MII_RT IO timing values published in the device data manual the ICSS_i_VCLK_CLK (where i = 0 or 1) clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 26.--27. "RESERVED,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "TX_32_MODE_EN," "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 9. "TX_AUTO_SEQUENCE,Enables transmit auto-sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_MUX_SEL,Selects transmit data source" "0,1"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "TX_BYTE_SWAP,Defines the order of Byte0/1 placement for TX R30" "0,1"
|
|
bitfld.long 0x00 2. "TX_EN_MODE,Enables transmit self clear on TX_EOF event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE,Transmit data auto-preamble" "0,1"
|
|
bitfld.long 0x00 0. "TX_ENABLE,Enables transmit traffic on TX PORT" "0,1"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_MII_RT"
|
|
base ad:0x20AF2000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_MII_RT_RXCFG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "Disable,Enable it must.."
|
|
newline
|
|
bitfld.long 0x00 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3 Nibble2}..,R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1 Nibble0}.."
|
|
newline
|
|
bitfld.long 0x00 4. "RX_L2_EN,Enables RX L2 buffer" "Disable (RX L2..,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "RX_MUX_SEL,Selects receive data source" "MII RX Data from Port 0 (default for..,MII RX Data from Port 1 (default for.."
|
|
newline
|
|
bitfld.long 0x00 2. "RX_CUT_PREAMBLE,Removes received preamble" "All data from Ethernet PHY are passed on to PRU..,MII interface suppresses preamble and sync frame.."
|
|
newline
|
|
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "Disable,Enable"
|
|
line.long 0x04 "PRUSS_MII_RT_RXCFG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "RX_L2_EN,Enables RX L2 buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "RX_MUX_SEL,Selects receive data source" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "RX_CUT_PREAMBLE,Removes received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "0,1"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PRUSS_MII_RT_TX_IPG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x04 "PRUSS_MII_RT_TX_IPG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x08 "PRUSS_MII_RT_PRS0,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "MII_CRS,Read the current state of pr1_mii0_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "MII_COL,Read the current state of pr1_mii0_col" "0,1"
|
|
line.long 0x0C "PRUSS_MII_RT_PRS1,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "MII_CRS,Read the current state of pr1_mii1_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "MII_COL,Read the current state of pr1_mii1_col" "0,1"
|
|
line.long 0x10 "PRUSS_MII_RT_RX_FRMS0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
line.long 0x14 "PRUSS_MII_RT_RX_FRMS1,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_FIFO_LEVEL,Define the number of valid nibbles in the TX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL,Define the number of valid bytes in the RX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_ERR$1,"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 3. "RX_MAX_FRM_ERR,Error status of received frame is more than the value of RX_MAX_FRM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_MIN_FRM_ERR,Error status of received frame is less than the value of RX_MIN_FRM" "0,1"
|
|
bitfld.long 0x00 1. "RX_MAX_PCNT_ERR,Error status of received preamble nibble is more than the value of RX_MAX_PCNT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_MIN_PCNT_ERR,Error status of received preamble nibble is less than the value of RX_MIN_PCNT" "0,1"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_PCNT$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 4.--7. "RX_MAX_PCNT,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RX_MIN_PCNT,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred which is matched the value 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x20)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TX_CRC$1,"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXCFG$1,"
|
|
rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "TX_CLK_DELAY,In order to guarantee the MII_RT IO timing values published in the device data manual the ICSS_i_VCLK_CLK (where i = 0 or 1) clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 26.--27. "RESERVED,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "TX_32_MODE_EN," "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 9. "TX_AUTO_SEQUENCE,Enables transmit auto-sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_MUX_SEL,Selects transmit data source" "0,1"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "TX_BYTE_SWAP,Defines the order of Byte0/1 placement for TX R30" "0,1"
|
|
bitfld.long 0x00 2. "TX_EN_MODE,Enables transmit self clear on TX_EOF event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE,Transmit data auto-preamble" "0,1"
|
|
bitfld.long 0x00 0. "TX_ENABLE,Enables transmit traffic on TX PORT" "0,1"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_PRU0_CTRL"
|
|
base ad:0x20AA2000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_PRU1_CTRL"
|
|
base ad:0x20AA4000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_PRU0_CTRL"
|
|
base ad:0x20AE2000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_PRU1_CTRL"
|
|
base ad:0x20AE4000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_0_UART"
|
|
base ad:0x20AA8000
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "PRUSS_UART_RBR_THR_REGISTERS,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register"
|
|
line.long 0x04 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 3. "EDSSI,Enable Modem Status Interrupt" "0,1"
|
|
bitfld.long 0x04 2. "ELSI,Receiver line status interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "ETBEI,Transmitter holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x04 0. "ERBI,Receiver data available interrupt and character timeout indication interrupt enable" "0,1"
|
|
line.long 0x08 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 6.--7. "FIFOEN_RXFIFTL,Read: FIFOs enabled" "0,1,2,3"
|
|
rbitfld.long 0x08 4.--5. "RESERVED,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 1.--3. "INTID,Read: Interrupt type" "No effect,RXCLR,TXCLR,DMAMODE1,?..."
|
|
bitfld.long 0x08 0. "IPEND_FIFOEN,Read: Interrupt pending" "0,1"
|
|
line.long 0x0C "PRUSS_UART_LINE_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "DLAB,Divisor latch access bit" "0,1"
|
|
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "SP,Stick parity" "0,1"
|
|
bitfld.long 0x0C 4. "EPS,Even parity select" "0,1"
|
|
bitfld.long 0x0C 3. "PEN,Parity enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "STB,Number of STOP bits generated" "0,1"
|
|
bitfld.long 0x0C 0.--1. "WLS,Word length select" "0,1,2,3"
|
|
line.long 0x10 "PRUSS_UART_MODEM_CONTROL_REGISTER,"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 5. "AFE,Autoflow control enable" "0,1"
|
|
bitfld.long 0x10 4. "LOOP,Loop back mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "OUT2,OUT2 Control Bit" "0,1"
|
|
bitfld.long 0x10 2. "OUT1,OUT1 Control Bit" "0,1"
|
|
bitfld.long 0x10 1. "RTS,RTS control" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "RESERVED,Reserved" "0,1"
|
|
line.long 0x14 "PRUSS_UART_LINE_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO error" "0,1"
|
|
bitfld.long 0x14 6. "TEMT,Transmitter empty (TEMT) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "THRE,Transmitter holding register empty (THRE) indicator" "0,1"
|
|
bitfld.long 0x14 4. "BI,Break indicator" "0,1"
|
|
bitfld.long 0x14 3. "FE,Framing error (FE) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PE,Parity error (PE) indicator" "0,1"
|
|
bitfld.long 0x14 1. "OE,Overrun error (OE) indicator" "0,1"
|
|
bitfld.long 0x14 0. "DR,Data-ready (DR) indicator for the receiver" "0,1"
|
|
line.long 0x18 "PRUSS_UART_MODEM_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 7. "CD,Complement of the Carrier Detect input" "0,1"
|
|
bitfld.long 0x18 6. "RI,Complement of the Ring Indicator input" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "DSR,Complement of the Data Set Ready input" "0,1"
|
|
bitfld.long 0x18 4. "CTS,Complement of the Clear To Send input" "0,1"
|
|
bitfld.long 0x18 3. "DCD,Change in DCD indicator bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "TERI,Trailing edge of RI (TERI) indicator bit" "0,1"
|
|
bitfld.long 0x18 1. "DDSR,Change in DSR indicator bit" "0,1"
|
|
bitfld.long 0x18 0. "DCTS,Change in CTS indicator bit" "0,1"
|
|
line.long 0x1C "PRUSS_UART_SCRATCH_REGISTER,"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DATA,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation"
|
|
line.long 0x20 "PRUSS_UART_DIVISOR_REGISTER_LSB_,"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DLL,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x24 "PRUSS_UART_DIVISOR_REGISTER_MSB_,"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DLH,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x28 "PRUSS_UART_PERIPHERAL_ID_REGISTER,"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 15. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 14. "UTRST,UART transmitter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "URRST,UART receiver reset" "0,1"
|
|
hexmask.long.word 0x00 1.--12. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "FREE,Free-running enable mode bit" "0,1"
|
|
line.long 0x04 "PRUSS_UART_MODE_DEFINITION_REGISTER,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "OSM_SEL,Over-Sampling Mode Select" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU_ICSS_1_UART"
|
|
base ad:0x20AE8000
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "PRUSS_UART_RBR_THR_REGISTERS,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register"
|
|
line.long 0x04 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 3. "EDSSI,Enable Modem Status Interrupt" "0,1"
|
|
bitfld.long 0x04 2. "ELSI,Receiver line status interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "ETBEI,Transmitter holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x04 0. "ERBI,Receiver data available interrupt and character timeout indication interrupt enable" "0,1"
|
|
line.long 0x08 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 6.--7. "FIFOEN_RXFIFTL,Read: FIFOs enabled" "0,1,2,3"
|
|
rbitfld.long 0x08 4.--5. "RESERVED,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 1.--3. "INTID,Read: Interrupt type" "No effect,RXCLR,TXCLR,DMAMODE1,?..."
|
|
bitfld.long 0x08 0. "IPEND_FIFOEN,Read: Interrupt pending" "0,1"
|
|
line.long 0x0C "PRUSS_UART_LINE_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "DLAB,Divisor latch access bit" "0,1"
|
|
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "SP,Stick parity" "0,1"
|
|
bitfld.long 0x0C 4. "EPS,Even parity select" "0,1"
|
|
bitfld.long 0x0C 3. "PEN,Parity enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "STB,Number of STOP bits generated" "0,1"
|
|
bitfld.long 0x0C 0.--1. "WLS,Word length select" "0,1,2,3"
|
|
line.long 0x10 "PRUSS_UART_MODEM_CONTROL_REGISTER,"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 5. "AFE,Autoflow control enable" "0,1"
|
|
bitfld.long 0x10 4. "LOOP,Loop back mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "OUT2,OUT2 Control Bit" "0,1"
|
|
bitfld.long 0x10 2. "OUT1,OUT1 Control Bit" "0,1"
|
|
bitfld.long 0x10 1. "RTS,RTS control" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "RESERVED,Reserved" "0,1"
|
|
line.long 0x14 "PRUSS_UART_LINE_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO error" "0,1"
|
|
bitfld.long 0x14 6. "TEMT,Transmitter empty (TEMT) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "THRE,Transmitter holding register empty (THRE) indicator" "0,1"
|
|
bitfld.long 0x14 4. "BI,Break indicator" "0,1"
|
|
bitfld.long 0x14 3. "FE,Framing error (FE) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PE,Parity error (PE) indicator" "0,1"
|
|
bitfld.long 0x14 1. "OE,Overrun error (OE) indicator" "0,1"
|
|
bitfld.long 0x14 0. "DR,Data-ready (DR) indicator for the receiver" "0,1"
|
|
line.long 0x18 "PRUSS_UART_MODEM_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 7. "CD,Complement of the Carrier Detect input" "0,1"
|
|
bitfld.long 0x18 6. "RI,Complement of the Ring Indicator input" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "DSR,Complement of the Data Set Ready input" "0,1"
|
|
bitfld.long 0x18 4. "CTS,Complement of the Clear To Send input" "0,1"
|
|
bitfld.long 0x18 3. "DCD,Change in DCD indicator bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "TERI,Trailing edge of RI (TERI) indicator bit" "0,1"
|
|
bitfld.long 0x18 1. "DDSR,Change in DSR indicator bit" "0,1"
|
|
bitfld.long 0x18 0. "DCTS,Change in CTS indicator bit" "0,1"
|
|
line.long 0x1C "PRUSS_UART_SCRATCH_REGISTER,"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DATA,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation"
|
|
line.long 0x20 "PRUSS_UART_DIVISOR_REGISTER_LSB_,"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DLL,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x24 "PRUSS_UART_DIVISOR_REGISTER_MSB_,"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DLH,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x28 "PRUSS_UART_PERIPHERAL_ID_REGISTER,"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 15. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 14. "UTRST,UART transmitter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "URRST,UART receiver reset" "0,1"
|
|
hexmask.long.word 0x00 1.--12. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "FREE,Free-running enable mode bit" "0,1"
|
|
line.long 0x04 "PRUSS_UART_MODE_DEFINITION_REGISTER,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "OSM_SEL,Over-Sampling Mode Select" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "RFBI"
|
|
base ad:0x2546000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RFBI_REVISION,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,TI internal data"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "RFBI_SYSCONFIG,"
|
|
bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management Idle req/ack control" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
|
|
bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
|
|
bitfld.long 0x00 0. "AUTOIDLE,Internal clock gating strategy (OCP clock and display controller clock) 0h (R/W) = OCP clock and display controller clock are free-running 1h (R/W) = Automatic clock gating strategy is applied for the OCP clock and display controller clock.." "AUTOIDLE_0,AUTOIDLE_1"
|
|
line.long 0x04 "RFBI_SYSSTATUS,"
|
|
bitfld.long 0x04 9. "BUSYRFBIDATA,Data are pending to be processed from internal FIFO" "BUSYRFBIDATA_0,BUSYRFBIDATA_1"
|
|
bitfld.long 0x04 8. "BUSY,OCP Slave port busy status bit 0h (R) = The access to the following register is not stall: 1h (R) = The access to any of the following registers is stall" "BUSY_0,BUSY_1"
|
|
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0,RESETDONE_1"
|
|
group.long 0x40++0x57
|
|
line.long 0x00 "RFBI_CONTROL,"
|
|
bitfld.long 0x00 8. "SMART_DMA_REQ,Smart DMA request 0h (R/W) = The dmareq is asserted and de-asserted depending on FIFO space even if MIdlereq is high in smart idle/no-idle mode and the entire burst gets error responses from the module" "SMART_DMA_REQ_0,SMART_DMA_REQ_1"
|
|
bitfld.long 0x00 7. "DISABLE_DMA_REQ,Disable DMA request 0h (R/W) = The dmareq is enabled and the signal is generated based on the space available and the request coming into the data register 1h (R/W) = The dmareq is disabled and the signal is not generated at all based on.." "DISABLE_DMA_REQ_0,DISABLE_DMA_REQ_1"
|
|
bitfld.long 0x00 5.--6. "HIGHTHRESHOLD,Defines the FIFO high threshold used by HW to assert DMA request" "HIGHTHRESHOLD_0,HIGHTHRESHOLD_1,HIGHTHRESHOLD_2,HIGHTHRESHOLD_3"
|
|
newline
|
|
bitfld.long 0x00 4. "ITE,Internal Trigger 0h (R/W) = H/W waits for ITE bit to be set if in internal trigger mode for the configuration in use" "ITE_0,ITE_1"
|
|
bitfld.long 0x00 2.--3. "CONFIGSELECT,Select the CS and configuration 0h (R/W) = No CS selected 1h (R/W) = CS0 selected and configuration #0 2h (R/W) = CS1 selected and configuration #1 3h (R/W) = CS0 and CS1 both selected (only the configuration for CS0 is used)" "CONFIGSELECT_0,CONFIGSELECT_1,CONFIGSELECT_2,CONFIGSELECT_3"
|
|
bitfld.long 0x00 1. "BYPASSMODE,Bypass Mode 0h (R/W) = The bypass mode not selected 1h (R/W) = The bypass mode is selected" "BYPASSMODE_0,BYPASSMODE_1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Enable/Disable flag 0h (R/W) = Disable the RFBI module 1h (R/W) = Enable the RFBI module" "ENABLE_0,ENABLE_1"
|
|
line.long 0x04 "RFBI_PIXEL_CNT,"
|
|
line.long 0x08 "RFBI_LINE_NUMBER,"
|
|
hexmask.long.word 0x08 0.--10. 1. "LINENUMBER,Programmable line number"
|
|
line.long 0x0C "RFBI_CMD,"
|
|
hexmask.long.word 0x0C 0.--15. 1. "CMD,Command Value"
|
|
line.long 0x10 "RFBI_PARAM,"
|
|
hexmask.long.word 0x10 0.--15. 1. "PARAM,Param Value"
|
|
line.long 0x14 "RFBI_DATA,"
|
|
line.long 0x18 "RFBI_READ,"
|
|
hexmask.long.word 0x18 0.--15. 1. "READ,Read Value"
|
|
line.long 0x1C "RFBI_STATUS,"
|
|
hexmask.long.word 0x1C 0.--15. 1. "STATUS,Status value"
|
|
line.long 0x20 "RFBI_CONFIG__0,"
|
|
bitfld.long 0x20 21. "HSYNCPOLARITY,HSYNC polarity 0h (R/W) = HSYNC active low 1h (R/W) = HSYNC active high" "0,1"
|
|
bitfld.long 0x20 20. "TE_VSYNC_POLARITY,TE or VSYNC Polarity 0h (R/W) = active low 1h (R/W) = active high" "0,1"
|
|
bitfld.long 0x20 19. "CSPOLARITY,CS Polarity 0h (R/W) = CS active low 1h (R/W) = CS active high" "0,1"
|
|
newline
|
|
bitfld.long 0x20 18. "WEPOLARITY,WE Polarity 0h (R/W) = active low 1h (R/W) = active high" "0,1"
|
|
bitfld.long 0x20 17. "REPOLARITY,RE Polarity 0h (R/W) = active low 1h (R/W) = active high" "0,1"
|
|
bitfld.long 0x20 16. "A0POLARITY,A0 Polarity 0h (R/W) = A0 active low 1h (R/W) = A0 active high" "0,1"
|
|
newline
|
|
bitfld.long 0x20 11.--12. "UNUSEDBITS,State of unused bits 0h (R/W) = low level (0) 1h (R/W) = high level (1) 2h (R/W) = unchanged from previous state" "0,1,2,3"
|
|
bitfld.long 0x20 9.--10. "CYCLEFORMAT,Cycle format 0h (R/W) = 1 cycle for 1 pixel 1h (R/W) = 2 cycles for 1 pixel 2h (R/W) = 3 cycles for 1 pixel 3h (R/W) = 3 cycles for 2 pixels" "0,1,2,3"
|
|
bitfld.long 0x20 7.--8. "OCPFORMAT,OCP Write Access format 0h (R/W) = 1 pixel per OCP access to the register data 2h (R/W) = 2 pixels per OCP access to the register data with 1st pixel at the position [15:0] 3h (R/W) = 2 pixels per OCP access to the register data with 1st pixel.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 5.--6. "DATATYPE,Data type from the display controller and OCP slave port 0h (R/W) = 12-bit 1h (R/W) = 16-bit 2h (R/W) = 18-bit 3h (R/W) = 24-bit" "0,1,2,3"
|
|
bitfld.long 0x20 4. "TIMEGRANULARITY,Multiplies signal timing latencies by two 0h (R/W) = x2 latencies disabled 1h (R/W) = x2 latencies enabled" "0,1"
|
|
bitfld.long 0x20 2.--3. "TRIGGERMODE,Trigger Mode 0h (R/W) = 00 Internal trigger mode ( 1h (R/W) = Tearing Effect Signal RFBI_TEVSYNC0 is used with programmable line counter defined in 2h (R/W) = External trigger mode (RFBI_TEVSYNC/RFBI_HSYNC with programmable line counter.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 0.--1. "PARALLELMODE,Parallel Mode 0h (R/W) = 8-bit parallel output interface selected 1h (R/W) = 9-bit parallel output interface selected 2h (R/W) = 12-bit parallel output interface selected 3h (R/W) = 16-bit parallel output interface selected" "0,1,2,3"
|
|
line.long 0x24 "RFBI_ONOFF_TIME__0,"
|
|
bitfld.long 0x24 24.--29. "REOFFTIME,Read Enable de-assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x24 20.--23. "REONTIME,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 14.--19. "WEOFFTIME,Write Enable de-assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x24 10.--13. "WEONTIME,Write Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 4.--9. "CSOFFTIME,CS de-assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x24 0.--3. "CSONTIME,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "RFBI_CYCLE_TIME__0,"
|
|
bitfld.long 0x28 22.--27. "ACCESSTIME,Access Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x28 21. "WRENABLE,Write to Read Pulse Width Enable (same CS) 0h (R/W) = CSPulseWidth does not apply on Write to Read access 1h (R/W) = CSPulseWidth applies on Write to Read access" "0,1"
|
|
bitfld.long 0x28 20. "WWENABLE,Write to Write Pulse Width Enable (same CS) 0h (R/W) = CSPulseWidth does not apply on Write to Write access 1h (R/W) = CSPulseWidth applies on Write to Write access" "0,1"
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newline
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bitfld.long 0x28 19. "RRENABLE,Read to Read Pulse Width Enable (same CS) 0h (R/W) = CSPulseWidth does not apply on Read to Read access 1h (R/W) = CSPulseWidth applies on Read to Read access" "0,1"
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bitfld.long 0x28 18. "RWENABLE,Read to Write Pulse Width Enable (same CS)" "0,1"
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bitfld.long 0x28 12.--17. "CSPULSEWIDTH,CS Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x28 6.--11. "RECYCLETIME,RE Cycle Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 0.--5. "WECYCLETIME,WE Cycle Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x2C "RFBI_DATA_CYCLE1__0,"
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bitfld.long 0x2C 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--20. "NBBITSPIXEL2,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x2C 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x2C 0.--4. "NBBITSPIXEL1,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x30 "RFBI_DATA_CYCLE2__0,"
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bitfld.long 0x30 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--20. "NBBITSPIXEL2,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x30 0.--4. "NBBITSPIXEL1,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x34 "RFBI_DATA_CYCLE3__0,"
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bitfld.long 0x34 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 16.--20. "NBBITSPIXEL2,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x34 0.--4. "NBBITSPIXEL1,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x38 "RFBI_CONFIG__1,"
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bitfld.long 0x38 21. "HSYNCPOLARITY,HSYNC polarity 0h (R/W) = HSYNC active low 1h (R/W) = HSYNC active high" "0,1"
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bitfld.long 0x38 20. "TE_VSYNC_POLARITY,TE or VSYNC Polarity 0h (R/W) = active low 1h (R/W) = active high" "0,1"
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bitfld.long 0x38 19. "CSPOLARITY,CS Polarity 0h (R/W) = CS active low 1h (R/W) = CS active high" "0,1"
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newline
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bitfld.long 0x38 18. "WEPOLARITY,WE Polarity 0h (R/W) = active low 1h (R/W) = active high" "0,1"
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bitfld.long 0x38 17. "REPOLARITY,RE Polarity 0h (R/W) = active low 1h (R/W) = active high" "0,1"
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bitfld.long 0x38 16. "A0POLARITY,A0 Polarity 0h (R/W) = A0 active low 1h (R/W) = A0 active high" "0,1"
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newline
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bitfld.long 0x38 11.--12. "UNUSEDBITS,State of unused bits 0h (R/W) = low level (0) 1h (R/W) = high level (1) 2h (R/W) = unchanged from previous state" "0,1,2,3"
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bitfld.long 0x38 9.--10. "CYCLEFORMAT,Cycle format 0h (R/W) = 1 cycle for 1 pixel 1h (R/W) = 2 cycles for 1 pixel 2h (R/W) = 3 cycles for 1 pixel 3h (R/W) = 3 cycles for 2 pixels" "0,1,2,3"
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bitfld.long 0x38 7.--8. "OCPFORMAT,OCP Write Access format 0h (R/W) = 1 pixel per OCP access to the register data 2h (R/W) = 2 pixels per OCP access to the register data with 1st pixel at the position [15:0] 3h (R/W) = 2 pixels per OCP access to the register data with 1st pixel.." "0,1,2,3"
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newline
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bitfld.long 0x38 5.--6. "DATATYPE,Data type from the display controller and OCP slave port 0h (R/W) = 12-bit 1h (R/W) = 16-bit 2h (R/W) = 18-bit 3h (R/W) = 24-bit" "0,1,2,3"
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bitfld.long 0x38 4. "TIMEGRANULARITY,Multiplies signal timing latencies by two 0h (R/W) = x2 latencies disabled 1h (R/W) = x2 latencies enabled" "0,1"
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bitfld.long 0x38 2.--3. "TRIGGERMODE,Trigger Mode 0h (R/W) = 00 Internal trigger mode (ITE bit mode) 1h (R/W) = Tearing Effect Signal RFBI_TE_VSYNC0 is used with programmable line counter defined in 2h (R/W) = External trigger mode (RFB_TE_VSYNC/RFB_HSYNC with programmable line.." "0,1,2,3"
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newline
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bitfld.long 0x38 0.--1. "PARALLELMODE,Parallel Mode 0h (R/W) = 8-bit parallel output interface selected 1h (R/W) = 9-bit parallel output interface selected 2h (R/W) = 12-bit parallel output interface selected 3h (R/W) = 16-bit parallel output interface selected" "0,1,2,3"
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line.long 0x3C "RFBI_ONOFF_TIME__1,"
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bitfld.long 0x3C 24.--29. "REOFFTIME,Read Enable de-assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x3C 20.--23. "REONTIME,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 14.--19. "WEOFFTIME,Write Enable de-assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x3C 10.--13. "WEONTIME,Write Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 4.--9. "CSOFFTIME,CS de-assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x3C 0.--3. "CSONTIME,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x40 "RFBI_CYCLE_TIME__1,"
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bitfld.long 0x40 22.--27. "ACCESSTIME,Access Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x40 21. "WRENABLE,Write to Read Pulse Width Enable (same CS) 0h (R/W) = CSPulseWidth does not apply on Write to Read access 1h (R/W) = CSPulseWidth applies on Write to Read access" "0,1"
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bitfld.long 0x40 20. "WWENABLE,Write to Write Pulse Width Enable (same CS) 0h (R/W) = CSPulseWidth does not apply on Write to Write access 1h (R/W) = CSPulseWidth applies on Write to Write access" "0,1"
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newline
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bitfld.long 0x40 19. "RRENABLE,Read to Read Pulse Width Enable (same CS) 0h (R/W) = CSPulseWidth does not apply on Read to Read access 1h (R/W) = CSPulseWidth applies on Read to Read access" "0,1"
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bitfld.long 0x40 18. "RWENABLE,Read to Write Pulse Width Enable (same CS)" "0,1"
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bitfld.long 0x40 12.--17. "CSPULSEWIDTH,CS Pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x40 6.--11. "RECYCLETIME,RE Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x40 0.--5. "WECYCLETIME,WE Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x44 "RFBI_DATA_CYCLE1__1,"
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bitfld.long 0x44 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 16.--20. "NBBITSPIXEL2,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x44 0.--4. "NBBITSPIXEL1,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x48 "RFBI_DATA_CYCLE2__1,"
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bitfld.long 0x48 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 16.--20. "NBBITSPIXEL2,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x48 0.--4. "NBBITSPIXEL1,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x4C "RFBI_DATA_CYCLE3__1,"
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bitfld.long 0x4C 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x4C 16.--20. "NBBITSPIXEL2,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x4C 0.--4. "NBBITSPIXEL1,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x50 "RFBI_VSYNC_WIDTH,"
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hexmask.long.word 0x50 0.--15. 1. "MINVSYNCPULSEWIDTH,Programmable min VSYNC pulse width"
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line.long 0x54 "RFBI_HSYNC_WIDTH,"
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hexmask.long.word 0x54 0.--15. 1. "MINHSYNCPULSEWIDTH,Programmable min HSYNC pulse width"
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width 0x0B
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tree.end
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tree "SPI"
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repeat 4. (list 0. 1. 2. 3. )(list ad:0x21805400 ad:0x21805800 ad:0x21805C00 ad:0x21806000)
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tree "SPI$1"
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base $2
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group.long 0x00++0x17
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line.long 0x00 "SPIGCR0,"
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bitfld.long 0x00 0. "RESET,Reset bit for the module" "0,1"
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line.long 0x04 "SPIGCR1,"
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bitfld.long 0x04 24. "ENABLE,SPI enable" "0,1"
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bitfld.long 0x04 16. "LOOPBACK,Internal loop-back test mode" "0,1"
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bitfld.long 0x04 8. "POWERDOWN,When active the SPI state machine enters a power-down state" "0,1"
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bitfld.long 0x04 1. "CLKMOD,Clock mode" "0,1"
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bitfld.long 0x04 0. "MASTER,SPIm_SIMO/SPIm_SOMI pin direction determination" "0,1"
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line.long 0x08 "SPIINT0,"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "0,1"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated every time data is written to the shift register so that a new data can be written to TXBUF" "0,1"
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bitfld.long 0x08 8. "RXINTENA,Receive interrupt enable" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "0,1"
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line.long 0x0C "SPILVL,"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit interrupt level" "0,1"
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive overrun interrupt level" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "0,1"
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line.long 0x10 "SPIFLG,"
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rbitfld.long 0x10 9. "TXINTFLG,Transmitter empty interrupt flag" "0,1"
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bitfld.long 0x10 8. "RXINTFLG,Receiver full interrupt flag" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,This bit is set when a mismatch of internal transmit data and transmitted data is detected" "0,1"
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line.long 0x14 "SPIPC0,"
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bitfld.long 0x14 11. "SOMIFUN,Slave out master in pin function" "0,1"
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bitfld.long 0x14 10. "SIMOFUN,Slave in master out pin function" "0,1"
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bitfld.long 0x14 9. "CLKFUN,SPI clock pin function" "0,1"
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bitfld.long 0x14 0.--1. "SCSFUN,SPI chip select pin function" "0,1,2,3"
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group.long 0x38++0x17
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line.long 0x00 "SPIDAT0,"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI transmit data (value = 0-FFFFh)"
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line.long 0x04 "SPIDAT1,"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "0,1"
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bitfld.long 0x04 24.--25. "DFSEL,Data word format select" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number (value = 0-FFh)"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,Transfer data (value = 0-FFFFh)"
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line.long 0x08 "SPIBUF,"
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bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "0,1"
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "0,1"
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rbitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "0,1"
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bitfld.long 0x08 28. "BITERR,Bit error" "0,1"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI receive data (value = 0-FFFFh)"
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line.long 0x0C "SPIEMU,"
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bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "0,1"
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "0,1"
|
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "0,1"
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "0,1"
|
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI receive data (value = 0-FFFFh)"
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line.long 0x10 "SPIDELAY,"
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hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start delay (value = 0-FFh).SPIDELAY[31-24] C2TDELAY bit is used in master mode only"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive delay (value = 0-FFh).SPIDELAY[23-16] T2CDELAY is used in master mode only"
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line.long 0x14 "SPIDEF,"
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bitfld.long 0x14 0.--1. "CSDEF,Chip Select Default pattern" "0,1,2,3"
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|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "SPI_INTVEC0,"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x04 "SPI_INTVEC1,"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "SPIREV,"
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "SPIFMT$1,"
|
|
bitfld.long 0x00 24.--29. "WDELAY,Delay in between transmissions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20. "SHIFTDIR,Shift direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DISCSTIMERS,Disable chip select timers for this format register" "0,1"
|
|
bitfld.long 0x00 17. "POLARITY,SPI clock polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PHASE,SPI clock delay" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI prescaler (value = 0-FFh)"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "CHARLEN,SPI data word length (value = 0-1Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "Timers"
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6.)(list ad:0x2200000 ad:0x2210000 ad:0x2220000 ad:0x2230000 ad:0x2240000 ad:0x2250000 ad:0x2260000)
|
|
tree "TIMER_$1"
|
|
base $2
|
|
rgroup.long 0x00++0x2B
|
|
line.long 0x00 "TIMER_PID12,"
|
|
line.long 0x04 "TIMER_EMUMGT_CLKSPD,"
|
|
rbitfld.long 0x04 16.--19. "CLKDIV,Clock divide-down ratio bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine how the timer responds to an emulation suspend event" "0,1"
|
|
bitfld.long 0x04 0. "FREE,Used in conjunction with SOFT bit to determine how the timer responds to an emulation suspend event" "0,1"
|
|
line.long 0x08 "TIMER_GPINT_EN,"
|
|
bitfld.long 0x08 25. "GPIO_ENO34,Enable the timer output TOUTH in GPIO mode" "0,1"
|
|
bitfld.long 0x08 24. "GPIO_ENI34,Enable the timer input TINPH in GPIO mode" "0,1"
|
|
bitfld.long 0x08 17. "GPIO_ENO12,Enable the timer output TOUTL in GPIO mode" "0,1"
|
|
bitfld.long 0x08 16. "GPIO_ENI12,Enable the timer input TINPL in GPIO mode" "0,1"
|
|
bitfld.long 0x08 13. "GPINT34_INVO,Invert bit for timer output TOUTH when it is used to source an interrupt or event (GPINT34_ENO=1)" "0,1"
|
|
bitfld.long 0x08 12. "GPINT34_INVI,Invert bit for timer input TINPH when it is used to source an interrupt or event (GPINT34_ENI=1)" "0,1"
|
|
bitfld.long 0x08 9. "GPINT34_ENO,Enable the timer output TOUTH to source the interrupt or event in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "GPINT34_ENI,Enable the timer input TINPH to source the interrupt or event in GPIO mode" "0,1"
|
|
bitfld.long 0x08 5. "GPINT12_INVO,Invert bit for timer output TOUTL when it is used to source an interrupt or event (GPINT12_ENO=1)" "0,1"
|
|
bitfld.long 0x08 4. "GPINT12_INVI,Invert bit for timer input TINPL when it is used to source an interrupt or event (GPINT12_ENI=1)" "0,1"
|
|
bitfld.long 0x08 1. "GPINT12_ENO,Enable the timer output TOUTL to source the interrupt or event in GPIO mode" "0,1"
|
|
bitfld.long 0x08 0. "GPINT12_ENI,Enable the timer input TINPL to source the interrupt or event in GPIO mode" "0,1"
|
|
line.long 0x0C "TIMER_GPDIR_DAT,"
|
|
bitfld.long 0x0C 25. "GPIO_DIRO34,Controls the direction of the timer output TOUTH in GPIO mode" "0,1"
|
|
bitfld.long 0x0C 24. "GPIO_DIRI34,Controls the direction of the timer input TINPH in GPIO mode" "0,1"
|
|
bitfld.long 0x0C 17. "GPIO_DIRO12,Controls the direction of the timer output TOUTL in GPIO mode" "0,1"
|
|
bitfld.long 0x0C 16. "GPIO_DIRI12,Controls the direction of the timer input TINPL in GPIO mode" "0,1"
|
|
bitfld.long 0x0C 9. "GPIO_DATO34,When GPIO_DIRO34=0: timer output TOUTH functions as a GPIO input the logic value read in this bit is equal to the logic level present at the timer input" "0,1"
|
|
bitfld.long 0x0C 8. "GPIO_DATI34,When GPIO_DIRI34=0: timer input TINPH functions as a GPIO input the logic value read in this bit is equal to the logic level present at the timer input" "0,1"
|
|
bitfld.long 0x0C 1. "GPIO_DATO12,When GPIO_DIRO12=0: timer output TOUTL functions as a GPIO input the logic value read in this bit is equal to the logic level present at the timer input" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "GPIO_DATI12,When GPIO_DIRI12=0: timer input TINPL functions as a GPIO input the logic value read in this bit is equal to the logic level present at the timer input" "0,1"
|
|
line.long 0x10 "TIMER_CNTLO,"
|
|
line.long 0x14 "TIMER_CNTHI,"
|
|
line.long 0x18 "TIMER_PRDLO,"
|
|
line.long 0x1C "TIMER_PRDHI,"
|
|
line.long 0x20 "TIMER_TCR,"
|
|
bitfld.long 0x20 28.--29. "CAPEVTMODE_HI,Capture event mode for TIMHI" "0,1,2,3"
|
|
bitfld.long 0x20 27. "CAPMODE_HI,Capture mode enable bit for TIMHI" "0,1"
|
|
bitfld.long 0x20 26. "READRSTMODE_HI,Read reset mode enable bit for TIMHI" "0,1"
|
|
bitfld.long 0x20 25. "TIEN_HI,Timer input enable bit determines if the timer clock is gated by the timer input" "0,1"
|
|
bitfld.long 0x20 24. "CLKSRC_HI,Clock source bit determines the clock source for the timer" "0,1"
|
|
bitfld.long 0x20 22.--23. "ENAMODE_HI,A value written to this Enabling mode bits determine the timer mode for TIMHI" "0,1,2,3"
|
|
bitfld.long 0x20 20.--21. "PWID_HI,Pulse width bits for TIMHI" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 19. "CP_HI,Clock/pulse mode bit for TIMHI" "0,1"
|
|
bitfld.long 0x20 18. "INVINP_HI,Timer input inverter control bit for TIMHI" "0,1"
|
|
bitfld.long 0x20 17. "INVOUTP_HI,Timer output inverter control bit for TIMHI" "0,1"
|
|
bitfld.long 0x20 16. "TSTAT_HI,Timer status bit for TIMHI" "0,1"
|
|
bitfld.long 0x20 12.--13. "CAPEVTMODE_LO,Capture event mode" "0,1,2,3"
|
|
bitfld.long 0x20 11. "CAPMODE_LO,Capture mode enable bit" "0,1"
|
|
bitfld.long 0x20 10. "READRSTMODE_LO,Read reset mode enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "TIEN_LO,Timer input enable bit determines if the timer clock is gated by the timer input" "0,1"
|
|
bitfld.long 0x20 8. "CLKSRC_LO,Clock source bit determines the clock source for the timer" "0,1"
|
|
bitfld.long 0x20 6.--7. "ENAMODE_LO,Enabling mode bits determine the timer mode" "0,1,2,3"
|
|
bitfld.long 0x20 4.--5. "PWID_LO,Pulse width bits" "0,1,2,3"
|
|
bitfld.long 0x20 3. "CP_LO,Clock/pulse mode bit for timer output" "0,1"
|
|
bitfld.long 0x20 2. "INVINP_LO,Timer input inverter control bit" "0,1"
|
|
bitfld.long 0x20 1. "INVOUTP_LO,Timer output inverter control bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "TSTAT_LO,Timer status bit" "0,1"
|
|
line.long 0x24 "TIMER_TGCR,"
|
|
bitfld.long 0x24 12.--15. "TDDRHI,Timer divide-down ratio bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 8.--11. "PSCHI,Prescale period bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 4. "PLUSEN,Enable Timer Plus features" "0,1"
|
|
bitfld.long 0x24 2.--3. "TIMMODE,Timer mode bits determine the timer operating mode" "0,1,2,3"
|
|
bitfld.long 0x24 1. "TIMHIRS,TIMHI reset bit" "0,1"
|
|
bitfld.long 0x24 0. "TIMLORS,TIMLO reset bit" "0,1"
|
|
line.long 0x28 "TIMER_WDTCR,"
|
|
hexmask.long.word 0x28 16.--31. 1. "WDKEY,Value = 0000h-FFFFhWatchdog timer service key bits"
|
|
bitfld.long 0x28 15. "WDFLAG,Watchdog timer flag bit" "0,1"
|
|
bitfld.long 0x28 14. "WDEN,Watchdog timer enable bit" "0,1"
|
|
bitfld.long 0x28 12.--13. "WDIKEY,Value = 0h-3hWatchdog idle enable key bits" "0,1,2,3"
|
|
group.long 0x34++0x13
|
|
line.long 0x00 "TIMER_RELLO,"
|
|
line.long 0x04 "TIMER_RELHI,"
|
|
line.long 0x08 "TIMER_CAPLO,"
|
|
line.long 0x0C "TIMER_CAPHI,"
|
|
line.long 0x10 "TIMER_INTCTL_STAT,"
|
|
bitfld.long 0x10 19. "EVTINTSTAT_HI,Interrupt status which reflects the condition that an external event caused a timeout when timer is in capture mode" "0,1"
|
|
bitfld.long 0x10 18. "EVTINTEN_HI,Enables the interrupt generation when timer is in capture mode" "0,1"
|
|
bitfld.long 0x10 17. "PRDINTSTAT_HI,Interrupt status which reflects the condition that timer counter matched the period register when timer is enabled" "0,1"
|
|
bitfld.long 0x10 16. "PRDINTEN_HI,Enable interrupt generation when timer is enabled in 64-bit/32-bit chained/unchained/watchdog modes" "0,1"
|
|
bitfld.long 0x10 3. "EVTINTSTAT_LO,Interrupt status which reflects the condition that an external event caused a timeout when timer is in capture mode" "0,1"
|
|
bitfld.long 0x10 2. "EVTINTEN_LO,Enables the interrupt generation when timer is in capture mode" "0,1"
|
|
bitfld.long 0x10 1. "PRDINTSTAT_LO,Interrupt status which reflects the condition that timer counter matched the period register when timer is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "PRDINTEN_LO,Enable interrupt generation when timer is enabled in 64-bit/32-bit chained/unchained/watchdog modes" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "UART"
|
|
repeat 3. (list 0. 1. 2.)(list ad:0x2530C00 ad:0x2531000 ad:0x2531400)
|
|
tree "UART_$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UART_RBR,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Received data"
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "UART_THR,"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data to transmit"
|
|
line.long 0x04 "UART_IER,"
|
|
bitfld.long 0x04 3. "EDSSI,Modem status interrupt enable" "Modem status interrupt is disabled,Modem status interrupt is enabled"
|
|
bitfld.long 0x04 2. "ELSI,Receiver line status interrupt enable" "Receiver line status interrupt is disabled,Receiver line status interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x04 1. "ETBEI,Transmitter holding register empty interrupt enable" "Transmitter holding register empty interrupt is..,Transmitter holding register empty interrupt is.."
|
|
bitfld.long 0x04 0. "ERBI,Receiver data available interrupt and character timeout indication interrupt enable" "Receiver data available interrupt and character..,Receiver data available interrupt and character.."
|
|
line.long 0x08 "UART_FCR,"
|
|
bitfld.long 0x08 6.--7. "RXFIFTL,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,14 bytes"
|
|
bitfld.long 0x08 3. "DMAMODE1,DMA MODE1 enable if FIFOs are enabled" "DMA MODE1 is disabled,DMA MODE1 is enabled"
|
|
newline
|
|
bitfld.long 0x08 2. "TXCLR,Transmitter FIFO clear" "No effect,Clears transmitter FIFO.."
|
|
bitfld.long 0x08 1. "RXCLR,Receiver FIFO clear" "No effect,Clears receiver FIFO and.."
|
|
newline
|
|
bitfld.long 0x08 0. "FIFOEN,Transmitter and receiver FIFOs mode enable" "Non-FIFO mode,FIFO mode"
|
|
rgroup.long 0x08++0x23
|
|
line.long 0x00 "UART_IIR,"
|
|
bitfld.long 0x00 6.--7. "FIFOEN,FIFOs enabled" "Non-FIFO mode,Reserved,Reserved,FIFOs are enabled"
|
|
bitfld.long 0x00 1.--3. "INTID,Interrupt type" "Modem status (priority 4 lowest),Transmitter holding register empty (priority 3),Receiver data available (priority 2),Receiver line status (priority 1 highest),Reserved,Reserved,Character timeout indication (priority 2),Reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "IPEND,Interrupt pending.When any UART interrupt is generated and is enabled in" "Interrupts pending,No interrupts pending"
|
|
line.long 0x04 "UART_LCR,"
|
|
bitfld.long 0x04 7. "DLAB,Divisor latch access bit" "Allows access to the receiver buffer register (,Allows access to the divisor latches of the baud.."
|
|
bitfld.long 0x04 6. "BC,Break control" "Break condition is disabled,Break condition is transmitted to the receiving.."
|
|
newline
|
|
bitfld.long 0x04 5. "SP,Stick parity" "Stick parity is disabled,Stick parity is enabled"
|
|
bitfld.long 0x04 4. "EPS,Even parity select" "Odd parity is selected (an odd number of logic..,Even parity is selected (an even number of logic.."
|
|
newline
|
|
bitfld.long 0x04 3. "PEN,Parity enable" "No PARITY bit is transmitted or checked,Parity bit is generated in transmitted data and.."
|
|
bitfld.long 0x04 2. "STB,Number of STOP bits generated" "One STOP bit is generated,WLS bit determines the number of STOP bits"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "WLS,Word length select" "5 bits,6 bits,7 bits,8 bits"
|
|
line.long 0x08 "UART_MCR,"
|
|
bitfld.long 0x08 5. "AFE,Autoflow control enable" "Autoflow control is disabled,Autoflow control is enabled"
|
|
bitfld.long 0x08 4. "LOOP,Loopback mode enable" "Loopback mode is disabled,Loopback mode is enabled"
|
|
newline
|
|
bitfld.long 0x08 3. "OUT2,OUT2 Control Bit" "0,1"
|
|
bitfld.long 0x08 2. "OUT1,OUT1 Control Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "RTS,RTS control" "RTS is disabled only CTS is enabled,RTS and CTS are enabled"
|
|
bitfld.long 0x08 0. "DTR,Data terminal ready control bit" "DTR_0,DTR_1"
|
|
line.long 0x0C "UART_LSR,"
|
|
bitfld.long 0x0C 7. "RXFIFOE,Receiver FIFO error" "There has been no error or RXFIFOE was cleared..,At least one parity error framing error or break.."
|
|
bitfld.long 0x0C 6. "TEMT,Transmitter empty (TEMT) indicator" "Either the transmitter FIFO or the transmitter..,Both the transmitter FIFO and the transmitter.."
|
|
newline
|
|
bitfld.long 0x0C 5. "THRE,Transmitter holding register empty (THRE) indicator" "Transmitter FIFO is not empty,Transmitter FIFO is empty"
|
|
bitfld.long 0x0C 4. "BI,Break indicator" "No break has been detected or the BI bit was..,A break has been detected with the character at.."
|
|
newline
|
|
bitfld.long 0x0C 3. "FE,Framing error (FE) indicator" "No framing error has been detected or the FE bit..,A framing error has been detected with the.."
|
|
bitfld.long 0x0C 2. "PE,Parity error (PE) indicator" "No parity error has been detected or the PE bit..,A parity error has been detected with the.."
|
|
newline
|
|
bitfld.long 0x0C 1. "OE,Overrun error (OE) indicator" "No overrun error has been detected or the OE bit..,Overrun error has been detected"
|
|
bitfld.long 0x0C 0. "DR,Data-ready (DR) indicator for the receiver" "Data is not ready or the DR bit was cleared..,Data is ready"
|
|
line.long 0x10 "UART_MSR,"
|
|
bitfld.long 0x10 7. "CD,Complement of the Carrier Detect input" "0,1"
|
|
bitfld.long 0x10 6. "RI,Complement of the Ring Indicator input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "DSR,Complement of the Data Set Ready input" "0,1"
|
|
bitfld.long 0x10 4. "CTS,Complement of the Clear To Send input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "DCD,Change in DCD indicator bit" "0,1"
|
|
bitfld.long 0x10 2. "TERI,Trailing edge of RI (TERI) indicator bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "DDSR,Change in DSR indicator bit" "0,1"
|
|
bitfld.long 0x10 0. "DCTS,Change in CTS indicator bit" "0,1"
|
|
line.long 0x14 "UART_SCR,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "SCR,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation"
|
|
line.long 0x18 "UART_DLL,"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DLL,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x1C "UART_DLH,"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DLH,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x20 "UART_PID,"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "UART_PWREMU_MGMT,"
|
|
bitfld.long 0x00 15. "URST,This bit resets and enables both the receiver and transmitter" "The receiver and transmitter are disabled and in..,The receiver and transmitter are enabled"
|
|
bitfld.long 0x00 14. "UTRST,UART transmitter reset" "Transmitter is disabled and in reset state,Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "URRST,UART receiver reset" "Receiver is disabled and in reset state,Receiver is enabled"
|
|
bitfld.long 0x00 0. "FREE,Free-running enable mode bit" "If a transmission is not in progress the UART..,Free-running mode is enabled"
|
|
line.long 0x04 "UART_MDR,"
|
|
bitfld.long 0x04 0. "OSM_SEL,Over-Sampling Mode Select" "16x oversampling,13x oversampling"
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.open "USB"
|
|
repeat 2. (list 0. 1.)(list ad:0x2680000 ad:0x2580000)
|
|
tree "USB_$1_CFG"
|
|
base $2
|
|
rgroup.long 0x00++0x1B
|
|
line.long 0x00 "USB_CAPLENGTH,"
|
|
hexmask.long.word 0x00 16.--31. 1. "HCIVERSION,Host Controller Interface Version (xHCI) Number in BCD.Set by"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,Capability Register Length: length of the xHCI Capabilities registers bank in bytes; also the offset of the xHCI Operational registers bank (starting with"
|
|
line.long 0x04 "USB_HCSPARAMS1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "MAXPORTS,See xHCI specification"
|
|
newline
|
|
hexmask.long.word 0x04 8.--18. 1. "MAXINTRS,See xHCI specification"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "MAXSLOTS,See xHCI specification"
|
|
line.long 0x08 "USB_HCSPARAMS2,"
|
|
bitfld.long 0x08 27.--31. "MAXSCRATCHPADBUFS,Max Scratchpad Buffers lower bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 26. "SPR,Scratchpad Restore" "0,1"
|
|
newline
|
|
bitfld.long 0x08 21.--25. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs higher bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 4.--7. "ERSTMAX,Event Ring Segment Table Max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 0.--3. "IST,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "USB_HCSPARAMS3,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency: Worst case latency to transition from U2 to U0 in us"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency: Worst case latency to transition a root hub Port Link State (PLS) from U1 to U0 in us"
|
|
line.long 0x10 "USB_HCCPARAMS,"
|
|
hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilties Pointer"
|
|
newline
|
|
bitfld.long 0x10 12.--15. "MAXPSASIZE,Maximum Primary Stream Array Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 10. "SEC,Stopped EDLTA Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "SPC,Short Packet Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "PAE,Parse All Event Data" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "NSS,No Secondary SID Support" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "LHRC,Light HC Reset Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "PIND,Port Indicators" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "PPC,Port Power Control" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "CSZ,Context Size" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "BNC,BW Negotiation Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "AC64,64-bit Addressing Capability" "0,1"
|
|
line.long 0x14 "USB_DBOFF,"
|
|
hexmask.long 0x14 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Byte address offset MSBs"
|
|
line.long 0x18 "USB_RTSOFF,"
|
|
hexmask.long 0x18 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Byte address offset MSBs"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "USBCMD,"
|
|
bitfld.long 0x00 12. "SPE,Stopped - Short Packet Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EU3S,Enable U3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "EWE,Enable Wrap Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CRS,Controller Restore State" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CSS,Controller Save State" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "LHCRST,Light Host Controller Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HSEE,Host System Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTE,Interrupter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "HCRST,Host Controller Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R_S,Run/Stop" "0,1"
|
|
line.long 0x04 "USBSTS,"
|
|
rbitfld.long 0x04 12. "HCE,Host Controller Error" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 11. "CNR,Controller Not Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10. "SRE,Save/Restore Error" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 9. "RSS,Restore State Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 8. "SSS,Save State Status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "PCD,Port Change Detect" "PCD_0,PCD_1"
|
|
newline
|
|
bitfld.long 0x04 3. "EINT,Event Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "HSE,Host System Error" "HSE_0,HSE_1"
|
|
newline
|
|
rbitfld.long 0x04 0. "HCH,Host Controller Halted" "HCH_0,HCH_1"
|
|
line.long 0x08 "USB_PAGESIZE,"
|
|
hexmask.long.word 0x08 0.--15. 1. "PAGE_SIZE,Supported system memory page size.When bit #n is set to 1 a page size of 2^(n+12) is supported"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "USB_DNCTRL,"
|
|
hexmask.long.word 0x00 0.--15. 1. "N0_N15,Notification Enable (N0 - N15)"
|
|
line.long 0x04 "USB_CRCR_LO,"
|
|
hexmask.long 0x04 6.--31. 1. "CMD_RING_PNTR,Command Ring Pointer"
|
|
newline
|
|
bitfld.long 0x04 3. "CRR,Command Ring Running" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "CA,Command Abort" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "CS,Command Stop" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "RCS,Ring Cycle State" "0,1"
|
|
line.long 0x08 "USB_CRCR_HI,"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "USB_DCBAAP_LO,"
|
|
hexmask.long 0x00 6.--31. 1. "DEVICE_CONTEXT_BAAP,Device Context Base Address Array Pointer"
|
|
line.long 0x04 "USB_DCBAAP_HI,"
|
|
line.long 0x08 "USB_CONFIG,"
|
|
hexmask.long.byte 0x08 0.--7. 1. "MAXSLOTSEN,Max Device Slots Enabled"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "USB_PORTLI,"
|
|
hexmask.long.word 0x00 0.--15. 1. "LINK_ERROR_COUNT,Link Error Count"
|
|
group.long 0x430++0x13
|
|
line.long 0x00 "USB_PORTSC,"
|
|
bitfld.long 0x00 31. "WPR,Warm Port Reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 30. "DR,Device Removable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "WOE,Wake on Over-current Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "WDE,Wake on Disconnect Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WCE,Wake on Connect Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24. "CAS,Cold Attach Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CEC,Port Config Error Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "PLC,Port Link State Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "PRC,Port Reset Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "OCC,Over-current Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "WRC,Warm Port Reset Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PEC,Port Enabled/Disabled Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CSC,Connect Status Change" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "LWS,Port Link State Write Strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PIC,Port Indicator Control" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 10.--13. "PORTSPEED,Port Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 9. "PP,Port Power" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "PLS,Port Link State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4. "PR,Port Reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "OCA,Over-current Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PED,Port Enabled/Disabled" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "CCS,Current Connect Status" "0,1"
|
|
line.long 0x04 "USB_PORTPMSC,"
|
|
bitfld.long 0x04 16. "FLA,Force Link PM Accept (FLA)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "U2_TIMEOUT,U2 Timeout"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "U1_TIMEOUT,U1 Timeout"
|
|
line.long 0x08 "USB_RESERVED,"
|
|
hexmask.long.word 0x08 0.--15. 1. "LINK_ERROR_COUNT,Link Error Count"
|
|
line.long 0x0C "USB_PORTHLPMC,"
|
|
bitfld.long 0x0C 10.--13. "HIRDD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x0C 2.--9. 1. "L1_TIMEOUT,L1 Timeout"
|
|
newline
|
|
bitfld.long 0x0C 0.--1. "HIRDM,Host Initiated Resume Duration Mode" "0,1,2,3"
|
|
line.long 0x10 "USB_MFINDEX,"
|
|
hexmask.long.word 0x10 0.--13. 1. "MICROFRAME_INDEX,The value in this register increments at the end of each microframe (e.g. 125us.)"
|
|
group.long 0xA60++0x07
|
|
line.long 0x00 "USBLEGSUP,"
|
|
bitfld.long 0x00 24. "HC_OS_OWNED,HC OS Owned Semaphore" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "HC_BIOS_OWNED,HC BIOS Owned Semaphore: See xHCI specification" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAPABILITY_POINTER,Next Capability Pointer: 32-bit dword offset of the next xHCI extended capability pointer"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_ID,Extended Capability ID code (descriptor size in bytes)"
|
|
line.long 0x04 "USBLEGCTLSTS,"
|
|
bitfld.long 0x04 31. "SMI_ON_BAR,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 30. "SMI_ON_PCI,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 29. "SMI_ON_OS,See xHCI specification" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 20. "SMI_ON_HOST,See xHCI specification" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 16. "SMI_ON_EVENT,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 15. "SMI_ON_BAR_E,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 14. "SMI_ON_PCI_E,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 13. "SMI_ON_OS_E,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "SMI_ON_HOST_E,See xHCI specification" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "USB_SMI_ENABLE,See xHCI specification" "0,1"
|
|
rgroup.long 0xA70++0x2B
|
|
line.long 0x00 "USB_SUPTPRT2_DW0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR_REVISION,Major Revision BCD-encoded"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR_REVISION,Minor Revision BCD-encoded"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAPABILITY_POINTER,Next Capability Pointer: 32-bit dword offset of the next xHCI extended capability pointer"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_ID,Extended Capability ID code (descriptor size in bytes)"
|
|
line.long 0x04 "USB_SUPTPRT2_DW1,"
|
|
line.long 0x08 "USB_SUPTPRT2_DW2,"
|
|
bitfld.long 0x08 28.--31. "PSIC,Port Speed ID Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 25.--27. "MHD,Hub Depth" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 20. "BLC,BESL LPM Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. "HLC,Hardware LPM Capability" "0,1"
|
|
newline
|
|
bitfld.long 0x08 18. "IHI,Integrated Hub Implemented" "0,1"
|
|
newline
|
|
bitfld.long 0x08 17. "HSO,High-Speed Only" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. "COMPATIBLE_PORT_COUNT,Compatible Port Count"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "COMPATIBLE_PORT_OFFSET,Compatible Port Offset"
|
|
line.long 0x0C "USB_SUPTPRT2_DW3,"
|
|
bitfld.long 0x0C 0.--4. "PROTCL_SLT_TY,Protocol Slot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "USB_SUPTPRT3_DW0,"
|
|
hexmask.long.byte 0x10 24.--31. 1. "MAJOR_REVISION,Major Revision BCD-encoded"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. "MINOR_REVISION,Minor Revision BCD-encoded"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NEXT_CAPABILITY_POINTER,Next Capability Pointer: 32-bit dword offset of the next xHCI extended capability pointer"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "CAPABILITY_ID,Extended Capability ID code (descriptor size in bytes)"
|
|
line.long 0x14 "USB_SUPTPRT3_DW1,"
|
|
line.long 0x18 "USB_SUPTPRT3_DW2,"
|
|
bitfld.long 0x18 28.--31. "PSIC,Port Speed ID Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 25.--27. "MHD,Hub Depth" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "COMPATIBLE_PORT_COUNT,Compatible Port Count"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "COMPATIBLE_PORT_OFFSET,Compatible Port Offset"
|
|
line.long 0x1C "USB_SUPTPRT3_DW3,"
|
|
bitfld.long 0x1C 0.--4. "PROTCL_SLT_TY,Protocol Slot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "USB_DCID,"
|
|
bitfld.long 0x20 16.--20. "DCERSTMAX,Debug Capability Event Ring Segment Table Max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--15. 1. "NEXT_CAPABILITY_POINTER,Next Capability Pointer"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "CAPABILITY_ID,Capability ID"
|
|
line.long 0x24 "USB_DCDB,"
|
|
hexmask.long.byte 0x24 8.--15. 1. "DBTARGET,Doorbell Target (DB Target)"
|
|
line.long 0x28 "USB_DCERSTSZ,"
|
|
hexmask.long.word 0x28 0.--15. 1. "ERS_TABLE_SIZE,Event Ring Segment Table Size"
|
|
group.long 0xAA0++0x1B
|
|
line.long 0x00 "USB_DCERSTBA_LO,"
|
|
hexmask.long 0x00 4.--31. 1. "ERS_TABLE_BAR,Event Ring Segment Table Base Address"
|
|
line.long 0x04 "USB_DCERSTBA_HI,"
|
|
line.long 0x08 "USB_DCERDP_LO,"
|
|
hexmask.long 0x08 4.--31. 1. "DEQUEUE_POINTER,Dequeue Pointer"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "DESI,Dequeue ERST Segment Index" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "USB_DCERDP_HI,"
|
|
line.long 0x10 "USB_DCCTRL,"
|
|
bitfld.long 0x10 31. "DCE,Debug Capability Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 24.--30. 1. "DEVICE_ADDRESS,Device Address"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. "DEBUG_MAX_BURST_SIZE,Debug Max Burst Size"
|
|
newline
|
|
bitfld.long 0x10 4. "DRC,DbC Run Change" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "HIT,Halt IN TR" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "HOT,Halt OUT TR" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "LSE,Link Status Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "DCR,DbC Run" "0,1"
|
|
line.long 0x14 "USB_DCST,"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DEBUG_PORT_NUMBER,Debug Port Number"
|
|
newline
|
|
bitfld.long 0x14 0. "ER,Event Ring Not Empty" "0,1"
|
|
line.long 0x18 "USB_DCPORTSC,"
|
|
bitfld.long 0x18 23. "CEC,Port Config Error Change" "0,1"
|
|
newline
|
|
bitfld.long 0x18 22. "PLC,Port Link Status Change" "0,1"
|
|
newline
|
|
bitfld.long 0x18 21. "PRC,Port Reset Change" "0,1"
|
|
newline
|
|
bitfld.long 0x18 17. "CSC,Connect Status Change" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10.--13. "PORTSPEED,Port Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x18 5.--8. "PLS,Port Link State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x18 4. "PR,Port Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "PED,Port Enabled/Disabled" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 0. "CCS,Current Connect Status" "0,1"
|
|
group.long 0xAC0++0x0F
|
|
line.long 0x00 "USB_DCCP_LO,"
|
|
hexmask.long 0x00 4.--31. 1. "DCCPR,Debug Capability Context Pointer"
|
|
line.long 0x04 "USB_DCCP_HI,"
|
|
line.long 0x08 "USB_DCDDI1,"
|
|
hexmask.long.word 0x08 16.--31. 1. "VENDORID,Vendor ID"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "DBCPROTOCOL,DbC Protocol"
|
|
line.long 0x0C "USB_DCDDI2,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "DEVICEREV,Device Revision"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "PRODUCTID,Product ID"
|
|
group.long 0xC100++0x77
|
|
line.long 0x00 "USB_GSBUSCFG0,"
|
|
bitfld.long 0x00 28.--31. "DATRDREQINFO,AHB-prot/AXI-cache/OCP-ReqInfo for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "DESRDREQINFO,AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DATWRREQINFO,AHB-prot/AXI-cache/OCP-ReqInfo for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DESWRREQINFO,AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14. "SINGREQ,Force Single Request on Bus" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "STOREANDFORWARD,SoC Bus Store-and-Forward Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DATBIGEND,Endian mode for data accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DESBIGEND,Descriptor Access is Big Endian" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INCR256BRSTENA,INCR256 Burst Type Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INCR128BRSTENA,INCR128 Burst Type Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INCR64BRSTENA,INCR64 Burst Type Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INCR32BRSTENA,INCR32 Burst Type Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INCR16BRSTENA,INCR16 Burst Type Enable" "0,1"
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newline
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bitfld.long 0x00 2. "INCR8BRSTENA,INCR8 Burst Type Enable" "0,1"
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newline
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bitfld.long 0x00 1. "INCR4BRSTENA,INCR4 Burst Type Enable" "0,1"
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bitfld.long 0x00 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable: DO NOT ENABLE When enabled this has higher priority than other burst types" "0,1"
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line.long 0x04 "USB_GSBUSCFG1,"
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bitfld.long 0x04 12. "EN1KPAGE,1k-page Boundary Enable" "0,1"
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bitfld.long 0x04 8.--11. "PIPETRANSLIMIT,AXI Pipelined Transfers Burst Request Limit: The field controls the number of outstanding pipelined transfers requests the AXI master pushes to the AXI slave" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. "DATADRSPC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "DESADRSPC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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line.long 0x08 "USB_GTXTHRCFG,"
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bitfld.long 0x08 31. "USBISOTHREN,USB Isochronous IN Endpoints Threshold Enable" "0,1"
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bitfld.long 0x08 29. "USBTXPKTCNTSEL,USB Transmit Packet Count Enable" "0,1"
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bitfld.long 0x08 24.--27. "USBTXPKTCNT,USB Transmit Packet Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x08 16.--23. 1. "USBMAXTXBURSTSIZE,USB Maximum TX Burst Size"
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newline
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bitfld.long 0x08 15. "SBUSISOTHREN,SoC Bus Isochronous IN Endpoints Threshold Enable" "0,1"
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line.long 0x0C "USB_GRXTHRCFG,"
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bitfld.long 0x0C 29. "USBRXPKTCNTSEL,USB ReceivePacket Count Enable" "0,1"
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bitfld.long 0x0C 24.--27. "USBRXPKTCNT,USB Receive Packet Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x0C 19.--23. "USBMAXRXBURSTSIZE,USB Maximum Receive Burst Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "USB_GCTL,"
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hexmask.long.word 0x10 19.--31. 1. "PWRDNSCALE,Power Down Scale: In P3 state PIPE clock stops and is replaced internally by the suspend clock to create a 16kHz reference"
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bitfld.long 0x10 18. "MASTERFILTBYPASS,Master Filter Bypass" "0,1"
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bitfld.long 0x10 17. "BYPSSETADDR,Bypass SetAddress in Device Mode" "0,1"
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bitfld.long 0x10 16. "U2RSTECN,If the super speed connection fails during POLL or LMP exchange the device connects at non-SS mode" "0,1"
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bitfld.long 0x10 14.--15. "FRMSCLDWN,Frame scale-down" "0,1,2,3"
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bitfld.long 0x10 12.--13. "PRTCAPDIR,Port Capability Direction" "0,1,2,3"
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newline
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bitfld.long 0x10 11. "CORESOFTRESET,Core Soft Reset" "0,1"
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bitfld.long 0x10 10. "SOFITPSYNC,If this bit is set to 0x0 operating in host mode the core keeps the UTMI/ULPI PHY on the first port in a non-suspended state whenever there is a SuperSpeed port that is not in Rx.Detect SS.Disable and U3" "0,1"
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bitfld.long 0x10 9. "U1U2TIMERSCALE,Disable U1/U2 Timer Scaledown" "0,1"
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newline
|
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bitfld.long 0x10 8. "DEBUGATTACH,Debug Attach" "0,1"
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newline
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bitfld.long 0x10 6.--7. "RAMCLKSEL,RAM Clock Select" "0,1,2,3"
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newline
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bitfld.long 0x10 4.--5. "SCALEDOWN,Scale - Down mode" "0,1,2,3"
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bitfld.long 0x10 3. "DISSCRAMBLE,Disable Scrambling" "0,1"
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bitfld.long 0x10 2. "U2EXIT_LFPS,This bit is added to improve interoperability with a third party host controller" "0,1"
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rbitfld.long 0x10 1. "GBLHIBERNATIONEN,This bit enables hibernation at the global level" "0,1"
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bitfld.long 0x10 0. "DSBLCLKGTNG,Disable Clock Gating" "0,1"
|
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line.long 0x14 "USB_GPMSTS,"
|
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bitfld.long 0x14 28.--31. "PORTSEL,This field selects the port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 12.--15. "U3WAKEUP,This field gives the following USB 3.0 port wakeup conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x14 0.--8. 1. "U2WAKEUP,This field indicates the following USB 2.0 port wakeup conditions"
|
|
line.long 0x18 "USB_GSTS,"
|
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hexmask.long.word 0x18 20.--31. 1. "CBELT,Current BELT Value: In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command"
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|
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bitfld.long 0x18 11. "SSIC_IP,Reg field SSIC_IP - SSIC Interuupt Pending" "0,1"
|
|
newline
|
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bitfld.long 0x18 10. "OTG_IP,OTG Interrupt Pending" "0,1"
|
|
newline
|
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bitfld.long 0x18 9. "BC_IP,Battery Charger Interrupt Pending" "0,1"
|
|
newline
|
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bitfld.long 0x18 8. "ADP_IP,ADP Interrupt Pending" "0,1"
|
|
newline
|
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bitfld.long 0x18 7. "HOST_IP,Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue" "0,1"
|
|
newline
|
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bitfld.long 0x18 6. "DEVICE_IP,Device Interrupt Pending: This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue" "0,1"
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|
newline
|
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bitfld.long 0x18 5. "CSRTIMEOUT,Control/Status Register access Timeout status flag" "No action,Clear the status flag"
|
|
newline
|
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bitfld.long 0x18 4. "BUSERRADDRVLD,Bus Error Address Valid status flag" "No action,Clear the status flag"
|
|
newline
|
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bitfld.long 0x18 0.--1. "CURMOD,Current Mode of Operation" "0,1,2,3"
|
|
line.long 0x1C "USB_GUCTL1,"
|
|
bitfld.long 0x1C 8. "L1_SUSP_THRLD_EN_FOR_HOST,This bit is used only in host mode" "0,1"
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|
newline
|
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bitfld.long 0x1C 4.--7. "L1_SUSP_THRLD_FOR_HOST,This field is effective only when the L1_SUSP_THRLD_FOR_HOST bit is set to 0x1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x1C 3. "HC_ERRATA_ENABLE,Host Errata Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "OVRLD_L1_SUSP_COM,If this bit is set the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal" "0,1"
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newline
|
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bitfld.long 0x1C 0. "LOA_FILTER_EN,If this bit is set the USB 2.0 port babble is checked at least three consecutive times before the port is disabled" "0,1"
|
|
line.long 0x20 "USB_GSNPSID,"
|
|
line.long 0x24 "USB_GGPIO,"
|
|
hexmask.long.word 0x24 16.--31. 1. "GPO,General Purpose Output"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "GPI,General Purpose Input"
|
|
line.long 0x28 "USB_GUID,"
|
|
line.long 0x2C "USB_GUCTL,"
|
|
hexmask.long.word 0x2C 22.--31. 1. "REFCLKPER,This field indicates in terms of nano seconds the period of ref_clk"
|
|
newline
|
|
bitfld.long 0x2C 21. "NOEXTRDL,No Extra Delay between SOF and the first packet (when host)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 18.--20. "PSQEXTRRESSP,Protocol Status Queue Extra Reserved Space" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x2C 17. "SPRSCTRLTRANSEN,Sparse Control Transaction Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 16. "RESBWHSEPS,Reserving 85% Bandwidth for HS Periodic EPs" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 15. "CMDEVADDR,Compliance Mode for Device Address" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 14. "USBHSTINAUTORETRYEN,Host IN Auto Retry" "0,1"
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|
newline
|
|
bitfld.long 0x2C 13. "ENOVERLAPCHK,Enable Check for LFPS Overlap During Remote Ux Exit" "When the link exists U1/U2/U3 because of a..,The SuperSpeed link when exiting U1/U2/U3 waits.."
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|
newline
|
|
bitfld.long 0x2C 12. "EXTCAPSUPPTEN,External Extended Capability Support Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 11. "INSRTEXTRFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions" "0,1"
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|
newline
|
|
bitfld.long 0x2C 9.--10. "DTCT,Device Timeout Coarse Tuning" "0,1,2,3"
|
|
newline
|
|
abitfld.long 0x2C 0.--8. "DTFT,Device Timeout Fine Tuning" "0x002=2*256*8 = 4usec timeout,0x005=5*256*8 = 10usec timeout0xA,0x010=16*256*8 = 32usec timeout0x19"
|
|
line.long 0x30 "USB_GBUSERRADDRLO,"
|
|
line.long 0x34 "USB_GBUSERRADDRHI,"
|
|
line.long 0x38 "USB_GPRTBIMAPLO,"
|
|
rbitfld.long 0x38 28.--31. "BINUM8,SS USB Instance Number for Port number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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rbitfld.long 0x38 24.--27. "BINUM7,SS USB Instance Number for Port number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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rbitfld.long 0x38 20.--23. "BINUM6,SS USB Instance Number for Port number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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rbitfld.long 0x38 16.--19. "BINUM5,SS USB Instance Number for Port number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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rbitfld.long 0x38 12.--15. "BINUM4,SS USB Instance Number for Port number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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rbitfld.long 0x38 8.--11. "BINUM3,SS USB Instance Number for Port number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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newline
|
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rbitfld.long 0x38 4.--7. "BINUM2,SS USB Instance Number for Port number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x38 0.--3. "BINUM1,SS USB Instance Number for Port number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x3C "USB_GPRTBIMAPHI,"
|
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bitfld.long 0x3C 24.--27. "BINUM15,SS USB Instance Number for Port number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x3C 20.--23. "BINUM14,SS USB Instance Number for Port number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x3C 16.--19. "BINUM13,SS USB Instance Number for Port number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x3C 12.--15. "BINUM12,SS USB Instance Number for Port number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x3C 8.--11. "BINUM11,SS USB Instance Number for Port number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x3C 4.--7. "BINUM10,SS USB Instance Number for Port number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x3C 0.--3. "BINUM9,SS USB Instance Number for Port number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x40 "USB_GHWPARAMS0,"
|
|
hexmask.long.byte 0x40 24.--31. 1. "GHWPARAMS0_31_24,Reg field CORECONSULTANT"
|
|
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|
|
hexmask.long.byte 0x40 16.--23. 1. "GHWPARAMS0_23_16,Reg field CORECONSULTANT"
|
|
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|
|
hexmask.long.byte 0x40 8.--15. 1. "GHWPARAMS0_15_8,Reg field CORECONSULTANT"
|
|
newline
|
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bitfld.long 0x40 6.--7. "GHWPARAMS0_7_6,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
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bitfld.long 0x40 3.--5. "GHWPARAMS0_5_3,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x40 0.--2. "GHWPARAMS0_2_0,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
|
|
line.long 0x44 "USB_GHWPARAMS1,"
|
|
bitfld.long 0x44 31. "GHWPARAMS1_31,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 30. "GHWPARAMS1_30,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 29. "GHWPARAMS1_29,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 28. "GHWPARAMS1_28,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 27. "GHWPARAMS1_27,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 26. "GHWPARAMS1_26,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 24.--25. "GHWPARAMS1_25_24,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x44 23. "GHWPARAMS1_23,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x44 21.--22. "GHWPARAMS1_22_21,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x44 15.--20. "GHWPARAMS1_20_15,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
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bitfld.long 0x44 12.--14. "GHWPARAMS1_14_12,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x44 9.--11. "GHWPARAMS1_11_9,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x44 6.--8. "GHWPARAMS1_8_6,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
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|
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|
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bitfld.long 0x44 3.--5. "GHWPARAMS1_5_3,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
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|
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|
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bitfld.long 0x44 0.--2. "GHWPARAMS1_2_0,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7"
|
|
line.long 0x48 "USB_GHWPARAMS2,"
|
|
line.long 0x4C "USB_GHWPARAMS3,"
|
|
bitfld.long 0x4C 31. "GHWPARAMS3_31,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
hexmask.long.byte 0x4C 23.--30. 1. "GHWPARAMS3_30_23,Reg field CORECONSULTANT"
|
|
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|
|
bitfld.long 0x4C 18.--22. "GHWPARAMS3_22_18,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
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bitfld.long 0x4C 12.--17. "GHWPARAMS3_17_12,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
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|
|
bitfld.long 0x4C 11. "GHWPARAMS3_11,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x4C 10. "GHWPARAMS3_10,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x4C 8.--9. "GHWPARAMS3_9_8,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x4C 6.--7. "GHWPARAMS3_7_6,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x4C 4.--5. "GHWPARAMS3_5_4,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x4C 2.--3. "GHWPARAMS3_3_2,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x4C 0.--1. "GHWPARAMS3_1_0,Reg field CORECONSULTANT" "0,1,2,3"
|
|
line.long 0x50 "USB_GHWPARAMS4,"
|
|
bitfld.long 0x50 28.--31. "GHWPARAMS4_31_28,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x50 24.--27. "GHWPARAMS4_27_24,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x50 23. "GHWPARAMS4_23,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x50 22. "GHWPARAMS4_22,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x50 21. "GHWPARAMS4_21,Reg field CORECONSULTANT" "0,1"
|
|
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|
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bitfld.long 0x50 17.--20. "GHWPARAMS4_20_17,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x50 13.--16. "GHWPARAMS4_16_13,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x50 12. "GHWPARAMS4_12,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x50 11. "GHWPARAMS4_11,Reg field CORECONSULTANT" "0,1"
|
|
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|
|
bitfld.long 0x50 9.--10. "GHWPARAMS4_10_9,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x50 7.--8. "GHWPARAMS4_8_7,Reg field CORECONSULTANT" "0,1,2,3"
|
|
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|
|
bitfld.long 0x50 6. "GHWPARAMS4_6,Reg field CORECONSULTANT" "0,1"
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bitfld.long 0x50 0.--5. "GHWPARAMS4_5_0,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x54 "USB_GHWPARAMS5,"
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bitfld.long 0x54 28.--31. "GHWPARAMS5_31_28,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x54 22.--27. "GHWPARAMS5_27_22,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x54 16.--21. "GHWPARAMS5_21_16,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x54 10.--15. "GHWPARAMS5_15_10,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x54 4.--9. "GHWPARAMS5_9_4,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x54 0.--3. "GHWPARAMS5_3_0,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x58 "USB_GHWPARAMS6,"
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hexmask.long.word 0x58 16.--31. 1. "GHWPARAMS6_31_16,Reg field CORECONSULTANT"
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bitfld.long 0x58 15. "BUSFLTRSSUPPORT,DWC_USB3_EN_BUS_FILTERS" "0,1"
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bitfld.long 0x58 14. "BCSUPPORT,DWC_USB3_EN_BC: OTG 3.0 Support Enabled" "No OTG 3.0 support,Supports OTG 3.0"
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bitfld.long 0x58 13. "OTG_SS_SUPPORT,Reg field CORECONSULTANT" "0,1"
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bitfld.long 0x58 12. "ADPSUPPORT,DWC_USB3_EN_ADP" "0,1"
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bitfld.long 0x58 11. "HNPSUPPORT,RSP/HNP Support Enabled: The application uses this bit to determine the DWC_usb3 core's RSP/HNP support" "0,1"
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bitfld.long 0x58 10. "SRPSUPPORT,SRP Support Enabled" "0,1"
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bitfld.long 0x58 8.--9. "GHWPARAMS6_9_8,Reg field CORECONSULTANT" "0,1,2,3"
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bitfld.long 0x58 7. "GHWPARAMS6_7,Reg field CORECONSULTANT" "0,1"
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bitfld.long 0x58 6. "GHWPARAMS6_6,Reg field CORECONSULTANT" "0,1"
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bitfld.long 0x58 0.--5. "GHWPARAMS6_5_0,Reg field CORECONSULTANT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x5C "USB_GHWPARAMS7,"
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hexmask.long.word 0x5C 16.--31. 1. "GHWPARAMS7_31_16,Reg field CORECONSULTANT"
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hexmask.long.word 0x5C 0.--15. 1. "GHWPARAMS7_15_0,Reg field CORECONSULTANT"
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line.long 0x60 "USB_GDBGFIFOSPACE,"
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hexmask.long.word 0x60 16.--31. 1. "SPACE_AVAILABLE,Space Available"
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abitfld.long 0x60 0.--7. "FIFO_QUEUE_SELECT,FIFO/Queue Select or port select" "0x00=SELECT-320xA2,0x1F=SELECT-1280x60,0x3F=RX FIFO number"
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line.long 0x64 "USB_GDBGLTSSM,"
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bitfld.long 0x64 29. "X3_XS_SWAPPING," "0,1"
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bitfld.long 0x64 28. "X3_DS_HOST_SHUTDOWN," "0,1"
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bitfld.long 0x64 27. "PRTDIRECTION,Current direction of the port" "0,1"
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bitfld.long 0x64 26. "LTDBTIMEOUT,LTSSM Debug Timeout" "0,1"
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bitfld.long 0x64 22.--25. "LTDBLINKSTATE,LTSSM Debug: Link State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x64 18.--21. "LTDBSUBSTATE,LTSSM Debug: Link Sub-State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x64 17. "ELASTICBUFFERMODE,Debug PIPE Status: Elastic Buffer Mode" "0,1"
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bitfld.long 0x64 16. "TXELECLDLE,Debug PIPE Status: Tx Elec Idle" "0,1"
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bitfld.long 0x64 15. "RXPOLARITY,Debug PIPE Status: Rx Polarity" "0,1"
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bitfld.long 0x64 14. "TXDETRXLOOPBACK,Debug PIPE Status: Tx Detect Rx/Loopback" "0,1"
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bitfld.long 0x64 11.--13. "LTDBPHYCMDSTATE,LTSSM Debug PHY Command State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 9.--10. "POWERDOWN,Debug PIPE Status: PowerDown" "0,1,2,3"
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bitfld.long 0x64 8. "RXEQTRAIN,Debug PIPE Status: RxEq Train" "0,1"
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bitfld.long 0x64 6.--7. "TXDEEMPHASIS,Debug PIPE Status: TxDeemphasis" "0,1,2,3"
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bitfld.long 0x64 3.--5. "LTDBCLKSTATE,LTSSM Clock State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 2. "TXSWING,Debug PIPE Status: TxSwing" "0,1"
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bitfld.long 0x64 1. "RXTERMINATION,Debug PIPE Status: RxTermination" "0,1"
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bitfld.long 0x64 0. "TXONESZEROS,Debug PIPE Status: TxOnes/Zeros" "0,1"
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line.long 0x68 "USB_GDBGLNMCC,"
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hexmask.long.word 0x68 0.--8. 1. "LNMCC_BERC,This field indicates the bit error rate information for the port selected in the [3:0] PORTSELECT field"
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line.long 0x6C "USB_GDBGBMU,"
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hexmask.long.tbyte 0x6C 8.--31. 1. "BMU_BCU,BMU Bus Control Unit Debug information"
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bitfld.long 0x6C 4.--7. "BMU_DCU,BMU Data Path (PTL) Control Unit Debug information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x6C 0.--3. "BMU_CCU,BMU Control Path (LSP) Control Unit Debug information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x70 "USB_GDBGLSPMUX_HST,"
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hexmask.long.byte 0x70 16.--23. 1. "LOGIC_ANALYZER_TRACE,Select the 64-bit analyzer trace vector"
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hexmask.long.word 0x70 0.--13. 1. "HOSTSELECT,HostSelect"
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line.long 0x74 "USB_GDBGLSP,"
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group.long 0xC180++0x0F
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line.long 0x00 "USB_GPRTBIMAP_HSLO,"
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rbitfld.long 0x00 28.--31. "BINUM8,HS USB instance number for port number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "BINUM7,HS USB instance number for port number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 20.--23. "BINUM6,HS USB instance number for port number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 16.--19. "BINUM5,HS USB instance number for port number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 12.--15. "BINUM4,HS USB instance number for port number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "BINUM3,HS USB instance number for port number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 4.--7. "BINUM2,HS USB instance number for port number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM1,HS USB instance number for port number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "USB_GPRTBIMAP_HSHI,"
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bitfld.long 0x04 24.--27. "BINUM15,HS USB instance number for port number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 20.--23. "BINUM14,HS USB instance number for port number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "BINUM13,HS USB instance number for port number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 12.--15. "BINUM12,HS USB instance number for port number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "BINUM11,HS USB instance number for port number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. "BINUM10,HS USB instance number for port number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "BINUM9,HS USB instance number for port number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "USB_GPRTBIMAP_FSLO,"
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rbitfld.long 0x08 28.--31. "BINUM8,FS USB instance number for port number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 24.--27. "BINUM7,FS USB instance number for port number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 20.--23. "BINUM6,FS USB instance number for port number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 16.--19. "BINUM5,FS USB instance number for port number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 12.--15. "BINUM4,FS USB instance number for port number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 8.--11. "BINUM3,FS USB instance number for port number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 4.--7. "BINUM2,FS USB instance number for port number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "BINUM1,FS USB instance number for port number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "USB_GPRTBIMAP_FSHI,"
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bitfld.long 0x0C 24.--27. "BINUM15,FS USB instance number for port number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "BINUM14,FS USB instance number for port number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "BINUM13,FS USB instance number for port number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 12.--15. "BINUM12,FS USB instance number for port number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. "BINUM11,FS USB instance number for port number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 4.--7. "BINUM10,FS USB instance number for port number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "BINUM9,FS USB instance number for port number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xC200++0x03
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line.long 0x00 "GUSB2PHYCFG,"
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bitfld.long 0x00 31. "PHYSOFTRST,UTMI PHY Soft Reset" "0,1"
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bitfld.long 0x00 30. "U2_FREECLK_EXISTS,Specifies whether your USB 2.0 PHY provides a free-running PHY clock which is active when the clock control input is active" "0,1"
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bitfld.long 0x00 29. "ULPI_LPM_WITH_OPMODE_CHK,Support the LPM over ULPI without NOPID token to the ULPI PHY" "0,1"
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bitfld.long 0x00 27.--28. "HSIC_CON_WIDTH_ADJ,This bit is used in the HSIC device mode of operation" "0,1,2,3"
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bitfld.long 0x00 26. "INV_SEL_HSIC,The application driver uses this bit to control the HSIC enable/disable function" "0,1"
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bitfld.long 0x00 18. "ULPIEXTVBUSINDIACTOR,Reg field ULPIEXTVBUSINDIACTOR" "0,1"
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bitfld.long 0x00 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive" "0,1"
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bitfld.long 0x00 16. "ULPICLKSUSM,Sets the ClockSuspendM bit in the Interface Control register on the ULPI PHY" "0,1"
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bitfld.long 0x00 15. "ULPIAUTORES,ULPI Auto Resume" "0,1"
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bitfld.long 0x00 10.--13. "USBTRDTIM,USB 2.0 Turnaround Time in PHY clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9. "XCVRDLY,Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp" "0,1"
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bitfld.long 0x00 8. "ENBLSLPM,Enable UTMI Sleep" "0,1"
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bitfld.long 0x00 7. "PHYSEL,PHY Select" "0,1"
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bitfld.long 0x00 6. "SUSPENDUSB20,Suspend enable for USB2.0 HS/FS/LS PHY (ULPI or UTMI)" "0,1"
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rbitfld.long 0x00 5. "FSINTF,Full-Speed Serial Interface Select" "0,1"
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bitfld.long 0x00 4. "ULPI_UTMI_SEL,ULPI or UTMI+ Select: The application uses this bit to select a UTMI+ or ULPI Interface" "0,1"
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bitfld.long 0x00 3. "PHYIF,PHY Interface" "0,1"
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bitfld.long 0x00 0.--2. "B1L,Reg field B1L" "0,1,2,3,4,5,6,7"
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rgroup.long 0xC280++0x03
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line.long 0x00 "GUSB2PHYACC_ULPI,"
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bitfld.long 0x00 26. "DISUIPIDRVR,Disable ULPI Drivers for carkit mode" "0,1"
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bitfld.long 0x00 25. "NEWREGREQ,New Register Request" "No request pendingRead,Access request pending"
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bitfld.long 0x00 24. "VSTSDONE,VStatus Done" "0,1"
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bitfld.long 0x00 23. "VSTSBSY,VStatus Busy" "0,1"
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bitfld.long 0x00 22. "REGWR,Register" "0,1"
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bitfld.long 0x00 16.--21. "REGADDR,Register Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--12. "EXTREGADDR,ULPI: PHY extended register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 0.--7. 1. "REGDATA,Register Data"
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group.long 0xC2C0++0x03
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line.long 0x00 "GUSB3PIPECTL,"
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bitfld.long 0x00 31. "PHYSOFTRST,USB3.0 PHY Soft Reset" "0,1"
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bitfld.long 0x00 30. "HSTPRTCMPL,This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable" "0,1"
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bitfld.long 0x00 29. "U2SSINACTP3OK,P3 OK for U2/SS Inactive" "0,1"
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bitfld.long 0x00 28. "DISRXDETP3,Disabled receiver detection in P3" "0,1"
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bitfld.long 0x00 27. "UX_EXIT_IN_PX,This bit is added for SS PHY workaround where SS PHY injects a glitch on pipe3_RxElecIdle while receiving Ux exit LFPS and pipe3_PowerDown change is in progress" "0,1"
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bitfld.long 0x00 26. "PING_ENHANCEMENT_EN,Ping Enhancement Enable" "0,1"
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bitfld.long 0x00 25. "U1U2EXITFAIL_TO_RECOV,Enhancement to prevent interoperability issue in case of incorrect LFPS handshake by the remote link" "0,1"
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bitfld.long 0x00 24. "REQUEST_P1P2P3,Control the systematic request of P1/P2/P3 for U1/U2/U3" "0,1"
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bitfld.long 0x00 23. "STARTRXDETU3RXDET,Manual control for periodic Rx detection required in U3 and Rx.Detect host mode" "0,1"
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bitfld.long 0x00 22. "DISRXDETU3RXDET,Disable the HW-scheduled periodic Rx detection required in U3 and SS.'Disabled for host mode" "0,1"
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bitfld.long 0x00 19.--21. "DELAYP1P2P3,If DelayP0toP1P2P3=1 delays the transition to P1/P2/P3 when entering U1/U2/U3 until P1P2P3Delay*8b10b errors occur or RxValid=0 on PIPE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18. "DELAYP1TRANS,Delay PHY change from P0 to P1/P2/P3 when link state changes from U0 to U1/U2/U3 respectively" "0,1"
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bitfld.long 0x00 17. "SUSPENDENABLE,Suspend Enable for USB3.0 SS PHY" "0,1"
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|
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rbitfld.long 0x00 15.--16. "DATWIDTH,PIPE Data Width (input from PHY: refer to PIPE standard) Field updated to the input's value immediately after reset" "0,1,2,3"
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bitfld.long 0x00 14. "ABORTRXDETINU2,Abort Rx Detect in U2: This bit is for Downstream port only" "0,1"
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bitfld.long 0x00 13. "SKIPRXDET,Skip Rx Detect: When set the core skips Rx Detection if pipe3_RxElecIdle is low" "0,1"
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bitfld.long 0x00 12. "LFPSP0ALGN,Reserved" "0,1"
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bitfld.long 0x00 11. "P3P2TRANOK,P3-to-P2 Transitions OK" "0,1"
|
|
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|
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bitfld.long 0x00 10. "P3EXSIGP2,PHY power state behaviour upon U3 exit handshake" "0,1"
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bitfld.long 0x00 9. "LFPSFILTER,LFPS Filter" "0,1"
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bitfld.long 0x00 8. "RX_DETECT_TO_POLLING_LFPS_CONTROL,RX_DETECT to Polling LFPS Control" "0,1"
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newline
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bitfld.long 0x00 7. "SSICEN,USB3.0 SSIC Enable" "Pipe interface is active,Pipe interface is inactive"
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bitfld.long 0x00 6. "TX_SWING,Tx Swing (output to PHY: refer to PIPE standard)" "0,1"
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bitfld.long 0x00 3.--5. "TX_MARGIN,Tx Margin[2:0] (output to PHY: refer to PIPE standard)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 1.--2. "TX_DE_EPPHASIS,Tx Deemphasis (output to phy: refer to PIPE standard)" "0,1,2,3"
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bitfld.long 0x00 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (output to PHY: refer to PIPE standard)" "0,1"
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rgroup.long 0xC600++0x03
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line.long 0x00 "USB_GHWPARAMS8,"
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group.long 0xC610++0x03
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line.long 0x00 "USB_GTXFIFOPRIDEV,"
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hexmask.long.word 0x00 0.--15. 1. "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority"
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group.long 0xC618++0x0F
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line.long 0x00 "USB_GTXFIFOPRIHST,"
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bitfld.long 0x00 0.--3. "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "USB_GRXFIFOPRIHST,"
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bitfld.long 0x04 0.--2. "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority" "0,1,2,3,4,5,6,7"
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line.long 0x08 "USB_GFIFOPRIDBC,"
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bitfld.long 0x08 0.--1. "GFIFOPRIDBC,Host DBC DMA priority" "0,1,2,3"
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line.long 0x0C "USB_GDMAHLRATIO,"
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bitfld.long 0x0C 8.--12. "HSTRXFIFO,Host RXFIFO DMA High-Low Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. "HSTTXFIFO,Host TXFIFO DMA High-Low Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC630++0x03
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line.long 0x00 "USB_GFLADJ,"
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bitfld.long 0x00 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,This field indicates that the decrement value that the controller applies for each ref_clk must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk" "0,1"
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hexmask.long.byte 0x00 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock"
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bitfld.long 0x00 23. "GFLADJ_REFCLK_LPM_SEL,This bit enables the functionality of running SOF/ITP counters on the ref_clk" "0,1"
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newline
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hexmask.long.word 0x00 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk"
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newline
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bitfld.long 0x00 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL" "0,1"
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bitfld.long 0x00 0.--5. "GFLADJ_30MHZ,This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0xC700++0x17
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line.long 0x00 "USB_DCFG,"
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bitfld.long 0x00 23. "IGNSTRMPP,Ignore Packet-Pending for Stream management" "0,1"
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bitfld.long 0x00 22. "LPMCAP,Link Power Management (LPM) Capability" "0,1"
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bitfld.long 0x00 17.--21. "NUMP,Number of Receive Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. "INTRNUM,Interrupt Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--11. "PERFRINT,Periodic Frame Interrupt" "0,1,2,3"
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hexmask.long.byte 0x00 3.--9. 1. "DEVADDR,Device Address"
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newline
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bitfld.long 0x00 0.--2. "DEVSPD,Device Speed: USB speed at which the core should connect" "0,1,2,3,4,5,6,7"
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line.long 0x04 "USB_DCTL,"
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bitfld.long 0x04 31. "RUN_STOP,Run/Stop" "0,1"
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newline
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bitfld.long 0x04 30. "CSFTRST,Core Soft Reset" "No ongoing reset reset complete.Read,Start reset (self-clearing)"
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|
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bitfld.long 0x04 24.--28. "HIRDTHRES,Host Initiated Resume Duration (HIRD) Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 20.--23. "LPM_NYET_THRES,LPM Response Programmed by Application: Handshake response made to LPM token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 17. "CRS,Controller Restore State" "0,1"
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bitfld.long 0x04 16. "CSS,Controller Save State" "0,1"
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newline
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bitfld.long 0x04 12. "INITU2ENA,Initiate U2 Enable" "0,1"
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bitfld.long 0x04 11. "ACCEPTU2ENA,Accept U2 Enable" "0,1"
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|
newline
|
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bitfld.long 0x04 10. "INITU1ENA,Initiate U1 Enable" "0,1"
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bitfld.long 0x04 9. "ACCEPTU1ENA,Accept U1 Enable" "0,1"
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bitfld.long 0x04 5.--8. "ULSTCHNGREQ,USB/Link State Change Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 1.--4. "TSTCTL,Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "USB_DEVTEN,"
|
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bitfld.long 0x08 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event" "0,1"
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newline
|
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bitfld.long 0x08 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1"
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newline
|
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bitfld.long 0x08 7. "SOFTEVTEN,Start of (micro)frame event enable" "0,1"
|
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newline
|
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bitfld.long 0x08 6. "U3L2L1SUSPEN,U3/L2-L1 Suspend Event Enable" "0,1"
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newline
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bitfld.long 0x08 5. "HIBERNATIONREQEVTEN,This bit enables/disables the generation of the Hibernation Request Event" "0,1"
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|
newline
|
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bitfld.long 0x08 4. "WKUPEVTEN,Resume/Remote Wakeup Detected Event Enable" "0,1"
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newline
|
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bitfld.long 0x08 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1"
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newline
|
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bitfld.long 0x08 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1"
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|
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bitfld.long 0x08 1. "USBRSTEVTEN,USB Reset Enable" "0,1"
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newline
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bitfld.long 0x08 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1"
|
|
line.long 0x0C "USB_DSTS,"
|
|
bitfld.long 0x0C 29. "DCNRD,Device Controller Not Ready" "0,1"
|
|
newline
|
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bitfld.long 0x0C 27. "PLC,Port Link Status Changed" "0,1"
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|
newline
|
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bitfld.long 0x0C 26. "CSC,Connect Status Changed" "0,1"
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|
newline
|
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bitfld.long 0x0C 25. "RSS,Restore State Status triggered by writing 1 to RSS" "0,1"
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|
newline
|
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bitfld.long 0x0C 24. "SSS,Save State Status triggered by writing 1 to CSS" "0,1"
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|
newline
|
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bitfld.long 0x0C 23. "COREIDLE,Core Idle status" "0,1"
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|
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|
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bitfld.long 0x0C 22. "DEVCTRLHLT,Device Controller Halted" "0,1"
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|
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|
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bitfld.long 0x0C 18.--21. "USBLNKST,USB/Link State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x0C 17. "RXFIFOEMPTY,RxFIFO Empty" "0,1"
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|
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|
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hexmask.long.word 0x0C 3.--16. 1. "SOFFN,Frame/Microframe Number of the Received SOF"
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|
newline
|
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bitfld.long 0x0C 0.--2. "CONNECTSPD,Connected Speed" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "USB_DGCMDPAR,"
|
|
line.long 0x14 "USB_DGCMD,"
|
|
rbitfld.long 0x14 12.--15. "CMDSTATUS,Command Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x14 10. "CMDACT,Command Active" "No action,Start generic command.."
|
|
newline
|
|
bitfld.long 0x14 8. "CMDIOC,Command Interrupt on Complete" "No interrupt on complete,Generic Command Completion event to be issued.."
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "CMDTYP,Command Type"
|
|
group.long 0xC720++0x03
|
|
line.long 0x00 "USB_DALEPENA,"
|
|
group.long 0xCC00++0x13
|
|
line.long 0x00 "USB_OCFG,"
|
|
bitfld.long 0x00 5. "DISPRTPWRCUTOFF,OTG Disable Port Power Cut Off" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "OTGHIBDISMASK,OTG Hibernation Disable Mask" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "OTGSFTRSTMSK,OTG Soft Reset Mask: This bit is used to mask specific soft resets from affecting the OTG functionality of the core" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "OTG_VERSION,This is a debug bit and always write 0x0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "HNPCAP,HNP Capability enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "SRPCAP,SRP Capability enable" "0,1"
|
|
line.long 0x04 "USB_OCTL,"
|
|
bitfld.long 0x04 7. "OTG3_GOERR,OTG 3.0 Go Error State" "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "PERIMODE,Peripheral Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "PRTPWRCTL,Port Power Control" "VBUS drive is offRead,VBUS is driven"
|
|
newline
|
|
bitfld.long 0x04 4. "HNPREQ,HNP Request" "0,1"
|
|
newline
|
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bitfld.long 0x04 3. "SESREQ,Session Request" "All reads return zero,Initiate the SRP (data line pulsing) on the.."
|
|
newline
|
|
bitfld.long 0x04 2. "TERMSELDLPULSE,TermSel Data Line Pulsing Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "DEVSETHNPEN,Device Set HNP Enable" "0,1"
|
|
newline
|
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bitfld.long 0x04 0. "HSTSETHNPEN,Host Set HNP Enable" "0,1"
|
|
line.long 0x08 "USB_OEVT,"
|
|
rbitfld.long 0x08 31. "DEVICEMODE,Device Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x08 27. "OTGXHCIRUNSTPSETEVNT,OTG Host Run Stop Set Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 26. "OTGDEVRUNSTPSETEVNT,OTG Device Run Stop Set Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. "OTGHIBENTRYEVNT,OTG Hibernation Entry Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 24. "OTGCONIDSTSCHNGEVNT,Connector ID Status Change Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 23. "HRRCONFNOTIFEVNT,Host Role Request Confirm Notifier Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 22. "HRRINITNOTIFEVNT,Host Role Request Initiate Notifier Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 21. "OTGADEVIDLEEVNT,A-device A-IDLE Event" "No action,Clear the event"
|
|
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|
|
bitfld.long 0x08 20. "OTGADEVBHOSTENDEVNT,A-device B-Host End Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 19. "OTGADEVHOSTEVNT,A-device host event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 18. "OTGADEVHNPCHNGEVNT,A-Dev HNP Change Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 17. "OTGADEVSRPDETEVNT,SRP Detect Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 16. "OTGADEVSESSENDDETEVNT,Session End Detected Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 11. "OTGBDEVBHOSTENDEVNT,B-Device B-Host End Event: Set in B-device Mode Only" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 10. "OTGBDEVHNPCHNGEVNT,B-Dev HNP Change Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 9. "OTGBDEVSESSVLDDETEVNT,Session Valid Detected Event" "No action Write,Clear the event"
|
|
newline
|
|
bitfld.long 0x08 8. "OTGBDEVVBUSCHNGEVNT,Vbus Change Event" "No action Write,Clear the event"
|
|
newline
|
|
rbitfld.long 0x08 3. "BSESVLD,Indicates the Device mode transceiver status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "HSTNEGSTS,Host Negotiation Status" "Host negotiation failure,Host negotiation success"
|
|
newline
|
|
rbitfld.long 0x08 1. "SESREQSTS,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "OEVTERROR,OTG Event Error: There are no errors currently defined" "No action Write,Clear the event"
|
|
line.long 0x0C "USB_OEVTEN,"
|
|
bitfld.long 0x0C 27. "OTGXHCIRUNSTPSETEVNTEN,OTG Host Run Stop Set Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 26. "OTGDEVRUNSTPSETEVNTEN,OTG Device Run Stop Set Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. "OTGHIBENTRYEVNTEN,OTG Hibernation Entry Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 24. "OTGCONIDSTSCHNGEVNTEN,Connector ID Status Change Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 23. "HRRCONFNOTIFEVNTEN,Host Role Request Confirm Notifier Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. "HRRINITNOTIFEVNTEN,Host Role Request Initiate Notifier Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 21. "OTGADEVIDLEEVNTEN,A-device A-IDLE Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 20. "OTGADEVBHOSTENDEVNTEN,A-device B-Host End Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. "OTGADEVHOSTEVNTEN,A-device host event" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 18. "OTGADEVHNPCHNGEVNTEN,A-device HNP Change EventEn" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "OTGADEVSRPDETEVNTEN,SRP Detect Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "OTGADEVSESSENDDETEVNTEN,Session End Detected Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11. "OTGBDEVBHOSTENDEVNTEN,B-device B-Host End Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "OTGBDEVHNPCHNGEVNTEN,B-device HNP Change Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "OTGBDEVSESSVLDDETEVNTEN,Session Valid Detected Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "OTGBDEVVBUSCHNGEVNTEN,Vbus Change Event Enable" "0,1"
|
|
line.long 0x10 "USB_OSTS,"
|
|
bitfld.long 0x10 13. "DEVRUNSTP,DevRunStp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "XHCIRUNSTP,xHciRunStp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8.--11. "OTGSTATE,This is a debug field indicating the current state of the OTG state machine" "A_IDLE,A_WAIT_VRISE0x2,?..."
|
|
newline
|
|
bitfld.long 0x10 4. "PERIPHERALSTATE,OTG state Indicates whether the core is acting as a peripheral or host" "Host,Peripheral"
|
|
newline
|
|
bitfld.long 0x10 3. "XHCIPRTPOWER,xHCI Host Port Power" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "BSESVLD,VBUS B-Session Valid status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "ASESVLD,VBUS A-Session Valid status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "CONIDSTS,Connector ID Status" "0,1"
|
|
group.long 0xCC20++0x13
|
|
line.long 0x00 "USB_ADPCFG,"
|
|
bitfld.long 0x00 30.--31. "PRBPER,Probe Period" "12.5ms,18.75ms,25 ms0x3,?..."
|
|
newline
|
|
bitfld.long 0x00 28.--29. "PRBDELTA,Probe Delta" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PRBDSCHG,Probe Discharge" "0,1,2,3"
|
|
line.long 0x04 "USB_ADPCTL,"
|
|
bitfld.long 0x04 28. "ENAPRB,Enable Probe" "0,1"
|
|
newline
|
|
bitfld.long 0x04 27. "ENASNS,Enable Sense" "0,1"
|
|
newline
|
|
bitfld.long 0x04 26. "ADPEN,ADP Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25. "ADPRES,ADP Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x04 24. "WB,Write Busy" "Write Completed,Write in Progress"
|
|
line.long 0x08 "USB_ADPEVT,"
|
|
bitfld.long 0x08 28. "ADPPRBEVNT,ADP Probe Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 27. "ADPSNSEVNT,ADP Sense Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 26. "ADPTMOUTEVNT,ADP Timeout Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. "ADPRSTCMPLTEVNT,This event when set indicates that the ADP Reset command is successful" "0,1"
|
|
newline
|
|
abitfld.long 0x08 0.--15. "RTIM,RAMP TIME" "0x0000=> 6250 usPrbDelta =,0x0001=> 3125 usPrbDelta =,0x0002=> 1562.5 usPrbDelta =,0x0003=> 781.25 us"
|
|
line.long 0x0C "USB_ADPEVTEN,"
|
|
bitfld.long 0x0C 28. "ADPPRBEVNTEN,ADP Probe Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 27. "ADPSNSEVNTEN,ADP Sense Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 26. "ADPTMOUTEVNTEN,ADP Timeout Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. "ADPRSTCMPLTEVNTEN,ADP Reset complete Event Enable" "0,1"
|
|
line.long 0x10 "USB_BCFG,"
|
|
bitfld.long 0x10 1. "IDDIG_SEL,IDDIG Select" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "CHIRP_EN,Chirp Enable" "0,1"
|
|
group.long 0xCC38++0x07
|
|
line.long 0x00 "USB_BCEVT,"
|
|
bitfld.long 0x00 24. "MV_CHNGEVNT,Multi-Valued input changed Event" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MULTVALIDBC,Multi Valued ID pin: Indicates the Battery Charger ACA inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "USB_BCEVTEN,"
|
|
bitfld.long 0x04 24. "MV_CHNGEVNTENA,Multi-Valued input changed Event Enable" "0,1"
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0xC380)++0x03
|
|
line.long 0x00 "USB_GRXFIFOSIZ$1,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RXFSTADDR_N,Receive FIFO RAM Start Address in 64-bit RAM words"
|
|
hexmask.long.word 0x00 0.--15. 1. "RXFDEP_N,Receive FIFO Depth in 64-bit RAM words"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xC300)++0x03
|
|
line.long 0x00 "USB_GTXFIFOSIZ$1,"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXFSTADDR_N,Transmit FIFO RAM Start Address in 64-bit RAM words"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXFDEP_N,Transmit FIFO Depth in 64-bit RAM words"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xC178)++0x03
|
|
line.long 0x00 "USB_GDBGEPINFO$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
repeat.end
|
|
tree "USB_WRAPPER"
|
|
base ad:0x2640000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB_REVISION,"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_IRQ_EOI_MAIN,"
|
|
bitfld.long 0x00 15. "EOI15," "0,1"
|
|
bitfld.long 0x00 14. "EOI14," "0,1"
|
|
bitfld.long 0x00 13. "EOI13," "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "EOI12," "0,1"
|
|
bitfld.long 0x00 11. "EOI11," "0,1"
|
|
bitfld.long 0x00 10. "EOI10," "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "EOI9," "0,1"
|
|
bitfld.long 0x00 8. "EOI8," "0,1"
|
|
bitfld.long 0x00 7. "EOI7," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "EOI6," "0,1"
|
|
bitfld.long 0x00 5. "EOI5," "0,1"
|
|
bitfld.long 0x00 4. "EOI4," "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EOI3," "0,1"
|
|
bitfld.long 0x00 2. "EOI2," "0,1"
|
|
bitfld.long 0x00 1. "EOI1," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EOI0," "0,1"
|
|
group.long 0x42C++0x13
|
|
line.long 0x00 "USB_IRQ_EOI_MISC,"
|
|
bitfld.long 0x00 0. "EOI_MISC," "0,1"
|
|
line.long 0x04 "USB_IRQ_STATUS_RAW_MISC,"
|
|
bitfld.long 0x04 19. "TRACE_CMPL,Set when Trace RAM has stored 1024 samples" "0,1"
|
|
bitfld.long 0x04 18. "AXI_ERROR,Set when there is an AXI transaction error" "0,1"
|
|
bitfld.long 0x04 17. "DMADISABLECLR,Set" "0,1"
|
|
line.long 0x08 "USB_IRQ_STATUS_MISC,"
|
|
bitfld.long 0x08 19. "TRACE_CMPL,Set when Trace RAM has stored 1024 samples" "0,1"
|
|
bitfld.long 0x08 18. "AXI_ERROR,Set when there is an AXI transaction error" "0,1"
|
|
bitfld.long 0x08 17. "DMADISABLECLR,Set" "0,1"
|
|
line.long 0x0C "USB_IRQ_ENABLE_SET_MISC,"
|
|
bitfld.long 0x0C 19. "TRACE_CMPL,Set when Trace RAM has stored 1024 samples" "0,1"
|
|
bitfld.long 0x0C 18. "AXI_ERROR,Set when there is an AXI transaction error" "0,1"
|
|
bitfld.long 0x0C 17. "DMADISABLECLR,DMA-disable self-clear IRQ event enable" "0,1"
|
|
line.long 0x10 "USB_IRQ_ENABLE_CLR_MISC,"
|
|
bitfld.long 0x10 19. "TRACE_CMPL,Set when Trace RAM has stored 1024 samples" "0,1"
|
|
bitfld.long 0x10 18. "AXI_ERROR,Set when there is an AXI transaction error" "0,1"
|
|
bitfld.long 0x10 17. "DMADISABLECLR,DMA-disable self-clear IRQ event enable" "0,1"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "USB_IRQ_EOI_OABS,"
|
|
bitfld.long 0x00 0. "EOI_OABS,Write 0x1 to flag End Of Interrupt 'OABS'" "0,1"
|
|
group.long 0x454++0x0B
|
|
line.long 0x00 "USB_IRQ_STATUS_OABS,"
|
|
bitfld.long 0x00 27. "OTGXHCIRUNSTPSETEVNT,Interrupt status for OTG Host Run Stop Set Event" "0,1"
|
|
bitfld.long 0x00 26. "OTGDEVRUNSTPSETEVNT,Interrupt status for OTG Device Run Stop Set Event" "0,1"
|
|
bitfld.long 0x00 25. "OTGHIBENTRYEVNT,Interrupt status for OTG Hibernation Entry Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "OTGCONIDSTSCHNGEVNT,Interrupt status for Connector ID Status Change Event" "0,1"
|
|
bitfld.long 0x00 23. "HRRCONFNOTIFEVNT,Interrupt status for Host Role Request Confirm Notifier Event" "0,1"
|
|
bitfld.long 0x00 22. "HRRINITNOTIFEVNT,Interrupt status for Host Role Request Initiate Notifier Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "OTGADEVIDLEEVNT,Interrupt status for A-device A-IDLE Event" "0,1"
|
|
bitfld.long 0x00 20. "OTGADEVBHOSTENDEVNT,Interrupt status for A-device B-Host End Event" "0,1"
|
|
bitfld.long 0x00 19. "OTGADEVHOSTEVNT,Interrupt status for A-device host event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "OTGADEVHNPCHNGEVNT,Interrupt status for A-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x00 17. "OTGADEVSRPDETEVNT,Interrupt status for SRP Detect Event" "0,1"
|
|
bitfld.long 0x00 16. "OTGADEVSESSENDDETEVNT,Interrupt status for Session End Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "OTGBDEVBHOSTENDEVNT,Interrupt status for B-Device B-Host End Event" "0,1"
|
|
bitfld.long 0x00 10. "OTGBDEVHNPCHNGEVNT,Interrupt status for B-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x00 9. "OTGBDEVSESSVLDDETEVNT,Interrupt status for Session Valid Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "OTGBDEVVBUSCHNGEVNT,Interrupt status for VBUS Change Event" "0,1"
|
|
bitfld.long 0x00 7. "ADPPRBEVNT,Interrupt status for ADP Probe Event" "0,1"
|
|
bitfld.long 0x00 6. "ADPSNSEVNT,Interrupt status for ADP Sense Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADPTMOUTEVNT,Interrupt status for ADP Timeout Event" "0,1"
|
|
bitfld.long 0x00 4. "ADPRSTCMPLTEVNT,Interrupt status for ADP Reset complete Event" "0,1"
|
|
bitfld.long 0x00 2. "MV_CHNGEVNT,Interrupt status for BC Multi-Valued input change event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SER_EVENT,Interrupt status for RAM SER event" "0,1"
|
|
line.long 0x04 "USB_IRQ_ENABLE_SET_OABS,"
|
|
bitfld.long 0x04 27. "OTGXHCIRUNSTPSETEVNT,Interrupt enable for OTG Host Run Stop Set Event" "0,1"
|
|
bitfld.long 0x04 26. "OTGDEVRUNSTPSETEVNT,Interrupt enable for OTG Device Run Stop Set Event" "0,1"
|
|
bitfld.long 0x04 25. "OTGHIBENTRYEVNT,Interrupt enable for OTG Hibernation Entry Event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 24. "OTGCONIDSTSCHNGEVNT,Interrupt enable for Connector ID Status Change Event" "0,1"
|
|
bitfld.long 0x04 23. "HRRCONFNOTIFEVNT,Interrupt enable for Host Role Request Confirm Notifier Event" "0,1"
|
|
bitfld.long 0x04 22. "HRRINITNOTIFEVNT,Interrupt enable for Host Role Request Initiate Notifier Event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 21. "OTGADEVIDLEEVNT,Interrupt enable for A-device A-IDLE Event" "0,1"
|
|
bitfld.long 0x04 20. "OTGADEVBHOSTENDEVNT,Interrupt enable for A-device B-Host End Event" "0,1"
|
|
bitfld.long 0x04 19. "OTGADEVHOSTEVNT,Interrupt enable for A-device host event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 18. "OTGADEVHNPCHNGEVNT,Interrupt enable for A-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x04 17. "OTGADEVSRPDETEVNT,Interrupt enable for SRP Detect Event" "0,1"
|
|
bitfld.long 0x04 16. "OTGADEVSESSENDDETEVNT,Interrupt enable for Session End Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 11. "OTGBDEVBHOSTENDEVNT,Interrupt enable for B-Device B-Host End Event" "0,1"
|
|
bitfld.long 0x04 10. "OTGBDEVHNPCHNGEVNT,Interrupt enable for B-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x04 9. "OTGBDEVSESSVLDDETEVNT,Interrupt enable for Session Valid Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8. "OTGBDEVVBUSCHNGEVNT,Interrupt enable for VBUS Change Event" "0,1"
|
|
bitfld.long 0x04 7. "ADPPRBEVNT,Interrupt enable for ADP Probe Event" "0,1"
|
|
bitfld.long 0x04 6. "ADPSNSEVNT,Interrupt enable for ADP Sense Event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "ADPTMOUTEVNT,Interrupt enable for ADP Timeout Event" "0,1"
|
|
bitfld.long 0x04 4. "ADPRSTCMPLTEVNT,Interrupt enable for ADP Reset complete Event" "0,1"
|
|
bitfld.long 0x04 2. "MV_CHNGEVNT,Interrupt enable for BC Multi-Valued input change event" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "SER_EVENT,Interrupt enable for RAM SER event" "0,1"
|
|
line.long 0x08 "USB_IRQ_ENABLE_CLR_OABS,"
|
|
bitfld.long 0x08 27. "OTGXHCIRUNSTPSETEVNT,Interrupt disable for OTG Host Run Stop Set Event" "0,1"
|
|
bitfld.long 0x08 26. "OTGDEVRUNSTPSETEVNT,Interrupt disable for OTG Device Run Stop Set Event" "0,1"
|
|
bitfld.long 0x08 25. "OTGHIBENTRYEVNT,Interrupt disable for OTG Hibernation Entry Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 24. "OTGCONIDSTSCHNGEVNT,Interrupt disable for Connector ID Status Change Event" "0,1"
|
|
bitfld.long 0x08 23. "HRRCONFNOTIFEVNT,Interrupt disable for Host Role Request Confirm Notifier Event" "0,1"
|
|
bitfld.long 0x08 22. "HRRINITNOTIFEVNT,Interrupt disable for Host Role Request Initiate Notifier Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 21. "OTGADEVIDLEEVNT,Interrupt disable for A-device A-IDLE Event" "0,1"
|
|
bitfld.long 0x08 20. "OTGADEVBHOSTENDEVNT,Interrupt disable for A-device B-Host End Event" "0,1"
|
|
bitfld.long 0x08 19. "OTGADEVHOSTEVNT,Interrupt disable for A-device host event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 18. "OTGADEVHNPCHNGEVNT,Interrupt disable for A-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x08 17. "OTGADEVSRPDETEVNT,Interrupt disable for SRP Detect Event" "0,1"
|
|
bitfld.long 0x08 16. "OTGADEVSESSENDDETEVNT,Interrupt disable for Session End Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 11. "OTGBDEVBHOSTENDEVNT,Interrupt disable for B-Device B-Host End Event" "0,1"
|
|
bitfld.long 0x08 10. "OTGBDEVHNPCHNGEVNT,Interrupt disable for B-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x08 9. "OTGBDEVSESSVLDDETEVNT,Interrupt disable for Session Valid Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "OTGBDEVVBUSCHNGEVNT,Interrupt disable for VBUS Change Event" "0,1"
|
|
bitfld.long 0x08 7. "ADPPRBEVNT,Interrupt disable for ADP Probe Event" "0,1"
|
|
bitfld.long 0x08 6. "ADPSNSEVNT,Interrupt disable for ADP Sense Event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "ADPTMOUTEVNT,Interrupt disable for ADP Timeout Event" "0,1"
|
|
bitfld.long 0x08 4. "ADPRSTCMPLTEVNT,Interrupt disable for ADP Reset complete Event" "0,1"
|
|
bitfld.long 0x08 2. "MV_CHNGEVNT,Interrupt disable for BC Multi-Valued input change event" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "SER_EVENT,Interrupt disable for RAM SER event" "0,1"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "USB_IRQ_STATUS_RAW_OABS,"
|
|
bitfld.long 0x00 27. "OTGXHCIRUNSTPSETEVNT,Interrupt status for OTG Host Run Stop Set Event" "0,1"
|
|
bitfld.long 0x00 26. "OTGDEVRUNSTPSETEVNT,Interrupt status for OTG Device Run Stop Set Event" "0,1"
|
|
bitfld.long 0x00 25. "OTGHIBENTRYEVNT,Interrupt status for OTG Hibernation Entry Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "OTGCONIDSTSCHNGEVNT,Interrupt status for Connector ID Status Change Event" "0,1"
|
|
bitfld.long 0x00 23. "HRRCONFNOTIFEVNT,Interrupt status for Host Role Request Confirm Notifier Event" "0,1"
|
|
bitfld.long 0x00 22. "HRRINITNOTIFEVNT,Interrupt status for Host Role Request Initiate Notifier Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "OTGADEVIDLEEVNT,Interrupt status for A-device A-IDLE Event" "0,1"
|
|
bitfld.long 0x00 20. "OTGADEVBHOSTENDEVNT,Interrupt status for A-device B-Host End Event" "0,1"
|
|
bitfld.long 0x00 19. "OTGADEVHOSTEVNT,Interrupt status for A-device host event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "OTGADEVHNPCHNGEVNT,Interrupt status for A-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x00 17. "OTGADEVSRPDETEVNT,Interrupt status for SRP Detect Event" "0,1"
|
|
bitfld.long 0x00 16. "OTGADEVSESSENDDETEVNT,Interrupt status for Session End Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "OTGBDEVBHOSTENDEVNT,Interrupt status for B-Device B-Host End Event" "0,1"
|
|
bitfld.long 0x00 10. "OTGBDEVHNPCHNGEVNT,Interrupt status for B-Dev HNP Change Event" "0,1"
|
|
bitfld.long 0x00 9. "OTGBDEVSESSVLDDETEVNT,Interrupt status for Session Valid Detected Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "OTGBDEVVBUSCHNGEVNT,Interrupt status for VBUS Change Event" "0,1"
|
|
bitfld.long 0x00 7. "ADPPRBEVNT,Interrupt status for ADP Probe Event" "0,1"
|
|
bitfld.long 0x00 6. "ADPSNSEVNT,Interrupt status for ADP Sense Event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADPTMOUTEVNT,Interrupt status for ADP Timeout Event" "0,1"
|
|
bitfld.long 0x00 4. "ADPRSTCMPLTEVNT,Interrupt status for ADP Reset complete Event" "0,1"
|
|
bitfld.long 0x00 2. "MV_CHNGEVNT,Interrupt status for BC Multi-Valued input change event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SER_EVENT,Interrupt status for RAM SER event" "0,1"
|
|
rgroup.long 0x500++0x0F
|
|
line.long 0x00 "USB_UTMI_OTG_CTRL,"
|
|
bitfld.long 0x00 5. "DRVVBUS,Drive 5V on VBUS" "0,1"
|
|
bitfld.long 0x00 4. "CHRGVBUS,Charge VBUS through a resistor for VBUS-pulsing SRP" "0,1"
|
|
bitfld.long 0x00 3. "DISCHRGVBUS,Discharge VBUS through a resistor until the session-end VBUS state is reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IDPULLUP,Pull-up to the (OTG) ID line to allow its sampling" "0,1"
|
|
line.long 0x04 "USB_UTMI_OTG_STATUS,"
|
|
bitfld.long 0x04 31. "SW_MODE,Controls the source of UTMI / PIPE status for VBUS and OTG ID (vbusvalid sessvalid sessend iddig powerpresent)" "0,1"
|
|
bitfld.long 0x04 10. "PORT_OVERCURRENT,Over-current status for non-OTG host only" "0,1"
|
|
bitfld.long 0x04 9. "POWERPRESENT,SW-programmed value of PIPE3.0 PowerPresent (VBUS status) seen by the core alternative to HW input" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8. "TXBITSTUFFENABLE,SW-programmed UTMI output txbitstuffenable[h]" "0,1"
|
|
bitfld.long 0x04 4. "IDDIG,SW-programmed value of UTMI+ IdDig (OTG ID status) seen by the core alternative to HW input" "0,1"
|
|
bitfld.long 0x04 3. "SESSEND,SW-programmed value of UTMI+ SessEnd (VBUS status) seen by the core alternative to HW input" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "SESSVALID,SW-programmed value of UTMI+ SessValid (VBUS status) seen by the core alternative to HW inputs AValid and BValid" "0,1"
|
|
bitfld.long 0x04 1. "VBUSVALID,SW-programmed value of UTMI+ VbusValid (VBUS status) seen by the core alternative to HW input" "0,1"
|
|
line.long 0x08 "USB_TXFIFO_DEPTH,"
|
|
hexmask.long.word 0x08 0.--15. 1. "TXFIFOSIZE,Number of addressable locations in the physical implementation of the TxFIFO"
|
|
line.long 0x0C "USB_RXFIFO_DEPTH,"
|
|
hexmask.long.word 0x0C 0.--15. 1. "RXFIFOSIZE,Number of addressable locations in the physical implementation of the RxFIFO"
|
|
group.long 0x600++0x17
|
|
line.long 0x00 "USB_SER_CONTROL,"
|
|
bitfld.long 0x00 1.--2. "BEC_EN,Block error correction and detection enable" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PAR_EN,Parity check detection enable" "0,1"
|
|
line.long 0x04 "USB_SER_STATUS,"
|
|
hexmask.long.word 0x04 16.--27. 1. "RAM_ERR,Indicates which RAM had the error event"
|
|
bitfld.long 0x04 14. "ADDR_VALID,Indicates whether the address of the RAM with the error event can be determined" "0,1"
|
|
rbitfld.long 0x04 8.--10. "BYTE_POS,Indicates which p byte of the RAM that had the parity detection error event for designs with p>1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 2.--3. "TYPE_ERR,Indicates the type of error" "0,1,2,3"
|
|
bitfld.long 0x04 1. "BEC_ERR,Block error correction and detection error status" "0,1"
|
|
rbitfld.long 0x04 0. "PAR_ERR,Parity check detection error" "0,1"
|
|
line.long 0x08 "USB_SER_ADDRESS,"
|
|
line.long 0x0C "USB_PHY2CONFIG,"
|
|
bitfld.long 0x0C 4. "ULPI_UTMI_MODE,Set mode equal to" "0,1"
|
|
bitfld.long 0x0C 1. "IDPULLUP_VAL,Value of IDPULLUP if bit [0] IDPULLUP_EN = 0x1" "0,1"
|
|
bitfld.long 0x0C 0. "IDPULLUP_EN,Selection of IDPULLUP source" "0,1"
|
|
line.long 0x10 "USB_PHY3CONFIG,"
|
|
line.long 0x14 "USBCONFIG,"
|
|
bitfld.long 0x14 0.--1. "ENDIANMODE,Endian mode when the USBSS is in big endian" "0,1,2,3"
|
|
group.long 0x700++0x1B
|
|
line.long 0x00 "USB_MMRAM_OFFSET,"
|
|
bitfld.long 0x00 15.--19. "OFFSET_MSB,Byte offset MSBits = page offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--14. 1. "OFFSET_LSB,Byte offset LSBits always 0"
|
|
line.long 0x04 "USB_FLADJ,"
|
|
bitfld.long 0x04 31. "CORE_SW_RESET,Active-high core software reset" "0,1"
|
|
bitfld.long 0x04 29. "XHCI_REVISION,Switches to the legacy xHCI 0.96 host SW API mode" "0,1"
|
|
bitfld.long 0x04 28. "HOST_U3_PORT_DISABLE,USB3 port disable overriding xHCI driver" "0,1"
|
|
newline
|
|
bitfld.long 0x04 27. "HOST_U2_PORT_DISABLE,USB2 port disable overriding xHCI driver" "0,1"
|
|
bitfld.long 0x04 21.--26. "FLADJ_30MHZ,HS Jitter Adjustment in 30 MHz periods" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "USB_DEBUG_CFG,"
|
|
bitfld.long 0x08 9. "TRIG_DATA_AVAL,Indicates if the trace RAM has data" "0,1"
|
|
bitfld.long 0x08 8. "EXT_TRIG_EN,External trigger enable" "0,1"
|
|
bitfld.long 0x08 3.--5. "SEL_THR,Selection of debug threshold local signals" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "SEL_DBG,Selection of observed local signals" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "USB_DEBUG_DATA,"
|
|
bitfld.long 0x0C 31. "DEBUG31,SEL=1: utmi_sessend" "0,1"
|
|
bitfld.long 0x0C 30. "DEBUG30,SEL=1: utmi_vbusvalid" "0,1"
|
|
bitfld.long 0x0C 29. "DEBUG29,SEL=1: utmi_bvalid" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. "DEBUG28,SEL=1: utmi_avalid" "0,1"
|
|
bitfld.long 0x0C 27. "DEBUG27,SEL=1: utmi_iddig" "0,1"
|
|
bitfld.long 0x0C 26. "DEBUG26,SEL=1: utmi_hostdisconnect" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. "DEBUG25,SEL=1: utmi_txbitstuffenableh" "0,1"
|
|
bitfld.long 0x0C 24. "DEBUG24,SEL=1: utmi_txbitstuffenable" "0,1"
|
|
bitfld.long 0x0C 23. "DEBUG23,SEL=1: utmi_dischrgvbus" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. "DEBUG22,SEL=1: utmi_chrgvbus" "0,1"
|
|
bitfld.long 0x0C 21. "DEBUG21,SEL=1: utmi_drvvbus" "0,1"
|
|
bitfld.long 0x0C 20. "DEBUG20,SEL=1: utmi_dmpulldown" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. "DEBUG19,SEL=1: utmi_dppulldown" "0,1"
|
|
bitfld.long 0x0C 18. "DEBUG18,SEL=1: utmi_idpullup" "0,1"
|
|
bitfld.long 0x0C 17. "DEBUG17,SEL=1: utmi_linestate[1]" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "DEBUG16,SEL=1: utmi_linestate[0]" "0,1"
|
|
bitfld.long 0x0C 15. "DEBUG15,SEL=1: utmi_opmode[1]" "0,1"
|
|
bitfld.long 0x0C 14. "DEBUG14,SEL=1: utmi_opmode[0]" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 13. "DEBUG13,SEL=1: utmi_termselect" "0,1"
|
|
bitfld.long 0x0C 12. "DEBUG12,SEL=1: utmi_xcvrselect[1]" "0,1"
|
|
bitfld.long 0x0C 11. "DEBUG11,SEL=1: utmi_xcvrselect[0]" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "DEBUG10,SEL=1: utmi_suspendm" "0,1"
|
|
bitfld.long 0x0C 9. "DEBUG9,SEL=1: utmi_sleepm" "0,1"
|
|
bitfld.long 0x0C 8. "DEBUG8,SEL=1: utmi_txdatah[6]" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "DEBUG7,SEL=1: utmi_txdatah[5]" "0,1"
|
|
bitfld.long 0x0C 6. "DEBUG6,SEL=1: utmi_txdatah[4]" "0,1"
|
|
bitfld.long 0x0C 5. "DEBUG5,SEL=1: utmi_txdatah[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "DEBUG4,SEL=1: utmi_txdatah[2]" "0,1"
|
|
bitfld.long 0x0C 3. "DEBUG3,SEL=1: utmi_txdatah[1]" "0,1"
|
|
bitfld.long 0x0C 2. "DEBUG2,SEL=1: utmi_txdatah[0]" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "DEBUG1,SEL=1: utmi_reset" "0,1"
|
|
bitfld.long 0x0C 0. "DEBUG0,SEL=1: utmi_clk" "0,1"
|
|
line.long 0x10 "USB_DEV_EBC_EN,"
|
|
bitfld.long 0x10 31. "OUTEP15,ENABLE EBC HW throttling (USB receive) for OUT EP 15" "0,1"
|
|
bitfld.long 0x10 30. "OUTEP14,ENABLE EBC HW throttling (USB receive) for OUT EP 14" "0,1"
|
|
bitfld.long 0x10 15. "INEP15,ENABLE EBC HW throttling (USB transmit) for IN EP 15" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "INEP14,ENABLE EBC HW throttling (USB transmit) for IN EP 14" "0,1"
|
|
line.long 0x14 "USB_HOST_HUB_CTRL,"
|
|
bitfld.long 0x14 8.--11. "BUS_FILTER_BYPASS,Bus Filter Bypass bit mapping:Bus Filter Bypass bit setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 6.--7. "HUB_PORT_PERM_ATTACH,Indicates if the device attached to a downstream port is permanently attached or not" "0,1,2,3"
|
|
bitfld.long 0x14 5. "XHC_BME,This signal is used to disable the bus mastering capability of the xHC" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "HOST_MSI_ENABLE,This enables the pulse type interrupt signal (one bus clock cycle) on interrupt port instead of level-sensitive interrupt" "0,1"
|
|
bitfld.long 0x14 2. "HOST_PORT_POWER_CONTROL_PRESENT,This port defines the bit [3] of Capability Parameters (" "0,1"
|
|
bitfld.long 0x14 0.--1. "HUB_PORT_OVERCURRENT,This is the per port Overcurrent indication of the root-hub ports" "0,1,2,3"
|
|
line.long 0x18 "USB_DEBUG_THR,"
|
|
bitfld.long 0x18 30. "EN3,Enable for trigger 3" "0,1"
|
|
bitfld.long 0x18 29. "VAL3,Binary value for trigger 3" "0,1"
|
|
bitfld.long 0x18 24.--28. "INDEX3,Index for trigger 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 22. "EN2,Enable for trigger 2" "0,1"
|
|
bitfld.long 0x18 21. "VAL2,Binary value for trigger 2" "0,1"
|
|
bitfld.long 0x18 16.--20. "INDEX2,Index for trigger 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 14. "EN1,Enable for trigger 1" "0,1"
|
|
bitfld.long 0x18 13. "VAL1,Binary value for trigger 1" "0,1"
|
|
bitfld.long 0x18 8.--12. "INDEX1,Index for trigger 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 6. "EN0,Enable for trigger 0" "0,1"
|
|
bitfld.long 0x18 5. "VAL0,Binary value for trigger 0" "0,1"
|
|
bitfld.long 0x18 0.--4. "INDEX0,Index for trigger 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x23DC0010++0x03
|
|
line.long 0x00 "USB_SYSCONFIG,"
|
|
bitfld.long 0x00 17. "WRAPRESET,Software reset for the USB_WRAPPER register set" "0,1"
|
|
bitfld.long 0x00 16. "DMADISABLE,Disable/Enable control of the DMA master (initiator) to block read/write accesses" "0,1"
|
|
bitfld.long 0x00 14. "REFCLKEN_N,Active low clock enable for ref_clk" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "SUSPCLKEN_N,Active low clock enable for suspend_clk" "0,1"
|
|
bitfld.long 0x00 12. "PIPECLKEN_N,Active low clock enable for pipe_clk" "0,1"
|
|
bitfld.long 0x00 11. "ULPICLKEN_N,Active low clock enable for ulpi_clk" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "UTMICLKEN_N,Active low clock enable for utmi_clk" "0,1"
|
|
bitfld.long 0x00 9. "PHYMMRCLKEN_N,Active low clock enable for phymmr_clk" "0,1"
|
|
bitfld.long 0x00 8. "BUSCLKEN_N,Active low clock enable for bus_clk" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SOFT_RESET,Software reset for the USB2SS" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
AUTOINDENT.ON center tree
|
|
tree.open "ICSS_0"
|
|
tree "ECC_CFG"
|
|
base eapb:0x20AA7000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "ECC_VECTOR,"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status to indicate if read on the serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
rbitfld.long 0x00 11.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,Value written to select the corresponding ECC RAM for control or status"
|
|
line.long 0x04 "ECC_MISC_STATUS,"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
|
|
line.long 0x08 "ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "ECC_CONTROL,"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/ FORCE_DED will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Column/ Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where FORCE_SEC or FORCE_DED needs to be applied"
|
|
line.long 0x14 "ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when FORCE_DED is set"
|
|
line.long 0x18 "ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
rbitfld.long 0x18 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,1 indicates a successive single-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
rbitfld.long 0x18 3.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 2. "ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,1 indicates pending double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "ECC_SEC,1 indicates pending single-bit error status" "0,1"
|
|
line.long 0x1C "ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the bit position in the RAM data that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "ECC_EOI,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "ECC_INT_STATUS_0,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_STATUS_1,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_STATUS_2,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_STATUS_3,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_STATUS_4,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_STATUS_5,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_STATUS_6,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_STATUS_7,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_STATUS_8,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_STATUS_9,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_STATUS_10,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_STATUS_11,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_STATUS_12,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_STATUS_13,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x3C "ECC_INT_STATUS_14,"
|
|
hexmask.long 0x3C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x3C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "ECC_INT_ENABLE_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_ENABLE_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_ENABLE_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_ENABLE_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_ENABLE_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_ENABLE_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_ENABLE_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_ENABLE_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_ENABLE_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_ENABLE_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_ENABLE_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_ENABLE_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_ENABLE_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_ENABLE_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_ENABLE_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "ECC_INT_CLEAR_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_CLEAR_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_CLEAR_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_CLEAR_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_CLEAR_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_CLEAR_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_CLEAR_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_CLEAR_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_CLEAR_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_CLEAR_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_CLEAR_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_CLEAR_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_CLEAR_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_CLEAR_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_CLEAR_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CFG"
|
|
base eapb:0x20AA6000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PRUSS_REVID,"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PRUSS_GPCFG0,"
|
|
rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 26.--29. "PR1_PRU0_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 25. "PRU0_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x00 20.--24. "PRU0_GPO_DIV1,Divisor value (divide by PRU0_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15.--19. "PRU0_GPO_DIV0,Divisor value (divide by PRU0_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. "PRU0_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x00 13. "PRU0_GPI_SB,Start Bit event for 28-bit shift mode" "0,1"
|
|
bitfld.long 0x00 8.--12. "PRU0_GPI_DIV1,Divisor value (divide by PRU0_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "PRU0_GPI_DIV0,Divisor value (divide by PRU0_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 2. "PRU0_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x00 0.--1. "PRU0_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_GPCFG1,"
|
|
rbitfld.long 0x04 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x04 26.--29. "PR1_PRU1_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 25. "PRU1_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x04 20.--24. "PRU1_GPO_DIV1,Divisor value (divide by PRU1_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 15.--19. "PRU1_GPO_DIV0,Divisor value (divide by PRU1_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. "PRU1_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x04 13. "PRU1_GPI_SB,28-bit shift mode Start Bit event" "0,1"
|
|
bitfld.long 0x04 8.--12. "PRU1_GPI_DIV1,Divisor value (divide by PRU1_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 3.--7. "PRU1_GPI_DIV0,Divisor value (divide by PRU1_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 2. "PRU1_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x04 0.--1. "PRU1_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_CGR,"
|
|
bitfld.long 0x08 31. "ICSS_STOP_ACK,Acknowledgement that ICSS clock can be stopped" "0,1"
|
|
rbitfld.long 0x08 30. "ICSS_STOP_REQ,ICSS request to stop clock" "0,1"
|
|
hexmask.long.word 0x08 18.--29. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 17. "IEP_CLK_EN,IEP clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 16. "IEP_CLK_STOP_ACK,Acknowledgement that IEP clock can be stopped" "0,1"
|
|
bitfld.long 0x08 15. "IEP_CLK_STOP_REQ,IEP request to stop clock" "0,1"
|
|
bitfld.long 0x08 14. "ECAP_CLK_EN,ECAP clock enable" "0,1"
|
|
rbitfld.long 0x08 13. "ECAP_CLK_STOP_ACK,Acknowledgement that ECAP clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "ECAP_CLK_STOP_REQ,ECAP request to stop clock" "0,1"
|
|
bitfld.long 0x08 11. "UART_CLK_EN,UART clock enable" "0,1"
|
|
rbitfld.long 0x08 10. "UART_CLK_STOP_ACK,Acknowledgement that UART clock can be stopped" "0,1"
|
|
bitfld.long 0x08 9. "UART_CLK_STOP_REQ,UART request to stop clock" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "PRUSS_INTC_CLK_EN,PRUSS_INTC clock enable" "0,1"
|
|
rbitfld.long 0x08 7. "PRUSS_INTC_CLK_STOP_ACK,Acknowledgement that PRUSS_INTC clock can be stopped" "0,1"
|
|
bitfld.long 0x08 6. "PRUSS_INTC_CLK_STOP_REQ,PRUSS_INTC request to stop clock" "0,1"
|
|
bitfld.long 0x08 5. "PRU1_CLK_EN,PRU1 clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 4. "PRU1_CLK_STOP_ACK,Acknowledgement that PRU1 clock can be stopped" "0,1"
|
|
bitfld.long 0x08 3. "PRU1_CLK_STOP_REQ,PRU1 request to stop clock" "0,1"
|
|
bitfld.long 0x08 2. "PRU0_CLK_EN,PRU0 clock enable" "0,1"
|
|
rbitfld.long 0x08 1. "PRU0_CLK_STOP_ACK,Acknowledgement that PRU0 clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PRU0_CLK_STOP_REQ,PRU0 request to stop clock" "0,1"
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "PRUSS_PMAO,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 1. "PMAO_PRU1,PRU1 Master Port Address Offset Enable" "0,1"
|
|
bitfld.long 0x00 0. "PMAO_PRU0,PRU0 Master Port Address Offset Enable" "0,1"
|
|
line.long 0x04 "PRUSS_MII_RT,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "MII_RT_EVENT_EN,Enables the MII_RT Events to the PRU-ICSS_INTC" "0,1"
|
|
line.long 0x08 "PRUSS_IEPCLK,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0. "OCP_EN,IEP clock source" "0,1"
|
|
line.long 0x0C "PRUSS_SPP,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 1. "XFR_SHIFT_EN,Enables XIN XOUT shift functionality" "0,1"
|
|
bitfld.long 0x0C 0. "PRU1_PAD_HP_EN,Defines which PRU wins write cycle arbitration to a common scratch pad bank" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PRUSS_PIN_MX,"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 10.--11. "PWM3_REMAP_EN,Remaps the eHRPWM3_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
bitfld.long 0x00 8.--9. "PWM0_REMAP_EN,Remaps the eHRPWM0_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED,Reserved"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU0_CTRL"
|
|
base eapb:0x20AA2000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU1_CTRL"
|
|
base eapb:0x20AA4000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "INTC"
|
|
base eapb:0x20AA0000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_INTC_REVID,"
|
|
line.long 0x04 "PRUSS_INTC_CR,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Reserved" "0,1"
|
|
bitfld.long 0x04 2.--3. "NEST_MODE,The nesting mode" "0,1,2,3"
|
|
bitfld.long 0x04 1. "WAKEUP_MODE,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 0. "RESERVED,Reserved" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRUSS_INTC_GER,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "ENABLE_HINT_ANY,The current global enable value when" "0,1"
|
|
group.long 0x1C++0x13
|
|
line.long 0x00 "PRUSS_INTC_GNLR,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Always read as 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,The current global nesting level (highest channel that is nested)"
|
|
line.long 0x04 "PRUSS_INTC_SISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Writes set the status of the interrupt given in the index value"
|
|
line.long 0x08 "PRUSS_INTC_SICR,"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Writes clear the status of the interrupt given in the index value"
|
|
line.long 0x0C "PRUSS_INTC_EISR,"
|
|
hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Writes set the enable of the interrupt given in the index value"
|
|
line.long 0x10 "PRUSS_INTC_EICR,"
|
|
hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Writes clear the enable of the interrupt given in the index value"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "PRUSS_INTC_HIEISR,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Writes set the enable of the host interrupt given in the index value"
|
|
line.long 0x04 "PRUSS_INTC_HIDISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Writes clear the enable of the host interrupt given in the index value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PRUSS_INTC_GPIR,"
|
|
bitfld.long 0x00 31. "GLB_NONE,No Interrupt is pending" "0,1"
|
|
hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,The currently highest priority interrupt index pending across all the host interrupts"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "PRUSS_INTC_SRSR0,"
|
|
line.long 0x04 "PRUSS_INTC_SRSR1,"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "PRUSS_INTC_SECR0,"
|
|
line.long 0x04 "PRUSS_INTC_SECR1,"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "PRUSS_INTC_ESR0,"
|
|
line.long 0x04 "PRUSS_INTC_ERS1,"
|
|
group.long 0x380++0x07
|
|
line.long 0x00 "PRUSS_INTC_ECR0,"
|
|
line.long 0x04 "PRUSS_INTC_ECR1,"
|
|
group.long 0x400++0x3F
|
|
line.long 0x00 "PRUSS_INTC_CMR_0,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "CH_MAP_3,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH_MAP_2,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH_MAP_1,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH_MAP_0,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PRUSS_INTC_CMR_1,"
|
|
rbitfld.long 0x04 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "CH_MAP_7,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "CH_MAP_6,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. "CH_MAP_5,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "CH_MAP_4,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PRUSS_INTC_CMR_2,"
|
|
rbitfld.long 0x08 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. "CH_MAP_11,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x08 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. "CH_MAP_10,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x08 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. "CH_MAP_9,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x08 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. "CH_MAP_8,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "PRUSS_INTC_CMR_3,"
|
|
rbitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. "CH_MAP_15,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. "CH_MAP_14,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x0C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. "CH_MAP_13,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CH_MAP_12,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "PRUSS_INTC_CMR_4,"
|
|
rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. "CH_MAP_19,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x10 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. "CH_MAP_18,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x10 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. "CH_MAP_17,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x10 0.--3. "CH_MAP_16,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x14 "PRUSS_INTC_CMR_5,"
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|
rbitfld.long 0x14 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x14 24.--27. "CH_MAP_23,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x14 16.--19. "CH_MAP_22,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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rbitfld.long 0x14 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x14 8.--11. "CH_MAP_21,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. "CH_MAP_20,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x18 "PRUSS_INTC_CMR_6,"
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rbitfld.long 0x18 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 24.--27. "CH_MAP_27,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "CH_MAP_26,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x18 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 8.--11. "CH_MAP_25,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 0.--3. "CH_MAP_24,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x1C "PRUSS_INTC_CMR_7,"
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rbitfld.long 0x1C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 24.--27. "CH_MAP_31,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "CH_MAP_30,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x1C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 8.--11. "CH_MAP_29,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 0.--3. "CH_MAP_28,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x20 "PRUSS_INTC_CMR_8,"
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rbitfld.long 0x20 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 24.--27. "CH_MAP_35,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "CH_MAP_34,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x20 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--11. "CH_MAP_33,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "CH_MAP_32,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "PRUSS_INTC_CMR_9,"
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rbitfld.long 0x24 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. "CH_MAP_39,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "CH_MAP_38,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x24 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 8.--11. "CH_MAP_37,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. "CH_MAP_36,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x28 "PRUSS_INTC_CMR_10,"
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rbitfld.long 0x28 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 24.--27. "CH_MAP_43,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. "CH_MAP_42,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x28 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--11. "CH_MAP_41,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "CH_MAP_40,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x2C "PRUSS_INTC_CMR_11,"
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rbitfld.long 0x2C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 24.--27. "CH_MAP_47,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--19. "CH_MAP_46,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x2C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 8.--11. "CH_MAP_45,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "CH_MAP_44,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x30 "PRUSS_INTC_CMR_12,"
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rbitfld.long 0x30 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 24.--27. "CH_MAP_51,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--19. "CH_MAP_50,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x30 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 8.--11. "CH_MAP_49,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "CH_MAP_48,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x34 "PRUSS_INTC_CMR_13,"
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rbitfld.long 0x34 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 24.--27. "CH_MAP_55,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 16.--19. "CH_MAP_54,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x34 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 8.--11. "CH_MAP_53,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 0.--3. "CH_MAP_52,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x38 "PRUSS_INTC_CMR_14,"
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rbitfld.long 0x38 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 24.--27. "CH_MAP_59,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x38 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "CH_MAP_58,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x38 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 8.--11. "CH_MAP_57,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x38 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 0.--3. "CH_MAP_56,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x3C "PRUSS_INTC_CMR_15,"
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rbitfld.long 0x3C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 24.--27. "CH_MAP_63,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x3C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 16.--19. "CH_MAP_62,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x3C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 8.--11. "CH_MAP_61,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x3C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0.--3. "CH_MAP_60,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x808++0x03
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line.long 0x00 "PRUSS_INTC_HMR2,"
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 8.--11. "HINT_MAP_9,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HINT_MAP_8,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x900++0x27
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line.long 0x00 "PRUSS_INTC_HIPIR_0,"
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bitfld.long 0x00 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x00 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x04 "PRUSS_INTC_HIPIR_1,"
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bitfld.long 0x04 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x04 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x04 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x08 "PRUSS_INTC_HIPIR_2,"
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bitfld.long 0x08 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x08 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x08 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x0C "PRUSS_INTC_HIPIR_3,"
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bitfld.long 0x0C 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x0C 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x10 "PRUSS_INTC_HIPIR_4,"
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bitfld.long 0x10 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x10 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x10 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x14 "PRUSS_INTC_HIPIR_5,"
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bitfld.long 0x14 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x14 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x14 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x18 "PRUSS_INTC_HIPIR_6,"
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bitfld.long 0x18 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x18 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x18 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x1C "PRUSS_INTC_HIPIR_7,"
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bitfld.long 0x1C 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x1C 10.--30. 1. "RESERVED,Reserved"
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hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x20 "PRUSS_INTC_HIPIR_8,"
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bitfld.long 0x20 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x20 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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line.long 0x24 "PRUSS_INTC_HIPIR_9,"
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bitfld.long 0x24 31. "NONE_HINT,No pending interrupt" "0,1"
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hexmask.long.tbyte 0x24 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
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group.long 0xD00++0x07
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line.long 0x00 "PRUSS_INTC_SIPR0,"
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line.long 0x04 "PRUSS_INTC_SIPR1,"
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group.long 0xD80++0x07
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line.long 0x00 "PRUSS_INTC_SITR0,"
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line.long 0x04 "PRUSS_INTC_SITR1,"
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group.long 0x1100++0x27
|
|
line.long 0x00 "PRUSS_INTC_HINLR_0,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x04 "PRUSS_INTC_HINLR_1,"
|
|
bitfld.long 0x04 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x08 "PRUSS_INTC_HINLR_2,"
|
|
bitfld.long 0x08 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x08 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x0C "PRUSS_INTC_HINLR_3,"
|
|
bitfld.long 0x0C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x0C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x10 "PRUSS_INTC_HINLR_4,"
|
|
bitfld.long 0x10 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x10 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x14 "PRUSS_INTC_HINLR_5,"
|
|
bitfld.long 0x14 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x14 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x18 "PRUSS_INTC_HINLR_6,"
|
|
bitfld.long 0x18 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x18 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x1C "PRUSS_INTC_HINLR_7,"
|
|
bitfld.long 0x1C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x1C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x20 "PRUSS_INTC_HINLR_8,"
|
|
bitfld.long 0x20 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x20 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x24 "PRUSS_INTC_HINLR_9,"
|
|
bitfld.long 0x24 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x24 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "PRUSS_INTC_HIER,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "ENABLE_HINT,The enable of the host interrupts (one per bit)"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "PRUSS_INTC_HMR$1,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "HINT_MAP_3,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "HINT_MAP_2,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HINT_MAP_1,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HINT_MAP_0,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART"
|
|
base eapb:0x20AA8000
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "PRUSS_UART_RBR_THR_REGISTERS,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register"
|
|
line.long 0x04 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 3. "EDSSI,Enable Modem Status Interrupt" "0,1"
|
|
bitfld.long 0x04 2. "ELSI,Receiver line status interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "ETBEI,Transmitter holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x04 0. "ERBI,Receiver data available interrupt and character timeout indication interrupt enable" "0,1"
|
|
line.long 0x08 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 6.--7. "FIFOEN_RXFIFTL,Read: FIFOs enabled" "0,1,2,3"
|
|
rbitfld.long 0x08 4.--5. "RESERVED,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 1.--3. "INTID,Read: Interrupt type" "No effect,RXCLR,TXCLR,DMAMODE1,?..."
|
|
bitfld.long 0x08 0. "IPEND_FIFOEN,Read: Interrupt pending" "0,1"
|
|
line.long 0x0C "PRUSS_UART_LINE_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "DLAB,Divisor latch access bit" "0,1"
|
|
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "SP,Stick parity" "0,1"
|
|
bitfld.long 0x0C 4. "EPS,Even parity select" "0,1"
|
|
bitfld.long 0x0C 3. "PEN,Parity enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "STB,Number of STOP bits generated" "0,1"
|
|
bitfld.long 0x0C 0.--1. "WLS,Word length select" "0,1,2,3"
|
|
line.long 0x10 "PRUSS_UART_MODEM_CONTROL_REGISTER,"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 5. "AFE,Autoflow control enable" "0,1"
|
|
bitfld.long 0x10 4. "LOOP,Loop back mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "OUT2,OUT2 Control Bit" "0,1"
|
|
bitfld.long 0x10 2. "OUT1,OUT1 Control Bit" "0,1"
|
|
bitfld.long 0x10 1. "RTS,RTS control" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "RESERVED,Reserved" "0,1"
|
|
line.long 0x14 "PRUSS_UART_LINE_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO error" "0,1"
|
|
bitfld.long 0x14 6. "TEMT,Transmitter empty (TEMT) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "THRE,Transmitter holding register empty (THRE) indicator" "0,1"
|
|
bitfld.long 0x14 4. "BI,Break indicator" "0,1"
|
|
bitfld.long 0x14 3. "FE,Framing error (FE) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PE,Parity error (PE) indicator" "0,1"
|
|
bitfld.long 0x14 1. "OE,Overrun error (OE) indicator" "0,1"
|
|
bitfld.long 0x14 0. "DR,Data-ready (DR) indicator for the receiver" "0,1"
|
|
line.long 0x18 "PRUSS_UART_MODEM_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 7. "CD,Complement of the Carrier Detect input" "0,1"
|
|
bitfld.long 0x18 6. "RI,Complement of the Ring Indicator input" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "DSR,Complement of the Data Set Ready input" "0,1"
|
|
bitfld.long 0x18 4. "CTS,Complement of the Clear To Send input" "0,1"
|
|
bitfld.long 0x18 3. "DCD,Change in DCD indicator bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "TERI,Trailing edge of RI (TERI) indicator bit" "0,1"
|
|
bitfld.long 0x18 1. "DDSR,Change in DSR indicator bit" "0,1"
|
|
bitfld.long 0x18 0. "DCTS,Change in CTS indicator bit" "0,1"
|
|
line.long 0x1C "PRUSS_UART_SCRATCH_REGISTER,"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DATA,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation"
|
|
line.long 0x20 "PRUSS_UART_DIVISOR_REGISTER_LSB_,"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DLL,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x24 "PRUSS_UART_DIVISOR_REGISTER_MSB_,"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DLH,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x28 "PRUSS_UART_PERIPHERAL_ID_REGISTER,"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 15. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 14. "UTRST,UART transmitter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "URRST,UART receiver reset" "0,1"
|
|
hexmask.long.word 0x00 1.--12. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "FREE,Free-running enable mode bit" "0,1"
|
|
line.long 0x04 "PRUSS_UART_MODE_DEFINITION_REGISTER,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "OSM_SEL,Over-Sampling Mode Select" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP"
|
|
base eapb:0x20AB0000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_ECAP_TSCNT,"
|
|
line.long 0x04 "PRUSS_ECAP_CNTPHS,"
|
|
line.long 0x08 "PRUSS_ECAP_CAP1,"
|
|
line.long 0x0C "PRUSS_ECAP_CAP2,"
|
|
line.long 0x10 "PRUSS_ECAP_CAP3,"
|
|
line.long 0x14 "PRUSS_ECAP_CAP4,"
|
|
group.word 0x28++0x09
|
|
line.word 0x00 "PRUSS_ECAP_ECCTL1,"
|
|
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. "CAPLDEN,Enable Loading of" "0,1"
|
|
bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x02 "PRUSS_ECAP_ECCTL2,"
|
|
rbitfld.word 0x02 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 10. "APWMPOL," "0,1"
|
|
bitfld.word 0x02 9. "CAPAPWM," "0,1"
|
|
bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1"
|
|
bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3"
|
|
bitfld.word 0x02 5. "SYNCI_EN," "0,1"
|
|
bitfld.word 0x02 4. "TSCNTSTP," "0,1"
|
|
bitfld.word 0x02 3. "REARMRESET," "0,1"
|
|
bitfld.word 0x02 1.--2. "STOPVALUE," "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x02 0. "CONTONESHT," "0,1"
|
|
line.word 0x04 "PRUSS_ECAP_ECEINT,"
|
|
hexmask.word.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x04 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x04 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x04 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x04 4. "CEVT4," "0,1"
|
|
bitfld.word 0x04 3. "CEVT3," "0,1"
|
|
bitfld.word 0x04 2. "CEVT2," "0,1"
|
|
bitfld.word 0x04 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x04 0. "RESERVED,Reserved" "0,1"
|
|
line.word 0x06 "PRUSS_ECAP_ECFLG,"
|
|
hexmask.word.byte 0x06 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x06 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x06 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x06 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x06 4. "CEVT4," "0,1"
|
|
bitfld.word 0x06 3. "CEVT3," "0,1"
|
|
bitfld.word 0x06 2. "CEVT2," "0,1"
|
|
bitfld.word 0x06 1. "CEVT1," "0,1"
|
|
bitfld.word 0x06 0. "INT," "0,1"
|
|
line.word 0x08 "PRUSS_ECAP_ECCLR,"
|
|
hexmask.word.byte 0x08 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x08 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x08 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x08 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x08 4. "CEVT4," "0,1"
|
|
bitfld.word 0x08 3. "CEVT3," "0,1"
|
|
bitfld.word 0x08 2. "CEVT2," "0,1"
|
|
bitfld.word 0x08 1. "CEVT1," "0,1"
|
|
bitfld.word 0x08 0. "INT," "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PRUSS_ECAP_ECFRC,"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x00 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x00 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x00 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x00 4. "CEVT4," "0,1"
|
|
bitfld.word 0x00 3. "CEVT3," "0,1"
|
|
bitfld.word 0x00 2. "CEVT2," "0,1"
|
|
bitfld.word 0x00 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x00 0. "RESERVED,Reserved" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "PRUSS_ECAP_PID,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IEP"
|
|
base eapb:0x20AAE000
|
|
group.long 0x00++0x57
|
|
line.long 0x00 "PRUSS_IEP_GLOBAL_CFG,"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,Defines the increment value when compensation is active"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DEFAULT_INC,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "CNT_ENABLE,Counter enable" "Disables the counter,Enables the counter"
|
|
line.long 0x04 "PRUSS_IEP_STATUS,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CNT_OVF,Counter overflow status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_COMPENSATION,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "COMPEN_CNT,Compensation counter"
|
|
line.long 0x0C "PRUSS_IEP_SLOW_COMPENSATION,"
|
|
line.long 0x10 "PRUSS_IEP_LOW_COUNTER,"
|
|
line.long 0x14 "PRUSS_IEP_HIGH_COUNTER,"
|
|
line.long 0x18 "PRUSS_IEP_CAPTURE_CFG,"
|
|
hexmask.long.word 0x18 18.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x18 10.--17. "CAP_ASYNC_EN,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable" "0x00=Disable synchronization,0x01=Enable synchronization"
|
|
newline
|
|
bitfld.long 0x18 9. "CAP7F_1ST_EVENT_EN,Capture 1st Event Enable for CAP7F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 8. "CAP7R_1ST_EVENT_EN,Capture 1st Event Enable for CAP7R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 7. "CAP6F_1ST_EVENT_EN,Capture 1st Event Enable for CAP6F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 6. "CAP6R_1ST_EVENT_EN,Capture 1st Event Enable for CAP6R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 0.--5. "CAP_1ST_EVENT_EN,Capture 1st Event Enable for registers" "Continues mode,First Event mode,?..."
|
|
line.long 0x1C "PRUSS_IEP_CAPTURE_STATUS,"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x1C 16.--23. "CAP_RAW,Raw/Current status bit for each of the capture registers where CAP_RAW[n] maps to CAPR[n]" "0x00=Current state is low,0x01=Current state is high"
|
|
newline
|
|
bitfld.long 0x1C 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x1C 10. "CAP_VALID,Valid status for capture function" "No Hit for any capture event i.e,Hit for 1 or more captures events is pending i.e"
|
|
newline
|
|
bitfld.long 0x1C 9. "CAPF7_VALID,Valid status for CAPF7 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 8. "CAPR7_VALID,Valid status for CAPR7 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 7. "CAPF6_VALID,Valid status for CAPF6 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 6. "CAPR6_VALID,Valid status for CAPR6 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. "CAPR_VALID,Valid status bit for each compare register where CAPR_VALID[n] maps to CAPR[n] (rise)" "No Hit no capture event occurred,Hit capture event occurred,?..."
|
|
line.long 0x20 "PRUSS_IEP_CAPTURE_RISE00,"
|
|
line.long 0x24 "PRUSS_IEP_CAPTURE_RISE10,"
|
|
line.long 0x28 "PRUSS_IEP_CAPTURE_RISE01,"
|
|
line.long 0x2C "PRUSS_IEP_CAPTURE_RISE11,"
|
|
line.long 0x30 "PRUSS_IEP_CAPTURE_RISE02,"
|
|
line.long 0x34 "PRUSS_IEP_CAPTURE_RISE12,"
|
|
line.long 0x38 "PRUSS_IEP_CAPTURE_RISE03,"
|
|
line.long 0x3C "PRUSS_IEP_CAPTURE_RISE13,"
|
|
line.long 0x40 "PRUSS_IEP_CAPTURE_RISE04,"
|
|
line.long 0x44 "PRUSS_IEP_CAPTURE_RISE14,"
|
|
line.long 0x48 "PRUSS_IEP_CAPTURE_RISE05,"
|
|
line.long 0x4C "PRUSS_IEP_CAPTURE_RISE15,"
|
|
line.long 0x50 "PRUSS_IEP_CAPTURE_RISE06,"
|
|
line.long 0x54 "PRUSS_IEP_CAPTURE_RISE16,"
|
|
rgroup.long 0x60++0xAB
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_RISE07,"
|
|
line.long 0x04 "PRUSS_IEP_CAPTURE_RISE17,"
|
|
line.long 0x08 "PRUSS_IEP_CAPTURE_FALL07,"
|
|
line.long 0x0C "PRUSS_IEP_CAPTURE_FALL17,"
|
|
line.long 0x10 "PRUSS_IEP_COMPARE_CFG,"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x10 1.--16. 1. "CMP_EN,Enable bits for each of the compare registers"
|
|
newline
|
|
bitfld.long 0x10 0. "CMP0_RST_CNT_EN,Enable the reset of the counter" "0,1"
|
|
line.long 0x14 "PRUSS_IEP_COMPARE_STATUS,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP_HIT,Status bit for each of the compare registers"
|
|
line.long 0x18 "PRUSS_IEP_COMPARE00,"
|
|
line.long 0x1C "PRUSS_IEP_COMPARE10,"
|
|
line.long 0x20 "PRUSS_IEP_COMPARE01,"
|
|
line.long 0x24 "PRUSS_IEP_COMPARE11,"
|
|
line.long 0x28 "PRUSS_IEP_COMPARE02,"
|
|
line.long 0x2C "PRUSS_IEP_COMPARE12,"
|
|
line.long 0x30 "PRUSS_IEP_COMPARE03,"
|
|
line.long 0x34 "PRUSS_IEP_COMPARE13,"
|
|
line.long 0x38 "PRUSS_IEP_COMPARE04,"
|
|
line.long 0x3C "PRUSS_IEP_COMPARE14,"
|
|
line.long 0x40 "PRUSS_IEP_COMPARE05,"
|
|
line.long 0x44 "PRUSS_IEP_COMPARE15,"
|
|
line.long 0x48 "PRUSS_IEP_COMPARE06,"
|
|
line.long 0x4C "PRUSS_IEP_COMPARE16,"
|
|
line.long 0x50 "PRUSS_IEP_COMPARE07,"
|
|
line.long 0x54 "PRUSS_IEP_COMPARE17,"
|
|
line.long 0x58 "PRUSS_IEP_RXIPG0,"
|
|
hexmask.long.word 0x58 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x58 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x5C "PRUSS_IEP_RXIPG1,"
|
|
hexmask.long.word 0x5C 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x5C 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x60 "PRUSS_IEP_COMPARE08,"
|
|
line.long 0x64 "PRUSS_IEP_COMPARE18,"
|
|
line.long 0x68 "PRUSS_IEP_COMPARE09,"
|
|
line.long 0x6C "PRUSS_IEP_COMPARE19,"
|
|
line.long 0x70 "PRUSS_IEP_COMPARE010,"
|
|
line.long 0x74 "PRUSS_IEP_COMPARE110,"
|
|
line.long 0x78 "PRUSS_IEP_COMPARE011,"
|
|
line.long 0x7C "PRUSS_IEP_COMPARE111,"
|
|
line.long 0x80 "PRUSS_IEP_COMPARE012,"
|
|
line.long 0x84 "PRUSS_IEP_COMPARE112,"
|
|
line.long 0x88 "PRUSS_IEP_COMPARE013,"
|
|
line.long 0x8C "PRUSS_IEP_COMPARE113,"
|
|
line.long 0x90 "PRUSS_IEP_COMPARE014,"
|
|
line.long 0x94 "PRUSS_IEP_COMPARE114,"
|
|
line.long 0x98 "PRUSS_IEP_COMPARE015,"
|
|
line.long 0x9C "PRUSS_IEP_COMPARE115,"
|
|
line.long 0xA0 "PRUSS_IEP_LOW_COUNTER_RESET_VALUE,"
|
|
line.long 0xA4 "PRUSS_IEP_HIGH_COUNTER_RESET_VALUE,"
|
|
line.long 0xA8 "PRUSS_IEP_PWM,"
|
|
hexmask.long 0xA8 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0xA8 3. "PWM3_HIT,The raw status bit of eHRPWM3_SYNCO event" "No eHRPWM3_SYNCO event,eHRPWM3_SYNCO event occurred Write 1h to Clear"
|
|
newline
|
|
bitfld.long 0xA8 2. "PWM3_RST_CNT_EN,Enable the reset of the counter by a eHRPWM3_SYNCO event" "Disable,Enable the reset of.."
|
|
newline
|
|
bitfld.long 0xA8 1. "PWM0_HIT,The raw status bit of eHRPWM0_SYNCO event" "No eHRPWM0_SYNCO event,eHRPWM0_SYNCO event occurred Write 1 to Clear"
|
|
newline
|
|
bitfld.long 0xA8 0. "PWM0_RST_CNT_EN,Enable the reset of the counter by a eHRPWM0_SYNCO event" "Disable,Enable the reset of.."
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "PRUSS_IEP_SYNC_CTRL,"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SYNC1_IND_EN,SYNC1 independent mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SYNC1_ACK_EN,SYNC1 acknowledgement mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SYNC0_ACK_EN,SYNC0 acknowledgement mode enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SYNC1_EN,SYNC1 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNC0_EN,SYNC0 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SYNC_EN,SYNC generation enable" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_SYNC_FIRST_STAT,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "FIRST_SYNC1,SYNC1 First Event status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "FIRST_SYNC0,SYNC0 First Event status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_SYNC0_STAT,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "SYNC0_PEND,SYNC0 pending state" "0,1"
|
|
line.long 0x0C "PRUSS_IEP_SYNC1_STAT,"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "SYNC1_PEND,SYNC1 pending state" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_SYNC_PWIDTH,"
|
|
line.long 0x14 "PRUSS_IEP_SYNC0_PERIOD,"
|
|
line.long 0x18 "PRUSS_IEP_SYNC1_DELAY,"
|
|
line.long 0x1C "PRUSS_IEP_SYNC_START,"
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "PRUSS_IEP_WD_PREDIV,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,Defines the number of ICSS_IEP_CLK cycles per WD clock event"
|
|
line.long 0x04 "PRUSS_IEP_PDI_WD_TIM,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,Defines the number of WD ticks (or increments) for PDI WD that is the number of WD increments"
|
|
line.long 0x08 "PRUSS_IEP_PD_WD_TIM,"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,Defines the number of WD ticks (or increments) for PD WD that is the number of WD increments"
|
|
line.long 0x0C "PRUSS_IEP_WD_STATUS,"
|
|
hexmask.long.word 0x0C 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 16. "PDI_WD_STAT,WD PDI status" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "PD_WD_STAT,WD PD status (triggered by Sync Mangers status)" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_WD_EXP_CNT,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,WD PD expiration counter"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,WD PDI expiration counter"
|
|
line.long 0x14 "PRUSS_IEP_WD_CTRL,"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 16. "PDI_WD_EN,Watchdog PDI" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "PD_WD_EN,Watchdog PD" "0,1"
|
|
group.long 0x300++0x1B
|
|
line.long 0x00 "PRUSS_IEP_DIGIO_CTRL,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OUT_MODE,Defines events that triggers data out to be updated" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IN_MODE,Defines event that triggers data in to be sampled" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "WD_MODE,Defines Watchdog behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2. "BIDI_MODE,Defines the digital input/output direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUTVALID_MODE,Defines the outvalid mode behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "OUTVALID_POL,Defines OUTVALID polarity" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_DIGIO_STATUS,"
|
|
line.long 0x08 "PRUSS_IEP_DIGIO_DATA_IN,"
|
|
line.long 0x0C "PRUSS_IEP_DIGIO_DATA_IN_RAW,"
|
|
line.long 0x10 "PRUSS_IEP_DIGIO_DATA_OUT,"
|
|
line.long 0x14 "PRUSS_IEP_DIGIO_DATA_OUT_EN,"
|
|
line.long 0x18 "PRUSS_IEP_DIGIO_EXP,"
|
|
hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x18 13. "EOF_SEL,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "SOF_SEL,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "SOF_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 4.--7. "OUTVALID_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "SW_OUTVALID,PR<k>_EDIO_OUTVALID = SW_OUTVALID only if OUTVALID_OVR_EN is set" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "OUTVALID_OVR_EN,Software override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "SW_DATA_OUT_UPDATE,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1" "0,1"
|
|
repeat 2. (list 06. 16. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x58)++0x03
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_FALL$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MII_RT"
|
|
base eapb:0x20AB2000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_MII_RT_RXCFG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "Disable,Enable it must.."
|
|
newline
|
|
bitfld.long 0x00 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3 Nibble2}..,R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1 Nibble0}.."
|
|
newline
|
|
bitfld.long 0x00 4. "RX_L2_EN,Enables RX L2 buffer" "Disable (RX L2..,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "RX_MUX_SEL,Selects receive data source" "MII RX Data from Port 0 (default for..,MII RX Data from Port 1 (default for.."
|
|
newline
|
|
bitfld.long 0x00 2. "RX_CUT_PREAMBLE,Removes received preamble" "All data from Ethernet PHY are passed on to PRU..,MII interface suppresses preamble and sync frame.."
|
|
newline
|
|
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "Disable,Enable"
|
|
line.long 0x04 "PRUSS_MII_RT_RXCFG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "RX_L2_EN,Enables RX L2 buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "RX_MUX_SEL,Selects receive data source" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "RX_CUT_PREAMBLE,Removes received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "0,1"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PRUSS_MII_RT_TX_IPG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x04 "PRUSS_MII_RT_TX_IPG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x08 "PRUSS_MII_RT_PRS0,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "MII_CRS,Read the current state of pr1_mii0_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "MII_COL,Read the current state of pr1_mii0_col" "0,1"
|
|
line.long 0x0C "PRUSS_MII_RT_PRS1,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "MII_CRS,Read the current state of pr1_mii1_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "MII_COL,Read the current state of pr1_mii1_col" "0,1"
|
|
line.long 0x10 "PRUSS_MII_RT_RX_FRMS0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
line.long 0x14 "PRUSS_MII_RT_RX_FRMS1,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_FIFO_LEVEL,Define the number of valid nibbles in the TX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL,Define the number of valid bytes in the RX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_ERR$1,"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 3. "RX_MAX_FRM_ERR,Error status of received frame is more than the value of RX_MAX_FRM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_MIN_FRM_ERR,Error status of received frame is less than the value of RX_MIN_FRM" "0,1"
|
|
bitfld.long 0x00 1. "RX_MAX_PCNT_ERR,Error status of received preamble nibble is more than the value of RX_MAX_PCNT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_MIN_PCNT_ERR,Error status of received preamble nibble is less than the value of RX_MIN_PCNT" "0,1"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_PCNT$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 4.--7. "RX_MAX_PCNT,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RX_MIN_PCNT,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred which is matched the value 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x20)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TX_CRC$1,"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXCFG$1,"
|
|
rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "TX_CLK_DELAY,In order to guarantee the MII_RT IO timing values published in the device data manual the ICSS_i_VCLK_CLK (where i = 0 or 1) clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 26.--27. "RESERVED,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "TX_32_MODE_EN," "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 9. "TX_AUTO_SEQUENCE,Enables transmit auto-sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_MUX_SEL,Selects transmit data source" "0,1"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "TX_BYTE_SWAP,Defines the order of Byte0/1 placement for TX R30" "0,1"
|
|
bitfld.long 0x00 2. "TX_EN_MODE,Enables transmit self clear on TX_EOF event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE,Transmit data auto-preamble" "0,1"
|
|
bitfld.long 0x00 0. "TX_ENABLE,Enables transmit traffic on TX PORT" "0,1"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MII_MDIO"
|
|
base eapb:0x20AB2400
|
|
rgroup.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_MII_MDIO_VER,"
|
|
line.long 0x04 "PRUSS_MII_MDIO_CONTROL,"
|
|
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
|
|
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
|
|
rbitfld.long 0x04 29. "RESERVED,Reserved" "0,1"
|
|
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
|
|
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
|
|
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
|
|
rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1"
|
|
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
|
|
line.long 0x08 "PRUSS_MII_MDIO_ALIVE,"
|
|
line.long 0x0C "PRUSS_MII_MDIO_LINK,"
|
|
line.long 0x10 "PRUSS_MII_MDIO_LINKINTRAW,"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
|
|
line.long 0x14 "PRUSS_MII_MDIO_LINKINTMASKED,"
|
|
hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERINTRAW,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERINTMASKED,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERINTMASKSET,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--1. "USERINTMASKEDSET,MDIO user interrupt mask set for userintmasked[1:0] respectively" "0,1,2,3"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERINTMASKCLR,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--1. "USERINTMASKEDCLR,MDIO user command complete interrupt mask clear for userintmasked[1:0] respectively" "0,1,2,3"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERACCESS0,"
|
|
bitfld.long 0x00 31. "GO,Go" "0,1"
|
|
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x00 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERPHYSEL0,"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x04 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERACCESS1,"
|
|
bitfld.long 0x08 31. "GO,Go" "0,1"
|
|
bitfld.long 0x08 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x08 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x08 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,User data"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERPHYSEL1,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x0C 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x0C 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DEBUG_0"
|
|
base eapb:0x20AA2400
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG31,"
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x80)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "DEBUG_1"
|
|
base eapb:0x20AA4400
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG31,"
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x80)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "ICSS_1"
|
|
tree "ECC_CFG"
|
|
base eapb:0x20AE7000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_REVISION,"
|
|
group.long 0x08++0x1F
|
|
line.long 0x00 "ECC_VECTOR,"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved"
|
|
rbitfld.long 0x00 24. "READ_DONE,Status to indicate if read on the serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "READ_ADDRESS,Read address"
|
|
bitfld.long 0x00 15. "TRIGGER_READ,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
rbitfld.long 0x00 11.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. "RAM_ID,Value written to select the corresponding ECC RAM for control or status"
|
|
line.long 0x04 "ECC_MISC_STATUS,"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
|
|
line.long 0x08 "ECC_WRAPPER_REVISION,"
|
|
line.long 0x0C "ECC_CONTROL,"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/ FORCE_DED will inject an error to the specified row only once" "0,1"
|
|
bitfld.long 0x0C 5. "FORCE_N_ROW,Force single/double-bit error on the next RAM" "0,1"
|
|
bitfld.long 0x0C 4. "FORCE_DED,Force double-bit error" "0,1"
|
|
bitfld.long 0x0C 3. "FORCE_SEC,Force single-bit error" "0,1"
|
|
bitfld.long 0x0C 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
|
|
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC generation" "0,1"
|
|
line.long 0x10 "ECC_ERROR_CONTROL1,"
|
|
hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Column/ Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set"
|
|
hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where FORCE_SEC or FORCE_DED needs to be applied"
|
|
line.long 0x14 "ECC_ERROR_CONTROL2,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped when FORCE_DED is set"
|
|
line.long 0x18 "ECC_ERROR_STATUS1,"
|
|
hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Indicates the row/address where the single or double-bit error occurred"
|
|
rbitfld.long 0x18 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 10. "CLR_ECC_OTHER,1 indicates a successive single-bit error" "0,1"
|
|
bitfld.long 0x18 9. "CLR_ECC_DED,1 indicates a pending double-bit error" "0,1"
|
|
bitfld.long 0x18 8. "CLR_ECC_SEC,1 indicates a pending single-bit error" "0,1"
|
|
rbitfld.long 0x18 3.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 2. "ECC_OTHER,1 indicates that successive single-bit errors have occurred while a writeback is still pending" "0,1"
|
|
bitfld.long 0x18 1. "ECC_DED,1 indicates pending double-bit error" "0,1"
|
|
bitfld.long 0x18 0. "ECC_SEC,1 indicates pending single-bit error status" "0,1"
|
|
line.long 0x1C "ECC_ERROR_STATUS2,"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Indicates the bit position in the RAM data that is in error"
|
|
group.long 0x3C++0x3F
|
|
line.long 0x00 "ECC_EOI,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host" "0,1"
|
|
line.long 0x04 "ECC_INT_STATUS_0,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_STATUS_1,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_STATUS_2,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_STATUS_3,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_STATUS_4,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_STATUS_5,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_STATUS_6,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_STATUS_7,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_STATUS_8,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_STATUS_9,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_STATUS_10,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_STATUS_11,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_STATUS_12,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_STATUS_13,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x3C "ECC_INT_STATUS_14,"
|
|
hexmask.long 0x3C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x3C 0.--4. "SRC_INTR,Level interrupt status from each ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x3B
|
|
line.long 0x00 "ECC_INT_ENABLE_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_ENABLE_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_ENABLE_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_ENABLE_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_ENABLE_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_ENABLE_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_ENABLE_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_ENABLE_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_ENABLE_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_ENABLE_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_ENABLE_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_ENABLE_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_ENABLE_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_ENABLE_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_ENABLE_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE,Write 1 to enable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0++0x3B
|
|
line.long 0x00 "ECC_INT_CLEAR_0,"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ECC_INT_CLEAR_1,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECC_INT_CLEAR_2,"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ECC_INT_CLEAR_3,"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ECC_INT_CLEAR_4,"
|
|
hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ECC_INT_CLEAR_5,"
|
|
hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "ECC_INT_CLEAR_6,"
|
|
hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "ECC_INT_CLEAR_7,"
|
|
hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x1C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "ECC_INT_CLEAR_8,"
|
|
hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x20 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "ECC_INT_CLEAR_9,"
|
|
hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x24 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "ECC_INT_CLEAR_10,"
|
|
hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x28 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "ECC_INT_CLEAR_11,"
|
|
hexmask.long 0x2C 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x2C 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "ECC_INT_CLEAR_12,"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x30 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "ECC_INT_CLEAR_13,"
|
|
hexmask.long 0x34 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x34 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x38 "ECC_INT_CLEAR_14,"
|
|
hexmask.long 0x38 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x38 0.--4. "ENABLE_CLEAR,Write 1 to disable interrupt from the associated ECC RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CFG"
|
|
base eapb:0x20AE6000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PRUSS_REVID,"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PRUSS_GPCFG0,"
|
|
rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 26.--29. "PR1_PRU0_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 25. "PRU0_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x00 20.--24. "PRU0_GPO_DIV1,Divisor value (divide by PRU0_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15.--19. "PRU0_GPO_DIV0,Divisor value (divide by PRU0_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. "PRU0_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x00 13. "PRU0_GPI_SB,Start Bit event for 28-bit shift mode" "0,1"
|
|
bitfld.long 0x00 8.--12. "PRU0_GPI_DIV1,Divisor value (divide by PRU0_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 3.--7. "PRU0_GPI_DIV0,Divisor value (divide by PRU0_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 2. "PRU0_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x00 0.--1. "PRU0_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_GPCFG1,"
|
|
rbitfld.long 0x04 30.--31. "RESERVED,Reserved" "0,1,2,3"
|
|
bitfld.long 0x04 26.--29. "PR1_PRU1_GP_MUX_SEL,Controls the PRU-ICSS wrap mux selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 25. "PRU1_GPO_SH_SEL,Defines which shadow register is currently getting used for GPO shifting" "0,1"
|
|
bitfld.long 0x04 20.--24. "PRU1_GPO_DIV1,Divisor value (divide by PRU1_GPO_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 15.--19. "PRU1_GPO_DIV0,Divisor value (divide by PRU1_GPO_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. "PRU1_GPO_MODE,PRU GPO (R30) modes" "0,1"
|
|
bitfld.long 0x04 13. "PRU1_GPI_SB,28-bit shift mode Start Bit event" "0,1"
|
|
bitfld.long 0x04 8.--12. "PRU1_GPI_DIV1,Divisor value (divide by PRU1_GPI_DIV1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 3.--7. "PRU1_GPI_DIV0,Divisor value (divide by PRU1_GPI_DIV0 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 2. "PRU1_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
|
|
bitfld.long 0x04 0.--1. "PRU1_GPI_MODE,PRU GPI (R31) modes" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_CGR,"
|
|
bitfld.long 0x08 31. "ICSS_STOP_ACK,Acknowledgement that ICSS clock can be stopped" "0,1"
|
|
rbitfld.long 0x08 30. "ICSS_STOP_REQ,ICSS request to stop clock" "0,1"
|
|
hexmask.long.word 0x08 18.--29. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 17. "IEP_CLK_EN,IEP clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 16. "IEP_CLK_STOP_ACK,Acknowledgement that IEP clock can be stopped" "0,1"
|
|
bitfld.long 0x08 15. "IEP_CLK_STOP_REQ,IEP request to stop clock" "0,1"
|
|
bitfld.long 0x08 14. "ECAP_CLK_EN,ECAP clock enable" "0,1"
|
|
rbitfld.long 0x08 13. "ECAP_CLK_STOP_ACK,Acknowledgement that ECAP clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "ECAP_CLK_STOP_REQ,ECAP request to stop clock" "0,1"
|
|
bitfld.long 0x08 11. "UART_CLK_EN,UART clock enable" "0,1"
|
|
rbitfld.long 0x08 10. "UART_CLK_STOP_ACK,Acknowledgement that UART clock can be stopped" "0,1"
|
|
bitfld.long 0x08 9. "UART_CLK_STOP_REQ,UART request to stop clock" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "PRUSS_INTC_CLK_EN,PRUSS_INTC clock enable" "0,1"
|
|
rbitfld.long 0x08 7. "PRUSS_INTC_CLK_STOP_ACK,Acknowledgement that PRUSS_INTC clock can be stopped" "0,1"
|
|
bitfld.long 0x08 6. "PRUSS_INTC_CLK_STOP_REQ,PRUSS_INTC request to stop clock" "0,1"
|
|
bitfld.long 0x08 5. "PRU1_CLK_EN,PRU1 clock enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x08 4. "PRU1_CLK_STOP_ACK,Acknowledgement that PRU1 clock can be stopped" "0,1"
|
|
bitfld.long 0x08 3. "PRU1_CLK_STOP_REQ,PRU1 request to stop clock" "0,1"
|
|
bitfld.long 0x08 2. "PRU0_CLK_EN,PRU0 clock enable" "0,1"
|
|
rbitfld.long 0x08 1. "PRU0_CLK_STOP_ACK,Acknowledgement that PRU0 clock can be stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PRU0_CLK_STOP_REQ,PRU0 request to stop clock" "0,1"
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "PRUSS_PMAO,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 1. "PMAO_PRU1,PRU1 Master Port Address Offset Enable" "0,1"
|
|
bitfld.long 0x00 0. "PMAO_PRU0,PRU0 Master Port Address Offset Enable" "0,1"
|
|
line.long 0x04 "PRUSS_MII_RT,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "MII_RT_EVENT_EN,Enables the MII_RT Events to the PRU-ICSS_INTC" "0,1"
|
|
line.long 0x08 "PRUSS_IEPCLK,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0. "OCP_EN,IEP clock source" "0,1"
|
|
line.long 0x0C "PRUSS_SPP,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 1. "XFR_SHIFT_EN,Enables XIN XOUT shift functionality" "0,1"
|
|
bitfld.long 0x0C 0. "PRU1_PAD_HP_EN,Defines which PRU wins write cycle arbitration to a common scratch pad bank" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PRUSS_PIN_MX,"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 10.--11. "PWM3_REMAP_EN,Remaps the eHRPWM3_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
bitfld.long 0x00 8.--9. "PWM0_REMAP_EN,Remaps the eHRPWM0_SYNCI to a PRU-ICSS Host Interrupt" "Disabled,PRU-ICSS_0 Host..,PRU-ICSS_1 Host..,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED,Reserved"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU0_CTRL"
|
|
base eapb:0x20AE2000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRU1_CTRL"
|
|
base eapb:0x20AE4000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PRU_CONTROL,"
|
|
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
|
|
bitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "PRU is halted and host has access to the..,PRU is currently running and the host is locked.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIG_ENDIAN," "0,1"
|
|
rbitfld.long 0x00 9.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "PRU will free run when enabled,PRU will execute a single instruction and then.."
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "Counters not enabled,Counters enabled"
|
|
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "PRU is not asleep,PRU is asleep If this bit is written to a 0 the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "PRU is disabled,PRU is enabled"
|
|
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
|
|
line.long 0x04 "PRU_STATUS,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
abitfld.long 0x04 0.--15. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" "0x0002=byte address of 8h or PC of,0x0008=byte address of 20h)"
|
|
line.long 0x08 "PRU_WAKEUP_EN,"
|
|
line.long 0x0C "PRU_CYCLE,"
|
|
line.long 0x10 "PRU_STALL,"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRU_CTBIR0,"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table"
|
|
line.long 0x04 "PRU_CTBIR1,"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table"
|
|
line.long 0x08 "PRU_CTPPR0,"
|
|
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table"
|
|
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table"
|
|
line.long 0x0C "PRU_CTPPR1,"
|
|
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table"
|
|
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table"
|
|
width 0x0B
|
|
tree.end
|
|
tree "INTC"
|
|
base eapb:0x20AE0000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_INTC_REVID,"
|
|
line.long 0x04 "PRUSS_INTC_CR,"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Reserved" "0,1"
|
|
bitfld.long 0x04 2.--3. "NEST_MODE,The nesting mode" "0,1,2,3"
|
|
bitfld.long 0x04 1. "WAKEUP_MODE,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 0. "RESERVED,Reserved" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRUSS_INTC_GER,"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "ENABLE_HINT_ANY,The current global enable value when" "0,1"
|
|
group.long 0x1C++0x13
|
|
line.long 0x00 "PRUSS_INTC_GNLR,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Always read as 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,The current global nesting level (highest channel that is nested)"
|
|
line.long 0x04 "PRUSS_INTC_SISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Writes set the status of the interrupt given in the index value"
|
|
line.long 0x08 "PRUSS_INTC_SICR,"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Writes clear the status of the interrupt given in the index value"
|
|
line.long 0x0C "PRUSS_INTC_EISR,"
|
|
hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Writes set the enable of the interrupt given in the index value"
|
|
line.long 0x10 "PRUSS_INTC_EICR,"
|
|
hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Writes clear the enable of the interrupt given in the index value"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "PRUSS_INTC_HIEISR,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Writes set the enable of the host interrupt given in the index value"
|
|
line.long 0x04 "PRUSS_INTC_HIDISR,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Writes clear the enable of the host interrupt given in the index value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PRUSS_INTC_GPIR,"
|
|
bitfld.long 0x00 31. "GLB_NONE,No Interrupt is pending" "0,1"
|
|
hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,The currently highest priority interrupt index pending across all the host interrupts"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "PRUSS_INTC_SRSR0,"
|
|
line.long 0x04 "PRUSS_INTC_SRSR1,"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "PRUSS_INTC_SECR0,"
|
|
line.long 0x04 "PRUSS_INTC_SECR1,"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "PRUSS_INTC_ESR0,"
|
|
line.long 0x04 "PRUSS_INTC_ERS1,"
|
|
group.long 0x380++0x07
|
|
line.long 0x00 "PRUSS_INTC_ECR0,"
|
|
line.long 0x04 "PRUSS_INTC_ECR1,"
|
|
group.long 0x400++0x3F
|
|
line.long 0x00 "PRUSS_INTC_CMR_0,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "CH_MAP_3,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH_MAP_2,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH_MAP_1,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH_MAP_0,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PRUSS_INTC_CMR_1,"
|
|
rbitfld.long 0x04 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "CH_MAP_7,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "CH_MAP_6,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. "CH_MAP_5,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "CH_MAP_4,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "PRUSS_INTC_CMR_2,"
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rbitfld.long 0x08 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 24.--27. "CH_MAP_11,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "CH_MAP_10,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x08 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "CH_MAP_9,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x08 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "CH_MAP_8,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "PRUSS_INTC_CMR_3,"
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rbitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 24.--27. "CH_MAP_15,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "CH_MAP_14,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x0C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. "CH_MAP_13,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "CH_MAP_12,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "PRUSS_INTC_CMR_4,"
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rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 24.--27. "CH_MAP_19,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "CH_MAP_18,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x10 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "CH_MAP_17,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--3. "CH_MAP_16,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x14 "PRUSS_INTC_CMR_5,"
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rbitfld.long 0x14 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 24.--27. "CH_MAP_23,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "CH_MAP_22,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x14 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "CH_MAP_21,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. "CH_MAP_20,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x18 "PRUSS_INTC_CMR_6,"
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rbitfld.long 0x18 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 24.--27. "CH_MAP_27,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "CH_MAP_26,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x18 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 8.--11. "CH_MAP_25,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x18 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 0.--3. "CH_MAP_24,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x1C "PRUSS_INTC_CMR_7,"
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rbitfld.long 0x1C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 24.--27. "CH_MAP_31,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "CH_MAP_30,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x1C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 8.--11. "CH_MAP_29,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 0.--3. "CH_MAP_28,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x20 "PRUSS_INTC_CMR_8,"
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rbitfld.long 0x20 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 24.--27. "CH_MAP_35,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "CH_MAP_34,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x20 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--11. "CH_MAP_33,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "CH_MAP_32,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "PRUSS_INTC_CMR_9,"
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rbitfld.long 0x24 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. "CH_MAP_39,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "CH_MAP_38,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x24 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 8.--11. "CH_MAP_37,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. "CH_MAP_36,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x28 "PRUSS_INTC_CMR_10,"
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rbitfld.long 0x28 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 24.--27. "CH_MAP_43,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. "CH_MAP_42,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x28 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--11. "CH_MAP_41,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "CH_MAP_40,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x2C "PRUSS_INTC_CMR_11,"
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rbitfld.long 0x2C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 24.--27. "CH_MAP_47,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--19. "CH_MAP_46,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x2C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 8.--11. "CH_MAP_45,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x2C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "CH_MAP_44,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x30 "PRUSS_INTC_CMR_12,"
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rbitfld.long 0x30 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 24.--27. "CH_MAP_51,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--19. "CH_MAP_50,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x30 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 8.--11. "CH_MAP_49,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x30 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "CH_MAP_48,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x34 "PRUSS_INTC_CMR_13,"
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rbitfld.long 0x34 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 24.--27. "CH_MAP_55,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 16.--19. "CH_MAP_54,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x34 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 8.--11. "CH_MAP_53,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x34 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 0.--3. "CH_MAP_52,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x38 "PRUSS_INTC_CMR_14,"
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rbitfld.long 0x38 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 24.--27. "CH_MAP_59,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x38 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "CH_MAP_58,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x38 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 8.--11. "CH_MAP_57,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x38 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 0.--3. "CH_MAP_56,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x3C "PRUSS_INTC_CMR_15,"
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rbitfld.long 0x3C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 24.--27. "CH_MAP_63,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x3C 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 16.--19. "CH_MAP_62,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x3C 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 8.--11. "CH_MAP_61,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x3C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0.--3. "CH_MAP_60,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x808++0x03
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line.long 0x00 "PRUSS_INTC_HMR2,"
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 8.--11. "HINT_MAP_9,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HINT_MAP_8,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x900++0x27
|
|
line.long 0x00 "PRUSS_INTC_HIPIR_0,"
|
|
bitfld.long 0x00 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x04 "PRUSS_INTC_HIPIR_1,"
|
|
bitfld.long 0x04 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x04 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x08 "PRUSS_INTC_HIPIR_2,"
|
|
bitfld.long 0x08 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x08 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x0C "PRUSS_INTC_HIPIR_3,"
|
|
bitfld.long 0x0C 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x0C 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x10 "PRUSS_INTC_HIPIR_4,"
|
|
bitfld.long 0x10 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x10 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x14 "PRUSS_INTC_HIPIR_5,"
|
|
bitfld.long 0x14 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x14 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x18 "PRUSS_INTC_HIPIR_6,"
|
|
bitfld.long 0x18 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x18 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x1C "PRUSS_INTC_HIPIR_7,"
|
|
bitfld.long 0x1C 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x1C 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x20 "PRUSS_INTC_HIPIR_8,"
|
|
bitfld.long 0x20 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x20 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
line.long 0x24 "PRUSS_INTC_HIPIR_9,"
|
|
bitfld.long 0x24 31. "NONE_HINT,No pending interrupt" "0,1"
|
|
hexmask.long.tbyte 0x24 10.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT,HOST INT j PRIORITIZED INTERRUPT"
|
|
group.long 0xD00++0x07
|
|
line.long 0x00 "PRUSS_INTC_SIPR0,"
|
|
line.long 0x04 "PRUSS_INTC_SIPR1,"
|
|
group.long 0xD80++0x07
|
|
line.long 0x00 "PRUSS_INTC_SITR0,"
|
|
line.long 0x04 "PRUSS_INTC_SITR1,"
|
|
group.long 0x1100++0x27
|
|
line.long 0x00 "PRUSS_INTC_HINLR_0,"
|
|
bitfld.long 0x00 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x00 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x04 "PRUSS_INTC_HINLR_1,"
|
|
bitfld.long 0x04 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x08 "PRUSS_INTC_HINLR_2,"
|
|
bitfld.long 0x08 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x08 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x0C "PRUSS_INTC_HINLR_3,"
|
|
bitfld.long 0x0C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x0C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x10 "PRUSS_INTC_HINLR_4,"
|
|
bitfld.long 0x10 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x10 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x14 "PRUSS_INTC_HINLR_5,"
|
|
bitfld.long 0x14 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x14 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x18 "PRUSS_INTC_HINLR_6,"
|
|
bitfld.long 0x18 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x18 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x1C "PRUSS_INTC_HINLR_7,"
|
|
bitfld.long 0x1C 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x1C 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x20 "PRUSS_INTC_HINLR_8,"
|
|
bitfld.long 0x20 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x20 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
line.long 0x24 "PRUSS_INTC_HINLR_9,"
|
|
bitfld.long 0x24 31. "AUTO_OVERRIDE,Reads return 0" "0,1"
|
|
hexmask.long.tbyte 0x24 9.--30. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT,Reads return the current nesting level for the host interrupt"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "PRUSS_INTC_HIER,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.word 0x00 0.--9. 1. "ENABLE_HINT,The enable of the host interrupts (one per bit)"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "PRUSS_INTC_HMR$1,"
|
|
rbitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "HINT_MAP_3,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "HINT_MAP_2,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HINT_MAP_1,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HINT_MAP_0,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART"
|
|
base eapb:0x20AE8000
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "PRUSS_UART_RBR_THR_REGISTERS,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register"
|
|
line.long 0x04 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 3. "EDSSI,Enable Modem Status Interrupt" "0,1"
|
|
bitfld.long 0x04 2. "ELSI,Receiver line status interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "ETBEI,Transmitter holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x04 0. "ERBI,Receiver data available interrupt and character timeout indication interrupt enable" "0,1"
|
|
line.long 0x08 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 6.--7. "FIFOEN_RXFIFTL,Read: FIFOs enabled" "0,1,2,3"
|
|
rbitfld.long 0x08 4.--5. "RESERVED,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 1.--3. "INTID,Read: Interrupt type" "No effect,RXCLR,TXCLR,DMAMODE1,?..."
|
|
bitfld.long 0x08 0. "IPEND_FIFOEN,Read: Interrupt pending" "0,1"
|
|
line.long 0x0C "PRUSS_UART_LINE_CONTROL_REGISTER,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "DLAB,Divisor latch access bit" "0,1"
|
|
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "SP,Stick parity" "0,1"
|
|
bitfld.long 0x0C 4. "EPS,Even parity select" "0,1"
|
|
bitfld.long 0x0C 3. "PEN,Parity enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "STB,Number of STOP bits generated" "0,1"
|
|
bitfld.long 0x0C 0.--1. "WLS,Word length select" "0,1,2,3"
|
|
line.long 0x10 "PRUSS_UART_MODEM_CONTROL_REGISTER,"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 5. "AFE,Autoflow control enable" "0,1"
|
|
bitfld.long 0x10 4. "LOOP,Loop back mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "OUT2,OUT2 Control Bit" "0,1"
|
|
bitfld.long 0x10 2. "OUT1,OUT1 Control Bit" "0,1"
|
|
bitfld.long 0x10 1. "RTS,RTS control" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "RESERVED,Reserved" "0,1"
|
|
line.long 0x14 "PRUSS_UART_LINE_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO error" "0,1"
|
|
bitfld.long 0x14 6. "TEMT,Transmitter empty (TEMT) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "THRE,Transmitter holding register empty (THRE) indicator" "0,1"
|
|
bitfld.long 0x14 4. "BI,Break indicator" "0,1"
|
|
bitfld.long 0x14 3. "FE,Framing error (FE) indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PE,Parity error (PE) indicator" "0,1"
|
|
bitfld.long 0x14 1. "OE,Overrun error (OE) indicator" "0,1"
|
|
bitfld.long 0x14 0. "DR,Data-ready (DR) indicator for the receiver" "0,1"
|
|
line.long 0x18 "PRUSS_UART_MODEM_STATUS_REGISTER,"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x18 7. "CD,Complement of the Carrier Detect input" "0,1"
|
|
bitfld.long 0x18 6. "RI,Complement of the Ring Indicator input" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "DSR,Complement of the Data Set Ready input" "0,1"
|
|
bitfld.long 0x18 4. "CTS,Complement of the Clear To Send input" "0,1"
|
|
bitfld.long 0x18 3. "DCD,Change in DCD indicator bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "TERI,Trailing edge of RI (TERI) indicator bit" "0,1"
|
|
bitfld.long 0x18 1. "DDSR,Change in DSR indicator bit" "0,1"
|
|
bitfld.long 0x18 0. "DCTS,Change in CTS indicator bit" "0,1"
|
|
line.long 0x1C "PRUSS_UART_SCRATCH_REGISTER,"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DATA,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation"
|
|
line.long 0x20 "PRUSS_UART_DIVISOR_REGISTER_LSB_,"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DLL,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x24 "PRUSS_UART_DIVISOR_REGISTER_MSB_,"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DLH,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator"
|
|
line.long 0x28 "PRUSS_UART_PERIPHERAL_ID_REGISTER,"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 15. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 14. "UTRST,UART transmitter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "URRST,UART receiver reset" "0,1"
|
|
hexmask.long.word 0x00 1.--12. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0. "FREE,Free-running enable mode bit" "0,1"
|
|
line.long 0x04 "PRUSS_UART_MODE_DEFINITION_REGISTER,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0. "OSM_SEL,Over-Sampling Mode Select" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP"
|
|
base eapb:0x20AF0000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_ECAP_TSCNT,"
|
|
line.long 0x04 "PRUSS_ECAP_CNTPHS,"
|
|
line.long 0x08 "PRUSS_ECAP_CAP1,"
|
|
line.long 0x0C "PRUSS_ECAP_CAP2,"
|
|
line.long 0x10 "PRUSS_ECAP_CAP3,"
|
|
line.long 0x14 "PRUSS_ECAP_CAP4,"
|
|
group.word 0x28++0x09
|
|
line.word 0x00 "PRUSS_ECAP_ECCTL1,"
|
|
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. "CAPLDEN,Enable Loading of" "0,1"
|
|
bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x02 "PRUSS_ECAP_ECCTL2,"
|
|
rbitfld.word 0x02 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 10. "APWMPOL," "0,1"
|
|
bitfld.word 0x02 9. "CAPAPWM," "0,1"
|
|
bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1"
|
|
bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3"
|
|
bitfld.word 0x02 5. "SYNCI_EN," "0,1"
|
|
bitfld.word 0x02 4. "TSCNTSTP," "0,1"
|
|
bitfld.word 0x02 3. "REARMRESET," "0,1"
|
|
bitfld.word 0x02 1.--2. "STOPVALUE," "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x02 0. "CONTONESHT," "0,1"
|
|
line.word 0x04 "PRUSS_ECAP_ECEINT,"
|
|
hexmask.word.byte 0x04 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x04 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x04 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x04 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x04 4. "CEVT4," "0,1"
|
|
bitfld.word 0x04 3. "CEVT3," "0,1"
|
|
bitfld.word 0x04 2. "CEVT2," "0,1"
|
|
bitfld.word 0x04 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x04 0. "RESERVED,Reserved" "0,1"
|
|
line.word 0x06 "PRUSS_ECAP_ECFLG,"
|
|
hexmask.word.byte 0x06 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x06 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x06 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x06 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x06 4. "CEVT4," "0,1"
|
|
bitfld.word 0x06 3. "CEVT3," "0,1"
|
|
bitfld.word 0x06 2. "CEVT2," "0,1"
|
|
bitfld.word 0x06 1. "CEVT1," "0,1"
|
|
bitfld.word 0x06 0. "INT," "0,1"
|
|
line.word 0x08 "PRUSS_ECAP_ECCLR,"
|
|
hexmask.word.byte 0x08 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x08 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x08 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x08 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x08 4. "CEVT4," "0,1"
|
|
bitfld.word 0x08 3. "CEVT3," "0,1"
|
|
bitfld.word 0x08 2. "CEVT2," "0,1"
|
|
bitfld.word 0x08 1. "CEVT1," "0,1"
|
|
bitfld.word 0x08 0. "INT," "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PRUSS_ECAP_ECFRC,"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved"
|
|
bitfld.word 0x00 7. "CMPEQ," "0,1"
|
|
bitfld.word 0x00 6. "PRDEQ," "0,1"
|
|
bitfld.word 0x00 5. "CNTOVF," "0,1"
|
|
bitfld.word 0x00 4. "CEVT4," "0,1"
|
|
bitfld.word 0x00 3. "CEVT3," "0,1"
|
|
bitfld.word 0x00 2. "CEVT2," "0,1"
|
|
bitfld.word 0x00 1. "CEVT1," "0,1"
|
|
rbitfld.word 0x00 0. "RESERVED,Reserved" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "PRUSS_ECAP_PID,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IEP"
|
|
base eapb:0x20AEE000
|
|
group.long 0x00++0x57
|
|
line.long 0x00 "PRUSS_IEP_GLOBAL_CFG,"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,Defines the increment value when compensation is active"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DEFAULT_INC,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "CNT_ENABLE,Counter enable" "Disables the counter,Enables the counter"
|
|
line.long 0x04 "PRUSS_IEP_STATUS,"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CNT_OVF,Counter overflow status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_COMPENSATION,"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "COMPEN_CNT,Compensation counter"
|
|
line.long 0x0C "PRUSS_IEP_SLOW_COMPENSATION,"
|
|
line.long 0x10 "PRUSS_IEP_LOW_COUNTER,"
|
|
line.long 0x14 "PRUSS_IEP_HIGH_COUNTER,"
|
|
line.long 0x18 "PRUSS_IEP_CAPTURE_CFG,"
|
|
hexmask.long.word 0x18 18.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x18 10.--17. "CAP_ASYNC_EN,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable" "0x00=Disable synchronization,0x01=Enable synchronization"
|
|
newline
|
|
bitfld.long 0x18 9. "CAP7F_1ST_EVENT_EN,Capture 1st Event Enable for CAP7F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 8. "CAP7R_1ST_EVENT_EN,Capture 1st Event Enable for CAP7R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 7. "CAP6F_1ST_EVENT_EN,Capture 1st Event Enable for CAP6F" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 6. "CAP6R_1ST_EVENT_EN,Capture 1st Event Enable for CAP6R" "Continues mode,First Event mode"
|
|
newline
|
|
bitfld.long 0x18 0.--5. "CAP_1ST_EVENT_EN,Capture 1st Event Enable for registers" "Continues mode,First Event mode,?..."
|
|
line.long 0x1C "PRUSS_IEP_CAPTURE_STATUS,"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
abitfld.long 0x1C 16.--23. "CAP_RAW,Raw/Current status bit for each of the capture registers where CAP_RAW[n] maps to CAPR[n]" "0x00=Current state is low,0x01=Current state is high"
|
|
newline
|
|
bitfld.long 0x1C 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x1C 10. "CAP_VALID,Valid status for capture function" "No Hit for any capture event i.e,Hit for 1 or more captures events is pending i.e"
|
|
newline
|
|
bitfld.long 0x1C 9. "CAPF7_VALID,Valid status for CAPF7 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 8. "CAPR7_VALID,Valid status for CAPR7 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 7. "CAPF6_VALID,Valid status for CAPF6 (fall)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 6. "CAPR6_VALID,Valid status for CAPR6 (rise)" "No Hit no capture event occurred,Hit capture event occurred"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. "CAPR_VALID,Valid status bit for each compare register where CAPR_VALID[n] maps to CAPR[n] (rise)" "No Hit no capture event occurred,Hit capture event occurred,?..."
|
|
line.long 0x20 "PRUSS_IEP_CAPTURE_RISE00,"
|
|
line.long 0x24 "PRUSS_IEP_CAPTURE_RISE10,"
|
|
line.long 0x28 "PRUSS_IEP_CAPTURE_RISE01,"
|
|
line.long 0x2C "PRUSS_IEP_CAPTURE_RISE11,"
|
|
line.long 0x30 "PRUSS_IEP_CAPTURE_RISE02,"
|
|
line.long 0x34 "PRUSS_IEP_CAPTURE_RISE12,"
|
|
line.long 0x38 "PRUSS_IEP_CAPTURE_RISE03,"
|
|
line.long 0x3C "PRUSS_IEP_CAPTURE_RISE13,"
|
|
line.long 0x40 "PRUSS_IEP_CAPTURE_RISE04,"
|
|
line.long 0x44 "PRUSS_IEP_CAPTURE_RISE14,"
|
|
line.long 0x48 "PRUSS_IEP_CAPTURE_RISE05,"
|
|
line.long 0x4C "PRUSS_IEP_CAPTURE_RISE15,"
|
|
line.long 0x50 "PRUSS_IEP_CAPTURE_RISE06,"
|
|
line.long 0x54 "PRUSS_IEP_CAPTURE_RISE16,"
|
|
rgroup.long 0x60++0xAB
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_RISE07,"
|
|
line.long 0x04 "PRUSS_IEP_CAPTURE_RISE17,"
|
|
line.long 0x08 "PRUSS_IEP_CAPTURE_FALL07,"
|
|
line.long 0x0C "PRUSS_IEP_CAPTURE_FALL17,"
|
|
line.long 0x10 "PRUSS_IEP_COMPARE_CFG,"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x10 1.--16. 1. "CMP_EN,Enable bits for each of the compare registers"
|
|
newline
|
|
bitfld.long 0x10 0. "CMP0_RST_CNT_EN,Enable the reset of the counter" "0,1"
|
|
line.long 0x14 "PRUSS_IEP_COMPARE_STATUS,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP_HIT,Status bit for each of the compare registers"
|
|
line.long 0x18 "PRUSS_IEP_COMPARE00,"
|
|
line.long 0x1C "PRUSS_IEP_COMPARE10,"
|
|
line.long 0x20 "PRUSS_IEP_COMPARE01,"
|
|
line.long 0x24 "PRUSS_IEP_COMPARE11,"
|
|
line.long 0x28 "PRUSS_IEP_COMPARE02,"
|
|
line.long 0x2C "PRUSS_IEP_COMPARE12,"
|
|
line.long 0x30 "PRUSS_IEP_COMPARE03,"
|
|
line.long 0x34 "PRUSS_IEP_COMPARE13,"
|
|
line.long 0x38 "PRUSS_IEP_COMPARE04,"
|
|
line.long 0x3C "PRUSS_IEP_COMPARE14,"
|
|
line.long 0x40 "PRUSS_IEP_COMPARE05,"
|
|
line.long 0x44 "PRUSS_IEP_COMPARE15,"
|
|
line.long 0x48 "PRUSS_IEP_COMPARE06,"
|
|
line.long 0x4C "PRUSS_IEP_COMPARE16,"
|
|
line.long 0x50 "PRUSS_IEP_COMPARE07,"
|
|
line.long 0x54 "PRUSS_IEP_COMPARE17,"
|
|
line.long 0x58 "PRUSS_IEP_RXIPG0,"
|
|
hexmask.long.word 0x58 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x58 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x5C "PRUSS_IEP_RXIPG1,"
|
|
hexmask.long.word 0x5C 16.--31. 1. "RX_MIN_IPG,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low"
|
|
newline
|
|
hexmask.long.word 0x5C 0.--15. 1. "RX_IPG,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
|
|
line.long 0x60 "PRUSS_IEP_COMPARE08,"
|
|
line.long 0x64 "PRUSS_IEP_COMPARE18,"
|
|
line.long 0x68 "PRUSS_IEP_COMPARE09,"
|
|
line.long 0x6C "PRUSS_IEP_COMPARE19,"
|
|
line.long 0x70 "PRUSS_IEP_COMPARE010,"
|
|
line.long 0x74 "PRUSS_IEP_COMPARE110,"
|
|
line.long 0x78 "PRUSS_IEP_COMPARE011,"
|
|
line.long 0x7C "PRUSS_IEP_COMPARE111,"
|
|
line.long 0x80 "PRUSS_IEP_COMPARE012,"
|
|
line.long 0x84 "PRUSS_IEP_COMPARE112,"
|
|
line.long 0x88 "PRUSS_IEP_COMPARE013,"
|
|
line.long 0x8C "PRUSS_IEP_COMPARE113,"
|
|
line.long 0x90 "PRUSS_IEP_COMPARE014,"
|
|
line.long 0x94 "PRUSS_IEP_COMPARE114,"
|
|
line.long 0x98 "PRUSS_IEP_COMPARE015,"
|
|
line.long 0x9C "PRUSS_IEP_COMPARE115,"
|
|
line.long 0xA0 "PRUSS_IEP_LOW_COUNTER_RESET_VALUE,"
|
|
line.long 0xA4 "PRUSS_IEP_HIGH_COUNTER_RESET_VALUE,"
|
|
line.long 0xA8 "PRUSS_IEP_PWM,"
|
|
hexmask.long 0xA8 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0xA8 3. "PWM3_HIT,The raw status bit of eHRPWM3_SYNCO event" "No eHRPWM3_SYNCO event,eHRPWM3_SYNCO event occurred Write 1h to Clear"
|
|
newline
|
|
bitfld.long 0xA8 2. "PWM3_RST_CNT_EN,Enable the reset of the counter by a eHRPWM3_SYNCO event" "Disable,Enable the reset of.."
|
|
newline
|
|
bitfld.long 0xA8 1. "PWM0_HIT,The raw status bit of eHRPWM0_SYNCO event" "No eHRPWM0_SYNCO event,eHRPWM0_SYNCO event occurred Write 1 to Clear"
|
|
newline
|
|
bitfld.long 0xA8 0. "PWM0_RST_CNT_EN,Enable the reset of the counter by a eHRPWM0_SYNCO event" "Disable,Enable the reset of.."
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "PRUSS_IEP_SYNC_CTRL,"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SYNC1_IND_EN,SYNC1 independent mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SYNC1_ACK_EN,SYNC1 acknowledgement mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SYNC0_ACK_EN,SYNC0 acknowledgement mode enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SYNC1_EN,SYNC1 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNC0_EN,SYNC0 generation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SYNC_EN,SYNC generation enable" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_SYNC_FIRST_STAT,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "FIRST_SYNC1,SYNC1 First Event status" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "FIRST_SYNC0,SYNC0 First Event status" "0,1"
|
|
line.long 0x08 "PRUSS_IEP_SYNC0_STAT,"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "SYNC0_PEND,SYNC0 pending state" "0,1"
|
|
line.long 0x0C "PRUSS_IEP_SYNC1_STAT,"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "SYNC1_PEND,SYNC1 pending state" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_SYNC_PWIDTH,"
|
|
line.long 0x14 "PRUSS_IEP_SYNC0_PERIOD,"
|
|
line.long 0x18 "PRUSS_IEP_SYNC1_DELAY,"
|
|
line.long 0x1C "PRUSS_IEP_SYNC_START,"
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "PRUSS_IEP_WD_PREDIV,"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,Defines the number of ICSS_IEP_CLK cycles per WD clock event"
|
|
line.long 0x04 "PRUSS_IEP_PDI_WD_TIM,"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,Defines the number of WD ticks (or increments) for PDI WD that is the number of WD increments"
|
|
line.long 0x08 "PRUSS_IEP_PD_WD_TIM,"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,Defines the number of WD ticks (or increments) for PD WD that is the number of WD increments"
|
|
line.long 0x0C "PRUSS_IEP_WD_STATUS,"
|
|
hexmask.long.word 0x0C 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 16. "PDI_WD_STAT,WD PDI status" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "PD_WD_STAT,WD PD status (triggered by Sync Mangers status)" "0,1"
|
|
line.long 0x10 "PRUSS_IEP_WD_EXP_CNT,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,WD PD expiration counter"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,WD PDI expiration counter"
|
|
line.long 0x14 "PRUSS_IEP_WD_CTRL,"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 16. "PDI_WD_EN,Watchdog PDI" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 1.--15. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "PD_WD_EN,Watchdog PD" "0,1"
|
|
group.long 0x300++0x1B
|
|
line.long 0x00 "PRUSS_IEP_DIGIO_CTRL,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "OUT_MODE,Defines events that triggers data out to be updated" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IN_MODE,Defines event that triggers data in to be sampled" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3. "WD_MODE,Defines Watchdog behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2. "BIDI_MODE,Defines the digital input/output direction" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUTVALID_MODE,Defines the outvalid mode behavior" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "OUTVALID_POL,Defines OUTVALID polarity" "0,1"
|
|
line.long 0x04 "PRUSS_IEP_DIGIO_STATUS,"
|
|
line.long 0x08 "PRUSS_IEP_DIGIO_DATA_IN,"
|
|
line.long 0x0C "PRUSS_IEP_DIGIO_DATA_IN_RAW,"
|
|
line.long 0x10 "PRUSS_IEP_DIGIO_DATA_OUT,"
|
|
line.long 0x14 "PRUSS_IEP_DIGIO_DATA_OUT_EN,"
|
|
line.long 0x18 "PRUSS_IEP_DIGIO_EXP,"
|
|
hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x18 13. "EOF_SEL,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "SOF_SEL,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "SOF_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 4.--7. "OUTVALID_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "SW_OUTVALID,PR<k>_EDIO_OUTVALID = SW_OUTVALID only if OUTVALID_OVR_EN is set" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "OUTVALID_OVR_EN,Software override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "SW_DATA_OUT_UPDATE,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1" "0,1"
|
|
repeat 2. (list 06. 16. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x58)++0x03
|
|
line.long 0x00 "PRUSS_IEP_CAPTURE_FALL$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MII_RT"
|
|
base eapb:0x20AF2000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PRUSS_MII_RT_RXCFG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x00 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "Disable,Enable it must.."
|
|
newline
|
|
bitfld.long 0x00 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3 Nibble2}..,R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1 Nibble0}.."
|
|
newline
|
|
bitfld.long 0x00 4. "RX_L2_EN,Enables RX L2 buffer" "Disable (RX L2..,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "RX_MUX_SEL,Selects receive data source" "MII RX Data from Port 0 (default for..,MII RX Data from Port 1 (default for.."
|
|
newline
|
|
bitfld.long 0x00 2. "RX_CUT_PREAMBLE,Removes received preamble" "All data from Ethernet PHY are passed on to PRU..,MII interface suppresses preamble and sync frame.."
|
|
newline
|
|
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "Disable,Enable"
|
|
line.long 0x04 "PRUSS_MII_RT_RXCFG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x04 9. "RX_L2_EOF_SCLR_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 8. "RX_ERR_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "RX_SFD_RAW," "0,1"
|
|
newline
|
|
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE,Enables auto-forward of received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "RX_BYTE_SWAP,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "RX_L2_EN,Enables RX L2 buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "RX_MUX_SEL,Selects receive data source" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "RX_CUT_PREAMBLE,Removes received preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS," "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "RX_ENABLE,Enables the receive traffic currently selected by RX_MUX_SELECT" "0,1"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PRUSS_MII_RT_TX_IPG0,"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x04 "PRUSS_MII_RT_TX_IPG1,"
|
|
hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--9. 1. "TX_IPG,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of ICSS_i_VCLK_CLK (where i = 0 or 1) cycles between the de-assertion of TX_EN and the assertion of TX_EN"
|
|
line.long 0x08 "PRUSS_MII_RT_PRS0,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "MII_CRS,Read the current state of pr1_mii0_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "MII_COL,Read the current state of pr1_mii0_col" "0,1"
|
|
line.long 0x0C "PRUSS_MII_RT_PRS1,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "MII_CRS,Read the current state of pr1_mii1_crs" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "MII_COL,Read the current state of pr1_mii1_col" "0,1"
|
|
line.long 0x10 "PRUSS_MII_RT_RX_FRMS0,"
|
|
hexmask.long.word 0x10 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
line.long 0x14 "PRUSS_MII_RT_RX_FRMS1,"
|
|
hexmask.long.word 0x14 16.--31. 1. "RX_MAX_FRM,Defines the maximum received frame count"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "RX_MIN_FRM,Defines the minimum received frame count"
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_FIFO_LEVEL,Define the number of valid nibbles in the TX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RXFLV$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL,Define the number of valid bytes in the RX FIFO"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_ERR$1,"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 3. "RX_MAX_FRM_ERR,Error status of received frame is more than the value of RX_MAX_FRM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_MIN_FRM_ERR,Error status of received frame is less than the value of RX_MIN_FRM" "0,1"
|
|
bitfld.long 0x00 1. "RX_MAX_PCNT_ERR,Error status of received preamble nibble is more than the value of RX_MAX_PCNT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RX_MIN_PCNT_ERR,Error status of received preamble nibble is less than the value of RX_MIN_PCNT" "0,1"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_RX_PCNT$1,"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 4.--7. "RX_MAX_PCNT,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RX_MIN_PCNT,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred which is matched the value 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x20)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TX_CRC$1,"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PRUSS_MII_RT_TXCFG$1,"
|
|
rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "TX_CLK_DELAY,In order to guarantee the MII_RT IO timing values published in the device data manual the ICSS_i_VCLK_CLK (where i = 0 or 1) clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 26.--27. "RESERVED,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "TX_32_MODE_EN," "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "RESERVED,Reserved" "0,1"
|
|
bitfld.long 0x00 9. "TX_AUTO_SEQUENCE,Enables transmit auto-sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_MUX_SEL,Selects transmit data source" "0,1"
|
|
rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "TX_BYTE_SWAP,Defines the order of Byte0/1 placement for TX R30" "0,1"
|
|
bitfld.long 0x00 2. "TX_EN_MODE,Enables transmit self clear on TX_EOF event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE,Transmit data auto-preamble" "0,1"
|
|
bitfld.long 0x00 0. "TX_ENABLE,Enables transmit traffic on TX PORT" "0,1"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MII_MDIO"
|
|
base eapb:0x20AF2400
|
|
rgroup.long 0x00++0x17
|
|
line.long 0x00 "PRUSS_MII_MDIO_VER,"
|
|
line.long 0x04 "PRUSS_MII_MDIO_CONTROL,"
|
|
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
|
|
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
|
|
rbitfld.long 0x04 29. "RESERVED,Reserved" "0,1"
|
|
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
|
|
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
|
|
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
|
|
rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1"
|
|
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
|
|
line.long 0x08 "PRUSS_MII_MDIO_ALIVE,"
|
|
line.long 0x0C "PRUSS_MII_MDIO_LINK,"
|
|
line.long 0x10 "PRUSS_MII_MDIO_LINKINTRAW,"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
|
|
line.long 0x14 "PRUSS_MII_MDIO_LINKINTMASKED,"
|
|
hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERINTRAW,"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERINTMASKED,"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERINTMASKSET,"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x08 0.--1. "USERINTMASKEDSET,MDIO user interrupt mask set for userintmasked[1:0] respectively" "0,1,2,3"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERINTMASKCLR,"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 0.--1. "USERINTMASKEDCLR,MDIO user command complete interrupt mask clear for userintmasked[1:0] respectively" "0,1,2,3"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PRUSS_MII_MDIO_USERACCESS0,"
|
|
bitfld.long 0x00 31. "GO,Go" "0,1"
|
|
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x00 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
|
|
line.long 0x04 "PRUSS_MII_MDIO_USERPHYSEL0,"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x04 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "PRUSS_MII_MDIO_USERACCESS1,"
|
|
bitfld.long 0x08 31. "GO,Go" "0,1"
|
|
bitfld.long 0x08 30. "WRITE,Write enable" "0,1"
|
|
bitfld.long 0x08 29. "ACK,Acknowledge" "0,1"
|
|
rbitfld.long 0x08 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,User data"
|
|
line.long 0x0C "PRUSS_MII_MDIO_USERPHYSEL1,"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved"
|
|
bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1"
|
|
bitfld.long 0x0C 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
rbitfld.long 0x0C 5. "RESERVED,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DEBUG_0"
|
|
base eapb:0x20AE2400
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG31,"
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x80)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "DEBUG_1"
|
|
base eapb:0x20AE4400
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG31,"
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x80)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_CT_REG$1,"
|
|
repeat.end
|
|
repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PRU_ICSS_DBG_GPREG$1,"
|
|
repeat.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
AUTOINDENT.OFF
|
|
newline
|