353 lines
13 KiB
Plaintext
353 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: S32M24 Specific Menu
|
|
; @Props: Released
|
|
; @Author: DAB, NEJ, JDU, KRZ
|
|
; @Changelog: 2022-01-13 DAB
|
|
; 2022-06-29 NEJ
|
|
; 2022-08-09 NEJ
|
|
; 2023-06-19 JDU
|
|
; 2023-10-19 KRZ
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: Cortex-M4F
|
|
; @Chip: S32M241, S32M242, S32M243, S32M244
|
|
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: mens32m24.men 16966 2023-11-09 08:27:09Z skrausse $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
separator
|
|
popup "ADC;Analog-to-Digital Converter"
|
|
(
|
|
menuitem "ADC0" "per , ""ADC (Analog-to-Digital Converter),ADC0"""
|
|
menuitem "ADC1" "per , ""ADC (Analog-to-Digital Converter),ADC1"""
|
|
)
|
|
menuitem "AEC_AE" "per , ""AEC_AE"""
|
|
menuitem "AIPS;Peripheral Bridge" "per , ""AIPS (Peripheral Bridge)"""
|
|
menuitem "CMP;Comparator" "per , ""CMP (Comparator)"""
|
|
menuitem "CRC;Cyclic Redundancy Check" "per , ""CRC (Cyclic Redundancy Check)"""
|
|
menuitem "DMA;Direct Memory Access" "per , ""DMA (Direct Memory Access)"""
|
|
menuitem "DMAMUX;Direct Memory Access Multiplexer" "per , ""DMAMUX (Direct Memory Access Multiplexer)"""
|
|
menuitem "DPGA_AE;Digitally Programmable Gain Amplifier" "per , ""DPGA_AE (Digitally Programmable Gain Amplifier)"""
|
|
menuitem "EIM;Error Injection Module" "per , ""EIM (Error Injection Module)"""
|
|
menuitem "ERM;Error Reporting Module" "per , ""ERM (Error Reporting Module)"""
|
|
menuitem "EWM;Hardware Watchdog" "per , ""EWM (Hardware Watchdog)"""
|
|
menuitem "FLEXCAN;Flexible CAN" "per , ""FLEXCAN (Flexible CAN)"""
|
|
menuitem "FLEXIO;Flexible I/O" "per , ""FLEXIO (Flexible I/O)"""
|
|
menuitem "FTFC;Flash Memory Module" "per , ""FTFC (Flash Memory Module)"""
|
|
menuitem "FTFM;Flash Memory Module" "per , ""FTFM (Flash Memory Module)"""
|
|
popup "FTM;FlexTimer Module"
|
|
(
|
|
menuitem "FTM0" "per , ""FTM (FlexTimer Module),FTM0"""
|
|
menuitem "FTM1" "per , ""FTM (FlexTimer Module),FTM1"""
|
|
menuitem "FTM2" "per , ""FTM (FlexTimer Module),FTM2"""
|
|
menuitem "FTM3" "per , ""FTM (FlexTimer Module),FTM3"""
|
|
)
|
|
menuitem "GDU_AE;Gate Drive Unit" "per , ""GDU_AE (Gate Drive Unit)"""
|
|
popup "GPIO;General-Purpose I/Os"
|
|
(
|
|
menuitem "PTA" "per , ""GPIO (General-Purpose I/Os),PTA"""
|
|
menuitem "PTB" "per , ""GPIO (General-Purpose I/Os),PTB"""
|
|
menuitem "PTC" "per , ""GPIO (General-Purpose I/Os),PTC"""
|
|
menuitem "PTD" "per , ""GPIO (General-Purpose I/Os),PTD"""
|
|
menuitem "PTE" "per , ""GPIO (General-Purpose I/Os),PTE"""
|
|
)
|
|
menuitem "HVI_AE;High Voltage Input" "per , ""HVI_AE (High Voltage Input)"""
|
|
menuitem "LMEM;Local Memory Controller" "per , ""LMEM (Local Memory Controller)"""
|
|
menuitem "LPI2C;Low Power Inter-Integrated Circuit" "per , ""LPI2C (Low Power Inter-Integrated Circuit)"""
|
|
menuitem "LPIT;Low Power Interrupt Timer" "per , ""LPIT (Low Power Interrupt Timer)"""
|
|
popup "LPSPI;Low Power Serial Peripheral Interface"
|
|
(
|
|
menuitem "LPSPI0" "per , ""LPSPI (Low Power Serial Peripheral Interface),LPSPI0"""
|
|
menuitem "LPSPI1" "per , ""LPSPI (Low Power Serial Peripheral Interface),LPSPI1"""
|
|
menuitem "LPSPI2" "per , ""LPSPI (Low Power Serial Peripheral Interface),LPSPI2"""
|
|
)
|
|
menuitem "LPTMR;Low Power Timer" "per , ""LPTMR (Low Power Timer)"""
|
|
popup "LPUART;Low Power Universal Asynchronous Receiver/Transmitter"
|
|
(
|
|
menuitem "LPUART0" "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter),LPUART0"""
|
|
menuitem "LPUART1" "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter),LPUART1"""
|
|
)
|
|
menuitem "MCM;Miscellaneous Control Module" "per , ""MCM (Miscellaneous Control Module)"""
|
|
menuitem "MDM-AP" "per , ""MDM-AP"""
|
|
menuitem "MEM_OTP_AE;One Time Programmable Memory" "per , ""MEM_OTP_AE (One Time Programmable Memory)"""
|
|
menuitem "MPU;Memory Protection Unit" "per , ""MPU (Memory Protection Unit)"""
|
|
menuitem "MSCM;Miscellaneous System Control Module" "per , ""MSCM (Miscellaneous System Control Module)"""
|
|
menuitem "PCC;Peripheral Clock Controller" "per , ""PCC (Peripheral Clock Controller)"""
|
|
popup "PDB;Programmable Delay Block"
|
|
(
|
|
menuitem "PDB0" "per , ""PDB (Programmable Delay Block),PDB0"""
|
|
menuitem "PDB1" "per , ""PDB (Programmable Delay Block),PDB1"""
|
|
)
|
|
menuitem "PMC;Power Management Controller" "per , ""PMC (Power Management Controller)"""
|
|
menuitem "PMC_142;Power Management Controller for S32M242/S32M241" "per , ""PMC_142 (Power Management Controller for S32M242/S32M241)"""
|
|
menuitem "PMC_AE;Power Management Controller" "per , ""PMC_AE (Power Management Controller)"""
|
|
popup "PORT;Port Control and Interrupts"
|
|
(
|
|
menuitem "PORTA" "per , ""PORT (Port Control and Interrupts),PORTA"""
|
|
menuitem "PORTB" "per , ""PORT (Port Control and Interrupts),PORTB"""
|
|
menuitem "PORTC" "per , ""PORT (Port Control and Interrupts),PORTC"""
|
|
menuitem "PORTD" "per , ""PORT (Port Control and Interrupts),PORTD"""
|
|
menuitem "PORTE" "per , ""PORT (Port Control and Interrupts),PORTE"""
|
|
)
|
|
menuitem "RCM;Reset Control Module" "per , ""RCM (Reset Control Module)"""
|
|
menuitem "RTC;Real Time Clock" "per , ""RTC (Real Time Clock)"""
|
|
menuitem "SCG;System Clock Generator" "per , ""SCG (System Clock Generator)"""
|
|
menuitem "SIM;System Integration Module" "per , ""SIM (System Integration Module)"""
|
|
menuitem "SMC;System Mode Controller" "per , ""SMC (System Mode Controller)"""
|
|
menuitem "TRGMUX;Trigger MUX Control" "per , ""TRGMUX (Trigger MUX Control)"""
|
|
menuitem "WDOG;Watchdog Timer" "per , ""WDOG (Watchdog Timer)"""
|
|
)
|
|
)
|