325 lines
9.5 KiB
Plaintext
325 lines
9.5 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: MT2523 Specific Menu
|
|
; @Props: Released
|
|
; @Author: BCA
|
|
; @Changelog: 2017-10-05 BCA
|
|
; @Manufacturer: MediaTek Inc.
|
|
; @Core: Cortex-M4F
|
|
; @Chip: MT2523
|
|
; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menmt2523.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
separator
|
|
menuitem "EINT" "per , ""EINT (External Interrupt Controller)"""
|
|
menuitem "DMA" "per , ""DMA (Direct Memory Access)"""
|
|
menuitem "RTC" "per , ""RTC (Real-Time Clock)"""
|
|
popup "UART"
|
|
(
|
|
menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART0"""
|
|
menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART1"""
|
|
menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART2"""
|
|
menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART3"""
|
|
)
|
|
popup "SPI_MSTR"
|
|
(
|
|
menuitem "SPI0" "per , ""SPI_MSTR (Serial Peripheral Interface Master Controller),SPI0"""
|
|
menuitem "SPI1" "per , ""SPI_MSTR (Serial Peripheral Interface Master Controller),SPI1"""
|
|
menuitem "SPI2" "per , ""SPI_MSTR (Serial Peripheral Interface Master Controller),SPI2"""
|
|
menuitem "SPI3" "per , ""SPI_MSTR (Serial Peripheral Interface Master Controller),SPI3"""
|
|
)
|
|
menuitem "SPI_SLV" "per , ""SPI_SLV (Serial Peripheral Interface Slave Controller)"""
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit Controller),I2C0"""
|
|
menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit Controller),I2C1"""
|
|
menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit Controller),I2C2"""
|
|
menuitem "I2C_D2D" "per , ""I2C (Inter-Integrated Circuit Controller),I2C_D2D"""
|
|
)
|
|
popup "SD_MEM_CARD_CON"
|
|
(
|
|
menuitem "MSDC0" "per , ""SD_MEM_CARD_CON (SD Memory Card Controller),MSDC0"""
|
|
menuitem "MSDC1" "per , ""SD_MEM_CARD_CON (SD Memory Card Controller),MSDC1"""
|
|
)
|
|
menuitem "USB2.0" "per , ""USB2.0 High-Speed Device Controller"""
|
|
menuitem "GPT" "per , ""GPT (General Purpose Timer)"""
|
|
popup "PWM"
|
|
(
|
|
menuitem "PWM0" "per , ""PWM (Pulse Width Modulation),PWM0"""
|
|
menuitem "PWM1" "per , ""PWM (Pulse Width Modulation),PWM1"""
|
|
menuitem "PWM2" "per , ""PWM (Pulse Width Modulation),PWM2"""
|
|
menuitem "PWM3" "per , ""PWM (Pulse Width Modulation),PWM3"""
|
|
menuitem "PWM4" "per , ""PWM (Pulse Width Modulation),PWM4"""
|
|
menuitem "PWM5" "per , ""PWM (Pulse Width Modulation),PWM5"""
|
|
)
|
|
menuitem "KS" "per , ""KS (Keypad Scanner)"""
|
|
menuitem "GPC" "per , ""GPC (General Purpose Counter)"""
|
|
menuitem "AUXADC" "per , ""AUXADC (Auxiliary ADC Unit)"""
|
|
menuitem "GPDAC" "per , ""GPDAC (General Purpose DAC)"""
|
|
menuitem "ACCDET" "per , ""ACCDET (Accessory Detector)"""
|
|
menuitem "TRNG" "per , ""TRNG (True Random Number Generator)"""
|
|
menuitem "AFE" "per , ""AFE (Audio Front End)"""
|
|
menuitem "2D" "per , ""2D Acceleration"""
|
|
menuitem "MSC" "per , ""Multimedia Subsystem Configuration"""
|
|
menuitem "LCD" "per , ""LCD (LCD display)"""
|
|
menuitem "DISP_DSI" "per , ""DISP_DSI (Display Serial Interface)"""
|
|
menuitem "IR" "per , ""Image Resizer"""
|
|
menuitem "ROT_DMA" "per , ""ROT_DMA (Image Rotator DMA)"""
|
|
menuitem "GPIO" "per , ""GPIO (General Purpose Inputs/Outputs)"""
|
|
menuitem "PMU" "per , ""PMU (Power Management Unit)"""
|
|
)
|
|
)
|