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Gen4_R-Car_Trace32/2_Trunk/menk50.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: Kinetis K50 Specific Menu
; @Props: Released
; @Author: KAP, KRW, KAO, PBU, ZUO, BCA
; @Changelog: 2014-01-23 KRW
; 2014-11-06 KAO
; 2015-10-20 ZUO
; 2018-08-07 BCA
; @Manufacturer: NXP
; @Core: Cortex-M4
; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menk50.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
popup "PORT (Pin control and interrupts)"
(
menuitem "PORTA" "per , ""PORT (Pin control and interrupts),PORTA"""
menuitem "PORTB" "per , ""PORT (Pin control and interrupts),PORTB"""
menuitem "PORTC" "per , ""PORT (Pin control and interrupts),PORTC"""
menuitem "PORTD" "per , ""PORT (Pin control and interrupts),PORTD"""
menuitem "PORTE" "per , ""PORT (Pin control and interrupts),PORTE"""
)
popup "System Modules"
(
menuitem "SIM" "per , ""System Modules,SIM (System Integration Module)"""
if (cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10")&&cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10"))
(
menuitem "RCM" "per , ""System Modules,RCM (Reset Control Module)"""
)
menuitem "SMC" "per , ""System Modules,SMC (System Mode Controller)"""
menuitem "PMC" "per , ""System Modules,PMC (Power Management Controller)"""
menuitem "LLWU" "per , ""System Modules,LLWU (Low-Leakage Wake-up Unit)"""
menuitem "MCM" "per , ""System Modules,MCM (Miscellaneous Control Module)"""
menuitem "AXBS" "per , ""System Modules,AXBS (Crossbar Switch)"""
if (cpuis("MK5?D*10"))
(
menuitem "MPU" "per , ""System Modules,MPU (Memory Protection Unit)"""
)
menuitem "PB" "per , ""System Modules,Peripheral Bridge"""
menuitem "DMAMUX" "per , ""System Modules,DMAMUX (Direct Memory Access Multiplexer)"""
menuitem "eDMA" "per , ""System Modules,eDMA (Enhanced Direct Memory Access)"""
menuitem "EWM" "per , ""System Modules,EWM (External Watchdog Monitor)"""
menuitem "WDOG" "per , ""System Modules,WDOG (Watchdog Timer)"""
)
popup "Clock Modules"
(
menuitem "MCG" "per , ""Clock Modules,MCG (Multipurpose Clock Generator)"""
menuitem "OSC" "per , ""Clock Modules,OSC (Oscillator)"""
)
popup "Memories and Memory Interfaces"
(
menuitem "FMC" "per , ""Memories and Memory Interfaces,FMC (Flash Memory Controller)"""
menuitem "FTFE" "per , ""Memories and Memory Interfaces,FTFE (Flash Memory Module)"""
if cpuis("?????X*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLL10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")
(
if (!cpuis("MK51DX256ZCMC10"))
(
menuitem "FLEXBUS" "per , ""Memories and Memory Interfaces,FLEXBUS (External Bus Interface)"""
)
)
)
popup "Security"
(
menuitem "CRC" "per , ""Security and integrity modules,CRC (Cyclic redundancy check)"""
if (cpuis("MK52*")||cpuis("MK53*"))
(
menuitem "MMCAU" "per , ""Security and integrity modules,MMCAU (Memory-Mapped Cryptographic Acceleration Unit)"""
)
if (cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10"))
(
menuitem "RNGB" "per , ""Security and integrity modules,RNGB (Random Number Generator)"""
)
if (!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10"))
(
menuitem "RNGA" "per , ""Security and integrity modules,RNGA (Random Number Generator Accelerator)"""
)
)
popup "Analog Modules"
(
menuitem "ADC" "per , ""Analog Modules,ADC (Analog-to-Digital Converter)"""
menuitem "HSCMP" "per , ""Analog Modules,HSCMP (Comparator/6-bit DAC Converter)"""
menuitem "DAC" "per , ""Analog Modules,DAC (12-bit Digital-to-Analog Converter)"""
menuitem "OPAMP" "per , ""Analog Modules,OPAMP (Operational amplifier)"""
menuitem "VREFV1" "per , ""Analog Modules,VREFV1 (Voltage Reference)"""
)
popup "Timers"
(
menuitem "PDB" "per , ""Timers,PDB (Programmable Delay Block)"""
menuitem "FTM" "per , ""Timers,FTM (FlexTimer)"""
menuitem "PIT" "per , ""Timers,PIT (Periodic Interrupt Timer)"""
menuitem "LPT" "per , ""Timers,LPT (Low Power Timer)"""
menuitem "CMT" "per , ""Timers,CMT (Carrier Modulator Transmitter)"""
menuitem "RTC" "per , ""Timers,RTC (Real Time Clock)"""
)
popup "Communication Interfaces"
(
if (cpuis("MK52*")||cpuis("MK53*"))
(
menuitem "ENET" "per , ""Communication Interfaces,ENET (10/100-Mbps Ethernet MAC)"""
)
menuitem "USBOTG" "per , ""Communication Interfaces,USBOTG (Universal Serial Bus OTG Controller)"""
menuitem "USBDCD" "per , ""Communication Interfaces,USBDCD (USB Device Charger Detection Module)"""
menuitem "SPI" "per , ""Communication Interfaces,SPI (Serial Peripheral Interface)"""
menuitem "I2C" "per , ""Communication Interfaces,I2C (Inter-Integrated Circuit)"""
menuitem "UART" "per , ""Communication Interfaces,UART (Universal asynchronous receiver/transmitter)"""
if (cpuis("MK5*10"))
(
menuitem "SDHC" "per , ""Communication Interfaces,SDHC (Secured digital host controller)"""
)
menuitem "I2S0/SAI0" "per , ""Communication Interfaces,I2S0/SAI0"""
)
popup "Human-Machine Interfaces"
(
menuitem "GPIO" "per , ""Human-Machine Interfaces,GPIO (GPIO Controller)"""
menuitem "TSI" "per , ""Human-Machine Interfaces,TSI (Touch sense input)"""
if (!cpuis("MK50D*")&&!cpuis("MK52D*"))
(
menuitem "SLCD" "per , ""Human-Machine Interfaces,SLCD (LCD Controller)"""
)
)
)
)
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