417 lines
15 KiB
Plaintext
417 lines
15 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Halo specific menu (Cortex-M4)
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; @Props: Released
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; @Author: KAO, WIL, KMB
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; @Changelog:
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; 2016-04-20 WIL
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; 2017-01-26 KMB
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; @Manufacturer: NXP
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; @Core: Cortex-M4
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; @Chip: MAC57D54H-CM4
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menhalocm4.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "IOP" "per , ""IO Processor (IOP)"""
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menuitem "SIUL2" "per , ""System Integration Unit Lite2 (SIUL2)"""
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popup "AIPS"
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(
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menuitem "AIPS 0" "per , ""Peripheral Bridge (AIPS),AIPS 0"""
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menuitem "AIPS 1" "per , ""Peripheral Bridge (AIPS),AIPS 1"""
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)
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menuitem "AXBS" "per , ""AHB Crossbar Switch (AXBS)"""
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menuitem "QoS301" "per , ""QoS301"""
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menuitem "SEMA42" "per , ""Semaphores2 (SEMA42)"""
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popup "MSCM"
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(
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menuitem "MSCM CPU" "per , ""Miscellaneous System Control Module (MSCM),MSCM CPU"""
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menuitem "MSCM On-Chip Memory" "per , ""Miscellaneous System Control Module (MSCM),MSCM On-Chip Memory"""
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menuitem "MSCM Interrupts" "per , ""Miscellaneous System Control Module (MSCM),MSCM Interrupts"""
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)
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menuitem "XRDC" "per , ""Extended Resource Domain Controller (XRDC)"""
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menuitem "WKPU" "per , ""Wake-up Unit (WKPU)"""
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menuitem "EIM" "per , ""Error Injection Module (EIM)"""
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menuitem "ERM" "per , ""Error Reporting Module (ERM)"""
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menuitem "MPR" "per , ""Multi Purpose Register Bank (MPR)"""
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popup "PLLDIG"
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(
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menuitem "PLL0" "per , ""PLL Digital Interface (PLLDIG),PLL0"""
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menuitem "PLL1" "per , ""PLL Digital Interface (PLLDIG),PLL1"""
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menuitem "PLL2" "per , ""PLL Digital Interface (PLLDIG),PLL2"""
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menuitem "PLL3" "per , ""PLL Digital Interface (PLLDIG),PLL3"""
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)
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menuitem "FIRC" "per , ""Fast internal 16 MHz RC oscillator (FIRC)"""
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menuitem "SIRC" "per , ""Slow internal 128 kHz oscillator (SIRC)"""
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menuitem "SXOSC" "per , ""Slow external 32 KHz oscillator (SXOSC)"""
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menuitem "FXOSC_CTL" "per , ""FXOSC Control Register (FXOSC_CTL)"""
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menuitem "CMU" "per , ""Clock Monitor Unit (CMU)"""
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menuitem "MC_CGM" "per , ""Clock Generation Module (MC_CGM)"""
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popup "TCON"
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(
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menuitem "TCON" "per , ""Timing Controller (TCON),TCON"""
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menuitem "TCON_1" "per , ""Timing Controller (TCON),TCON_1"""
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)
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popup "DCU"
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(
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menuitem "DCU_0" "per , ""Display Controller Unit (DCU),DCU_0"""
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menuitem "DCU_1" "per , ""Display Controller Unit (DCU),DCU_1"""
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)
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menuitem "GPU2D Memory Map/Register Definition" "per , ""GC355 Vector Graphics Processing Unit (GC355)"""
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menuitem "RLE_DEC" "per , ""Run Length Encoding Decoder (RLE_DEC)"""
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menuitem "LVDS Display Bridge" "per , ""LDB (LVDS Display Bridge)"""
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menuitem "VIU4" "per , ""Video-In (VIU4)"""
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menuitem "LCD64F6B" "per , ""LCD Driver (LCD64F6B)"""
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menuitem "ADC" "per , ""Analog-to-Digital Converted (ADC)"""
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popup "CMP"
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(
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menuitem "CMP0" "per , ""Analogue Comparator (CMP),CMP0"""
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menuitem "CMP1" "per , ""Analogue Comparator (CMP),CMP1"""
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)
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popup "FTM"
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(
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menuitem "FTM0" "per , ""FlexTimer Module (FTM),FTM0"""
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menuitem "FTM1" "per , ""FlexTimer Module (FTM),FTM1"""
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menuitem "FTM2" "per , ""FlexTimer Module (FTM),FTM2"""
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menuitem "FTM3" "per , ""FlexTimer Module (FTM),FTM3"""
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)
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popup "SWT"
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(
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menuitem "SWT0" "per , ""Software Watchdog (SWT),SWT0"""
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menuitem "SWT1" "per , ""Software Watchdog (SWT),SWT1"""
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menuitem "SWT2" "per , ""Software Watchdog (SWT),SWT2"""
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)
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popup "STM"
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(
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menuitem "STM0" "per , ""System Timer Module (STM),STM0"""
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menuitem "STM1" "per , ""System Timer Module (STM),STM1"""
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)
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menuitem "PIT" "per , ""Periodic Interrupt Timer (PIT)"""
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menuitem "RTC" "per , ""Real Time Clock (RTC)"""
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menuitem "MC_PCU" "per , ""Power Control Unit (MC_PCU)"""
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menuitem "MC_ME" "per , ""Mode Entry Module (MC_ME)"""
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menuitem "PMCDIG" "per , ""Power Management Controller digital interface (PMCDIG)"""
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menuitem "MLB" "per , ""Media Local Bus Block (MLB)"""
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popup "FlexCAN"
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(
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menuitem "CAN0" "per , ""FlexCAN,CAN0"""
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menuitem "CAN1" "per , ""FlexCAN,CAN1"""
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menuitem "CAN2" "per , ""FlexCAN,CAN2"""
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)
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popup "I2C"
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(
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menuitem "I2C_0" "per , ""Inter-Integrated Circuit (I2C),I2C_0"""
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menuitem "I2C_1" "per , ""Inter-Integrated Circuit (I2C),I2C_1"""
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)
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popup "SPI"
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(
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menuitem "SPI_0" "per , ""Serial Peripheral Interface (SPI),SPI_0"""
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menuitem "SPI_1" "per , ""Serial Peripheral Interface (SPI),SPI_1"""
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menuitem "SPI_2" "per , ""Serial Peripheral Interface (SPI),SPI_2"""
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menuitem "SPI_3" "per , ""Serial Peripheral Interface (SPI),SPI_3"""
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menuitem "SPI_4" "per , ""Serial Peripheral Interface (SPI),SPI_4"""
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)
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popup "LINFlex"
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(
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menuitem "LINFlex_0" "per , ""LIN CONTROLLER (LINFlex),LINFlex_0"""
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menuitem "LINFlex_1" "per , ""LIN CONTROLLER (LINFlex),LINFlex_1"""
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menuitem "LINFlex_2" "per , ""LIN CONTROLLER (LINFlex),LINFlex_2"""
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)
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menuitem "ENET" "per , ""10/100-Mbps Ethernet MAC (ENET)"""
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menuitem "SGM" "per , ""Sound Generator Module (SGM)"""
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popup "SSD"
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(
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menuitem "SSD 0" "per , ""Stepper Stall Detect (SSD),SSD 0"""
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menuitem "SSD 1" "per , ""Stepper Stall Detect (SSD),SSD 1"""
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menuitem "SSD 2" "per , ""Stepper Stall Detect (SSD),SSD 2"""
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menuitem "SSD 3" "per , ""Stepper Stall Detect (SSD),SSD 3"""
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menuitem "SSD 4" "per , ""Stepper Stall Detect (SSD),SSD 4"""
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menuitem "SSD 5" "per , ""Stepper Stall Detect (SSD),SSD 5"""
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)
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menuitem "SMC" "per , ""Stepper Motor Controller (SMC)"""
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menuitem "SSCM" "per , ""System Status and Configuration Module (SSCM)"""
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menuitem "MC_RGM" "per , ""Reset Generation Module (MC_RGM)"""
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popup "EDMA"
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(
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menuitem "DMA0" "per , ""Enhanced Direct Memory Access (EDMA),DMA0"""
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menuitem "DMA1" "per , ""Enhanced Direct Memory Access (EDMA),DMA1"""
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)
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menuitem "DMA_MUX" "per , ""Direct Memory Access Multiplexer (DMA_MUX)"""
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|
menuitem "PFLASH" "per , ""Flash memory controller (PFLASH)"""
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popup "PRAMC"
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(
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menuitem "PRAMC_0" "per , ""RAM Controller (PRAMC),PRAMC_0"""
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menuitem "PRAMC_1" "per , ""RAM Controller (PRAMC),PRAMC_1"""
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)
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menuitem "c55fmc" "per , ""Embedded Flash Memory (c55fmc)"""
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|
menuitem "MDDRC" "per , ""Multi-Port DRAM Controller (MDDRC)"""
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menuitem "DDRC_PRIOMAN" "per , ""DRAM Controller Priority Manager (DDRC_PRIOMAN)"""
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popup "QuadSPI"
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(
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menuitem "QSPI0" "per , ""Quad Serial Peripheral Interface (QuadSPI),QSPI0"""
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menuitem "QSPI1" "per , ""Quad Serial Peripheral Interface (QuadSPI),QSPI1"""
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)
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menuitem "LMEM" "per , ""Local Memory Controller (LMEM)"""
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menuitem "JDC" "per , ""JTAG Data Communication (JDC)"""
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menuitem "FCCU" "per , ""Fault Collection and Control Unit (FCCU)"""
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menuitem "STCU2" "per , ""Self Test Control Unit (STCU2)"""
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menuitem "CRC" "per , ""Cyclic Redundancy Check (CRC)"""
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menuitem "TDM" "per , ""Tamper Detection Module (TDM)"""
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menuitem "PASS" "per , ""Password and Device Security Module (PASS)"""
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menuitem "CSE" "per , ""Cryptographic Services Engine (CSE)"""
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)
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)
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