452 lines
16 KiB
Plaintext
452 lines
16 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AWR2944 Specific Menu
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; @Props: Released
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; @Author: KMB, ADR, KRZ, NEJ
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; @Changelog: 2021-08-30 KMB
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; 2021-12-14 ADR
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; 2022-04-26 KRZ
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; 2023-11-14 NEJ
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-M4, Cortex-R5F, C66x
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; @Chip: AWR2944, AWR2944-HSM, AWR2944-HWA, AWR2944DSP
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menawr2944.men 17044 2023-11-21 16:23:45Z kwisniewski $
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add
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menu
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(
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if (CPUFAMILY()=="C6000")
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(
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popup "&CPU"
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(
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after "FPU Registers"
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separator
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popup "[:cache]Cache"
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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popup "&Trace"
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(
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("AET")
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(
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menuitem "[:oconfig]AET settings..." "AET.state"
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)
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)
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popup "&Perf"
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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else
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXM4")
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(
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popup "[:chip]Core Registers (Cortex-M4)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else if (CORENAME()=="CORTEXR5F")
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(
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popup "[:chip]Core Registers (Cortex-R5F)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R5F),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R5F),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R5F),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R5F),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R5F),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers"""
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)
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)
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else
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(
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popup "[:chip]Core Registers (c66x)"
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(
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menuitem "[:chip]L1P;L1P Registers" "per , ""Core Registers (c66x),Cache,L1P Cache"""
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menuitem "[:chip]L1D;L1D Registers" "per , ""Core Registers (c66x),Cache,L1D Cache"""
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menuitem "[:chip]L2;L2 Registers" "per , ""Core Registers (c66x),Cache,L2 Cache"""
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menuitem "[:chip]IDMA;IDMA Registers" "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)"""
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menuitem "[:chip]XMC;XMC Registers" "per , ""Core Registers (c66x),XMC (Extended Memory Controller)"""
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menuitem "[:chip]BM;BM Registers" "per , ""Core Registers (c66x),Bandwith Management"""
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menuitem "[:chip]IC;IC Registers" "per , ""Core Registers (c66x),Interrupt Controller"""
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menuitem "[:chip]PD;PD Registers" "per , ""Core Registers (c66x),Power-Down Controller"""
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)
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)
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separator
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if (cpuis("AWR2944DSP"))
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(
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menuitem "DSP_ICFG" "per , ""DSP_ICFG"""
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)
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menuitem "DSS_CBUFF" "per , ""DSS_CBUFF"""
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menuitem "DSS_CTRL" "per , ""DSS_CTRL"""
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menuitem "DSS_DCCA" "per , ""DSS_DCCA"""
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menuitem "DSS_DCCB" "per , ""DSS_DCCB"""
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menuitem "DSS_DSP_PBIST" "per , ""DSS_DSP_PBIST"""
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menuitem "DSS_DSP_STC" "per , ""DSS_DSP_STC"""
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menuitem "DSS_ECC_AGG" "per , ""DSS_ECC_AGG"""
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menuitem "DSS_ESM" "per , ""DSS_ESM"""
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menuitem "DSS_HWA_CFG" "per , ""DSS_HWA_CFG"""
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menuitem "DSS_MCRC" "per , ""DSS_MCRC"""
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menuitem "DSS_PCR" "per , ""DSS_PCR"""
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menuitem "DSS_RCM" "per , ""DSS_RCM"""
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menuitem "DSS_RTIA" "per , ""DSS_RTIA"""
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menuitem "DSS_RTIB" "per , ""DSS_RTIB"""
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menuitem "DSS_SCIA" "per , ""DSS_SCIA"""
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menuitem "DSS_TPCC_A" "per , ""DSS_TPCC_A"""
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menuitem "DSS_TPCC_B" "per , ""DSS_TPCC_B"""
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menuitem "DSS_TPCC_C" "per , ""DSS_TPCC_C"""
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menuitem "DSS_TPTC_A0" "per , ""DSS_TPTC_A0"""
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menuitem "DSS_TPTC_A1" "per , ""DSS_TPTC_A1"""
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menuitem "DSS_TPTC_B0" "per , ""DSS_TPTC_B0"""
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menuitem "DSS_TPTC_B1" "per , ""DSS_TPTC_B1"""
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menuitem "DSS_TPTC_C0" "per , ""DSS_TPTC_C0"""
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menuitem "DSS_TPTC_C1" "per , ""DSS_TPTC_C1"""
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menuitem "DSS_TPTC_C2" "per , ""DSS_TPTC_C2"""
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menuitem "DSS_TPTC_C3" "per , ""DSS_TPTC_C3"""
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menuitem "DSS_TPTC_C4" "per , ""DSS_TPTC_C4"""
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menuitem "DSS_TPTC_C5" "per , ""DSS_TPTC_C5"""
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menuitem "DSS_WDT" "per , ""DSS_WDT"""
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menuitem "MPU_DSS_HWA_DMA0" "per , ""MPU_DSS_HWA_DMA0"""
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menuitem "MPU_DSS_HWA_DMA1" "per , ""MPU_DSS_HWA_DMA1"""
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menuitem "MPU_DSS_HWA_PROC" "per , ""MPU_DSS_HWA_PROC"""
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menuitem "MPU_DSS_L3_BANKA" "per , ""MPU_DSS_L3_BANKA"""
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menuitem "MPU_DSS_L3_BANKB" "per , ""MPU_DSS_L3_BANKB"""
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menuitem "MPU_DSS_L3_BANKC" "per , ""MPU_DSS_L3_BANKC"""
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menuitem "MPU_DSS_L3_BANKD" "per , ""MPU_DSS_L3_BANKD"""
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menuitem "MPU_DSS_MBOX" "per , ""MPU_DSS_MBOX"""
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menuitem "MPU_MSS_CR5A_AXIS" "per , ""MPU_MSS_CR5A_AXIS"""
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menuitem "MPU_MSS_CR5B_AXIS" "per , ""MPU_MSS_CR5B_AXIS"""
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menuitem "MPU_MSS_L2_BANKA" "per , ""MPU_MSS_L2_BANKA"""
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menuitem "MPU_MSS_L2_BANKB" "per , ""MPU_MSS_L2_BANKB"""
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menuitem "MPU_MSS_MBOX" "per , ""MPU_MSS_MBOX"""
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menuitem "MPU_MSS_PCRA" "per , ""MPU_MSS_PCRA"""
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menuitem "MPU_MSS_QSPI" "per , ""MPU_MSS_QSPI"""
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menuitem "MSS_CCMR" "per , ""MSS_CCMR"""
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menuitem "MSS_CPSW" "per , ""MSS_CPSW"""
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menuitem "MSS_CTRL" "per , ""MSS_CTRL"""
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menuitem "MSS_DCCA" "per , ""MSS_DCCA"""
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menuitem "MSS_DCCB" "per , ""MSS_DCCB"""
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menuitem "MSS_DCCC" "per , ""MSS_DCCC"""
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menuitem "MSS_DCCD" "per , ""MSS_DCCD"""
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menuitem "MSS_DMM_A" "per , ""MSS_DMM_A"""
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menuitem "MSS_DMM_B" "per , ""MSS_DMM_B"""
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menuitem "MSS_ECC_AGG_MSS" "per , ""MSS_ECC_AGG_MSS"""
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menuitem "MSS_ECC_AGG_R5A" "per , ""MSS_ECC_AGG_R5A"""
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menuitem "MSS_ECC_AGG_R5B" "per , ""MSS_ECC_AGG_R5B"""
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menuitem "MSS_ESM" "per , ""MSS_ESM"""
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menuitem "MSS_ETPWMA" "per , ""MSS_ETPWMA"""
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menuitem "MSS_ETPWMB" "per , ""MSS_ETPWMB"""
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menuitem "MSS_ETPWMC" "per , ""MSS_ETPWMC"""
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menuitem "MSS_GIO" "per , ""MSS_GIO"""
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menuitem "MSS_GPADC_DATA_RAM" "per , ""MSS_GPADC_DATA_RAM"""
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menuitem "MSS_GPADC_PKT_RAM" "per , ""MSS_GPADC_PKT_RAM"""
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menuitem "MSS_GPADC_REG" "per , ""MSS_GPADC_REG"""
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menuitem "MSS_I2C" "per , ""MSS_I2C"""
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menuitem "MSS_IOMUX" "per , ""MSS_IOMUX"""
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menuitem "MSS_MCANA_CFG" "per , ""MSS_MCANA_CFG"""
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menuitem "MSS_MCANA_ECC" "per , ""MSS_MCANA_ECC"""
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menuitem "MSS_MCANB_CFG" "per , ""MSS_MCANB_CFG"""
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menuitem "MSS_MCANB_ECC" "per , ""MSS_MCANB_ECC"""
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menuitem "MSS_MCRC" "per , ""MSS_MCRC"""
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menuitem "MSS_PCR1" "per , ""MSS_PCR1"""
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menuitem "MSS_PCR2" "per , ""MSS_PCR2"""
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menuitem "MSS_QSPI" "per , ""MSS_QSPI"""
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menuitem "MSS_R5SS_STC" "per , ""MSS_R5SS_STC"""
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menuitem "MSS_RCM" "per , ""MSS_RCM"""
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menuitem "MSS_RTIA" "per , ""MSS_RTIA"""
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menuitem "MSS_RTIB" "per , ""MSS_RTIB"""
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menuitem "MSS_RTIC" "per , ""MSS_RTIC"""
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menuitem "MSS_SCIA" "per , ""MSS_SCIA"""
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menuitem "MSS_SCIB" "per , ""MSS_SCIB"""
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menuitem "MSS_SPIA" "per , ""MSS_SPIA"""
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menuitem "MSS_SPIB" "per , ""MSS_SPIB"""
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menuitem "MSS_TOPRCM" "per , ""MSS_TOPRCM"""
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menuitem "MSS_TPCC_A" "per , ""MSS_TPCC_A"""
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menuitem "MSS_TPCC_B" "per , ""MSS_TPCC_B"""
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menuitem "MSS_TPTC_A0" "per , ""MSS_TPTC_A0"""
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menuitem "MSS_TPTC_A1" "per , ""MSS_TPTC_A1"""
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menuitem "MSS_TPTC_B0" "per , ""MSS_TPTC_B0"""
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menuitem "MSS_VIM_R5A" "per , ""MSS_VIM_R5A"""
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menuitem "MSS_VIM_R5B" "per , ""MSS_VIM_R5B"""
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menuitem "MSS_WDT" "per , ""MSS_WDT"""
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menuitem "RSS_CSI2A" "per , ""RSS_CSI2A"""
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menuitem "RSS_CTRL" "per , ""RSS_CTRL"""
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menuitem "RSS_RCM" "per , ""RSS_RCM"""
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menuitem "RSS_TPCC_A" "per , ""RSS_TPCC_A"""
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menuitem "RSS_TPTC_A0" "per , ""RSS_TPTC_A0"""
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menuitem "TOP_AURORA_TX" "per , ""TOP_AURORA_TX"""
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menuitem "TOP_CTRL" "per , ""TOP_CTRL"""
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menuitem "TOP_MDO_INFRA" "per , ""TOP_MDO_INFRA"""
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menuitem "TOP_PBIST" "per , ""TOP_PBIST"""
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)
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|
)
|