336 lines
9.7 KiB
Plaintext
336 lines
9.7 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Measure MC/DC
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; @Description:
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; Measure MC/DC for sample application using imported ECA data.
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;
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; Supported Targets:
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; RM57 (Arm Cortex-R5)
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; STM32F407IG (Arm Cortex-M4)
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; LA-3854 "Bolero3M Adapter" with MPC5646C
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; T2080 (PPC QorIQ)
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; TC399XE (TriCore TC39X)
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;
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; @Author: CSA
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; @Board: RM57, LA-3854, T2080QDS
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; @Chip: RM57L843-ZWT, STM32F407IG, MPC5646C, T2080, TC399XE
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; @Keywords: coverage mc/dc eca
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: measure_mcdc.cmm 19349 2022-05-17 12:40:44Z meick $
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WinCLEAR
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PMACRO.EXPLICIT
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; --------------------------------------------------------------------------------
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; Check TRACE32 version
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; --------------------------------------------------------------------------------
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PRIVATE &min_build
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&min_build=70316.
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IF VERSION.BUILD.BASE()<&min_build
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(
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DIALOG.OK "Sorry, the script" """"+OS.PPF()+"""" "requires at least TRACE32 build "+FORMAT.Decimal(1,&min_build)+"."
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ENDDO FALSE()
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)
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RESet
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SYStem.RESet
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IF CPUFAMILY()=="ARM"
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(
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SYStem.CPU RM57L843-ZWT
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SYStem.DETECT IDCode
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IF (IDCODE(0)==0x06413041)&&((IDCODE(1)&0x0fffffff)==0x0BA00477)
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(
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SYStem.CPU STM32F407IG
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SYStem.MemAccess DAP
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SYStem.JtagClock CTCK 10MHz
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IF Analyzer()
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(
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Trace.METHOD Analyzer
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Analyzer.TERMination OFF
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)
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ELSE IF hardware.COMBIPROBE()||hardware.UTRACE()
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(
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Trace.METHOD CAnalyzer
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SYStem.CONFIG CONNECTOR MIPI20T
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)
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SYStem.Up
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Register.Init
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sYmbol.SourcePATH.SetBaseDir arm
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Data.LOAD.Elf "~~~~/arm/coverage_cm.elf" /RelPath /PlusVM
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IF Analyzer()||hardware.COMBIPROBE()||hardware.UTRACE()
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(
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Data.Set E:0x40023830 %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXX1xxxx // RCC_AHB1ENR : IO port E clock enable
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Data.Set E:0x40021000 %Long 0yXXXXxxxxXXXXxxxxXX1010101010xxxx // GPOIE_PORTMODE : Enable "alternate funtion" on trace pins (PE2..PE6)
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Data.Set E:0x40021020 %Long 0yXXXX00000000000000000000XXXXxxxx // GPIOE_AFRL : Use ETM as "alternate funtion" for trace pins (PE2..PE6)
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Data.Set E:0x40021008 %Long 0yXXXXxxxxXXXXxxxxXX0101010101xxxx // GPOIE_PORTSPEED : Use "Medium speed" for trace pins (PE2..PE6)
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ETM.RESet
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ETM.TImeMode ExternalInterpolated
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ITM.RESet
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ITM.ON
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ITM.DataTrace CorrelatedData
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TPIU.PortMode Continuous
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TPIU.PortSize 4
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Trace.ACCESS DualPort
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Trace.AutoArm ON
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Trace.AutoInit ON
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Trace.THreshold 1.5
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Trace.CLOCK 16.MHz
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Trace.TraceCLOCK 16.MHz
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)
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)
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ELSE
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(
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SYStem.CPU RM57L843-ZWT
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SYStem.Option EnReset OFF // Stop the CPU at RESET Vector
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SYStem.Option ICEPICK SystemReset.ON
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SYStem.Option ICEPICK WaitInReset.ON
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SYStem.MemAccess DAP
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SYStem.JtagClock CTCK 10MHz
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SYStem.Up
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Data.Set 0x08000000++0x7ffff %Quad 0x0 // Init ECC - via CPU
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sYmbol.SourcePATH.SetBaseDir arm
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Data.LOAD.Elf "~~~~/arm/coverage.elf" /RelPath /PlusVM
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GOSUB CtiSetup
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IF Analyzer()
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(
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Data.Set APB:0x80003404 %Long 0x00000001 // Enable TPIU, by setting input clock to VCLK
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TPIU.PortSize 16
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TPIU.PortMode Continuous
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ETM.Trace ON
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ETM.ON
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Trace.METHOD Analyzer
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Trace.AutoFocus
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)
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)
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)
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ELSE IF CPUFAMILY()=="POWERPC"
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(
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IF CPUIS64BIT()
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(
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SYStem.BdmClock 15.MHz ;try lower debug frequencies if problems occur
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SYStem.CPU T2080
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SYStem.DETECT CPU
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CORE.ASSIGN 1. ;Assign just the first core to this T32 instance
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;NEXUS.CoreENable 0. ;Optional: trace only core 1
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SYStem.Option.SLOWRESET ON ;Needed by some Freescale/NXP boards
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DO ~~/demo/powerpc64bit/hardware/qoriq_t2/t2080qds/demo_set_rcw.cmm ; Set a temporary RCW if needed by the target
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DO ~~/demo/powerpc64bit/hardware/qoriq_t2/t2080qds/qixis_config_serdes_aurora_mux.cmm ; Ensure Aurora trace works
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SYStem.Option.IMASKASM ON ;disable insterrupts for assembler single steps
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SYStem.Option.FREEZE ON ;stop time base when in debug mode
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SYStem.MemAccess NEXUS ;allow non-intrusive run-time memory access
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PRIVATE &base_path
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&base_path=OS.PWD()
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;Set CCSRBAR to 0x40000000
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Data.Set ANC:IOBASE.ADDRESS()+0x00004 %Long 0x40000000
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Data.Set ANC:IOBASE.ADDRESS()+0x00008 %Long 0x80000000 ;commit
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Data.Set ANC:IOBASE.ADDRESS()+0x00008 %Long 0x00000000
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;Set up local access window, 0x0000000--0x0007FFFF, memory complex (for CPC, 512kB)
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Data.Set ANC:IOBASE.ADDRESS()+0x00C00 %Long %BE 0x00000000
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Data.Set ANC:IOBASE.ADDRESS()+0x00C04 %Long %BE 0x00000000
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Data.Set ANC:IOBASE.ADDRESS()+0x00C08 %Long %BE 0x81000012
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;Enable CoreNet Platform Cache (CPC) as SRAM
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Data.Set ANC:IOBASE.ADDRESS()+0x10000 %Long %BE 0x80200000
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Data.Set ANC:IOBASE.ADDRESS()+0x10100 %Long %BE 0x00000000
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Data.Set ANC:IOBASE.ADDRESS()+0x10104 %Long %BE 0x00000009 ;Set maximum (512kB) and enable, start at 0x0
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;reset stack pointer
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Register.Set R1 0x00000000
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;TLB entry for 512kB CPC-SRAM 0x40000000--0x4007ffff
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MMU.TLB1.Set 1. 0x80000480 0x40000002 0x00000015 0x00000000 0x00000000
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;reset stack pointer
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Register.Set R1 0x00000000
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sYmbol.SourcePATH.SetBaseDir ppc
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Data.LOAD.Elf ~~~~/ppc/coverage.elf /RelPATH /PlusVM
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)
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ELSE
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(
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SYStem.CPU MPC55XX
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SYStem.BdmClock 1.MHz
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SYStem.Option IMASKASM ON
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SYStem.Option IMASKHLL ON
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SYStem.Option WATCHDOG OFF
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SYStem.Option DisMode AUTO
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IF !SIMULATOR()
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(
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SYStem.MemAccess NEXUS
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)
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SYStem.Mode Up
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Register.Init
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MMU.Set TLB1 1 0xC0000200 0x40000000 0x4000003F ; Map 16 KB of SRAM to logical address space
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MMU.Set TLB1 2 0xC0000500 0xFFF0000A 0xFFF0003F ; Map 1 MB of peripheral reg. to logical address space
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Data.Set EA:0x40000000++0x3FFF %Quad 0x55AA55AA55AA55AA ; Initialize 16 KB of internal SRAM
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sYmbol.SourcePATH.SetBaseDir ppc
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Data.LOAD.Elf ~~~~/ppc/coverage.elf /RelPATH /PlusVM
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Data.Set SPR:0x03f3 3 // Enable (and invalidate) instruction cache (if available)
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IF Analyzer()
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(
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Analyzer.Init
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Analyzer.CLOCK 8.MHz
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Analyzer.Mode FIFO
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Analyzer.AutoArm ON
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NEXUS.BTM ON
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NEXUS.HTM ON // Treat isel/fsel as conditional instruction
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)
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)
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)
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ELSE IF CPUFAMILY()=="TRICORE"
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(
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IF SIMULATOR()
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SYStem.CPU TC399XE
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ELSE
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SYStem.DETECT CPU
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SYStem.Mode Up
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sYmbol.SourcePATH.SetBaseDir tricore
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IF CPUIS("TC3*")
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Data.LOAD.Elf ~~~~/tricore/coverage.elf /RelPATH /PlusVM /SingleLineAdjacent
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ELSE IF CPUIS("TC2*")
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Data.LOAD.Elf ~~~~/tricore/coverage_tc2.elf /RelPATH /PlusVM /SingleLineAdjacent
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ELSE
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(
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PRINT %ERROR "CPU "+CPU()+" not supported."
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ENDDO FALSE()
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)
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IF (Onchip())&&(!Analyzer())
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(
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Trace.METHOD Onchip
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)
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)
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ELSE IF CPUFAMILY()=="RISCV"
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(
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SYStem.CPU RV32
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IF !SIMULATOR()
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(
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SYStem.CONFIG.NEXUS.Type SiFive
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SYStem.CONFIG.NEXUS.Base SB:0x10000000
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SYStem.CONFIG.NEXUS.NTB OFF
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Trace.METHOD CAnalyzer
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NEXUS.ON
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NEXUS.PIBMode 4TDATA
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NEXUS.PIBDivider 1.
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NEXUS.PTM HTM+ReturnStack
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NEXUS.TimeStamps ON
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CAnalyzer.CLOCK 64.MHz
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CAnalyzer.PortFilter AUTO
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CAnalyzer.TERMination ON
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)
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SYStem.Mode Up
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IF CAnalyzer()
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(
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CAnalyzer.AutoFocus
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)
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sYmbol.SourcePATH.SetBaseDir riscv
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Data.LOAD.Elf ~~~~/riscv/coverage.rv32.elf /RelPATH /PlusVM /SingleLineAdjacent
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)
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Go main
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WAIT !RUN()
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Break.Set sYmbol.EXIT(TestObcDiffersMcdc)
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Var.Break.Set RunCoverageDemo\tic /Write
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Mode.Hll
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GOSUB RestoreWindows
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; --------------------------------------------------------------------------------
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; Import ECA data
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; --------------------------------------------------------------------------------
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sYmbol.ECA.LOAD \coverage
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COVerage.Option.SourceMetric MCDC
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ENDDO TRUE()
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; --------------------------------------------------------------------------------
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; Display windows for HLL coverage
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; --------------------------------------------------------------------------------
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RestoreWindows:
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(
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WinCLEAR
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WinPOS 0.0 0.0 125. 33. 28. 1. W001
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List /COVerage
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WinPOS 0.0 41.667 125. 35. 27. 1. W002
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List.Mix /COVerage /Track
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WinPOS 132.57 0.083333 108. 33. 26. 1. W004
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COVerage.ListFunc.sYmbol \coverage
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WinPOS 194.43 41.5 64. 21. 0. 0. W003
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Trace
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WinPOS 135.57 45.333 45. 16. 0. 0. W000
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COVerage
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RETURN
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)
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; --------------------------------------------------------------------------------
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; Setup CTI to freeze peripherals while debugging
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; --------------------------------------------------------------------------------
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CtiSetup: ;()
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(
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PRIVATE &CoreCtiBase &PeriphCtiBase
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&CoreCtiBase=COMPonent.BASE("CTI",0.)
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&CoreCtiBase=CONVert.ADDRESSTODUALPORT(&CoreCtiBase)
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&PeriphCtiBase=EDAP:0x8000a000
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; <do not change>
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; MAP CR5-"Core-Stopped" (CTITRIGIN7) to CTM Channel 2
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Data.Set &CoreCtiBase+0x3c %Long 0x4
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; ensure CTM2 is not GATED
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Data.Set &CoreCtiBase+0x40 %Long Data.Long(&CoreCtiBase+0x40)|0x4
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; enable CR5-CTI
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Data.Set &CoreCtiBase+0x00 %Long 0x1
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; </do not change>
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; <user config>
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; the following Data.Set's connect "Core-Stopped" signal to the
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; listed peripherals
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; L2FMC, CCMR5, CRCx, and SYS modules
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Data.Set &PeriphCtiBase+0xa0 %Long 0x4
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; DMA, RTIx, AWMx, HTUx, SCIx, LINx, I2Cx, EMAC, EQEP, ECAP, DMM and DCCx modules
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Data.Set &PeriphCtiBase+0xa4 %Long 0x4
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; DCANx
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Data.Set &PeriphCtiBase+0xa8 %Long 0x4
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; ETPWMx
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Data.Set &PeriphCtiBase+0xac %Long 0x4
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; </user config>
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; <do not change>
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; ensure CTM2 is not GATED
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Data.Set &PeriphCtiBase+0x40 %Long Data.Long(&CoreCtiBase+0x40)|0x4
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; enable PERIPH-CTI
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Data.Set &PeriphCtiBase+0x00 %Long 0x1
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; </do not change>
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RETURN
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)
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