168 lines
5.3 KiB
Plaintext
168 lines
5.3 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: R-Car3 System Evaluation Board QSPI Flash script
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; @Description:
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; SPI FLASH Program script by the core (Cortex-A53) for the RCARV3M Evaluation
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; The S25FL128 (Spansion, 64KB block non uniform) is on the SPI Multi I/O
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; Bus controller
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;
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; Prerequisites:
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; start description in here
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; &sysup_script="&pdd/hardware/<cpu_name>/
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; <cpu_name>-ca53/<cpu_name>-ca53_sieve_sram.cmm"
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;
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; * activate QSPI0 flash
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; SW5 = 3 pin SPI-FLASH (128M) or EX-SPI
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; SW6 = 1 pin SPI-FLASH (128M)
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; SW7 = all ON
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;
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; SRAM: 0xE6328000
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; SPI Multi I/O Bus(controller) Base: 0xEE200000
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;
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; @Author: jjeong
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; @Chip: R8A77960
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; @Keywords: S25FS128S Spansion Flash SPI RCarV3M
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: rcarv3m-ca53-spi.cmm 12742 2023-11-17 08:05:09Z mschaeffner $
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PRIVATE ¶meters
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ENTRY %LINE ¶meters
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PRIVATE ¶m_prepareonly
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¶meters=STRing.UPpeR("¶meters")
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¶m_prepareonly=(STRing.SCAN("¶meters","PREPAREONLY",0)!=-1)
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LOCAL &pdd
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&pdd=OS.PresentDemoDirectory()
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&SPI_BASE=0xEE200000
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; ------------------------------------------------------------------------------
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; Setup CPU
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RESet
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SYStem.RESet
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SYStem.CPU R8A77970
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SYStem.JtagClock CTCK 10MHz
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CORE.ASSIGN 1.
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SYStem.Up
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Register.Set I 0
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Register.Set M 0x5 ;EL1h
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GOSUB WDOG_DISABLE
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; ------------------------------------------------------------------------------
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; Flash Controller Power & Clock Enable
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; ------------------------------------------------------------------------------
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; Flash Pin Mux Configuration
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; ------------------------------------------------------------------------------
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; Flash Controller Init
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Data.Set A:&QSPI_BASE %LE %Long 0x01fff300 ;enable RPC AHB read
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Data.Set A:&QSPI_BASE+0x010 %LE %Long (0x03<<16.) ;DRCMR, read 3byte address mode command
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Data.Set A:&QSPI_BASE+0x01C %LE %Long 0x4700 ;DRENR, 24bit address mode, (24bit==0x4700)
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Data.Set A:&QSPI_BASE+0x014 %LE %Long 0x0 ;DREAR, 24bit Extended External Address Valid Range, A[25:0] enabled
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;Data.Set A:&QSPI_BASE+0x07C %LE %Long 0x80000260 ;PHYCNT
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; ------------------------------------------------------------------------------
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; Flash Read ID Test
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GOSUB READ_ID_TEST
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&pdd=OS.PresentDemoDirectory()
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; ------------------------------------------------------------------------------
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; Init SRAM (16KB) for the flash algorithm
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Data.Set A:0xE67F0018 %Long 0x1
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Data.Set A:0xE6260604 %Long 0x8
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; ------------------------------------------------------------------------------
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; Flash declaration
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Break.RESet
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FLASH.RESet
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FLASH.Create 0x08000000++0x7FFF 0x01000 TARGET Byte
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FLASH.Create 0x08008000++0x7FFF 0x08000 TARGET Byte
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FLASH.Create 0x08010000--0x8FFFFFF 0x10000 TARGET Byte
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FLASH.TARGET 0xE6328000 0xE632A000 0x2000 &pdd/flash/byte/snor3b_rcar3.bin
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; Flash script ends here if called with parameter PREPAREONLY
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IF ¶m_prepareonly
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ENDDO PREPAREDONE
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; ------------------------------------------------------------------------------
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; Flash programming example
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DIALOG.YESNO "Program flash memory?"
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LOCAL &progflash
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ENTRY &progflash
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IF &progflash
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(
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FLASH.ReProgram.ALL
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Data.LOAD.auto *
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FLASH.ReProgram.off
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; Reset device
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PRINT "Please power-cycle the board after flash program is complete"
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)
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ENDDO
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WDOG_DISABLE:
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(
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//RCLK Watchdog Timer disable
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Data.Set EZAXI:0xE6020004 %Long 0xA5A5A500|0x00 ; Write 0 to the RCLK Watchdog Timer Control Register A
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Data.Set EZAXI:0xE6020008 %Long 0xA5A5A500|0x00 ; Write 0 to the RCLK Watchdog Timer Control Register B
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//System Watchdog Timer disable
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Data.Set EZAXI:0xE6030004 %Long 0xA5A5A500|0x00 ; Write 0 to the System Watchdog Timer Control Register A
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Data.Set EZAXI:0xE6030008 %Long 0xA5A5A500|0x00 ; Write 0 to the System Watchdog Timer Control Register B
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RETURN
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)
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READ_ID_TEST:
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(
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&CMNCR=(&QSPI_BASE)
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&SMCR=(&QSPI_BASE+0x20) ; SMCR_0 , SPI mode control
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&SMCMR=(&QSPI_BASE+0x24) ; SMCMR_0 , SPI mode command setting register
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&SMADR=(&QSPI_BASE+0x28) ;address
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&SMOPR=(&QSPI_BASE+0x2C) ;option data setting
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&SMENR=(&QSPI_BASE+0x30) ;enable setting
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&SMRDR=(&QSPI_BASE+0x38)
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&SMRDR1=(&QSPI_BASE+0x3C)
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&SMWDR=(&QSPI_BASE+0x40)
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&SMWDR1=(&QSPI_BASE+0x44)
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&SMDMCR=(&QSPI_BASE+0x60) ;dummy cycle
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®Data=Data.Long(A:&CMNCR)
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Data.Set A:&CMNCR %Long 0x80000000|®Data ;enable manual mode, disable AHB read
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Data.Set A:&SMCMR %Long (0x9f<<16.) ;read-id cmd
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Data.Set A:&SMADR %Long 0x0 ;address 0x0
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Data.Set A:&SMOPR %Long 0x0 ;address 0x0
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;Data.Set A:&SMDMCR %l 0x7 ; dummy 8 cycle number
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&smenr=(0x1<<14.)|0xF; cmd enable, 4byte data read
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Data.Set A:&SMENR %Long &smenr
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//start spi transfer
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&smcr=0x1|(0x2<<1.) ; spie and spire , SPI Read data
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Data.Set A:&SMWDR %LE %Long 0x00000000 ; write Tx buffer init
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Data.Set A:&SMCR %Long &smcr
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&read_data=Data.Long(A:&SMRDR)
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PRINT "Read 1st: 0x" (&read_data)&0xFF " (Manufacturer) "
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PRINT "Read 2nd: 0x" (&read_data>>8.)&0xFF " (Device) "
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PRINT "Read 3rd: 0x" (&read_data>>16.)&0xFF
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PRINT "Read 4th: 0x" (&read_data>>24.)&0xFF
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Data.Set A:&CMNCR %Long ®Data ;disable manual mode, enable AHB read
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RETURN
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)
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